200905653 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種平面顯示裝置、晝素結構及晝素驅 動方法。 【先前技術】 隨著數位時代的來臨，液晶顯示裝置之技術亦快速成 長，已成為不可或缺的電子產品，故對於液晶顯示裝置之 技術及功能要求亦越來越高。 一般而言，液晶顯示裝置主要係包含一液晶面板以及 一背光模組。其中，液晶面板主要係具有彩色濾光基板、 薄膜電晶體基板以及一夾設於兩基板間的液晶層。而背光 模組係作為背光源使用，其係可將來自一光源的光線均勻 地分佈在液晶面板之表面。 一般而言，人眼所看到的影像，通常係由複數個晝素 所組成，而其中係包含紅色、綠色與藍色畫素。每個晝素 藉由液晶分子依據不同的驅動電壓而旋轉或傾斜時，因旋 轉的角度不同，光線通過液晶所產生的亮度亦不同，因此 可產生不同色階。 當使用者於側視液晶顯示裝置時，通常會造成顏色的 偏移，即色差（color shift)問題。目前的改善方式為，藉由 輸入一驅動電壓至一晝素，並對畫素中之兩個不同電容值 之液晶電容充電，而產生兩種不同晝素電壓，例如一高電 壓及一低電壓，使每個晝素呈現亮區及暗區兩個區域，以 200905653 減少色偏的現象，讓使用者於每個視角所見之色彩亮度皆 較為平均。 一此外，每個畫素都會連接至一個相同的共同電極，故 當使用上述改善方式時，畫素的亮區及暗區亦共同使用一 個/、同電壓。然' 而’當停止送人驅動電壓至晝素時，則因 寄生電容效應，岐晝素電壓之電壓值係分別下降，而其 電壓下降量(feed thi；〇Ug_兩個液晶電容之值不同而不相 同’因而導致亮區及暗區的共同電壓難以控制於相同的準 位故雖改善了色偏的問題，但仍會造成晝面閃燦現象。 因此，如何提供一種能夠避免因寄生電容效應所造成 之電壓下降量，以改善晝面閃爍現象之平面顯示裝置、畫 素結構及晝素驅動方法，正是當前的重要課題之一。 【發明内容】 因卑上述課題，本發明之目的為提供—種能夠改. 產生的電壓下降量，以改善晝面閃爍現象: 千面顯不裝置、晝素結構及晝素驅動方法。 緣是’為達上述目的，佑摅士欢nn ^ ^ ^ 依據本發明之晝素結構係分) 補仏迴路及一資料線驅動支 路電性連接，並包含一第—笼 容、一 $相電晶體、-第-等效1 η日姐 、•琪一 3E 容以及一第二補償電容。第一 一 極、-第-沒極及一第—源11電晶體具有-[ 描線驅動迴路電性連接1 /第1極係與第一 k路職連n源極係與資料線驅動辦 谷弟一仙電容、—第二薄膜雷旦-第二等效1 200905653 :連接；第一等效電容與第— ，。第-補償電容分別與第一等效：：=::及極電性 二接。第二薄棋電晶艘具有—第電性 第二源極，其中笛—叫托於t 弟一及極及— 接；第l u—掃描線驅動迴路電性連 按弟-源極係與資料線驅動 兔*'生連 咖薄膜電晶體之第二沒極電:^接第第效電 为別等致電容及補償迴路電性連接。員電容 马運上迷目的，依據本發 / 一平面顯示面板，Α ,ί裝i，係具有 結構係分別與個晝素結構’而該等晝素 料線驅動迴路電二=iT路、一補償迴路及-資 晶體、-第二以=補償電广第二薄膜電 晶體具有一第〜 弟一補侦電容。第一薄膜電 —閘極俜鱼篦4 甲和、一苐—汲極及一第一源極，其中第 二係與弟〜掃描線驅 、中第 -貝料線驅動迴路電性 錄連接’弟―减極係與 體之第-_電性$ & —等效電容與第—薄膜電晶 容及補償迴路電性連接W補償電容分別與第1效電 極、-第二没極及—第薄膜電晶體具有1二閘 描線驅動迴路電性連極’其中第二閘㈣與第-掃 性連接；第二等效電4源極係财料線驅動迴路電 連接。第二補償電容:別與；薄：電，之第:沒極電性 連接。 ^第一專效電容及補償迴路電性 係與 為達上述目的’依本發明之晝素驅動方法， 200905653 素結構配合應用，其中晝素結構係具有一第一薄膜電晶 體、一第二薄膜電晶體、一第一等效電容、一第二等效電 容、一第一補償電容、一第二補償電容。第一等效電容係 電性連接於第一薄膜電晶體及第一補償電容之間，第二等 效電容係電性連接於第二薄膜電晶體及第二補償電容之 間。晝素結構係分別接收一第一掃描訊號及一補償訊號， 其中第一掃描訊號係具有一第一子掃描訊號及一第二子 掃描訊號，補償訊號係具有一第一子補償訊號、一第二子 補償訊號及一第三子補償訊號。晝素,驅動方法包含下列步 驟：於一第一時間，第一薄膜電晶體及第二薄膜電晶體係 分別接收第一子掃描訊號；於一第二時間，第一補償電容 及第二補償電容係分別接收第一子補償訊號，第一薄膜電 晶體及第二薄膜電晶體係分別接收及依據第二子掃描訊 號，以接收一資料訊號；於一第三時間，第一補償電容及 第二補償電容係分別接收第二子補償訊號；以及於一第四 時間，第一補償電容及第二補償電容係分別接收第三子補 償訊號。 為達上述目的，依本發明之畫素驅動方法，係與一晝 素結構配合應用，其中晝素結構係具有一第一薄膜電晶 體、一第二薄膜電晶體、一第一等效電容、一第二等效電 容、一第一補償電容、一第二補償電容。第一等效電容係 電性連接於第一薄膜電晶體及第一補償電容之間，第二等 效電容係電性連接於第二薄膜電晶體及第二補償電容之 間，畫素結構係分別接收一第一掃描訊號、一第一補償訊 200905653 號及-第二補償訊號。晝素驅動方法包含下列步驟：於一 時間，第-薄膜電晶體及第二薄膜電晶體係分別接收及依 據第-掃描訊號，以接收一資料訊號；以及於該時間，第 補ΊΜ電各係接收第一補償訊辨·，禁_娃、於& + 二補償訊號。 糾訊號，弟一補償電容係接收第 承上所述，因依本發明之平面顯示裝置、晝素 晝素驅動方法，係藉由晝素結:…°冓 薄膜電晶體分別，、電00體及第二 路電性連接，動迴路及資料線驅動迴 -補償電容電性連接，第：=二第一薄膜電晶體及第 償電容係分別血肝、㈣Ϊ ❿第—_電容及第二補 發明之平面顯示裝二C。與習知技術相較’本 及第二補償電容，廿八佴你增加了第一補償電容 式，不僅可藉由補償迴刀路1 與H偾迴路電性連接，此種方 第二補償電容分別對Μ —補侦錢透過第一補償電容及 償，以抵鐵第—等效電々效電容及第二等效電容做補 應，且消除書料:弟二等效電容產生寄生電容效 改善畫面閃爍素電壓有電壓下降的問題，進而 升平面顯示裝置之顯示品質。 【實施方式】 以下將參照相關 種平面顯示裝置、查 次明依本發明較佳實施例之一 請同時參照圖i二，及晝素驅動方法。 圖所示，本發明第-實施例之平 11 200905653 面顯示裝置1係具有一平面顯示面板11，而平面顯示面板 11則具有複數個晝素結構111。各晝素結構m係分別與 第一掃描線驅動迴路SL、一補償迴路CL及一資料線驅動 迴路DL電性連接。本實施例之平面顯示裝置1，於實施 上係為一液晶顯示裝置，故平面顯示面板11係為一液晶 顯示面板。 於本實施例中，如圖2所示，畫素結構111係包含一 第一薄膜電晶體Q1、一第一等效電容CA、一第一補償電 容C7、一第二薄膜電晶體Q2、一第二等效電容CB及一 第二補償電容C8。 第一薄膜電晶體Q1係具有一第一閘極G1、一第一汲 極D1及一第一源極S1。而第一閘極G1係與第一掃描線 驅動迴路SL電性連接，第一源極S1與資料線驅動迴路 DL電性連接。 第一等效電容CA係與第一薄膜電晶體Q1之第一汲 極D1電性連接，並具有一第一寄生電容C1、一第一液晶 電容C2以及一第一儲存電容C3。而第一寄生電容C1係 分別與第一薄膜電晶體Q1之第一汲極D1及第一閘極G1 電性連接，第一液晶電容C2及第一儲存電容C3係相互電 性連接，並分別與第一薄膜電晶體Q1之第一汲極D1電性 連接，且第一液晶電容C2係接收一共同電壓VC，而第一 儲存電容C3則接收一儲存電壓VS1。 第一補償電容C7係分別與第一等效電容CA及補償 迴路CL電性連接。 12 200905653 第二薄膜電晶體Q2係具有一第二閘極G2、一第二汲 極D2及一第二源極S2。而第二閘極G2係與第一掃描線 驅動迴路SL電性連接，第二源極S2與資料線驅動迴路 DL電性連接。 第二等效電容CB係分別與第二薄膜電晶體Q2之第 二汲極D2及第二閘極G2電性連接，並具有一第二寄生電 容C4、一第二液晶電容C5及一第二儲存電容C6。而第二 寄生電容C4係分別與第二薄膜電晶體Q2之第二閘極G2 及第二汲極D2電性連接，第二液晶電容C5及第二儲存電 容C6係相互電性連接，並分別與第二薄膜電晶體Q2之第 二汲極D2電性連接，且第二液晶電容C5係接收共同電壓 VC，而第二儲存電容C6則接收一儲存電壓VS2。 第二補償電容C8係分別與第二等效電容CB及補償迴 路CL電性連接。 於本實施例中，第一等效電容CA與第二等效電容CB 於實施上係可為相同或相異之值，在此係以相異之值為 例。 請參照圖3所示，本實施例之第一掃描線驅動迴路SL 係傳送第一掃描訊號SS，而第一掃描訊號SS係具有一第 一子掃描訊號SS1及一第二子掃描訊號SS2。於本實施 中，第一掃描線訊號SS係為一脈波訊號。 本實施例之資料線驅動迴路D.L，係傳送資料訊號（圖 未示），且資料訊號於實施上係為一電壓訊號。 請再參照圖3所示，補償迴路CL係產生補償訊號 13 200905653 cs，而補償訊號CS係具有一第一子補償訊號CS1及一第 二子補償訊號CS2。本實施例之補償迴路CL於實施上係 為一第二掃描線驅動迴路，故補償訊號CS係為一第二掃 描訊號，而第二掃描線驅動迴路係作為驅動另一個晝素結 構111之用。 於本實施例中，第一子掃描訊號SS1及第一子補償訊 號CS1係分別為一低準位，第二子掃描訊號SS2及第二子 補償訊號CS2係分別為一高準位，而且第二子掃描訊號 SS2之相位與第一子補償訊號CS1之相位係相反。 請再同時參照圖2與圖3所示，本實施例之平面顯示 裝置1，其畫素驅動方法如下：晝素結構111係分別與第 一掃描線驅動迴路SL、資料線驅動迴路DL及補償迴路 CL電性連接。 於一第一時間T1，第一薄膜電晶體Q1之第一閘極 G1及第二薄膜電晶體Q2之第二閘極G2係分別接收第一 子掃描訊號SS1，此時，因第一子掃描訊號SS1為低準位， 故第一薄膜電晶體Q1及第二薄膜電晶體Q2皆未導通。 於一第二時間T2,第一薄膜電晶體Q1之第一閘極 G1及第二薄膜電晶體Q2之第二閘極G2係分別接收及依 據第二子掃描訊號SS2為高準位而導通，以使第一薄膜電 晶體Q1之第一源極S1及第二薄膜電晶體Q2之第二源極 S2分別接收資料訊號，此時，第一薄膜電晶體Q1之第一 汲極D1及第二薄膜電晶體Q2之第二汲極D2為相同電 壓。同時，第一補償電容C7及第二補償電容C8係分別接 14 200905653 收第一子補償訊號CS1。 於一第三時間T3，第一補償電容C7及第二補償電容 C8係分別接收第二子補償訊號CS2，而同時，在第一掃描 線驅動迴路SL停止將第一掃描訊號SS的第二子掃描訊號 SS2送入第一薄膜電晶體Q1及第二薄膜電晶體Q2的瞬 間，意即第一子補償訊號CS1轉換到第二子補償訊號CS2 時，係因第一等效電容CA及第二等效電容CB已藉由第 一子補償訊號CS1轉換到第二子補償訊號CS2的改變而得 到補償，故不會產生寄生電容效應，且同時也消除了晝素 結構111的第一晝素電壓VI及第二晝素電壓V2有電壓值 下降(feed through)的問題。 於本實施例中，亦可依據不同需求而藉由第二子補償 訊號CS2分別與第一等效電容CA及第二等效電容CB相 配合，而補償使得晝素結構111的第一晝素電壓VI及第 二晝素電壓V2的改變量相同或不相同，在此即以第一晝 素電壓VI之值大於第二晝素電壓V2之值為例。而此時， 畫素結構111係透過第一晝素電壓VI及第二晝素電壓V2 以呈現一亮區及一暗區。 於一第四時間T4，第一補償電容C7及第二補償電容 C8係分別接收第三子補償訊號CS3,而此時第一補償電容 C7及第二補償電容C8係受到第二子補償訊號CS2轉換到 第三子補償訊號CS3的影響，而分別使第一晝素電壓VI 及第二畫素電壓V2之值拉降至適當的準位。 由於平面顯示裝置1係的晝素結構111，其第一薄膜 15 200905653 電晶體Q1及第二薄膜電晶體Q2分別與第一掃描線驅動迴 路SL及資料線驅動迴路DL電性連接，第一等效電容CA 係分別與第一薄膜電晶體Q1之第一閘極G1、第一汲極 D1及第一補償電容C7電性連接，第二等效電容CB係分 別與第二薄膜電晶體Q2之第二閘極G2、第二汲極D2及 第二補償電容C8電性連接，第一補償電容C7及第二補償 電容C8係分別與補償迴路CL電性連接。晝素結構111係 藉由補償迴路CL之第一子補償訊號CS1轉換為第二子補 償訊號CS2的改變，而透過第一補償電容C7及第二補償 電容C8對第一等效電容CA及第二等效電容CB做補償。 此種方式，即使在停止送入第二子掃描訊號SS2時，第一 等效電容CA及第二等效電容CB因已得到補償，故不僅 不會產生寄生電容效應，更可消除晝素結構111之第一晝 素電壓VI及第二晝素電壓V2有電壓下降的問題，進而改 善晝面閃爍現象。 以下，請參照圖4所示，本發明較佳實施例之一種晝 素驅動方法係應用於上述第一較佳實施例之平面顯示裝 置1 (如圖1及圖2所示），平面顯示裝置1係具有平面顯 示面板11，而平面顯示面板11係具有複數個晝素結構 111，在此係以晝素驅動方法係應用於晝素結構111(如圖2 所示）為例。此外，本實施例之畫素結構111係與上述第一 較佳實施例之晝素結構111具有相同構成、特徵及功效， 故於此不再贅述。 請再同時參照圖2至圖4所示，本實施例之晝素驅動 16 200905653 方法係包括步驟SOI至S04。 於步驟S01中，於一第一時間T1，第一薄膜電晶體 Q1及第二薄膜電晶體Q2係分別接收第一子掃描訊號 SS1 ° 於步驟S02中，於一第二時間T2，第一補償電容C7 及第二補償電容C8係分別接收第一子補償訊號CS1，第 一薄膜電晶體Q1及第二薄膜電晶體Q2係分別接收及依據 第二子掃描訊號SS2，以接收一資料訊號。 於步驟S03中，於一第三時間T3，第一補償電容C7 及第二補償電容C8係分別接收第二子補償訊號CS2。 於步驟S04中，於一第四時間T4，第一補償電容C7 及第二補償電容C8係分別接收第三子補償訊號CS3。 其中詳細的晝素驅動方法，於上述第一較佳實施例 中，已一併詳述，故於此不再加以贅述。 請參照圖5所示，本發明第二較佳實施例之平面顯示 裝置2係具有一平面顯示面板（圖未示）。平面顯示面板係 具有複數個晝素結構211，各畫素結構211係分別與第一 掃描線驅動迴路SL、一補償迴路CL及一資料線驅動迴路 DL電性連接。本實施例之平面顯示裝置2，於實施上係為 一液晶顯示裝置，故平面顯示面板係為一液晶顯示面板。 請再參照圖5所示，於本實施例中，晝素結構211係 包含一第一薄膜電晶體Q1、一第一等效電容CA、一第一 補償電容C7、一第二薄膜電晶體Q2、一第二等效電容CB 及一第二補償電容C8。而第一薄膜電晶體Q1及第二薄膜 17 200905653 電晶體Q2係分職第—掃描線轉迴路SL及資料線驅動 迴路DL電性連接，第-等效電容CA係分別與第一薄膜 電晶體Q1及第—補償電容C7電性連接，第二等效電容 CB係分別與第二薄膜電晶體Q2及第二補償電容C8電性 連接。 本實施例之第〜掃描線驅動迴路S L、資料線驅動迴路 ^、晝素結構2U及其第—薄膜電晶體qi、第〆等效電 =A、第一補償電容〇、第二薄膜電晶體q2、第二等效 笛谷CB及第二補償電容以之構成、特徵及功效係與上述 較佳實施例(如圖2及圖3所示)之 、貧料線驅㈣路DL、畫素結構⑴及動迥 電晶體Q1、第一等欵電容ca、 一第—薄膜 膜電晶體Q2、第補&電^C7、苐二薄 故於此不：;:4政電容㈣第二補償電容CM目同4 此外，請再同時參照圖5與圖6所示 面顯示褒置2斑上祕钕. 貫施例之平 F1 9二 第—較佳實施例之平面顯示货番 圖2及圖3所示）不同之處在於 丁^置i(如 第-掃描訊號ss;而補償二二動趣路此 ::，CL1及-第二子輪有:第-Lli讀第―補償電容口電性連接，第 補償 路山係與第二補償電容C8電性連接。 子補償趣 此：，第一子補償迴路⑴係傳送一 ’紅子補償迴路CL2係傳送—第二㈣號 而第一補償訊號CSA及第二補償訊號⑽之值^’ 18 200905653 可相同或相異，在此係以第—福 號CSB之值係分別相異為例。貝Λ號CSA及第二補償訊 於她例第一掃描訊 及第二補償訊號CSB係分別為」SS、弟1償訊號CSA 號CSA及第二補償訊號CSB係^波^^虎。而帛一補償訊 描訊號ss係為一高準位，且第〜刀另1 ”’、一低準位，第—掃 第-補償減CSA及第二補償^錢SS之相位係與 請同時參照圖5與圖6上，二SB之相位相反。 置2,其中畫素結構211·^別2施例之平面顯示装 SL、資料線驅—補=路 CL1及第二子補償迴路CL2電性連接。 $員迴路 晝素驅動方法如下： 於一時間T，第一薄膜電晶體 二薄臈電晶體Q2之第二閘極G2 ¥ 及第 描吒鲈以盏、i v 係分別接收及依據第—掃 =就SS. #通，而可分別接收—資料訊號，而資料訊 號係分別對第-等效電容CA及第二等效電容⑶充電以 產生相異值之第-晝素電壓V3及第二晝素電壓V4。 於此時間T ’第—補償電容〇係接收第—補償訊號 CSA，第二補償電容C8係接收第二補償訊號⑽，而第 補仏讯唬CSA係透過第一補償電容C7對第一等效電容 _ K員第一補償訊號CSB係透過第二補償電容c8 宁弟=等效電容CB做補償。 二薄田第—掃描訊號SS停止送入第一薄膜電晶體Q1及第 膜電晶體Q2時’此時，第—補償訊號CSA及第二補 19 200905653 償訊號CSB係分別由低準位漸漸向上提升其準位，古 等效電容CA及第二等效電容CB係已分 =第— 訊號CSA及第二補償訊號CSB之改變而做補償償 對寄生電容效應做補償，以消除第—晝素電壓^ 針 V4有電壓值下降的問題，亦進而改善畫面_ 以下，請參照圖7所示，本發明較佳實施例之全 =方法係應用於上述第二較佳實施例之平面顯“ (如圖5及圖6所示)，平面顯示裝置2係具 不面板’而平面顯示面板係具有複數個畫素結構扣，在 ^以=鶴方法係應㈣晝素結構211(如圖5所 此外，本實施例之晝素結構211係與上述第二較佳 I:::晝素結構211具有相同構成、特徵及功效，故於 此不再贅述。 ==時參„5至圖7所示，本實施例之晝素驅動 在係包括步驟S11至步驟S12。 於步驟S11中，於'一 ^ ** _ ^ ^ ^ 時間第一薄膜電晶體Q1及第 :收一\晶體Q 2係分別接收及依據第—掃描訊號s s，以 接收賁料訊號。 ^驟S12中’於此時間’第一補償電容c7係接收 =SB訊號CSA，第二補償電容C8係接收第二補償訊 ^中詳細的畫素驅動方法，於上述第二較佳實施例 巳一併詳述，故於此不再加以贅述。 20 200905653 綜上所述，因依本發明之平面顯示裝置、晝素結構及 晝素驅動方法，係藉由晝素結構之第一薄膜電晶體及第二 薄膜電晶體分別與第一掃描線驅動迴路及資料線驅動迴 路電性連接，第一等效電容係分別與第一薄膜電晶體及第 一補償電容電性連接，第二等效電容係分別與第二薄膜電 晶體及第二補償電容電性連接，而第一補償電容及第二補 償電容係分別與補償迴路電性連接。與習知技術相較，本 發明之平面顯示裝置的晝素結構，係增加了第一補償電容 及第二補償電容，並分別與補償迴路電性連接，此種方 式，不僅可藉由補償迴路之補償訊號透過第一補償電容及 第二補償電容分別對第一等效電容及第二等效電容做補 償，更可避免第一等效電容及第二等效電容產生寄生電容 效應，且消除晝素結構之晝素電壓有電壓下降的問題，進 而改善晝面閃爍現象，提升平面顯示裝置之顯示品質。 以上所述僅為舉例性，而非為限制性者。任何未脫離 本發明之精神與範疇，而對其進行之等效修改或變更，均 應包含於後附之申請專利範圍中。 【圖式簡單說明】 圖1為顯示依本發明第一較佳實施例之一種平面顯示 裝置之示意圖； 圖2為顯示依本發明第一較佳實施例之平面顯示裝置 之平面顯示面板，其之晝素結構示意圖； 圖3為顯示依本發明第一較佳實施例之晝素驅動方法 21 200905653 之第一掃描訊號及補償訊號於第一時間、第二時間及第三 時間之波形不意圖； 圖4為顯示依本發明較佳實施例之一種畫素驅動方法 之流程圖； 圖5為顯示依本發明第二較佳實施例之一種平面顯示 裝置之平面顯示面板，其之晝素結構示意圖； 圖6為顯示依本發明第二較佳實施例之畫素驅動方法 之第一掃描訊號、第一補償訊號及第二補償訊號於時間之 波形示意圖；以及 圖7為顯示依本發明較佳實施例之另一種畫素驅動方 法之流程圖。 【主要元件符號說明】 1、2 :平面顯示裝置 11 :平面顯示面板 111、211 :晝素結構 CA :第一等效電容 CB ··第二等效電容 CL :補償迴路 CL1 :第一子補償迴路 CL2 :第二子補償迴路 C1 :第一寄生電容 C2 :第一液晶電容 C3 :第一儲存電容 22 200905653 C4 第二寄生電容 C5 苐二液晶電容 C6 第二儲存電容 C7 第一補償電容 C8 第二補償電容 cs 補償訊號 CS1 :第一子補償訊號 CS2 :第二子補償訊號 CS3 :第三子補償訊號 DL :資料線驅動迴路 D1 :第一 ί及極 D2 :第二汲極 G1 :第一閘極 G2 :第二閘極 Ql :第一薄膜電晶體 Q2 :第二薄膜電晶體 SL 第一掃描線驅動迴路 SI : 第一源極 S2 第二源極 ss 第一掃描訊號 SSI :第一子掃描訊號 SS2 :第二子掃描訊號 T ： 時間 T1 第一時間 200905653 Τ2 :第二時間 Τ3 :第三時間 VI、V3 :第一晝素電壓 V2、V4 :第二晝素電壓 VC :共同電壓 VS1、VS2 :儲存電壓 S01-S04、S11-S12 :晝素驅動方法之步驟 24200905653 IX. Description of the Invention: [Technical Field] The present invention relates to a flat display device, a halogen structure, and a halogen driving method. [Prior Art] With the advent of the digital age, the technology of liquid crystal display devices has also grown rapidly and has become an indispensable electronic product, so the technical and functional requirements for liquid crystal display devices are also increasing. In general, a liquid crystal display device mainly includes a liquid crystal panel and a backlight module. The liquid crystal panel mainly has a color filter substrate, a thin film transistor substrate, and a liquid crystal layer interposed between the two substrates. The backlight module is used as a backlight to uniformly distribute light from a light source on the surface of the liquid crystal panel. In general, the images seen by the human eye are usually composed of a plurality of elements, including red, green and blue pixels. When the liquid crystal molecules are rotated or tilted according to different driving voltages, the brightness of the light passing through the liquid crystal is different depending on the angle of rotation, and thus different color gradations can be produced. When the user views the liquid crystal display device sideways, it usually causes a color shift, that is, a color shift problem. The current improvement method is to generate two different pixel voltages, such as a high voltage and a low voltage, by inputting a driving voltage to a halogen and charging two liquid crystal capacitors of different capacitance values in the pixel. In order to make each element appear in the bright area and the dark area, the phenomenon of color shift is reduced by 200905653, so that the brightness of the color seen by the user at each viewing angle is relatively average. In addition, each pixel is connected to the same common electrode, so when using the above improvement method, the bright and dark areas of the pixel also use a /, the same voltage. However, when the voltage of the driving voltage is stopped to the halogen, the voltage value of the halogen voltage is decreased by the parasitic capacitance effect, and the voltage drop amount (feed thi; 〇 Ug_ the value of the two liquid crystal capacitors) Different and not the same 'thus, the common voltage of the bright area and the dark area is difficult to control at the same level. Although the problem of color shift is improved, the phenomenon of flashing on the surface is still caused. Therefore, how to provide a kind of parasitic phenomenon can be avoided. The amount of voltage drop caused by the capacitance effect, the planar display device, the pixel structure, and the pixel driving method for improving the flickering phenomenon of the facet are one of the current important topics. [Summary of the Invention] The purpose is to provide a kind of voltage drop that can be changed. In order to improve the flickering phenomenon of the kneading surface: the surface of the device, the structure of the alizarin and the driving method of the alizarin. The edge is 'for the above purpose, you can enjoy nn ^ ^ ^ According to the present invention, the halogen structure is divided into a circuit and a data line driving branch electrically connected, and includes a first - cage, a $ phase transistor, - a - equivalent 1 η 日 sister, • Qi Yi 3E And a second compensation capacitor. The first one, the -th-thin pole and one first-source 11 transistor have -[the line driving circuit electrical connection 1 / the first pole system and the first k road position n source system and the data line drive valley Brother Yixian capacitor, - second film Leidan - second equivalent 1 200905653: connection; first equivalent capacitance and the first -,. The first-compensation capacitor is respectively equivalent to the first: :=:: and the polarity is connected. The second thin chess electric crystal ship has a second electric source of the first electric quantity, wherein the flute is called the t-one and the pole and the connection; the lu-scan line driving circuit is electrically connected to the brother-source system and the data. The second drive of the line-driven rabbit*'s raw coffee film transistor is: the first power is connected to the capacitor and the compensation circuit. Capacitor horses are fascinating, according to the hair / a flat display panel, Α, ί loading i, has a structural system and a single element structure 'and the 昼 element line drive circuit electric two = iT road, one The compensation circuit and the - crystal, - the second to = compensation electric wide second thin film transistor has a first - brother - a capacitor. The first thin film electric-gate squid 4 A, one 苐-bungee and a first source, wherein the second line is connected with the younger brother to the scan line drive, and the middle-before-line feed line drive circuit is electrically recorded. The younger brother - the body of the body and the body - _ $ & - equivalent capacitance and the first - film electric crystal capacity and compensation circuit electrical connection W compensation capacitance and the first effect electrode, - second immersion and - The first thin film transistor has a two-gate line driving circuit electrical connection pole 'where the second gate (four) is connected with the first sweeping; the second equivalent power 4 source is the fuel line driving loop electrically connected. The second compensation capacitor: do not; thin: electricity, the first: no electrical connection. ^The first special effect capacitor and the compensation circuit electrical system are combined with the use of the elemental driving method according to the present invention for the above purpose, wherein the halogen structure has a first thin film transistor and a second film. The transistor, a first equivalent capacitor, a second equivalent capacitor, a first compensation capacitor, and a second compensation capacitor. The first equivalent capacitor is electrically connected between the first thin film transistor and the first compensation capacitor, and the second equivalent capacitor is electrically connected between the second thin film transistor and the second compensation capacitor. The pixel structure receives a first scan signal and a compensation signal, wherein the first scan signal has a first sub-scan signal and a second sub-scan signal, and the compensation signal has a first sub-compensation signal, a first The second sub-compensation signal and a third sub-compensation signal. The driving method includes the following steps: at a first time, the first thin film transistor and the second thin film electro-crystal system respectively receive the first sub-scanning signal; and at a second time, the first compensating capacitor and the second compensating capacitor Receiving a first sub-compensation signal, respectively, the first thin film transistor and the second thin film electro-crystal system respectively receive and according to the second sub-scanning signal to receive a data signal; at a third time, the first compensation capacitor and the second The compensation capacitors respectively receive the second sub-compensation signal; and at a fourth time, the first compensation capacitor and the second compensation capacitor respectively receive the third sub-compensation signal. In order to achieve the above object, the pixel driving method according to the present invention is applied in combination with a halogen structure having a first thin film transistor, a second thin film transistor, a first equivalent capacitance, a second equivalent capacitor, a first compensation capacitor, and a second compensation capacitor. The first equivalent capacitor is electrically connected between the first thin film transistor and the first compensation capacitor, and the second equivalent capacitor is electrically connected between the second thin film transistor and the second compensation capacitor, and the pixel structure is Receiving a first scan signal, a first compensation signal 200905653 and a second compensation signal respectively. The halogen driving method includes the following steps: at a time, the first-thin film transistor and the second thin film electro-crystal system respectively receive and according to the first-scan signal to receive a data signal; and at this time, the first circuit Receive the first compensation signal, ban _ wa, and & + two compensation signals. The correction signal, the brother-one compensation capacitor is received by the above, because the flat display device and the halogen-based halogen driving method according to the present invention are made by a bismuth layer: ... 冓 冓 thin film transistor respectively, And the second electrical connection, the dynamic circuit and the data line drive back-compensation capacitor electrical connection, the first: two first thin film transistor and the first compensation transistor are blood liver, (four) Ϊ ❿ first - _ capacitor and second supplement The flat display of the invention is equipped with two C. Compared with the conventional technology, the present and second compensation capacitors, you add the first compensation capacitor type, not only can be electrically connected by the compensation return path 1 and the H偾 circuit, the second compensation capacitor Responding to the 补偿 补 补 补 补 补 补 补 补 补 补 补 补 补 补 补 补 补 补 补 补 补 补 补 补 补 补 补 补 补 补 补 补 补 补 补 补 补 补 补 补 补 补 补The flickering voltage of the picture has a problem of voltage drop, and the display quality of the flat display device is increased. [Embodiment] Hereinafter, referring to a related flat display device, one of the preferred embodiments of the present invention, please refer to FIG. 2 and the pixel driving method. As shown in the figure, the flat display device 1 of the first embodiment of the present invention has a flat display panel 11, and the flat display panel 11 has a plurality of halogen structures 111. Each of the pixel structures m is electrically connected to the first scan line driving circuit SL, a compensation circuit CL, and a data line driving circuit DL. The flat display device 1 of the present embodiment is embodied as a liquid crystal display device, so that the flat display panel 11 is a liquid crystal display panel. In this embodiment, as shown in FIG. 2, the pixel structure 111 includes a first thin film transistor Q1, a first equivalent capacitor CA, a first compensation capacitor C7, and a second thin film transistor Q2. The second equivalent capacitor CB and a second compensation capacitor C8. The first thin film transistor Q1 has a first gate G1, a first drain D1 and a first source S1. The first gate G1 is electrically connected to the first scan line driving circuit SL, and the first source S1 is electrically connected to the data line driving circuit DL. The first equivalent capacitor CA is electrically connected to the first drain D1 of the first thin film transistor Q1, and has a first parasitic capacitor C1, a first liquid crystal capacitor C2, and a first storage capacitor C3. The first parasitic capacitor C1 is electrically connected to the first drain D1 and the first gate G1 of the first thin film transistor Q1, and the first liquid crystal capacitor C2 and the first storage capacitor C3 are electrically connected to each other, and respectively The first drain TFT D1 of the first thin film transistor Q1 is electrically connected, and the first liquid crystal capacitor C2 receives a common voltage VC, and the first storage capacitor C3 receives a storage voltage VS1. The first compensation capacitor C7 is electrically connected to the first equivalent capacitor CA and the compensation loop CL, respectively. 12 200905653 The second thin film transistor Q2 has a second gate G2, a second drain D2 and a second source S2. The second gate G2 is electrically connected to the first scan line driving circuit SL, and the second source S2 is electrically connected to the data line driving circuit DL. The second equivalent capacitor CB is electrically connected to the second drain D2 and the second gate G2 of the second thin film transistor Q2, respectively, and has a second parasitic capacitor C4, a second liquid crystal capacitor C5 and a second Store capacitor C6. The second parasitic capacitor C4 is electrically connected to the second gate G2 and the second drain D2 of the second thin film transistor Q2, respectively, and the second liquid crystal capacitor C5 and the second storage capacitor C6 are electrically connected to each other and respectively The second drain D2 of the second thin film transistor Q2 is electrically connected, and the second liquid crystal capacitor C5 receives the common voltage VC, and the second storage capacitor C6 receives a storage voltage VS2. The second compensation capacitor C8 is electrically connected to the second equivalent capacitor CB and the compensation loop CL, respectively. In this embodiment, the first equivalent capacitance CA and the second equivalent capacitance CB may be the same or different values in the implementation, and the difference values are exemplified herein. As shown in FIG. 3, the first scan line driving circuit SL of the present embodiment transmits a first scan signal SS, and the first scan signal SS has a first sub-scan signal SS1 and a second sub-scan signal SS2. In the present embodiment, the first scan line signal SS is a pulse signal. The data line driving circuit D.L of this embodiment transmits a data signal (not shown), and the data signal is implemented as a voltage signal. Referring to FIG. 3 again, the compensation circuit CL generates a compensation signal 13 200905653 cs, and the compensation signal CS has a first sub-compensation signal CS1 and a second sub-compensation signal CS2. The compensation circuit CL of this embodiment is implemented as a second scan line drive circuit, so the compensation signal CS is a second scan signal, and the second scan line drive circuit is used to drive another pixel structure 111. . In this embodiment, the first sub-scanning signal SS1 and the first sub-compensation signal CS1 are respectively a low level, and the second sub-scanning signal SS2 and the second sub-compensation signal CS2 are respectively a high level, and the first The phase of the two sub-scanning signals SS2 is opposite to the phase of the first sub-compensation signal CS1. Referring to FIG. 2 and FIG. 3 simultaneously, the planar display device 1 of the present embodiment has the pixel driving method as follows: the pixel structure 111 is respectively coupled to the first scan line driving circuit SL, the data line driving circuit DL, and the compensation. The loop CL is electrically connected. The first gate G1 of the first thin film transistor Q1 and the second gate G2 of the second thin film transistor Q2 respectively receive the first sub-scanning signal SS1 at a first time T1, at this time, due to the first sub-scan The signal SS1 is at a low level, so that the first thin film transistor Q1 and the second thin film transistor Q2 are not turned on. In a second time T2, the first gate G1 of the first thin film transistor Q1 and the second gate G2 of the second thin film transistor Q2 are respectively received and turned on according to the second sub-scanning signal SS2. The first source S1 of the first thin film transistor Q1 and the second source S2 of the second thin film transistor Q2 respectively receive the data signal, and at this time, the first drain D1 and the second of the first thin film transistor Q1 The second drain D2 of the thin film transistor Q2 is the same voltage. At the same time, the first compensation capacitor C7 and the second compensation capacitor C8 are respectively connected to the first sub-compensation signal CS1. At a third time T3, the first compensation capacitor C7 and the second compensation capacitor C8 respectively receive the second sub-compensation signal CS2, and at the same time, stop the second sub-signal SS in the first scan line drive loop SL. When the scan signal SS2 is sent to the first thin film transistor Q1 and the second thin film transistor Q2, that is, when the first sub-compensation signal CS1 is switched to the second sub-compensation signal CS2, the first equivalent capacitance CA and the second The equivalent capacitance CB is compensated by the change of the first sub-compensation signal CS1 to the second sub-compensation signal CS2, so that the parasitic capacitance effect is not generated, and the first pixel voltage of the halogen structure 111 is also eliminated. The VI and the second halogen voltage V2 have a problem of a voltage value drop. In this embodiment, the first sub-compensation signal CS2 can be matched with the first equivalent capacitance CA and the second equivalent capacitance CB according to different requirements, thereby compensating the first element of the halogen structure 111. The amount of change in the voltage VI and the second pixel voltage V2 is the same or different, and the value of the first pixel voltage VI is greater than the value of the second pixel voltage V2. At this time, the pixel structure 111 transmits the first pixel voltage VI and the second pixel voltage V2 to present a bright area and a dark area. In a fourth time T4, the first compensation capacitor C7 and the second compensation capacitor C8 respectively receive the third sub-compensation signal CS3, and at this time, the first compensation capacitor C7 and the second compensation capacitor C8 are subjected to the second sub-compensation signal CS2. The effect of the third sub-compensation signal CS3 is switched to the appropriate value of the first pixel voltage VI and the second pixel voltage V2, respectively. The first film 15 200905653 transistor Q1 and the second film transistor Q2 are electrically connected to the first scan line driving circuit SL and the data line driving circuit DL, respectively, by the pixel structure 111 of the flat display device 1 . The capacitor CA is electrically connected to the first gate G1, the first drain D1 and the first compensation capacitor C7 of the first thin film transistor Q1, respectively, and the second equivalent capacitor CB is respectively connected to the second thin film transistor Q2. The second gate G2, the second drain D2 and the second compensation capacitor C8 are electrically connected, and the first compensation capacitor C7 and the second compensation capacitor C8 are electrically connected to the compensation loop CL, respectively. The pixel structure 111 is converted into the second sub-compensation signal CS2 by the first sub-compensation signal CS1 of the compensation loop CL, and the first equivalent capacitor CA and the first compensating capacitor C7 and the second compensating capacitor C8 are transmitted through the first compensating capacitor C7 and the second compensating capacitor C8. The second equivalent capacitor CB is used for compensation. In this way, even when the second sub-scanning signal SS2 is stopped, the first equivalent capacitance CA and the second equivalent capacitance CB are compensated, so that not only the parasitic capacitance effect but also the halogen structure can be eliminated. The first halogen voltage VI and the second halogen voltage V2 of 111 have a problem of voltage drop, thereby improving the flickering phenomenon of the face. Hereinafter, referring to FIG. 4, a pixel driving method according to a preferred embodiment of the present invention is applied to the flat display device 1 (shown in FIGS. 1 and 2) of the first preferred embodiment, and the flat display device is used. The 1 series has a flat display panel 11, and the flat display panel 11 has a plurality of halogen structures 111. Here, the halogen driving method is applied to the halogen structure 111 (shown in FIG. 2) as an example. In addition, the pixel structure 111 of the present embodiment has the same configuration, features, and functions as the pixel structure 111 of the first preferred embodiment, and thus will not be described again. Referring to FIG. 2 to FIG. 4 simultaneously, the method of the pixel drive 16 200905653 of the present embodiment includes steps S01 to S04. In step S01, at a first time T1, the first thin film transistor Q1 and the second thin film transistor Q2 respectively receive the first sub-scanning signal SS1 ° in step S02, and at a second time T2, the first compensation The capacitor C7 and the second compensation capacitor C8 respectively receive the first sub-compensation signal CS1, and the first thin film transistor Q1 and the second thin film transistor Q2 respectively receive and according to the second sub-scanning signal SS2 to receive a data signal. In step S03, at a third time T3, the first compensation capacitor C7 and the second compensation capacitor C8 receive the second sub-compensation signal CS2, respectively. In step S04, at a fourth time T4, the first compensation capacitor C7 and the second compensation capacitor C8 receive the third sub-compensation signal CS3, respectively. The detailed method for driving the element in the above-mentioned first preferred embodiment has been described in detail, and thus will not be further described herein. Referring to Figure 5, the flat display device 2 of the second preferred embodiment of the present invention has a flat display panel (not shown). The planar display panel has a plurality of pixel structures 211, and each pixel structure 211 is electrically connected to the first scan line driving circuit SL, a compensation circuit CL and a data line driving circuit DL, respectively. The flat display device 2 of the present embodiment is a liquid crystal display device, so the flat display panel is a liquid crystal display panel. Referring to FIG. 5 again, in the embodiment, the halogen structure 211 includes a first thin film transistor Q1, a first equivalent capacitor CA, a first compensation capacitor C7, and a second thin film transistor Q2. a second equivalent capacitor CB and a second compensation capacitor C8. The first thin film transistor Q1 and the second thin film 17 200905653 transistor Q2 are divided into the first scanning line switching circuit SL and the data line driving circuit DL are electrically connected, and the first-equivalent capacitance CA is respectively associated with the first thin film transistor Q1 and the first compensation capacitor C7 are electrically connected, and the second equivalent capacitor CB is electrically connected to the second thin film transistor Q2 and the second compensation capacitor C8, respectively. The first scan line driving circuit SL, the data line driving circuit ^, the halogen structure 2U and the first thin film transistor qi, the second equivalent electric power A, the first compensation capacitor 〇, the second thin film transistor Q2, the second equivalent Cartesian CB and the second compensation capacitor are composed, characteristics and functions are the same as the above preferred embodiment (as shown in FIG. 2 and FIG. 3), the lean line drive (four) road DL, pixel Structure (1) and dynamic 迥 crystal Q1, first 欵 tantalum capacitor ca, a first film film transistor Q2, 补补 & 电^C7, 苐二薄, therefore not:;: 4 political capacitance (four) second compensation Capacitor CM is the same as 4, in addition, please refer to the surface shown in Figure 5 and Figure 6 at the same time to show the spot 2 tips. The embodiment of the flat F1 9 2 - the preferred embodiment of the plane shows the goods Figure 2 and The difference shown in Figure 3 is that the setting is i (such as the first-scan signal ss; and the compensation of the second two-way action::, CL1 and - the second sub-wheel has: the first - Lli read the - compensation capacitor port Electrical connection, the first compensation road mountain system is electrically connected with the second compensation capacitor C8. The sub-compensation is interesting: the first sub-compensation circuit (1) transmits a 'red child compensation circuit CL2 system transmission- (4) The value of the first compensation signal CSA and the second compensation signal (10) ^' 18 200905653 may be the same or different, in this case, the value of the CS-Blessing CSB is different. The number of CSA and the number The second compensation message is that the first scan signal and the second compensation signal CSB are "SS, the brother 1 compensation signal CSA number CSA and the second compensation signal CSB system ^ ^ tiger. The first compensation signal ss The system is a high level, and the phase of the first knife is another 1"', a low level, the first - sweep first - compensation minus CSA and the second compensation ^ money SS and please refer to Figure 5 and Figure 6, The phase of the two SBs is opposite. In the case where the pixel structure 211·^2 is applied, the plane display device SL, the data line driver-compensation=channel CL1, and the second sub-compensation circuit CL2 are electrically connected. The driving method is as follows: At a time T, the second gate G2 of the first thin film transistor and the second gate G2 of the thin film Q2 are respectively received by the iv, iv, and according to the first sweep = SS. #通And separately receiving the data signal, and the data signal is respectively charging the first-equivalent capacitor CA and the second equivalent capacitor (3) to generate the difference value - The voltage V3 and the second pixel voltage V4. At this time, the T'-compensation capacitor receives the first compensation signal CSA, and the second compensation capacitor C8 receives the second compensation signal (10), and the second compensation signal CSA The first equivalent capacitor _ K first compensation signal CSB is compensated by the second compensation capacitor c8 Ningdi = equivalent capacitance CB through the first compensation capacitor C7. The second field scan signal SS stops feeding the first film At the time of transistor Q1 and film transistor Q2, 'the first compensation signal CSA and the second compensation 19 200905653 compensation signal CSB are gradually raised from the low level to the level, the ancient equivalent capacitance CA and the second, etc. The effective capacitance CB is compensated by the change of the -signal CSA and the second compensation signal CSB to compensate for the parasitic capacitance effect, so as to eliminate the problem that the voltage value of the first halogen voltage V4 is lowered, and thus improve Please refer to FIG. 7 , the full method of the preferred embodiment of the present invention is applied to the planar display of the second preferred embodiment (as shown in FIG. 5 and FIG. 6 ), and the flat display device 2 The system has no panel 'and the flat display panel has a complex number The pixel structure buckle is in the ^== crane method system (4) the halogen structure 211 (as shown in Fig. 5, the halogen structure 211 of the present embodiment has the same as the second preferred I::: halogen structure 211 described above. The composition, characteristics and effects are therefore not described here. When the == is shown in FIG. 7 , the pixel driving in the embodiment includes steps S11 to S12. In step S11, the first thin film transistor Q1 is at the time of '1 ** _ ^ ^ ^ And the first: the crystal Q 2 system receives and according to the first scan signal ss, in order to receive the data signal. ^ In step S12, 'this time' the first compensation capacitor c7 receives = SB signal CSA, the second compensation The capacitor C8 receives the detailed pixel driving method in the second compensation signal, which is described in detail in the second preferred embodiment, and therefore will not be further described herein. 20 200905653 In summary, according to the present invention The flat display device, the halogen structure, and the halogen driving method are electrically connected to the first scan line driving circuit and the data line driving circuit by the first thin film transistor and the second thin film transistor of the halogen structure, respectively. An equivalent capacitance is electrically connected to the first thin film transistor and the first compensation capacitor, and the second equivalent capacitance is electrically connected to the second thin film transistor and the second compensation capacitor, respectively, and the first compensation capacitor and the first The two compensation capacitors are electrically connected to the compensation circuit respectively. Compared with the prior art, the pixel structure of the flat display device of the present invention increases the first compensation capacitor and the second compensation capacitor, and is electrically connected to the compensation loop respectively. In this way, not only the compensation loop can be used. The compensation signal compensates the first equivalent capacitor and the second equivalent capacitor respectively through the first compensation capacitor and the second compensation capacitor, thereby avoiding parasitic capacitance effects of the first equivalent capacitor and the second equivalent capacitor, and eliminating 昼The voltage of the elemental structure has a voltage drop problem, thereby improving the flickering phenomenon of the facet and improving the display quality of the flat display device. The above description is merely exemplary and not limiting. Any without departing from the spirit of the present invention The scope of the invention should be included in the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a plan view showing a flat display device according to a first preferred embodiment of the present invention. 2 is a schematic view showing a planar display panel of a flat display device according to a first preferred embodiment of the present invention; FIG. The waveforms of the first scan signal and the compensation signal of the first preferred embodiment of the first preferred embodiment are not intended for the first time, the second time and the third time; FIG. 4 is a view showing a preferred embodiment of the present invention. FIG. 5 is a schematic diagram showing a planar display panel of a flat display device according to a second preferred embodiment of the present invention; FIG. 6 is a view showing a second structure according to the present invention; A waveform diagram of a first scan signal, a first compensation signal, and a second compensation signal in a pixel driving method of a preferred embodiment; and FIG. 7 is a flow chart showing another pixel driving method according to a preferred embodiment of the present invention. Fig. [Description of main component symbols] 1, 2: Flat display device 11: Flat display panel 111, 211: Alizarin structure CA: First equivalent capacitance CB · Second equivalent capacitance CL: Compensation circuit CL1: First Subcompensation loop CL2: second subcompensation loop C1: first parasitic capacitor C2: first liquid crystal capacitor C3: first storage capacitor 22 200905653 C4 second parasitic capacitor C5 苐 two liquid crystal capacitor C6 second storage Capacitor C7 First compensation capacitor C8 Second compensation capacitor cs Compensation signal CS1: First sub-compensation signal CS2: Second sub-compensation signal CS3: Third sub-compensation signal DL: Data line drive circuit D1: First and extreme D2: Second drain G1: first gate G2: second gate Q1: first thin film transistor Q2: second thin film transistor SL first scan line drive circuit SI: first source S2 second source ss A scan signal SSI: first sub-scan signal SS2: second sub-scan signal T: time T1 first time 200905653 Τ2: second time Τ3: third time VI, V3: first pixel voltage V2, V4: second Alizarin voltage VC: common voltage VS1, VS2: storage voltage S01-S04, S11-S12: step 24 of the halogen driving method