200905655 九、發明說明 【發明所屬之技術領域】 本發明是例如有關光電裝置、半導體裝置 及具備該裝置的電子機器。 【先前技術】 近年來，在顯示裝置上，特別是在使用薄 液晶顯示裝置中搭載光感測器機能的技術之開 (例如專利文獻1)。搭載光感測器的目的，可: 定外光來調整亮度等，而謀求消費電力低減· (2)測定背光調整亮度或色度，（3)辨識手指写 pen)的位置作爲觸控鍵使用等3個。光感測器 晶體、PIN(p-intrinsic-n)二極體、PN 二極體 光部爲矽薄膜，爲了使製造上的成本不増大， 成顯示的開關元件之矽薄膜同一製造工程來製 電晶體、PIN二極體、PN二極體等來構成光 流至感測器的電流是形成按照所照射的光的照 光電流與以感測器的絶對温度的指數函數來増 的和。因此，爲了即是在比較的高温下也能取 度，必須有效地除去此熱電流。因此’有時配 考（reference)用之被遮光的遮光感測器、及未 光感測器。 此時，就（1 )·( 3 )的目的而言’必須以背光 入感測器的方式，將與外光射入側呈相反的側 、顯示裝置 膜電晶體的 發正進行著 箏（1)藉由測 畫質提升， β 光筆（light 可舉薄膜電 等。皆是受 而使用與構 造。以薄膜 感測器時， 度而變化的 大的熱電流 得正確的照 置熱電流參 被遮光的受 的光不會進 予以遮光。 -4- 200905655 針對（1)的目的，當光感測器位於顯示裝置的外周部時， 可使用構成模組的金屬框或遮光帶等作爲背光的遮光材’ ，但近年來、基於設計上的制約等，被要求儘可能接近顯 示區域，或在顯示區域的内側設置光感測器。另一方面， 針對（3 )的目的，基於該機能，必須在顯示區域的内側內 藏光感測器。並且，就（2)的目的而言’相反的必須遮蔽 外光，以外光不會影響背光的照度檢出之方式來對光感測 器進行遮光。依照該等的要求，必須在光感測器設置某些 的遮光膜。 [專利文獻1]特開2006- 1 1 8965號公報 【發明內容】 (發明所欲解決的課題） 若將遮光電極·透明電極及光感測器重疊配置，則依 照遮光電極.透明電極的電位，熱電流會變化，因此熱電 流不會被正確地除去。本發明是爲了解決此課題，而提案 一可使賦予遮光電極及透明電極的電位最適化之構造·電 路。 並且，將遮光感測器及受光感測器放置於顯示區域近 邊時，來自顯示區域的光會形成迷光而一部份被照射於受 光感測器及遮光感測器，因此迷光部份的光電流會形成誤 差而被檢測出。而且，在受光感測器與遮光感測器間產生 温度差，熱電流不會形成均一，此熱電流差也會形成誤差 。本發明是在於解決該等的課題，實現具備更精度佳的光 -5- 200905655 電感測器之光電裝置。 (用以解決課題的手段） 本發明之光電裝置的特徵係具備：在第1及第2基板間 夾著光電物質（在實施形態中是向列相液晶材料922)之面 板（在實施形態中是液晶面板9 1 1 )、及對上述面板的上述 第1基板（在實施形態中是主動矩陣基板101)或第2基板（在 實施形態中是對向基板91 2)的面照射光之照明裝置（在實 施形態中是背光單元926、導光板927)、及檢測出周圍的 光照度之光檢測部（在實施形態中是檢測電路360、受光感 測器3 50P及其他）、及按照上述光檢測部的檢測結果來控 制上述照明裝置之照明控制部（在實施形態中是中央運算 電路781、外部電源電路784)， 上述光檢測部係設於上述第1或第2基板，具備： 第1光感測器（在實施形態中是受光感測器3 50P)，其 係被照射外光； 第2光感測器（在實施形態中是遮光感測器3 5 0 D )，其 係被遮斷外光的照射； 第1電極（在實施形態中是背光遮光電極6 1 1 P、透明電 極612P)，其係構成隔著絶緣層來與上述第1光感測器平面 性重疊； 第2電極（在實施形態中是背光遮光電極61 1D、透明電 極6 1 2 D )，其係構成隔著絶緣層來與上述第2光感測器平面 性重疊；及 -6- 200905655 電位施加部（在實施形態中是自己補正電壓電路361) ’其係控制上述第1電極的電位（在實施形態中是配線P B T 的電位VPBT(在實施形態中是3.6V))與上述第2電極的電 位（在實施形態中是配線DBT的電位VDBT(在實施形態中 是 1.4V))。 又’更具體而言，上述電位施加部係控制上述第1及 或第2電極的電位’而使上述第1及或第2光感測器的光電 流量能夠形成大略最大値。 又’更具體而言，上述第1或第2基板係具備形成於上 述基板上的電晶體（在實施形態中是第6N型電晶體N 1 1、 第6P型電晶體P11、第7N型電晶體N21、第7P型電晶體 P2 1 )，上述電位施加部係根據上述電晶體的臨界値電壓（ 在實施形態中是Vth)來控制施加於上述第1及或第2電極 的電位。 本發明之半導體裝置，係形成於基板上的半導體裝置 ，其特徵係具備： 第1光感測器（在實施形態中是受光感測器3 5 0P)，其 係被照射外光； 第2光感測器（在實施形態中是遮光感測器3 50D)，其 係被遮斷外光的照射； 第1電極（在實施形態中是背光遮光電極6 1 1 P、透明電 極6 1 2P)，其係構成與上述第1光感測器平面性重疊； 第2電極（在實施形態中是背光遮光電極6 1 1 D、透明電 極612D)，其係構成與上述第2光感測器平面性重疊；及 200905655 壓 電 正 補 己 自 坛巨 是2m 中第 態述 形上 施及 實極 在電 (> 1 部第 加述 施上 位對 電係 其 ) ΰ 1 湏 6 、 3 感 路光 電 1 第 述 上 加 施 極 器及或第2光感測器的光電流量形成大略最大値的電位（在 實施形態中是配線PBT的電位VPBT(在實施形態中是 3.6V)及配線DBT的電位VDBT(在實施形態中是1.4V))。 以往是上述第1電極的電位與上述第2電極的電位爲相 同，典型的是形成浮動，或連接至模組的GND，在如此 地構成下，可使電位最適化，使第1光感測器與第2光感測 器的熱電流能夠形成相等。 又，更具體而言，上述第1光感測器（在實施形態中是 350P)爲發光二極體（在實施形態中是350P-1)，上述第2光 感測器（在實施形態中是3 5 0D)爲發光二極體（在實施形態 中是 3 50D-1 )， 若將上述第1光感測器的陰極電極（在實施形態中是 350P-1N)與第1電極（在實施形態中是背光遮光電極611P、 透明電極612P)的電位差設爲VI， 將上述第1光感測器的陰極電極（在實施形態中是 3 5 0P-1N)與第1光感測器的陽極電極（在實施形態中是 3 5 0P-1P)的電位差設爲VD1， 將上述第2光感測器的陰極電極（在實施形態中是 350D-1N)與第.2電極（在實施形態中是背光遮光電極611D、 透明電極612D)的電位差設爲V2’ 將上述第2光感測器的陰極電極（在實施形態中是 350D-1N)與第2光感測器的陽極電極（在實施形態中是 200905655 3 50D-1P)的電位差設爲VD2，200905655 IX. Description of the Invention [Technical Field] The present invention relates to, for example, an optoelectronic device, a semiconductor device, and an electronic device including the same. [Prior Art] In recent years, in the display device, in particular, a technique of mounting a photosensor function in a thin liquid crystal display device has been used (for example, Patent Document 1). The purpose of the optical sensor is to adjust the brightness, etc., and to reduce the consumption power. (2) Measure the brightness or chromaticity of the backlight, and (3) recognize the position of the finger writing pen as the touch key. Wait for three. The photo sensor crystal, the PIN (p-intrinsic-n) diode, and the PN diode are made of tantalum film. In order to reduce the cost of manufacturing, the thin film of the switching element of the display is manufactured by the same manufacturing process. The current that constitutes the optical flow to the sensor by the transistor, the PIN diode, the PN diode, or the like is the sum of the illumination current according to the illuminated light and the exponential function of the absolute temperature of the sensor. Therefore, in order to be able to take it at a relatively high temperature, it is necessary to effectively remove this thermal current. Therefore, it is sometimes used as a light-shielding shading sensor and a non-light sensor. At this time, for the purpose of (1)·( 3 ), it is necessary to carry out the splicing of the display device film transistor on the side opposite to the external light incident side by means of backlighting into the sensor ( 1) By measuring the quality of the image, the β-ray pen (light can be used for thin film electricity, etc. It is used and constructed. The large thermal current that changes with the thickness of the film sensor is correct. The light that is blocked by light will not be shielded from light. -4- 200905655 For the purpose of (1), when the light sensor is located on the outer peripheral portion of the display device, a metal frame or a light-shielding tape constituting the module can be used as the backlight. The light-shielding material', but in recent years, based on design constraints, etc., it is required to be as close as possible to the display area, or to provide a light sensor inside the display area. On the other hand, for the purpose of (3), based on the function The light sensor must be hidden inside the display area. And, for the purpose of (2), the opposite side must shield the external light, and the external light does not affect the illumination detection of the backlight to the light sensor. Shading. According to these requirements, It is necessary to provide a certain light-shielding film in the photosensor. [Patent Document 1] JP-A-2006- 1 18965 SUMMARY OF INVENTION [Problems to be Solved by the Invention] When a light-shielding electrode, a transparent electrode, and a light sensor are used According to the potential of the light-shielding electrode and the transparent electrode, the thermal current changes, so that the thermal current is not correctly removed. The present invention has been made to solve the problem, and a potential for imparting a light-shielding electrode and a transparent electrode can be proposed. Optimum structure and circuit. When the light-shielding sensor and the light-receiving sensor are placed near the display area, the light from the display area will be lost and some will be illuminated by the light-receiving sensor and the light-shielding sensor. Therefore, the photocurrent of the faint portion is detected by an error, and a temperature difference is generated between the photodetector and the shading sensor, and the thermal current does not form a uniformity, and the thermal current difference also causes an error. The present invention solves these problems and realizes an optoelectronic device having a more accurate optical-5-200905655 inductive detector. (Means for Solving the Problem) The photovoltaic device of the present invention The fascia includes a panel in which a photoelectric substance (in the embodiment, a nematic liquid crystal material 922) is interposed between the first and second substrates (in the embodiment, the liquid crystal panel 9 1 1 ), and the above-described panel An illumination device that illuminates the surface of the first substrate (the active matrix substrate 101 in the embodiment) or the second substrate (the opposite substrate 91 2 in the embodiment) (in the embodiment, the backlight unit 926 and the light guide plate 927) And a light detecting unit that detects the surrounding illuminance (in the embodiment, the detecting circuit 360, the light receiving sensor 350P and the like), and the lighting control unit that controls the lighting device according to the detection result of the light detecting unit (In the embodiment, the central processing circuit 781 and the external power supply circuit 784), the photodetecting unit is provided on the first or second substrate, and includes: a first photosensor (in the embodiment, a photodetector) 3 50P), which is irradiated with external light; a second photosensor (in the embodiment, a light-shielding sensor 350D), which is blocked by external light; the first electrode (in the embodiment) Medium backlighting electrode 6 1 1 P, transparent The electrode 612P) is formed to be planarly overlapped with the first photosensor via an insulating layer, and the second electrode (in the embodiment, the backlight shading electrode 61 1D and the transparent electrode 6 1 2 D) is configured. The second photosensor is planarly overlapped with the insulating layer; and -6-200905655 potential applying unit (in the embodiment, the self-correcting voltage circuit 361) is configured to control the potential of the first electrode (in the implementation) In the form, the potential VPBT (3.6 V in the embodiment) of the wiring PBT and the potential of the second electrode (in the embodiment, the potential VDBT of the wiring DBT (1.4 V in the embodiment)). Further, more specifically, the potential application unit controls the potential of the first and second electrodes to cause the photoelectric flow rate of the first or second photosensor to be substantially maximal. Further, more specifically, the first or second substrate includes a transistor formed on the substrate (in the embodiment, the sixth N-type transistor N 1 1 , the sixth P-type transistor P11, and the 7-N-type battery) In the crystal N21 and the seventh P-type transistor P2 1 ), the potential application unit controls the potential applied to the first or second electrode based on the critical threshold voltage (Vth in the embodiment) of the transistor. A semiconductor device according to the present invention is a semiconductor device formed on a substrate, characterized by comprising: a first photosensor (in the embodiment, a photodetector 3500P), which is irradiated with external light; The photo sensor (in the embodiment, the light-shielding sensor 350D) is configured to block the irradiation of the external light; the first electrode (in the embodiment, the backlight-shielding electrode 6 1 1 P, the transparent electrode 6 1 2P) The structure of the first photosensor overlaps with the first photosensor; the second electrode (in the embodiment, the backlight shading electrode 6 1 1 D, the transparent electrode 612D), and the second photosensor Planar overlap; and 200,905,655 Piezoelectric positive self-supporting giant is 2m in the first state of the description of the application of the real pole in the electricity (> 1 part of the application of the upper position to the electric system) ΰ 1 湏6, 3 sense In the first embodiment, the photoelectric flow rate of the upper application electrode or the second photo sensor forms a potential of substantially the maximum 値 (in the embodiment, the potential VPBT of the wiring PBT (3.6 V in the embodiment) and the wiring DBT The potential VDBT (1.4V in the embodiment)). Conventionally, the potential of the first electrode is the same as the potential of the second electrode, and is typically formed floating or connected to the GND of the module. With such a configuration, the potential can be optimized to make the first light sensing. The thermal current of the device and the second photo sensor can be equalized. More specifically, the first photosensor (350P in the embodiment) is a light-emitting diode (350P-1 in the embodiment), and the second photosensor (in the embodiment) 305 is a light-emitting diode (3 50D-1 in the embodiment), and the cathode electrode (350P-1N in the embodiment) and the first electrode of the first photosensor are In the embodiment, the potential difference between the backlight light-shielding electrode 611P and the transparent electrode 612P) is VI, and the cathode electrode of the first photosensor (in the embodiment, 305P-1N) and the first photosensor are used. The potential difference of the anode electrode (in the embodiment, 550P-1P) is VD1, and the cathode electrode of the second photosensor (350D-1N in the embodiment) and the second electrode (in the embodiment) The potential difference between the backlight light-shielding electrode 611D and the transparent electrode 612D) is V2'. The cathode electrode of the second photosensor (350D-1N in the embodiment) and the anode electrode of the second photosensor (at In the embodiment, the potential difference of 200905655 3 50D-1P) is set to VD2,
則丨V1-V2|<|VD1| 且 |V1-V2|<|VD2|，更理想是丨V1-V2|<1V 〇 藉由如此地設定電位，第1光感測器與第2光感測器的 熱電流的差異幾乎可無視。 更提案 V1=0V、V2 = 0V、V1=VD1、V2 = VD2的其中之 一的半導體裝置。亦即，藉由連接第1光感測器的陰極電 極.源極電極.陽極電極.汲極電極的其中之一與第1電極或 第2光感測器的陰極電極.源極電極.陽極電極.汲極電極的 其中之一與第2電極，幾乎可消去第1光感測器與第2光感 測器的熱電流的差異，且可使配線數形成最低限度。 在此，本發明所提案之半導體裝置中，所謂第1電極 爲遮住光的第1遮光電極（在實施形態中是背光遮光電極 611P)，所謂第2電極爲遮住光的第2遮光電極（在實施形態 中是背光遮光電極611D)，及，所謂第1電極爲不遮光的第 1透明電極（在實施形態中是透明電極612P)，所謂第2電極 是不遮光的第2透明電極（在實施形態中是透明電極612D) ，以及所謂第1電極爲用以遮住光的第1遮光電極及不遮光 的第1透明電極，第2電極爲用以遮住光的第2遮光電極及 不遮光的第2透明電極。 在重疊如此遮住來自多餘方向的光之遮光電極、及一 面使來自射入方向的光透過一面作爲電磁雜訊屏蔽的機能 之透明電極、及光感測器時，如前述般設定電位，便不使 檢出精度降低。 -9- 200905655 又’本發明所提案之半導體裝置中，上述第1遮光電 極與第2遮光電極係於其間形成有未被形成遮光電極的遮 光電極間隙區域，在與上述遮光電極間隙區域重疊的區域 形成有非透明性的間隙遮光體。 爲了如此在第1遮光電極及第2遮光電極施加各別的電 位，必須在遮光電極設置遮光電極間隙區域，但背光的光 會從此間隙射入，在玻璃或介電體的表面引起多重散亂而 形成迷光，一旦射入第1光感測器或第2光感測器，則檢出 精度會降低。 於是’在與遮光電極間隙區域重疊的區域形成非透明 性的間隙遮光體，藉此以間隙遮光體來吸収自遮光電極間 隙區域射入的光，可避免如此的精度降低。 又，本發明所提案之半導體裝置中，上述第1遮光電 極與第2遮光電極係於其間有未被形成遮光電極的遮光電 極間隙區域（在實施形態中是6 1 1 G )，上述第1透明電極與 上述第2透明電極係於其間有未被形成透明電極的透明電 極間隙區域（在實施形態中是6 1 2 G )，上述遮光電極間隙區 域與上述透明電極間隙區域係於上述基板的鉛直方向上形 成互相不重疊。 爲了如此地施加各別的電位，分別在遮光電極及透明 電極需要遮光電極間隙區域及透明電極間隙區域，但若電 磁雜訊從該等的間隙進入’則感測器的檢出精度會降低。 於是若以上述遮光電極間隙區域與上述透明電極間隙 區域不會互相重疊的方式配置，則其中之一的電極可屏蔽 -10- 200905655 從各個的間隙進入的電磁雜訊，因此相較於使上述遮光電 極間隙區域及上述透明電極間隙區域形成於同位置時，精 度會提升。 又，本發明所提案之半導體裝置中，上述第1遮光電 極與上述第1透明電極爲同一電位，上述第2遮光電極與上 述第2透明電極爲同一電位。 若取如此的構成，則因爲可使用同一配線來供給施加 於遮光電極及透明電極的電位，所以配線數·實裝端子數· 電路面積可節約。又，因爲遮光電極及透明電極的總電容 變大，所以電磁屏蔽性會提升。 又，本發明所提案之半導體裝置中，上述電位施加部 係具備由電晶體所構成的自己補正電壓電路，上述自己補 正電路係構成可輸出對應於上述電晶體的臨界値電壓而變 化的電壓，上述輸出係連接至上述第1電極及或上述第2電 極。 最能取得光電流的遮光電極或透明電極的最適電位的 製造不均是與在同一半導體裝置上形成電晶體時，電晶體 的臨界値電壓（Vth)的製造不均有關，因此若使用輸出對 應於電晶體的臨界値電壓而變化的電壓之自己補正電壓電 路，則即使有製造不均，還是可經常將最適電位施加於遮 光電極或透明電極。 又，本發明的特徵係上述第1光感測器及上述第2光感 測器爲使用薄膜多晶矽的PIN接合二極體或PN接合二極 體。 -11 - 200905655 如此的二極體雖具有在使用多晶矽薄膜電晶體的半導 體裝置上可無製造上的追加工程形成之優點，但熱電流對 光電流的比要比單結晶晶圓上所形成的光電感測器類更大 ，且熱電流容易依照藉由平面性重疊的電極所被施加的電 位而變動，因此適於適用本發明。 又’本發明之光電裝置，係具備：形成有在第1及第2 基板間夾著光電物質（在實施形態中是向列相液晶材料 9 2 2)而成的顯示區域之面板（在實施形態中是液晶面板 9 1 1 )、及檢測出上述面板的周圍光的照度之光檢測部（在 實施形態中是檢測電路3 6 0、受光感測器3 5 0 P及其他）， 其特徵爲： 上述光檢測部係設於上述第1或第2基板的上述顯示區 域周緣部，具備： 第1光感測器（在實施形態中是受光感測器3 5 0 P )，其 係被照射外光；及 第2光感測器（在實施形態中是遮光感測器3 5 0 D )，其 係被遮斷外光的照射， 上述第1光感測器與第2光感測器係複數配置於上述顯 示區域周緣部。 若如此地配置，則可防止因手指或小的陰影造成檢測 結果顯著變化的同時，可防止因裝置内的温度分布所引起 之熱電流差所造成的精度降低。 又，本發明之光電裝置中，具備對上述面板的顯示區 域照射光的光源（在實施形態中是背光單元926)，上述光 -12- 200905655 源係於顯示區域周緣部，被配置於未配置有上述第1光感 測器與第2光感測器的邊。 若如此地構成，則因爲可極力縮小光源的温度梯度所 產生之上述第1光感測器與上述第2光感測器間的熱電流的 差異，所以可精度佳地將熱電流予以除外。 又，本發明之光電裝置中，上述第1光感測器與上述 第2光感測器係互相交替配置。 若如此地配置，則即使在顯示裝置内有温度分布，遼 是會因爲第1光感測器與第2光感測器的平均温度沒有大的 差異，所以可更精度佳地將熱電流予以除外。 又，本發明之光電裝置中，上述第1光感測器與隣接 配置的上述第2光感測器係彼此來自上述顯示區域的境界 邊（在實施形態中是表示顯示區域3 1 0的境界邊的點線）的 距離大略相等。 若如此地配置，則因爲來自顯示區域的光在玻璃基板 或絶緣膜的界面被多重反射而產生的所謂迷光會在第1光 感測器及第2光感測器被均等地照射，所以藉由去掉第1光 感測器與第2光感測器的電流差，不會發生迷光所造成的 精度降低。 又，本發明之光電裝置中，爲了對上述第1光感測器 照射上述面板的周圍光’而將設於第1或第2基板的複數的 開口部（在實施形態中是受光開口部990- 1〜990- 1 0)大小形 成：與配置有上述開口部的顯示區域周緣部的境界邊平行 的方向爲〇.5mm以上且20mm以下的範圍、且與配置有上 -13- 200905655 述開口部的上述顯示區域周緣部的境界邊正交的方向爲 0.05mm以上且上述對向基板的厚度以下。 若如此地設定開口部，則迷光少，且因裝置内的温度 分布所引起的熱電流差亦小，所以可防止精度降低。 又，本發明之光電裝置中，上述複數的開口部係於上 述顯示區域周緣部，具備：被配置於與配置有上述光源的 配置邊對向的邊之第1開口部（在實施形態中是受光開口部 990-1〜990-6)、及被配置於與配置邊大略正交的邊之第2 開口部（在實施形態中是受光開口部99 0-7〜990-1 0)，上述 第1開口部的開口面積係比上述第2開口面積更大。 又，依開口部的配置場所而温度梯度有所差異時，温 度梯度越大則只要縮小開口部的大小便可降低温度梯度的 影響。更具體而言是在上述顯示區域的四邊中接近上述第 1開口部的邊與接近上述第2開口部的邊爲相異的顯示裝置 。越是温度梯度大的邊越是縮小開口部的大小即可。 又，本發明係提案使用該等的半導體裝置之顯示裝置 。藉此，無製造成本的上昇，使設於顯示裝置上的光電感 測器的温度依存性提升，可不受温度左右進行配合外光環 境的顯示設定，光電感測器的配置位置也可非常接近顯示 區域。 又’本發明係提案使用該等的顯示裝置之電子機器。 藉此’例如在數位相機、行動電話、PDA(Pers〇nal Digital Assistant)等的電子機器中，因爲內藏不靠温度精度佳的 光感測器，所以可容易配合外光來控制背光，沒有使消費 -14 - 200905655 電力無意義地増大的情況，成本也不會上昇。又，由於可 在顯示區域附近配置光電感測器，因此設計的自由度也會 提升。 【實施方式】 以下，根據圖面來說明有關本發明的光電裝置、半導 體裝置、顯示裝置及具備彼之電子機器的實施形態。 [第1實施形態] 圖1是本實施例的液晶顯示裝置9 1 0的立體構成圖（一 部份剖面圖）。液晶顯示裝置910是具備：藉由密封材923 以一定的間隔來貼合主動矩陣基板1 0 1與對向基板9 1 2，夾 持向列相液晶材料9 2 2的液晶面板9 1 1。在主動矩陣基板 1〇1上雖未圖示，但實際塗佈有由聚醯亞胺等所構成的配 向材料，經面磨處理而形成配向膜。並且，對向基板912 是形成有未圖示對應於畫素的彩色濾光片、及防止光漏， 使對比（contrast)提升的低反射·低透過率樹脂所構成的黑 矩陣940、及與主動矩陣基板101上的對向導通部330-1〜 3 3 0-2短路被供給共通電位之IT0膜的對向電極93 0。在與 向列相液晶材料922接觸的面是塗佈有由聚醯亞胺等所構 成的配向材料，在與主動矩陣基板1〇1的配向膜的面磨處 理的方向正交的方向進行面磨處理。 更分別在對向基板9 1 2的外側配置上偏光板924，在主 動矩陣基板1 0 1的外側配置下偏光板925，以彼此的偏光方 -15- 200905655 向能夠正交的方式（正交偏光狀）配置。更在下偏光板92 5 下配置有背光單元926及導光板927，從背光單元926往導 光板927照射光’導光板927是以使來自背光單元926的光 能夠往主動矩陣基板1〇1形成垂直且均一的面光源之方式 使光反射折射而具有作爲液晶顯示裝置9 1 0的光源之機能 。背光單元926是在本實施例爲LED單元，但亦可爲冷陰 極燈管（CCFL(Cold Cathode Fluorescent Lamp))。背光單 元92 6是經由連接器929來連接至電子機器本體，供給電源 ，就本實施例而言是具有在電源被調整成適宜適切的電流 •電壓下調整來自背光單元926的光量之機能。 雖未圖示，但更亦可因應所需，以外殻來覆蓋周圍， 或在上偏光板924的更上面安裝保護用的玻璃或壓克力板 ，或爲了改善視野角，而貼上光學補償薄膜。 並且，在液晶顯示裝置9 1 0的外周部設有光感測器受 光開口部990。而且，主動矩陣基板101設有從對向基板 9 12突出的突出部102，在位於該突出部102的信號輸入端 子320是安裝有FPC(可撓性基板）928且被電性連接。FPC( 可撓性基板）92 8是被連接至電子機器本體，供給必要的電 源、控制信號等。 更在液晶顯示裝置9 1 0上設有6個的光感測器的受光開 口部990-1〜990-6。此受光開口部990-1〜990-6是藉由部 份地除去對向電極9 3 0上的黑矩陣9 4 0來形成，使外部的光 能夠到達主動矩陣基板101上。各受光開口部990-1〜990-6的周圍是對向電極93 0上的黑矩陣940不被除去，使外光 -16- 200905655 不會到達主動矩陣基板101上。 圖2是主動矩陣基板101的方塊圖。在主動矩陣基板 101上，480條的掃描線201-1〜201-480與1920條的資料線 202-1〜202-1920會正交形成，480條的電容線203-1〜203-480是與掃描線201-1〜20 1 -480並行配置。電容線203 - 1〜 203 -48 0是相互短路，與共通電位配線3 3 5連接，更與2個 的對向導通部330-1〜330-2連接，由信號輸入端子320賦 予0V-5V的反轉信號、反轉時間爲35μ秒的共通電位。掃 描線201-1〜20 1 -48 0是被連接至掃描線驅動電路301，且 資料線202- 1〜202- 1 920是被連接至資料線驅動電路3 02， 分別適當地被驅動。 又，掃描線驅動電路3 0 1、資料線驅動電路3 02是從信 號輸入端子3 20供給驅動所必要的信號。信號輸入端子32〇 是被配置於突出部102上。另一方面，掃描線驅動電路301 、資料線驅動電路3 02是被配置於與對向基板912重疊的區 域、亦即突出部102外。掃描線驅動電路301、資料線驅動 電路3 02是藉由低温多晶矽TFT製程’利用在主動矩陣基 板上集成驅動所必要的電路機能之玻璃上系統（SOG : System On Glass)技術，在主動矩陣基板上集成多晶矽薄 膜電晶體而形成，以和後述的畫素開關元件401-n-m同一 工程來製造所謂的驅動電路內藏型的液晶顯示裝置。 並且，在與6個的受光開口部990-1〜990-6平面性重 疊的區域分別形成有6個的受光感測器350P-1〜3 50P-6 ’ 且以能夠與其交替的方式形成有6個的遮光感測器3 5 0D-1 -17- 200905655 〜3 50D-6。此受光感測器3 5 0P-1〜3 5 0P-6及遮光感測器 350D-1〜350D-6亦藉由玻璃上系統技術來形成於主動矩陣 基板上。如此在玻璃基板上以和畫素開關元件4 0 1 - η - m同 一工程來製造，可降低製造成本。 受光感測器35〇Ρ-1〜350P-6是與受光開口部990-1〜 9 9 0 - 6平面性重疊，外光會到達感測器，但遮光感測器 350D-1〜350D-6是不與受光開口部990-1〜990-6平面性重 疊，外光是在對向電極93 0上的黑矩陣940被吸収幾乎不到 達。受光感測器3 5 0P-1〜3 5 0P-6是與配線PBT、配線VSH 、配線SENSE連接’遮光感測器3 5 0D-1〜3 5 0D-6是與配 線DBT、配線VSL、配線SENSE連接。該等的配線PBT 、配線VSH、配線SENSE、配線DBT、配線VSL是被連 接至檢測電路360。檢測電路360是變換成對應於具有與來 自受光感測器350P-1〜350P-6及遮光感測器350D-1〜 3 5 0 D - 6的外光照度相關的輸出類比電流之脈衝長的二値輸 出信號OUT，輸出至信號輸入端子320。並且’配線 VCHG、配線RST、配線VSL、配線VSH亦經由信號輸入 端子320來供給至檢測電路360。 詳細如後述，受光感測器3 5 0P-1〜3 5 0P-6是與背光遮 光電極611P-1〜611P-6平面性重疊’遮光感測器以015-1〜 350D-6是與背光遮光電極611D-1〜611D-6平面性重疊’各 來自背光的光是被遮蔽，所以構成不會有因來自背光的光 而造成外光的檢出精度降低之情況。並且’受光感測器 350P-1〜350P-6與透明電極612P-1〜612P-6重疊’遮光感 -18- 200905655 測器350D-1〜350D-6與透明電極612D-1〜612D-6’不會 有因爲在驅動顯示區域310(點線是表示顯示區域31〇的境 界邊）時所發生的電磁雜訊而造成檢出精度降低之情況。 藉由該等的構成，即使受光感測器350P-1〜350P-6及遮光 感測器3 5 0D-1〜3 5 0D-6配置於顯示區域310附近，檢出精 度也不會降低，因此比起以往的製品，設計的自由度會提 升。 在此，有關受光開口部990- 1〜990-6是如本實施例所 示，最好分割成複數，儘可能使廣範圍分散配置。例如若 考量即使手指等的陰影部份地覆蓋液晶顯示裝置9 1 〇上’ 還是可減少對外光檢出的影響，則最好受光開口部的總面 積是儘可能廣，但若將面積廣的受光感測器集中於一處， 則不得不使與遮光感測器的距離分開，在液晶顯示裝置 910内形成温度分布，因此在受光感測器部及遮光感測器 部產生平均温度差。於是，如本實施例那樣將感測器分割 成幾個’更理想是若交替配置，則可使受光感測器部與遮 光感測器部的平均温度大致相等。就本實施例而言是6分 割，但當然亦可更少或更多。 又，此時，以從各受光開口部990-1〜990-6的端部到 顯示區域310爲止的距離能夠形成相等的方式來配置爲佳 。同樣以從各受光感測器3 5 0P-1〜3 5 0P-6、各遮光感測器 3 5 0D-1〜3 5 0D-6到顯示區域310爲止的距離能夠形成相等 的方式來配置爲佳。爲了從顯示區域310往外部顯示而透 過的光是例如在構成主動矩陣基板1 〇 1或對向基板9 1 2的玻 -19- 200905655 璃或上偏光板924的表面或各種絶緣膜的界面等被多重反 射，雖一部份的迷光會進入各光感測器，但此時，若如上 述般配置，則因爲在各受光感測器3 50P-1〜3 5 0P-6、各遮 光感測器3 5 0D-1〜3 50D-6間，迷光的光量會大致成一定， 所以如本實施例那樣若去掉各受光感測器3 5 0P-1〜3 5 0P-6 與各遮光感測器3 50D-1〜3 5 0D-6間的電流差分，則迷光部 份可大致除去。由此觀點也是一旦受光開口部990- 1〜 990-6被分割成複數，儘可能使廣範圍分散配置，則不易 被顯示區域310的顯示圖案影響。 又’各受光感測器3 50P-1〜3 5 0P-6、各遮光感測器 350D-1〜350D_6是如本實施例所示與背光單元926儘可能 配置於遠的邊。這是因爲背光單元926不管是LED或是 CCFL皆會形成熱源，所以越接近背光單元926，在主動矩 陣基板101内熱梯度會越變大，在各受光感測器35 0Ρ-1〜 350P-6、各遮光感測器350D-1〜350D-6之間容易形成温度 差。 又，有關受光開口部990-1〜990-6的大小，是若在與 配置有該受光開口部990_1〜990_6的顯示區域31〇的周緣 部的境界邊平行的方向（以下設爲X方向）增大，則會受到 温度分布或迷光的影響。又，若在與顯示區域31〇的境界 邊正父的方向（以下設爲γ方向）增大，則框緣區域會變大 液晶顯示裝置9 1 0的外形大小會變大，而且在對向基板 912與上偏光板924的界面被反射之顯示區域31〇的光會成 爲迷光強射於各受光感測器3 5 〇 p _ i〜3 5 〇 p _ 6、各遮光感測 -20- 200905655 器350D-1〜350D-6，形成測定誤差的要因。另一方面，若 在X方向太小，則配置效率會變差，P IN二極體的通道寬 (W)會變小，若在Y方向縮小，則光的取入效率會變差， 對檢出精度產生影響。檢討以上的條件結果，結論是在X 方向爲0.5mm〜20mm，在Y方向是從0.05mm起之對向基 板912的板厚（在本實施例是0.6mm)的範圍内爲佳。根據以 上，本實施例是 X方向設定成10mm、Y方向設定成 0.3 m m的大小。 又，從受光開口部990- 1〜990-6的端部到顯示區域 310爲止的距離是0.5mm。 受光感測器350P-1〜350P-6與遮光感測器350D-1〜 3 5 0D_ 6會以10mm間距來交替配置，而使受光開口部990-1 〜990-6的配置間距爲20mm，且受光感測器350P-1與遮光 感測器3 5 0D-1的間距爲l〇mm，遮光感測器3 50D-1的間距 與受光感測器3 50P-2的間距亦爲l〇mm。 圖3是在圖2的點線310部所示的顯示區域的第m個的 資料線2 〇 2 - m與第η個的掃描線2 〇 1 _ n的交叉部附近的電 路圖。在掃描線2 0 1 - η與資料線2 0 2 - m的各交點形成有由 N通道型場效多晶矽薄膜電晶體所構成的畫素開關元件 40 1-n-m，該閘極電極是被連接至掃描線2〇1_n ,源極.汲 極電極是分別被連接至資料線202-m與畫素電極402-n-m 。畫素電極402-n-m及被短路成同—電位的電極是形成電 容線203-n與輔助電容電容器4〇3-n-m，且作爲液晶顯示裝 置組裝時，夾著液晶元件而與對向電極9 3 0 (共通電極）形 -21 - 200905655 成電容器。 圖4是表示在本實施例的電子機器的具體構成的方塊 圖。液晶顯示裝置9 1 0是圖1所説明的液晶顯示裝置，外部 電源電路784、影像處理電路780會經由FPC(可撓性基板 )9 2 8及連接器9 2 9來將必要的信號及電源供給至液晶顯示 裝置910。中央運算電路781是經由外部i/f電路782來取 得來自輸出入機器783的輸入資料。在此，所謂輸出入機 器7 8 3是例如鍵盤、滑鼠、軌跡球、l E D、喇叭、天線等 。中央運算電路781是根據來自外部的資料進行各種運算 處理，將結果作爲命令來轉送至影像處理電路7 8 〇或外部 I/F 電路 7 82。 影像處理電路780是根據來自中央運算電路781的命令 更新影像資訊’變更往液晶顯示裝置9 i 〇的信號，藉此液 晶顯不裝置9 1 0的顯示影像會變化。並且，來自液晶顯示 裝置910上的檢測電路36〇的二値輸出信號out會經由 FPC(可撓性基板）928來輸入至中央運算電路781，中央運 算電路781會將二値輸出信號out的脈衝長變換成所對應 的離散値。其次’中央運算電路781會對由EEPROM( Electronically Erasable and Programmable Read Only Memory)所構成的參照表785進行存取，將變換後的離散 値再變換成對應於適當的背光單元9 2 6的電壓之値，且傳 送至外部電源電路784。外部電源電路784是經由連接器 929來供給對應於該被傳送的値之電壓的電位電源至液晶 顯示裝置910内的背光單元926。背光單元926的亮度是依 -22- 200905655 照由外部電源電路7 8 4所供給的電壓來變化’因此液晶顯 示裝置910的全白顯示時亮度也會變化。在此所謂電子機 器，具體而言是監視器、TV、筆記型電腦、PDA、數位相 機、攝影機、行動電話、攜帶型圖片瀏覽器、攜帶型影像 播放器、攜帶型DVD播放器、攜帶型音樂播放器等。 另外，本實施例是藉由電子機器上的中央運算電路 78 1來控制背光單元926的亮度，但例如亦可設爲在液晶顯 示裝置910内具有驅動器1C及EEPROM的構成，使該驅 動器1C具有從二値輸出信號OUT往離散値的變換機能、 參照EEPROM的再變換機能、往背光單元926之輸出電壓 的調整機能。又，亦可構成不使用參照表，藉由數値計算 來從離散値再變換成對應於背光單元926的電壓之値。 圖5是表示在圖3所示的畫素顯示區域的電路圖的實際 構成的平面圖。如圖5的凡例所示，各掛網的相異部位是 分別顯示相異的材料配線，以同掛網顯示的部位是表示同 材料配線。由鉻薄膜（Cr)、多晶矽薄膜（Poly-Si)、鉬薄膜 (Mo)、鋁·鈸合金薄膜（AINd)、氧化銦.錫薄膜（Indium Tin 〇xiced = ITO)的5層薄膜所構成，在各個的層間形成有氧化 矽、氮化矽、有機絶緣膜的其中之一或積層該等的絶緣膜 〇 具體而言，鉻薄膜（Cr)是膜厚lOOnm，多晶矽薄膜 (Poly-Si)是膜厚50nm，鉬薄膜（Mo)是膜厚2 00nm，鋁·钕 合金薄膜（AINd)是膜厚5 00nm，氧化銦.錫薄膜（ιτο)是膜 厚100nm。並且，在鉻薄膜（Cr)與多晶矽薄膜（p〇iy_Si)之 -23- 200905655 間形成有積層lOOnm的氮化矽膜與100nm的氧化矽膜之底 層絶緣膜，在多晶矽薄膜（Poly-Si)與鉬薄膜（Mo)之間形成 有由1 OOnm的氧化矽膜所構成的閘極絶緣膜，在鉬薄膜 (Mo)與鋁·銨合金薄膜（AINd)之間形成有積層200nm的氮 化矽膜與5 OOnm的氧化矽膜之層間絶緣膜，在鋁·鈦合金 薄膜（AINd)與氧化銦·錫薄膜（ITO)之間形成有積層200nm 的氮化矽膜與平均Ιμπι的有機平坦化膜之保護絶緣膜，將 彼此的配線間予以絶緣，在適當的位置開啓接觸孔彼此連 接。另外，在圖5中是鉻薄膜（Cr)圖案不存在。 如圖5所示，資料線202-m是藉由鋁·銨合金薄膜 (AINd)所形成，經由接觸孔來連接至畫素開關元件401-n-m的源極電極。掃描線20 1-η是以鉬薄膜（Mo)所構成，兼 作爲畫素開關元件401-n-m的閘極電極用。電容線203 -η 是由與掃描線201-η同配線材料所構成，畫素電極402-n-m 是由氧化銦·錫薄膜所構成’經由接觸孔來連接至畫素開 關元件401-n-m的汲極電極。並且，畫素開關元件401-n-m的汲極電極亦被連接至被高濃度摻雜磷之n +型多晶矽 薄膜所構成的電容部電極605 ’與電容線203 -n平面性地 重疊來構成輔助電容電容器403_n-m。 圖6是用以說明畫素開關元件40 1 -n-m的構造之對應 於圖5的A-A4泉部的液晶顯示裝置910的一部份的剖面構 造。另外，爲了容易看圖’而縮小比例不一定。主動矩陣 基板1 〇 1是由無鹼玻璃所構成之厚度〇. 6mm的絶緣基板， 在其上經由積層2〇〇nm的氮化矽膜與300nm的氧化矽膜之 -24- 200905655 底層絶緣膜來配置有由多晶矽薄膜所構成的矽島602，掃 描線20 1-η是與矽島602夾著前述的閘極絶緣膜來配置於 上方。 在與掃描線201-η重疊（overlap)的區域是矽島602爲磷 離子完全或僅低濃度摻雜的固有半導體區域6021，其左右 存在磷離子被低濃度摻雜之薄膜電阻（sheet resistance )201ίΩ程度的η-區域602L，更在其左右存在磷離子被高濃 度摻雜之薄膜電阻lkn程度的 η+區域602Ν之 LDD( Lightly Doped Drain)構造。左右的n +區域602N是經由分 別形成於層間絶緣膜的接觸孔來與源極電極6 0 3、汲極電 極6 0 4連接，源極電極6 0 3是與資料線2 0 2 - m連接，汲極電 極604是與形成於平坦化絶緣膜上的畫素電極402-n-m連 接。在畫素電極402-n-m與對向基板912上的對向電極930 之間存在向列相液晶材料9 2 2。並且，以能夠和畫素電極 402-n-m部份重疊之方式，在對向基板912上形成黑矩陣 940。另外，當畫素開關元件4〇l-n-m的光洩漏電流造成 問題時’可在矽島602下形成由Cr膜所構成的遮光層。本 實施例是光洩漏電流幾乎無問題，且若取如此的構造，則 因爲畫素開關元件401 -n-m的移動度降低，所以選擇矽島 602下的Cr膜除去的構成。 圖7是用以說明輔助電容電容器4〇3_n_m的構造之對 應於圖5的B - B '線部的液晶顯示裝置9丨〇的一部份的剖面 構造’與汲極電極604連接的電容部電極605及電容線203-n會夾著閘極絶緣膜來重疊而形成蓄積電容。 -25- 200905655 圖8是受光感測器3 5 0P-1 (第1光感測器）與遮光感測器 3 5 0D-1(第2光感測器）附近的擴大平面圖。另外，爲了容 易看圖，縱與橫的縮小比例非一定。並且，凡例是與圖5 同樣。受光感測器350P-1是與以粗點線所示的受光開口部 990-1平面性重疊，可被照射外光。受光感測器3 5 0P-1是 藉由4處孤立的受光部3 5 0P-1I及相隣之連接至配線 SENSE的陽極區域350P-1P、及連接至配線VSH的陰極區 域3 5 0P-1N所構成。受光部3 5 0P-1I、陽極區域3 50P-1P、 陰極區域35 0P-1N皆是同一多晶矽薄膜島會藉由摻雜濃度 的不同來分離構成，陽極區域35〇Ρ-1Ρ是被摻雜比較高濃 度的硼離子，陰極區域3 50P-1N是被摻雜比較高濃度的磷 離子，受光部350P-1I是只在極低濃度下含硼離子♦磷離子 〇 又，陽極區域3 50P-1P、陰極區域3 50P-1N、受光部 3 5 0P-1I是分別寬1〇μηι，受光部3 5 0P-1I的長度是分別爲 ΙΟΟΟμιη。如此受光感測器3 50Ρ-1是構成複數的並列連接 的PIN接合二極體。在接近受光感測器3 5 0Ρ-1及遮光感測 器3 5 0D-1的顯示區域310的側配置有共通電位配線3 3 5，但 在本實施例是未被連接至受光感測器3 5 0P-1及遮光感測器 350D-1，爲了避免電磁雜訊的影響，離ΙΟΟμηι配置。 遮光感測器350D-1是藉由4處孤立的受光部350D-1I 及相鄰之連接至配線VSL的陽極區域350D-1P、及連接至 配線SENSE的陰極區域3 5 0D-1N所構成。除了連接陰極 及陽極的配線不同，以及未與受光開口部990- 1平面性重 -26- 200905655 疊以外，其餘則與受光感測器3 50P-1及遮光感測器3 5 0D-1 同一構成，因此省略以上的説明。並且’受光感測器 350P-2〜350P-5與受光感測器350P-1、及遮光感測器 350D-2〜350D-5與遮光感測器350D-1，除了各配置位置以 外，爲同樣的構成，因此省略説明。 圖9是用以說明受光感測器3 50P-1的構造之對應於圖8 的線C-C·線部的液晶顯示裝置910的一部份的剖面構造。 在主動矩陣基板1 〇 1上隔著底層絶緣膜來配置有背光遮光 電極611P-1(第1遮光電極），在其上由薄膜多晶矽所構成 的受光感測器3 5 0P-1會夾著閘極絶緣膜來形成。如前述， 受光感測器3 5 0P-1是藉由4處的受光部3 5 0P-1I及相隣之連 接至配線VSL的陽極區域3 5 0P-1P、及連接至配線SENSE 的陰極區域3 5 0P-1N所構成。在受光感測器3 5 0P-1的上方 隔著層間絶緣膜、平坦化絶緣膜來配置有由氧化銦·錫薄 膜（ITO)所構成的透明電極612P-1(第1透明電極），具有作 爲對受光部3 5 0P-1I之電場屏蔽的機能。 透明電極612P-1的上方是向列相液晶材料922會被封 入，對向基板912上的對向電極930會被配置。另外，依受 光感測器3 50P-1配置位置，也會有取代向列相液晶材料 922而配置密封材923的情況。受光開口部990- 1是藉由部 份除去對向基板91 2上的黑矩陣940來形成。雖未圖示，但 因爲在遮光感測器350D-1上不存在受光開口部，所以黑矩 陣940不會被除去。 形成從對向基板912的上方是被照射外光LA，另一方 -27- 200905655 面，從主動矩陣基板101的下方是被照射來自背光單元926 的光（背光光LB)之構成。另外’雖在本實施例未實施’ 但亦可在受光開口部9 9 0 - 1部放入光學性的補正層。例如 亦可使構成彩色濾光片（對應於在對向基板9 1 2所形成的畫 素）的色材中的一個或複數個與受光開口部990-1重疊形成 ，而使視感度分光特性與受光感測器350P-1更一致。例如 若將對應於綠色的畫素之色材重疊形成於受光開口部990-1上，則因爲去掉短波長及長波長側，所以即使受光感測 器3 50P-1的分光特性要比視感度分光特性更偏至短波長或 長波長，還是可補正。其他，只要與反射防止膜或干渉層 、偏光層等只要按照目的來重疊受光開口部990- 1部即可 。又，本圖中雖未圖示，但上偏光板924亦可與受光開口 部9 90- 1重疊，或除去。重疊是受光開口部990- 1較不明顯 ，但若除去則光感度會提升。 本實施例是液晶顯示裝置910爲了低消費電力化，而 進行對共通電位配線3 3 5施加反轉信號的共通電極反轉驅 動（共通AC驅動），因此在對向電極930會被施加振幅0V 〜5V、頻率14KHz的AC信號。而然，由對向電極93 0產 生的電磁波會被透明電極6 1 2P-1所屏蔽，因此在對向電極 930反轉時雜訊幾乎不會載入受光感測器wop]。同様對 於來自下方的電磁雜訊而言，背光遮光電極611P_；1具有作 爲屏蔽的機能。 圖1〇是表示對應於圖8的線D_D，線部之液晶顯示裝置 9 1 0的一部份的剖面構造。形成於底層絶緣膜上的背光遮 -28 - 200905655 光電極611P-1(第1遮光電極）與背光遮光電極6111)_1(第2遮 光電極）是藉由遮光電極間隙6UG來彼此分離，被賦予各 別的電位。並且被形成於平坦化絶緣膜上的透明電極 612P-1(第1透明電極）與透明電極612D-1(第2透明電極）也 是藉由透明電極間隙612G來彼此分離，被賦予各別的電 位。背光遮光電極611P-1與透明電極612P-1是彼此經由中 間電極613P-1及被形成於閘極絶緣膜、層間絶緣膜及平坦 化絶緣膜的接觸孔來連接，最終連接至配線PBT。背光遮 光電極6 1 1 D -1與透明電極6 1 2 D -1是彼此經由中間電極 6 1 3 D -1及形成於閘極絶緣膜、層間絶緣膜及平坦化絶緣膜 的接觸孔來連接，最終被連接至配線DBT。 在此，遮光電極間隙6 1 1 G與透明電極間隙6 1 2G是在 主動矩陣基板1 〇1及對向基板9 1 2的鉛直方向彼此不重疊。 若如此地構成，則平面性上下皆未被屏蔽的區域會變無， 因此從間隙進入的電磁雜訊難以左右擴散，可減輕間隙所 造成之屏蔽性能的降低。 又，以能夠和遮光電極間隙6 1 1 G重疊之方式形成由 鉬薄膜（Mo)所構成的間隙遮光體610。藉此，可大幅度地 減輕由遮光電極間隙6 1 1 G進入的背光光在各種絶緣膜或 玻璃的界面等被多重反射，形成迷光而到達受光感測器 3 5 0 P - 1或遮光感測器3 5 0 D -1的比例。 以上那樣構成的受光感測器3 5 0P-1〜3 5 0P-6、遮光感 測器3 5 0D-1〜3 5 0D-6的等效電路爲圖1 1。各受光感測器 350P-1〜350P-6、遮光感測器350D-1〜350D-6是分別並聯 -29- 200905655 有4個的PIN二極體。並且，各受光感測器350P_1〜350p-6亦彼此被並聯’遮光感測器3500-1〜350D_6亦彼此被並 聯。所以，最終圖1 1是與圖1 2的電路圖等效。 亦即，遮光感測器350D-1〜3 5 0D-6是通道寬24000μιη 、通道長10 μπι的PIN二極體’其陽極是被連接至配線 VSL，其陰極是被連接至配線SENSE。並且’與遮光感測 器350D-1〜350D-6平面性重疊的背光遮光電極611D-1〜 611D-6及透明電極612D-1〜612D-6是被連接至配線DBT 。受光感測器3 5 0P-1〜3 5 0P-6是通道寬24000μηι、通道長 10 μηι的PIN二極體，其陽極是被連接至配線SENSE，其 陰極是被連接至配線VSH。而且，與受光感測器3 5 0P-1〜 350P-6平面性重疊的背光遮光電極611P-1〜611P-6及透明 電極612P-1〜612P-6是被連接至配線PBT。 圖1 3是表示一定的外光照度LX被照射於液晶顯示裝 置910時之構成受光感測器3 5 0P-1〜3 50P-6及遮光感測器 3 5 0D-1〜3 5 0D-6的PIN二極體的特性曲線圖。橫軸是偏 壓電位Vd( =陽極電位-陰極電位），縱軸是流動於陽極-陰 極間的電流量Id。以實線所示的曲線圖（A)是受光感測器 3 5 0P-1〜3 5 0P-6的特性，以虛線所示的曲線圖（B)是遮光 感測器35〇D-l〜3 5 0D-6的特性。如此在順偏壓區域（Id>0) 大致兩者一致，但在逆偏壓區域（ld<0)是受光感測器 3 50P-1〜35〇P-6的曲線圖（B)的電流絶對値較大。這是因 爲在遮光感測器3 5 0 D -1〜3 5 0 D - 6未被照射外光，所以僅温 度所引起的熱電流量Ileak會流動，但若在構成受光感測 -30- 200905655 器3 5 0P-1〜3 50P-6的PIN二極體的受光部3 5 0P-1I〜3 50P- 61照射光，則會產生載流子對，流動光電流量Iphoto，因 此在受光感測器350P-1〜3 50P-6流動光電流量與熱電流量 的和、Iphoto + Ileak。在此，所謂熱電流量neak是意指在 圖13左側的逆偏壓區域（Id<〇)中，施加電壓流動至負數V 位之處的電流，半導體會藉由温度來一點一點地製作電子 及電洞，其爲依流動電流者。 熱電流量Ileak是顯示Vd( =陽極電位-陰極電位）依存 性，在-5.0$乂(1$-1.5的區域，可近似傾斜度1^(1^>0)的 直線。在此，KA是對温度的函數，一旦温度上昇，則會 指數函數性地上昇。在此Vd區域（Vd = -5.0SVdg-1.5)是 流動於受光感測器3 5 0P-1〜3 5 0P-6的光電流量Iphoto具有 大致一定的値，與外光照度 LX成比例（以下記爲 Iphoto = LXxk)。所以，流至受光感測器3 5 0P-1〜3 50P-6的 電流（曲線圖（A))、流至遮光感測器350D-1〜350D-6的電 流（曲線圖（B))皆是在-5.0 SVdS-1.5的區域圍傾斜度 ΚΑ(ΚΑ>0)的直線。 在此以使遮光感測器3 5 0D-1〜3 5 0D-6與受光感測器 3 5 0P-1〜3 5 0P-6的Vd能夠形成相同的方式來設定偏壓， 亦即若將配線SENSE的電位VSENSE設定成配線VSH的 電位 VVSH與配線 VSL的電位 VVSL的正好中間之 (VVSH + VVSL) + 2，則流至受光感測器350P-1〜350P-6及遮 光感測器350D-1〜350D-6的熱電流量Ileak完全一致。此 時，流至配線VSH的電流量（=流至受光感測器3 5 0P-1〜 -31 - 200905655 350P-6的電流量）爲Iphoto + Ileak，流至配線VSL的電流 量（=流至遮光感測器350D-1〜350D-6的電流量）爲Heak ’ 因此由基爾霍夫第1法則流至配線SΕΝSE的電流量是形成 Iphoto = LX X k 5與外光照度LX成比例。另外，在貫施例 中雖是將受光感測器連接至高電位側，將遮光感測器連接 至低電位側，但當然即使是其他情況也無妨，結論是相同 〇 圖1 4是檢測電路3 6 0的電路圖。配線 v C H G、配線 RST、配線VSL、配線VSH、配線OUT是與信號輸入端 子320連接，且配線VSL、配線VSH、配線SENSE、配線 PBT、配線DBT配線是被連接至受光感測器3 5 0P-1〜 3 50P-6及遮光感測器3 5 0D-1〜3 5 0D-6。在此，配線 VCHG 、配線VSL、配線VSH是被連接至由外部電源電路784所 供給的DC電源，VCHG配線是供給電位VVCHG( = 2.0V) ，V S L配線是供給電位V V S L ( = 0.0 V )，V S Η配線是供給電 位VVSH( = 5.0V)。另外，在此VSL配線的電位VVSL是 液晶顯示裝置910的GND。 配線SENSE是被連接至第1電容器C1、及第3電容器 C3的各一端。並且，被連接至初期充電電晶體NC的汲極 電極。第3電容器C3的另一端是被連接至配線VSL。第1 電容器C1的另一端是被連接至節點A。初期充電電晶體 NC的源極電極是被連接至配線 VCHG，供給電位 VVCHG( = 2.0V)電源。初期充電電晶體NC的閘極電極是 被連接至配線RST。節點A是更被連接至第1 N型電晶體 -32- 200905655 N 1的閘極電極、第1 P型電晶體P 1的閘極電極及復位電晶 體NR的汲極電極，且被連接至第2電容器C2的一端。第 2電容器C2的另一端是被連接至配線RST。 第1 N型電晶體N 1的汲極電極、第1 P型電晶體P 1的 汲極電極及復位電晶體NR的源極電極是被連接至節點B ，節點B是更被連接至第2N型電晶體N2的閘極電極及第 2P型電晶體P2的閘極電極。第2N型電晶體N2的汲極電 極與第2P型電晶體P2的汲極電極是被連接至節點C，節 點C是更被連接至第3N型電晶體N3的閘極電極及第3P 型電晶體P3的閘極電極。第3N型電晶體N3的汲極電極及 第3P型電晶體P3的汲極電極是被連接至節點D，節點D 是更被連接至第4N型電晶體N4的閘極電極及第4P型電晶 體P4的閘極電極。第4N型電晶體N4的汲極電極及第4P 型電晶體P4的汲極電極是被連接至配線OUT，配線OUT 是更被連接至第5N型電晶體N5的汲極電極。第5N型電 晶體N5的閘極電極及第5P型電晶體P5的閘極電極是被連 接至配線R S T，第5 P型電晶體P 5的汲極電極是被連接至 第4P型電晶體P4的源極電極。第1〜第5N型電晶體N1〜 N 5的源極電極是被連接至配線 V S L ’供給電位 VVSL( = 0V)。並且，第1〜第3P型電晶體P1〜P3及第5P 型電晶體P 5的源極電極是被連接至配線V S Η ’供給電位 VVSH( = + 5V)。 並且，在檢測電路360也具備自己補正電壓電路361’ 其係由電晶體的臨界値電壓（Vth)來自動地補正施加於配 -33- 200905655 線PBT及配線DBT的電位。自己補正電壓電路361是第 6N型電晶體Nl 1及第6P型電晶體PI 1的汲極電極及閘極 電極會分別被連接至配線PBT，第7N型電晶體N21及第 7P型電晶體P21的汲極電極及閘極電極會分別被連接至配 線DBT，第6N型電晶體Nl 1及第7N型電晶體N21的源極 電極是被連接至配線VSL而供給電位VVSL( = 0V)，第6P 型電晶體PI 1及第7P型電晶體P21的源極電極是被連接至 配線VSH，供給電位VVSH( = + 5V)。 並且，檢測電路3 60是藉由與構成畫素電極402_n-m 的氧化銦·錫薄膜（ITO)同一膜所形成的屏蔽電極3 69來覆 蓋全面。屏蔽電極3 69是經由配線VSL來連接至液晶顯示 裝置9 1 0的GND電位，具有作爲對電磁雜訊的屏蔽之機能 〇 在此，本實施例是第1N型電晶體N1的通道寬爲ΙΟμπα ’第2Ν型電晶體Ν2的通道寬是35μιη，第3Ν型電晶體Ν3 的通道寬是ΙΟΟμιη，第4Ν型電晶體Ν4的通道寬是150μηι ’第5Ν型電晶體Ν5的通道寬是150μηι，第6Ν型電晶體 NU的通道寬是4μιη，第7Ν型電晶體 Ν2 1的通道寬是 2〇〇μπι ’第1Ρ型電晶體Pi的通道寬是l(^m，第2Ρ型電晶 體Ρ2的通道寬是35μιη，第3Ρ型電晶體Ρ3的通道寬是 ΐΟΟμιη’第4Ρ型電晶體Ρ4的通道寬是3 00μιη，第5Ρ型電 晶體ρ5的通道寬是300μιη，第6Ρ型電晶體Ρ11的通道寬是 2 00μηι ’第7Ρ型電晶體Ρ21的通道寬是4μηι，復位電晶體 NR的通道寬是2μιη，初期充電電晶體NC的通道寬是 -34- 200905655 5 0μηι，全部的N型電晶體的通道長是8μιη，全部的p型電 晶體的通道長是6μιη ’全部的N型電晶體的移動度是 80cm2/VSec，全部的Ρ型電晶體的移動度是6〇em2/Vsec ’全部的N型電晶體的臨界値電壓（Vth)是+. 1·〇ν，全部的 P型電晶體的臨界値電壓（Vth)是-1.0V，第1電容器ci的 電容是IpF，第2電容器C2的電容是i〇〇fF，第3電容器C3 的電容是i〇〇pF。 配線R S T是電位振幅0 - 5 V的脈衝波，每周期5 1 〇 m秒 ，在脈衝長1 〇〇μ秒之間保持於High電位（5 V)，剩下的 509.9m秒間是保持於Low電位（0V)。一旦RST配線每 5 10m秒形成High(5V)，則初期充電電晶體NC及復位電 晶體NR會形成ON，在配線SENSE被充電VCHG配線的 電位（2.0V)，節點A與節點B係短路。因爲第1N型電晶 體N 1及第1 P型電晶體Ρ 1是構成倒相電路，所以倒相電路 的IN/OUT會被短路。此時，節點A及節點B的電位最終 是到達以下的數式所示的電位VS(詳細的計算是例如參照 Kang Leblebici 著” CMOS Digital Integrated Circuits” Third Edition P206等）。 [數1] VS =Then 丨V1-V2| <|VD1| and |V1-V2| <|VD2|, more ideally 丨V1-V2| <1V 〇 By setting the potential as described above, the difference in the thermal current between the first photosensor and the second photosensor can be almost ignored. Further, a semiconductor device in which one of V1 = 0 V, V2 = 0 V, and V1 = VD1 and V2 = VD2 is proposed. That is, by connecting the cathode electrode of the first photo sensor. Source electrode. Anode electrode. One of the gate electrodes and the cathode electrode of the first electrode or the second photo sensor. Source electrode. Anode electrode. One of the gate electrodes and the second electrode can almost eliminate the difference in the thermal current between the first photosensor and the second photosensor, and the number of wirings can be minimized. Here, in the semiconductor device proposed by the present invention, the first electrode is a first light-shielding electrode that blocks light (in the embodiment, the backlight light-shielding electrode 611P), and the second electrode is a second light-shielding electrode that blocks light. (In the embodiment, the backlight electrode 611D), and the first electrode is a first transparent electrode (in the embodiment, the transparent electrode 612P), and the second electrode is a second transparent electrode that does not block light. In the embodiment, the transparent electrode 612D) and the first electrode are a first light-shielding electrode for shielding light and a first transparent electrode that is not shielded from light, and the second electrode is a second light-shielding electrode for blocking light and The second transparent electrode that does not block light. When the light-shielding electrode that shields the light from the excess direction and the transparent electrode that transmits the light from the incident direction as the electromagnetic noise shielding function and the photosensor are stacked, the potential is set as described above. Does not reduce the detection accuracy. -9-200905655 In the semiconductor device of the present invention, the first light-shielding electrode and the second light-shielding electrode are formed with a light-shielding electrode gap region in which the light-shielding electrode is not formed, and overlap with the light-shielding electrode gap region. The region is formed with a non-transparent gap light-shielding body. In order to apply the respective potentials to the first light-shielding electrode and the second light-shielding electrode in this manner, it is necessary to provide a light-shielding electrode gap region in the light-shielding electrode, but the light of the backlight is incident from the gap, causing multiple scattering on the surface of the glass or the dielectric body. When the fog is formed, once the first photo sensor or the second photo sensor is incident, the detection accuracy is lowered. Then, a non-transparent gap light-blocking body is formed in a region overlapping the light-shielding electrode gap region, whereby the light incident from the light-shielding electrode gap region is absorbed by the gap light-blocking body, and such a decrease in accuracy can be avoided. Further, in the semiconductor device of the present invention, the first light-shielding electrode and the second light-shielding electrode have a light-shielding electrode gap region (in the embodiment, 6 1 1 G) in which the light-shielding electrode is not formed, and the first The transparent electrode and the second transparent electrode have a transparent electrode gap region (in the embodiment, 6 1 2 G) in which the transparent electrode is not formed, and the light-shielding electrode gap region and the transparent electrode gap region are attached to the substrate. The vertical directions do not overlap each other. In order to apply the respective potentials as described above, the light-shielding electrode gap region and the transparent electrode gap region are required for the light-shielding electrode and the transparent electrode, respectively, but if the electromagnetic noise enters from the gaps, the detection accuracy of the sensor is lowered. Therefore, if the light-shielding electrode gap region and the transparent electrode gap region do not overlap each other, one of the electrodes can shield the electromagnetic noise that is entered from each gap by -10, 2009,056, and thus When the light-shielding electrode gap region and the transparent electrode gap region are formed at the same position, the accuracy is improved. Further, in the semiconductor device of the present invention, the first light-shielding electrode and the first transparent electrode have the same potential, and the second light-shielding electrode and the second transparent electrode have the same potential. According to this configuration, since the potential applied to the light-shielding electrode and the transparent electrode can be supplied using the same wiring, the number of wirings, the number of mounting terminals, and the circuit area can be saved. Further, since the total capacitance of the light-shielding electrode and the transparent electrode is increased, the electromagnetic shielding property is improved. Further, in the semiconductor device of the present invention, the potential application unit includes a self-correcting voltage circuit including a transistor, and the self-correcting circuit is configured to output a voltage that changes in accordance with a threshold voltage of the transistor. The output is connected to the first electrode and the second electrode. The manufacturing unevenness of the optimum potential of the light-shielding electrode or the transparent electrode that can obtain the photocurrent is related to the manufacturing unevenness of the critical threshold voltage (Vth) of the transistor when the transistor is formed on the same semiconductor device. The self-correcting voltage circuit of the voltage which changes with the critical 値 voltage of the transistor can always apply the optimum potential to the light-shielding electrode or the transparent electrode even if there is manufacturing unevenness. Further, in the first aspect of the invention, the first photosensor and the second photosensor are PIN junction diodes or PN junction diodes using a thin film polysilicon. -11 - 200905655 Although such a diode has the advantage of being fabricated without additional fabrication on a semiconductor device using a polycrystalline germanium film transistor, the ratio of the thermal current to the photocurrent is higher than that formed on a single crystal wafer. The photodetector type is larger, and the thermal current is easily changed in accordance with the potential applied by the planar overlapping electrodes, and thus is suitable for use in the present invention. Further, the photovoltaic device of the present invention includes a panel in which a display region in which a photoelectric substance (in the embodiment, a nematic liquid crystal material 9 2 2) is interposed between the first and second substrates is formed (in the implementation) In the embodiment, the liquid crystal panel 9 1 1 ) and the light detecting unit (in the embodiment, the detecting circuit 3 60 and the light receiving sensor 3 0 0 P and the like) for detecting the illuminance of the ambient light of the panel are characterized. The photodetecting unit is provided on a peripheral portion of the display region of the first or second substrate, and includes a first photosensor (in the embodiment, a photosensor 3500P). Irradiating the external light; and the second photosensor (in the embodiment, the shading sensor 350D), which is to block the irradiation of the external light, the first photosensor and the second photo sensing The plurality of devices are disposed on the peripheral portion of the display area. By arranging in this way, it is possible to prevent a significant change in the detection result due to a finger or a small shadow, and it is possible to prevent a decrease in accuracy due to a difference in thermal current caused by a temperature distribution in the device. Further, the photovoltaic device of the present invention includes a light source (in the embodiment, a backlight unit 926) that emits light to a display region of the panel, and the light -12-200905655 is applied to a peripheral portion of the display region and is disposed not. There are sides of the first photo sensor and the second photo sensor. According to this configuration, since the difference in the thermal current between the first photosensor and the second photosensor caused by the temperature gradient of the light source can be minimized, the thermal current can be accurately excluded. Further, in the photovoltaic device of the present invention, the first photosensor and the second photosensor are alternately arranged. If it is configured in this way, even if there is a temperature distribution in the display device, Liao is because the average temperature of the first photo sensor and the second photo sensor are not greatly different, so that the thermal current can be more accurately performed. except. Further, in the photovoltaic device of the present invention, the first photosensor and the second photosensor disposed adjacent to each other are derived from the boundary of the display region (in the embodiment, the boundary of the display region 3 1 0 is displayed) The distances of the dotted lines are slightly equal. By arranging in such a manner that the light from the display region is multi-reflected at the interface between the glass substrate and the insulating film, the first photo sensor and the second photo sensor are uniformly irradiated. By removing the current difference between the first photosensor and the second photosensor, the accuracy reduction caused by the fog does not occur. Further, in the photovoltaic device of the present invention, the plurality of openings provided in the first or second substrate are irradiated to the first photosensor to illuminate the ambient light of the panel (in the embodiment, the light receiving opening 990 is used). - 1 to 990 - 1 0) Size formation: a direction parallel to the boundary edge of the peripheral portion of the display region where the opening portion is disposed is 〇. In the range of 5 mm or more and 20 mm or less, the direction orthogonal to the boundary edge of the peripheral portion of the display region in which the opening portion of the above-mentioned -13-200905655 is disposed is 0. 05 mm or more and less than the thickness of the above opposing substrate. When the opening portion is set in this way, the amount of fogging is small, and the difference in thermal current due to the temperature distribution in the device is small, so that the accuracy can be prevented from being lowered. Further, in the photovoltaic device of the present invention, the plurality of openings are provided in a peripheral portion of the display region, and are provided in a first opening portion disposed on a side opposite to an arrangement side on which the light source is disposed (in the embodiment, The light-receiving opening portions 990-1 to 990-6) and the second opening portion (in the embodiment, the light-receiving opening portions 99 0-7 to 990-1 0) disposed on the side substantially orthogonal to the arrangement side, The opening area of the first opening is larger than the second opening area. Further, when the temperature gradient differs depending on the arrangement place of the openings, the larger the temperature gradient, the smaller the size of the opening, the lower the influence of the temperature gradient. More specifically, the side closer to the first opening portion and the side closer to the second opening portion of the four sides of the display region are different display devices. The more the temperature gradient is larger, the smaller the size of the opening is. Further, the present invention proposes a display device using these semiconductor devices. Therefore, the temperature dependency of the photodetector provided on the display device is improved without increasing the manufacturing cost, and the display setting of the external light environment can be performed regardless of the temperature, and the position of the photodetector can be very close. Display area. Further, the present invention proposes an electronic device using the display devices. In this way, for example, in an electronic device such as a digital camera, a mobile phone, or a PDA (Pers〇nal Digital Assistant), since a light sensor that does not rely on temperature accuracy is built in, it is easy to control the backlight with external light, and there is no To make consumption - 200905655 power insignificantly large, the cost will not rise. Moreover, since the photodetector can be disposed near the display area, the degree of freedom in design is also improved. [Embodiment] Hereinafter, embodiments of an optoelectronic device, a semiconductor device, a display device, and an electronic device including the same according to the present invention will be described with reference to the drawings. [First Embodiment] Fig. 1 is a perspective structural view (partial sectional view) of a liquid crystal display device 910 of the present embodiment. The liquid crystal display device 910 includes a liquid crystal panel 9 1 1 in which the active matrix substrate 110 and the opposite substrate 9 1 2 are bonded to each other at a predetermined interval by the sealing member 923, and the nematic liquid crystal material 9 2 2 is sandwiched. Although not shown in the active matrix substrate 1〇1, an alignment material made of polyimide or the like is actually applied, and an alignment film is formed by surface grinding treatment. Further, the counter substrate 912 is a black matrix 940 formed of a low-reflection/low-transmission resin in which a color filter corresponding to a pixel is not shown, and a light leakage is prevented, and contrast is improved. The opposite-direction electrodes 330-1 to 3 3 0-2 on the active matrix substrate 101 are short-circuited with the counter electrode 93 0 of the IT0 film to which the common potential is supplied. The surface in contact with the nematic liquid crystal material 922 is coated with an alignment material made of polyimide or the like, and is surfaced in a direction orthogonal to the direction of the surface grinding treatment of the alignment film of the active matrix substrate 1〇1. Grinding treatment. Further, the upper polarizing plate 924 is disposed on the outer side of the counter substrate 9 1 2, and the lower polarizing plate 925 is disposed on the outer side of the active matrix substrate 110, so that the polarization directions -15-200905655 of each other can be orthogonal (orthogonal Polarized configuration. Further, a backlight unit 926 and a light guide plate 927 are disposed under the lower polarizing plate 92 5 , and the light guide plate 927 is irradiated from the backlight unit 926 to the light guide plate 927 to enable the light from the backlight unit 926 to form a vertical direction to the active matrix substrate 1〇1. The uniform surface light source is configured to refract light and has a function as a light source of the liquid crystal display device 910. The backlight unit 926 is an LED unit in this embodiment, but may be a Cold Cathode Fluorescent Lamp (CCFL). The backlight unit 92 6 is connected to the electronic device body via the connector 929 to supply power, and in the present embodiment, has the function of adjusting the amount of light from the backlight unit 926 when the power source is adjusted to a suitable current/voltage. Although not shown, it is also possible to cover the surroundings with the outer casing as needed, or to install a protective glass or acrylic plate on the upper surface of the upper polarizing plate 924, or to provide optical compensation for improving the viewing angle. film. Further, a photo sensor light receiving opening portion 990 is provided on the outer peripheral portion of the liquid crystal display device 910. Further, the active matrix substrate 101 is provided with a protruding portion 102 projecting from the opposite substrate 912, and an FPC (flexible substrate) 928 is attached to the signal input terminal 320 located at the protruding portion 102 and electrically connected. The FPC (Flexible Substrate) 92 8 is connected to the electronic device body to supply necessary power, control signals, and the like. Further, the light-receiving opening portions 990-1 to 990-6 of the six photo sensors are provided on the liquid crystal display device 910. The light-receiving openings 990-1 to 990-6 are formed by partially removing the black matrix 940 on the counter electrode 930, and the external light can reach the active matrix substrate 101. The periphery of each of the light-receiving openings 990-1 to 990-6 is such that the black matrix 940 on the counter electrode 930 is not removed, so that the external light -16-200905655 does not reach the active matrix substrate 101. 2 is a block diagram of the active matrix substrate 101. On the active matrix substrate 101, 480 scanning lines 201-1 to 201-480 and 1920 data lines 202-1 to 202-1920 are orthogonally formed, and 480 capacitance lines 203-1 to 203-480 are It is arranged in parallel with the scanning lines 201-1 to 20 1 - 480. The capacitance lines 203 - 1 to 203 - 48 0 are short-circuited to each other, connected to the common potential wiring 3 3 5 , and further connected to the two pairs of the conduction-passing portions 330-1 to 330-2, and the signal input terminal 320 is given 0V - 5V. The inversion signal and the inversion time are common potentials of 35 μsec. The scanning lines 201-1 to 20 1 - 48 0 are connected to the scanning line driving circuit 301, and the data lines 202-1 to 202-1 920 are connected to the data line driving circuit 302, and are respectively driven appropriately. Further, the scanning line driving circuit 301 and the data line driving circuit 312 are signals necessary for driving from the signal input terminal 312. The signal input terminal 32A is disposed on the protruding portion 102. On the other hand, the scanning line driving circuit 301 and the data line driving circuit 312 are disposed outside the protruding portion 102 in a region overlapping the counter substrate 912. The scanning line driving circuit 301 and the data line driving circuit 312 are on the active matrix substrate by the low temperature polysilicon TFT process 'SOG (System On Glass) technology using the circuit function necessary for integrated driving on the active matrix substrate A polycrystalline germanium thin film transistor is integrated and formed, and a so-called drive circuit built-in type liquid crystal display device is manufactured in the same manner as the pixel switching element 401-nm described later. Further, six light receiving sensors 350P-1 to 350P-6' are formed in regions that are planarly overlapped with the six light receiving openings 990-1 to 990-6, and are formed so as to be alternately formed therewith. 6 shade sensors 3 5 0D-1 -17- 200905655 ~ 3 50D-6. The light-receiving sensors 3500-15-1 0 0P-6 and the light-shielding sensors 350D-1 350350D-6 are also formed on the active matrix substrate by a glass on-system technique. Thus, it is manufactured on the glass substrate in the same manner as the pixel switching elements 4 0 1 - η - m, and the manufacturing cost can be reduced. The light-receiving sensors 35〇Ρ-1 to 350P-6 are planarly overlapped with the light-receiving opening portions 990-1 to 990--6, and the external light reaches the sensor, but the light-shielding sensors 350D-1 to 350D- 6 is not planarly overlapped with the light receiving openings 990-1 to 990-6, and the external light is absorbed by the black matrix 940 on the counter electrode 930. The light-receiving sensor 3 5 0P-1 to 3 5 0P-6 is connected to the wiring PBT, the wiring VSH, and the wiring SENSE. The light-shielding sensor 3 5 0D-1 to 3 5 0D-6 is the wiring DBT, the wiring VSL, Wiring SENSE connection. The wiring PBT, the wiring VSH, the wiring SENSE, the wiring DBT, and the wiring VSL are connected to the detection circuit 360. The detecting circuit 360 is converted into a pulse length corresponding to an output analog current having an external illuminance associated with the light receiving sensors 350P-1 350350P-6 and the light blocking sensors 350D-1 305 050 D-6 The output signal OUT is output to the signal input terminal 320. Further, the wiring VCHG, the wiring RST, the wiring VSL, and the wiring VSH are also supplied to the detection circuit 360 via the signal input terminal 320. As will be described later in detail, the light-receiving sensor 3 5 0P-1 to 3 5 0P-6 is planarly overlapped with the backlight light-shielding electrodes 611P-1 to 611P-6 'the light-shielding sensor is 015-1 to 350D-6 is the backlight Since the light-shielding electrodes 611D-1 to 611D-6 are planarly overlapped, each of the light from the backlight is shielded, so that the detection accuracy of the external light is not lowered due to the light from the backlight. And 'the light-receiving sensors 350P-1 to 350P-6 overlap the transparent electrodes 612P-1 to 612P-6'. The light-shielding sensation-18-200905655 the detectors 350D-1 to 350D-6 and the transparent electrodes 612D-1 to 612D-6 'There is no possibility that the detection accuracy is lowered due to electromagnetic noise generated when the display area 310 is driven (the dotted line is the boundary of the display area 31〇). With such a configuration, even if the light-receiving sensors 350P-1 to 350P-6 and the light-shielding sensors 3 5 0D-1 to 3 5 0D-6 are arranged in the vicinity of the display area 310, the detection accuracy does not decrease. Therefore, the degree of freedom in design will increase compared to previous products. Here, the light-receiving opening portions 990-1 to 990-6 are as shown in the present embodiment, and are preferably divided into a plurality of numbers to be distributed as wide as possible. For example, if the shadow of a finger or the like partially covers the liquid crystal display device 9 1 还是 'to reduce the influence of external light detection, it is preferable that the total area of the light receiving opening portion is as wide as possible, but if the area is wide When the light-receiving sensors are concentrated in one place, the distance from the light-shielding sensor has to be separated, and a temperature distribution is formed in the liquid crystal display device 910. Therefore, an average temperature difference is generated in the light-receiving sensor portion and the light-shielding sensor portion. Therefore, the sensor is divided into a plurality as in the present embodiment. More preferably, if alternately arranged, the average temperatures of the light receiving sensor portion and the light sensing portion can be made substantially equal. For the purposes of this embodiment, it is 6 divisions, but of course fewer or more. Further, in this case, it is preferable that the distance from the end of each of the light receiving openings 990-1 to 990-6 to the display region 310 can be formed to be equal. Similarly, the distances from the respective light-receiving sensors 3 0 0P-1 to 3 5 0P-6 and the respective light-shielding sensors 3 5 0D-1 to 3 5 0D-6 to the display area 310 can be configured in an equal manner. It is better. The light transmitted for display from the display area 310 to the outside is, for example, the surface of the glass or upper polarizing plate 924 constituting the active matrix substrate 1 〇 1 or the opposite substrate 9 1 2 or the interface of various insulating films, etc. Multiple reflections, although some of the fog will enter each photosensor, but at this time, if it is arranged as described above, it will be light-sensitive to each of the light-receiving sensors 3 50P-1 to 3 5 0P-6. Between the detectors 3 5 0D-1 〜 3 50D-6, the amount of light of the faint light will be substantially constant, so if the light-receiving sensors 3 5 0P-1~3 5 0P-6 are removed as in this embodiment, The current difference between the detectors 3 50D-1 and 3 5 0D-6, the faint portion can be roughly removed. From this point of view, once the light-receiving apertures 990-1 to 990-6 are divided into a plurality of numbers and distributed over a wide range as much as possible, it is less likely to be affected by the display pattern of the display region 310. Further, each of the light-receiving sensors 3 50P-1 to 3 5 0P-6 and the light-shielding sensors 350D-1 to 350D_6 are disposed as far as possible from the backlight unit 926 as shown in the present embodiment. This is because the backlight unit 926 forms a heat source regardless of whether the LED or the CCFL is formed. Therefore, the closer to the backlight unit 926, the larger the thermal gradient in the active matrix substrate 101 is, and the respective photodetectors 35 0 -1 to 350 P- 6. A temperature difference is easily formed between each of the shading sensors 350D-1 to 350D-6. In addition, the size of the light-receiving opening portions 990-1 to 990-6 is parallel to the boundary edge of the peripheral edge portion of the display region 31A in which the light-receiving opening portions 990_1 to 990_6 are disposed (hereinafter referred to as the X direction). If it is increased, it will be affected by temperature distribution or fog. In addition, when the direction of the positive edge of the display area 31〇 is increased (hereinafter referred to as the γ direction), the frame edge area becomes larger, and the outer shape of the liquid crystal display device 910 becomes larger, and is in the opposite direction. The light of the display area 31 反射 where the interface between the substrate 912 and the upper polarizing plate 924 is reflected becomes a glare and is incident on each of the light receiving sensors 3 5 〇p _ i~3 5 〇p _ 6 , and each opaque sensing -20- 200905655 The devices 350D-1 to 350D-6 form the cause of the measurement error. On the other hand, if the X direction is too small, the arrangement efficiency will be deteriorated, and the channel width (W) of the P IN diode will become small. If the Y direction is reduced, the light extraction efficiency will be deteriorated. The accuracy of the detection has an effect. Review the above conditions and conclude that the result is 0 in the X direction. 5mm~20mm, in the Y direction is from 0. The thickness of the opposite substrate 912 from 05 mm (in this embodiment is 0. The range of 6mm) is preferred. According to the above, in the embodiment, the X direction is set to 10 mm, and the Y direction is set to 0. 3 m m in size. Further, the distance from the end of the light receiving opening portions 990-1 to 990-6 to the display area 310 is 0. 5mm. The light receiving sensors 350P-1 to 350P-6 and the light blocking sensors 350D-1 to 3 5 0D_6 are alternately arranged at a pitch of 10 mm, and the arrangement pitch of the light receiving openings 990-1 to 990-6 is 20 mm. The distance between the light-receiving sensor 350P-1 and the light-receiving sensor 3 50D-1 is l〇mm, and the distance between the light-shielding sensor 3 50D-1 and the light-receiving sensor 3 50P-2 is also Mm. Fig. 3 is a circuit diagram showing the vicinity of the intersection of the mth data line 2 〇 2 - m and the nth scanning line 2 〇 1 _ n in the display region shown by the dotted line 310 in Fig. 2 . A pixel switching element 40 1-nm composed of an N-channel type field effect polysilicon thin film transistor is formed at each intersection of the scanning line 2 0 1 - η and the data line 2 0 2 - m, and the gate electrode is connected To the scan line 2〇1_n, source. The 极 pole electrodes are connected to the data line 202-m and the pixel electrode 402-n-m, respectively. The electrode of the pixel electrode 402-nm and the short-circuited to the same potential are formed by the capacitance line 203-n and the auxiliary capacitor capacitor 4〇3-nm, and when assembled as a liquid crystal display device, the liquid crystal element and the counter electrode 9 are sandwiched. 3 0 (common electrode) shaped -21 - 200905655 into a capacitor. Fig. 4 is a block diagram showing a specific configuration of the electronic apparatus of the embodiment. The liquid crystal display device 910 is the liquid crystal display device illustrated in FIG. 1. The external power supply circuit 784 and the image processing circuit 780 provide necessary signals and power via the FPC (flexible substrate) 928 and the connector 209. It is supplied to the liquid crystal display device 910. The central processing circuit 781 takes the input data from the input/output device 783 via the external i/f circuit 782. Here, the input/output device 783 is, for example, a keyboard, a mouse, a trackball, an E E D, a speaker, an antenna, or the like. The central processing circuit 781 performs various arithmetic processing based on data from the outside, and transfers the result to the image processing circuit 7 8 or the external I/F circuit 7 82 as a command. The video processing circuit 780 changes the video information to the liquid crystal display device 9 i according to a command from the central processing circuit 781, whereby the display image of the liquid crystal display device 9 1 0 changes. Further, the binary output signal out from the detecting circuit 36A on the liquid crystal display device 910 is input to the central processing circuit 781 via the FPC (flexible substrate) 928, and the central processing circuit 781 outputs the pulse of the output signal out of the second output. The length is transformed into the corresponding discrete 値. Next, the central processing circuit 781 accesses the reference table 785 composed of EEPROM (Electronically Erasable and Programmable Read Only Memory), and converts the converted discrete 値 into a voltage corresponding to the appropriate backlight unit 926. That is, and is transferred to the external power supply circuit 784. The external power supply circuit 784 supplies a potential power source corresponding to the voltage of the transferred turns to the backlight unit 926 in the liquid crystal display device 910 via the connector 929. The brightness of the backlight unit 926 varies depending on the voltage supplied from the external power supply circuit 784 according to -22-200905655. Therefore, the brightness of the liquid crystal display device 910 is also changed when it is displayed in full white. The so-called electronic devices, in particular, monitors, TVs, notebook computers, PDAs, digital cameras, video cameras, mobile phones, portable picture viewers, portable video players, portable DVD players, portable music Player, etc. Further, in the present embodiment, the brightness of the backlight unit 926 is controlled by the central processing circuit 78 1 on the electronic device. For example, the liquid crystal display device 910 may have a configuration in which the driver 1C and the EEPROM are provided, so that the driver 1C has The conversion function from the binary output signal OUT to the discrete 、, the readjustment function of the reference EEPROM, and the adjustment function of the output voltage to the backlight unit 926. Further, it is also possible to form a 电压 which is converted from the discrete 値 to the voltage corresponding to the backlight unit 926 by the number calculation without using the reference table. Fig. 5 is a plan view showing the actual configuration of a circuit diagram of the pixel display region shown in Fig. 3; As shown in the example of Fig. 5, the different portions of the respective nets are respectively displayed with different material wirings, and the portions displayed on the same net are the same material wiring. From chromium thin film (Cr), polycrystalline germanium film (Poly-Si), molybdenum thin film (Mo), aluminum alloy film (AINd), indium oxide. A five-layer film of a tin film (Indium Tin 〇xiced = ITO) is formed, and one of yttrium oxide, tantalum nitride, and an organic insulating film is formed between the respective layers or an insulating film is laminated. Specifically, chromium The film (Cr) is a film thickness of 100 nm, the polycrystalline silicon film (Poly-Si) is a film thickness of 50 nm, the molybdenum film (Mo) is a film thickness of 200 nm, and the aluminum bismuth alloy film (AINd) is a film thickness of 500 nm, indium oxide. The tin film (ιτο) is a film thickness of 100 nm. Further, between the chrome film (Cr) and the polycrystalline germanium film (p〇iy_Si) -23-200905655, an underlying insulating film of a 100 nm tantalum nitride film and a 100 nm yttrium oxide film is formed, in a polycrystalline silicon film (Poly-Si). A gate insulating film composed of a ruthenium oxide film of 100 nm is formed between the molybdenum film (Mo), and a tantalum nitride layer of 200 nm is formed between the molybdenum film (Mo) and the aluminum-ammonium alloy film (AINd). An interlayer insulating film of a film and a cerium oxide film of 50,000 nm is formed with a tantalum nitride film of 200 nm and an organic planarizing film of an average Ιμπι between an aluminum-titanium alloy film (AINd) and an indium tin oxide film (ITO). The protective insulating film insulates the wirings of each other and connects the contact holes at appropriate positions to each other. In addition, in FIG. 5, the chromium thin film (Cr) pattern does not exist. As shown in FIG. 5, the data line 202-m is formed by an aluminum-ammonium alloy film (AINd) and is connected to the source electrode of the pixel switching element 401-n-m via a contact hole. The scanning line 20 1-n is composed of a molybdenum film (Mo) and also serves as a gate electrode of the pixel switching element 401-n-m. The capacitance line 203 - η is composed of the same wiring material as the scanning line 201 - η, and the pixel electrode 402 - nm is composed of an indium oxide tin film "connected to the pixel switching element 401 - nm via a contact hole" Polar electrode. Further, the drain electrode of the pixel switching element 401-nm is also connected to the capacitor portion electrode 605' which is formed of a high-concentration doped phosphorus n + -type polysilicon film, and the capacitance line 203 - n is planarly overlapped to constitute an auxiliary. Capacitor capacitor 403_n-m. Fig. 6 is a cross-sectional view showing a portion of the liquid crystal display device 910 corresponding to the A-A4 spring portion of Fig. 5 for explaining the configuration of the pixel switching elements 40 1 -n-m. In addition, it is not necessary to reduce the scale in order to make it easy to see the figure. The active matrix substrate 1 〇 1 is the thickness of the alkali-free glass. A 6 mm insulating substrate on which a strontium island 602 composed of a polycrystalline germanium film is disposed via a laminate of a 2 〇〇 nm tantalum nitride film and a 300 nm yttrium oxide film of a bottom layer insulating film, scan line 20 1 -n is disposed above the erbium island 602 with the gate insulating film interposed therebetween. In the region overlapping with the scanning line 201-n, the island 602 is an intrinsic semiconductor region 6021 in which phosphorus ions are completely or only doped at a low concentration, and there is a sheet resistance in which phosphorus ions are doped at a low concentration. The η-region 602L of the order of 201 Ω Ω has an LDD (Lightly Doped Drain) structure of η+ region 602 程度 to the left and right of the film resistance lkn to which the phosphorus ions are doped at a high concentration. The left and right n + regions 602N are connected to the source electrode 603 and the drain electrode 604 via contact holes respectively formed in the interlayer insulating film, and the source electrode 605 is connected to the data line 2 0 2 - m. The drain electrode 604 is connected to the pixel electrode 402-nm formed on the planarization insulating film. A nematic liquid crystal material 9 2 2 is present between the pixel electrodes 402-n-m and the counter electrode 930 on the counter substrate 912. Further, a black matrix 940 is formed on the counter substrate 912 so as to be partially overlapped with the pixel electrodes 402-n-m. Further, when the light leakage current of the pixel switching elements 4?1-n-m causes a problem, a light shielding layer composed of a Cr film can be formed under the island 602. In the present embodiment, the light leakage current has almost no problem, and with such a configuration, since the mobility of the pixel switching element 401 - n-m is lowered, the configuration in which the Cr film under the island 602 is removed is selected. 7 is a view showing a cross-sectional structure of a portion of the liquid crystal display device 9A corresponding to the BB' line portion of the auxiliary capacitance capacitor 4〇3_n_m, and a capacitance portion connected to the drain electrode 604. The electrode 605 and the capacitor line 203-n are stacked with a gate insulating film interposed therebetween to form a storage capacitor. -25- 200905655 Figure 8 is an enlarged plan view of the vicinity of the light-receiving sensor 305P-1 (first light sensor) and the light-shielding sensor 305D-1 (second light sensor). In addition, in order to easily view the figure, the reduction ratio of vertical and horizontal is not constant. And, the example is the same as Figure 5. The light-receiving sensor 350P-1 is planarly overlapped with the light-receiving opening portion 990-1 indicated by a thick dotted line, and can be irradiated with external light. The light-receiving sensor 305P-1 is composed of four isolated light-receiving portions 305P-1I and adjacent anode regions 350P-1P connected to the wiring SENSE, and a cathode region 305P-connected to the wiring VSH. 1N is composed. The light receiving portion 3 5 0P-1I, the anode region 3 50P-1P, and the cathode region 35 0P-1N are all the same polycrystalline tantalum film islands separated by the difference in doping concentration, and the anode region 35〇Ρ-1Ρ is doped. Compared with the high concentration of boron ions, the cathode region 3 50P-1N is doped with a relatively high concentration of phosphorus ions, and the light receiving portion 350P-1I is only containing boron ions at a very low concentration, and the anode region is 3 50P- 1P, the cathode region 3 50P-1N, and the light receiving portion 3 5 0P-1I are each 1 μηηηι, and the lengths of the light receiving portions 3 5 0P-1I are respectively ΙΟΟΟμηη. The thus received photosensor 3 50 Ρ-1 is a PIN-bonded diode constituting a plurality of parallel connections. The common potential wiring 3 3 5 is disposed on the side of the display region 310 close to the light receiving sensor 3500-1, and the light shielding sensor 350D-1, but is not connected to the light receiving sensor in this embodiment. 3 5 0P-1 and shading sensor 350D-1, in order to avoid the influence of electromagnetic noise, from ΙΟΟμηι configuration. The light-shielding sensor 350D-1 is constituted by four isolated light-receiving portions 350D-1I and an adjacent anode region 350D-1P connected to the wiring VSL, and a cathode region 305D-1N connected to the wiring SENSE. Except that the wiring connecting the cathode and the anode is different, and the plane of the light-receiving opening portion 990-1 is not more than -26-200905655, the other is the same as the light-receiving sensor 3 50P-1 and the light-shielding sensor 3 5 0D-1. Since it is constituted, the above description is omitted. And the 'light-receiving sensors 350P-2 to 350P-5 and the light-receiving sensor 350P-1, and the light-shielding sensors 350D-2 to 350D-5 and the light-shielding sensor 350D-1, except for the respective arrangement positions, The same configuration is omitted, and thus the description is omitted. FIG. 9 is a cross-sectional view showing a part of the liquid crystal display device 910 corresponding to the line C-C. of FIG. 8 in the configuration of the light receiving sensor 350P-1. A backlight light-shielding electrode 611P-1 (first light-shielding electrode) is disposed on the active matrix substrate 1 〇1 via an underlying insulating film, and a light-receiving sensor 305P-1 composed of a thin film polysilicon is sandwiched therebetween. A gate insulating film is formed. As described above, the light-receiving sensor 350-P-1 is a light-receiving portion 3 5 0P-1I at four places and an anode region 3 5 0P-1P adjacent to the wiring VSL, and a cathode region connected to the wiring SENSE. 3 5 0P-1N is composed. A transparent electrode 612P-1 (first transparent electrode) made of an indium oxide-tin thin film (ITO) is disposed above the light-receiving sensor 305P-1 via an interlayer insulating film or a planarizing insulating film. It functions as a shield for the electric field of the light receiving unit 3500P-1I. Above the transparent electrode 612P-1, the nematic liquid crystal material 922 is sealed, and the counter electrode 930 on the counter substrate 912 is disposed. Further, depending on the position where the photosensor 505P-1 is disposed, the sealing material 923 may be disposed instead of the nematic liquid crystal material 922. The light-receiving opening portion 990-1 is formed by removing the black matrix 940 on the counter substrate 91 2 by a portion. Although not shown, since the light-receiving opening portion is not present on the light-shielding sensor 350D-1, the black matrix 940 is not removed. The upper surface of the opposite substrate 912 is irradiated with the external light LA, and the other side is -27-200905655, and the light from the backlight unit 926 (backlight LB) is irradiated from below the active matrix substrate 101. Further, although it is not implemented in the present embodiment, an optical correction layer may be placed in the light-receiving opening portion 9 9 0 - 1 . For example, one or a plurality of color materials constituting the color filter (corresponding to the pixels formed on the counter substrate 9 1 2) may be formed by overlapping with the light-receiving opening portion 990-1 to make the luminosity characteristic. More consistent with the light sensor 350P-1. For example, when the color material corresponding to the green pixel is superimposed on the light receiving opening portion 990-1, since the short wavelength and the long wavelength side are removed, the spectral characteristics of the light receiving sensor 3 50P-1 are more than the visual sensitivity. The spectral characteristics are more short-wavelength or longer-wavelength, and can be corrected. Other than the anti-reflection film, the dry layer, the polarizing layer, and the like, the light-receiving opening portion 990-1 may be overlapped as needed. Further, although not shown in the figure, the upper polarizing plate 924 may be overlapped or removed from the light receiving opening portion 900-1. The overlap is less noticeable by the light-receiving opening portion 990-1, but if it is removed, the light sensitivity is improved. In the present embodiment, the liquid crystal display device 910 performs common electrode inversion driving (common AC driving) for applying an inversion signal to the common potential wiring 353 for low power consumption, and therefore an amplitude of 0 V is applied to the counter electrode 930. ~5V, frequency 14KHz AC signal. However, the electromagnetic wave generated by the counter electrode 930 is shielded by the transparent electrode 6 1 2P-1, so that the noise is hardly loaded into the photodetector wop when the counter electrode 930 is reversed. At the same time, the backlight shading electrode 611P_;1 has a function as a shield for electromagnetic noise from below. Fig. 1A is a cross-sectional view showing a part of a liquid crystal display device 910 of a line portion corresponding to the line D_D of Fig. 8. The backlight -28 - 200905655 formed on the underlying insulating film is separated from the backlight electrode 6111)_1 (the second light-shielding electrode) by the light-shielding electrode gap 6UG, and is given Individual potentials. Further, the transparent electrode 612P-1 (first transparent electrode) and the transparent electrode 612D-1 (second transparent electrode) formed on the planarizing insulating film are also separated from each other by the transparent electrode gap 612G, and are given respective potentials. . The backlight light-shielding electrode 611P-1 and the transparent electrode 612P-1 are connected to each other via the intermediate electrode 613P-1 and a contact hole formed in the gate insulating film, the interlayer insulating film, and the planarizing insulating film, and are finally connected to the wiring PBT. The backlight light-shielding electrode 6 1 1 D -1 and the transparent electrode 6 1 2 D -1 are connected to each other via the intermediate electrode 6 1 3 D -1 and a contact hole formed in the gate insulating film, the interlayer insulating film, and the planarizing insulating film. It is finally connected to the wiring DBT. Here, the light-shielding electrode gap 6 1 1 G and the transparent electrode gap 6 1 2G do not overlap each other in the vertical direction of the active matrix substrate 1 〇 1 and the opposite substrate 9 1 2 . According to this configuration, the unshielded area of the planar upper and lower sides becomes unnecessary, so that the electromagnetic noise entering from the gap is difficult to spread left and right, and the reduction in the shielding performance due to the gap can be alleviated. Further, a gap light blocking body 610 made of a molybdenum thin film (Mo) is formed so as to overlap the light-shielding electrode gap 6 1 1 G. Thereby, the backlight light entering from the light-shielding electrode gap 6 1 1 G can be greatly reduced to be multi-reflected at the interface of various insulating films or glass, and the like can be formed to be lost to the light-receiving sensor 3 0 0 P - 1 or the light-shielding sensation. The ratio of the detector 3 5 0 D -1. The equivalent circuit of the light-receiving sensor 3 5 0P-1 to 3 5 0P-6 and the light-shielding sensor 3 5 0D-1 to 3 5 0D-6 configured as described above is shown in Fig. 11. Each of the light-receiving sensors 350P-1 to 350P-6 and the light-shielding sensors 350D-1 to 350D-6 are respectively connected in parallel -29-200905655 with four PIN diodes. Further, each of the light receiving sensors 350P_1 to 350p-6 is also connected in parallel with each other, and the light blocking sensors 3500-1 to 350D_6 are also connected to each other. Therefore, finally Figure 11 is equivalent to the circuit diagram of Figure 12. That is, the shading sensors 350D-1 to 3500D-6 are PIN diodes having a channel width of 24000 μm and a channel length of 10 μm, the anode of which is connected to the wiring VSL, and the cathode of which is connected to the wiring SENSE. Further, the backlights 611D-1 to 611D-6 and the transparent electrodes 612D-1 to 612D-6 which are planarly overlapped with the light-shielding sensors 350D-1 to 350D-6 are connected to the wiring DBT. The light-receiving sensor 3 5 0P-1 to 3 5 0P-6 is a PIN diode having a channel width of 24000 μm and a channel length of 10 μm, the anode of which is connected to the wiring SENSE, and the cathode thereof is connected to the wiring VSH. Further, the backlight light-shielding electrodes 611P-1 to 611P-6 and the transparent electrodes 612P-1 to 612P-6 which are planarly overlapped with the light-receiving sensors 530P-1 to 350P-6 are connected to the wiring PBT. FIG. 13 is a configuration of the light-receiving sensor 3 5 0P-1 to 3 50P-6 and the light-shielding sensor 3 5 0D-1 to 3 5 0D-6 when a certain external light illuminance LX is irradiated onto the liquid crystal display device 910. The characteristic curve of the PIN diode. The horizontal axis is the bias voltage Vd (=anode potential - cathode potential), and the vertical axis is the amount of current Id flowing between the anode and the cathode. The graph (A) shown by the solid line is the characteristic of the light-receiving sensor 3 0 0P-1 to 3 5 0P-6, and the graph shown by the broken line (B) is the shading sensor 35〇Dl~3. 5 0D-6 characteristics. Thus, in the forward bias region (Id > 0), the two are approximately the same, but in the reverse bias region (ld <0) is a graph (B) of the light receiving sensor 3 50P-1 to 35 〇 P-6 having a large absolute current. This is because the shading sensor 3 5 0 D -1 to 3 5 0 D - 6 is not irradiated with external light, so only the amount of thermal current Ileak caused by the temperature will flow, but if it is configured to receive light sensing -30-200905655 When the light receiving unit 3 5 0P-1I to 3 50P- 61 of the PIN diode of the 3 0 0P-1 to 3 50P-6 emits light, a carrier pair is generated and the photoelectric flow rate Iphoto flows, so that the light is sensed. The current of 350P-1~3 50P-6 flows the sum of photoelectric flow and thermal current, Iphoto + Ileak. Here, the amount of thermal current neak means the reverse bias region on the left side of Fig. 13 (Id) In <〇), when a voltage is applied to a current at a negative V position, the semiconductor generates electrons and holes by temperature, which is a current flowing. The amount of thermal current Ileak is a line showing the dependence of Vd (=anode potential-cathode potential) at -5.0$乂 (1$-1.5, which can approximate the inclination of 1^(1^>0). Here, KA It is a function of temperature, and once the temperature rises, it exponentially rises. In this Vd region (Vd = -5.0SVdg-1.5), it flows through the light-receiving sensor 3 5 0P-1~3 5 0P-6. The photoelectric flow rate Iphoto has a substantially constant 値, which is proportional to the external illuminance LX (hereinafter referred to as Iphoto = LXxk). Therefore, the current flows to the light-receiving sensor 3 5 0P-1 to 3 50P-6 (graph (A) The currents flowing to the shading sensors 350D-1 to 350D-6 (graph (B)) are straight lines at an inclination of -(ΚΑ>0) in the region of -5.0 SVdS-1.5. The shading sensor 3 5 0D-1~3 5 0D-6 and the Vd of the light receiving sensor 3 5 0P-1~3 5 0P-6 can form the bias voltage in the same way, that is, if the wiring SENSE is The potential VSENSE is set to the middle of the potential VVSH of the wiring VSH and the potential VVSL of the wiring VSL (VVSH + VVSL) + 2, and flows to the light receiving sensors 350P-1 to 350P-6 and the light blocking sensor 350D-1. 350D-6 thermal current Ileak is exactly the same. At this time, the amount of current flowing to the wiring VSH (= the amount of current flowing to the light-receiving sensor 3 5 0P-1 to -31 - 200905655 350P-6) is Iphoto + Ileak, the current flowing to the wiring VSL The amount (=the amount of current flowing to the shading sensors 350D-1 to 350D-6) is "Heak'. Therefore, the amount of current flowing from the Kirchhoff's first rule to the wiring SΕΝSE is Iphoto = LX X k 5 and external illuminance. In addition, in the case of the embodiment, the light-receiving sensor is connected to the high-potential side, and the light-shielding sensor is connected to the low-potential side, but of course, even in other cases, the conclusion is the same as in Fig. 14. It is a circuit diagram of the detection circuit 360. The wiring v CHG, the wiring RST, the wiring VSL, the wiring VSH, and the wiring OUT are connected to the signal input terminal 320, and the wiring VSL, the wiring VSH, the wiring SENSE, the wiring PBT, and the wiring DBT wiring are Connected to the light-receiving sensor 3 5 0P-1 to 3 50P-6 and the light-shielding sensor 3 5 0D-1 to 3 5 0D-6. Here, the wiring VCHG, the wiring VSL, and the wiring VSH are connected to the outside. The DC power supply supplied by the power supply circuit 784, the VCHG wiring is the supply potential VVCHG (= 2.0V), VSL The line is the supply potential V V S L (= 0.0 V ), and the V S Η wiring is the supply potential VVSH (= 5.0V). Further, the potential VVSL of the VSL wiring is the GND of the liquid crystal display device 910. The wiring SENSE is connected to each end of the first capacitor C1 and the third capacitor C3. Further, it is connected to the drain electrode of the initial charging transistor NC. The other end of the third capacitor C3 is connected to the wiring VSL. The other end of the first capacitor C1 is connected to the node A. The initial charge transistor NC source electrode is connected to the wiring VCHG and supplies a potential VVCHG (= 2.0V). The gate electrode of the initial charging transistor NC is connected to the wiring RST. The node A is a gate electrode further connected to the first N-type transistor-32-200905655 N 1 , a gate electrode of the first P-type transistor P 1 , and a drain electrode of the reset transistor NR, and is connected to One end of the second capacitor C2. The other end of the second capacitor C2 is connected to the wiring RST. The drain electrode of the first N-type transistor N 1 , the drain electrode of the first P-type transistor P 1 , and the source electrode of the reset transistor NR are connected to the node B, and the node B is further connected to the 2N. The gate electrode of the transistor N2 and the gate electrode of the second P-type transistor P2. The drain electrode of the 2N-type transistor N2 and the drain electrode of the 2P-type transistor P2 are connected to the node C, and the node C is the gate electrode and the 3P-type electrode which are further connected to the 3N-type transistor N3. The gate electrode of crystal P3. The drain electrode of the 3N-type transistor N3 and the drain electrode of the 3P-type transistor P3 are connected to the node D, and the node D is the gate electrode further connected to the 4N-type transistor N4 and the 4P-type electric The gate electrode of crystal P4. The drain electrode of the 4N-type transistor N4 and the drain electrode of the 4P-type transistor P4 are connected to the wiring OUT, and the wiring OUT is a drain electrode which is further connected to the 5N-type transistor N5. The gate electrode of the 5N-type transistor N5 and the gate electrode of the 5P-type transistor P5 are connected to the wiring RST, and the drain electrode of the 5th P-type transistor P 5 is connected to the 4P-type transistor P4 Source electrode. The source electrodes of the first to fifth N-type transistors N1 to N 5 are connected to the wiring V S L ' supply potential VVSL (= 0V). Further, the source electrodes of the first to third P-type transistors P1 to P3 and the fifth P-type transistor P 5 are connected to the wiring V S Η ' supply potential VVSH (= + 5 V). Further, the detection circuit 360 also includes a self-correcting voltage circuit 361' that automatically corrects the potential applied to the line PBT and the wiring DBT of the -33-200905655 line by the critical threshold voltage (Vth) of the transistor. The self-correcting voltage circuit 361 is that the drain electrodes and the gate electrodes of the sixth N-type transistor N11 and the sixth P-type transistor PI 1 are respectively connected to the wiring PBT, the seventh-type transistor N21 and the seventh-type transistor P21. The drain electrode and the gate electrode are respectively connected to the wiring DBT, and the source electrodes of the sixth N-type transistor N11 and the 7N-type transistor N21 are connected to the wiring VSL to supply the potential VVSL (= 0V), The source electrodes of the 6P type transistor PI 1 and the 7P type transistor P21 are connected to the wiring VSH, and are supplied with a potential VVSH (= + 5 V). Further, the detecting circuit 366 is covered with a shield electrode 3 69 formed of the same film as the indium tin oxide film (ITO) constituting the pixel electrode 402_n-m. The shield electrode 3 69 is connected to the GND potential of the liquid crystal display device 9 10 via the wiring VSL, and has a function as a shield for electromagnetic noise. Here, in the present embodiment, the channel width of the first N-type transistor N1 is ΙΟμπα. 'The channel width of the 2nd transistor Ν2 is 35μιη, the channel width of the 3rd transistor Ν3 is ΙΟΟμιη, and the channel width of the 4th transistor Ν4 is 150μηι 'The channel width of the 5th transistor Ν5 is 150μηι, The channel width of the 6Ν-type transistor NU is 4μιη, and the channel width of the 7th-type transistor Ν2 1 is 2〇〇μπι 'The channel width of the first-type transistor Pi is l (^m, the channel of the second-type transistor Ρ2) The width is 35 μm, the channel width of the 3rd transistor Ρ3 is ΐΟΟμιη', the channel width of the 4th transistor Ρ4 is 300 μm, the channel width of the 5th transistor ρ5 is 300 μm, and the channel width of the 6th transistor Ρ11 It is 2 00μηι 'the channel width of the 7th transistor Ρ21 is 4μηι, the channel width of the reset transistor NR is 2μηη, the channel width of the initial charging transistor NC is -34- 200905655 5 0μηι, the channel of all N-type transistors Length is 8μιη The channel length of all p-type transistors is 6μηη 'The mobility of all N-type transistors is 80cm2/VSec, and the mobility of all Ρ-type transistors is 6〇em2/Vsec'. The criticality of all N-type transistors. The 値 voltage (Vth) is +. 1·〇ν, the critical 値 voltage (Vth) of all P-type transistors is -1.0V, the capacitance of the first capacitor ci is IpF, and the capacitance of the second capacitor C2 is i〇〇 fF, the capacitance of the third capacitor C3 is i 〇〇 pF. The wiring RST is a pulse wave having a potential amplitude of 0 - 5 V, which is 5 1 〇 m seconds per cycle, and is maintained at a high potential between 1 〇〇 μ second and a pulse length ( 5 V), the remaining 509.9 m seconds is maintained at the Low potential (0 V). Once the RST wiring forms High (5 V) every 5 10 m seconds, the initial charging transistor NC and the reset transistor NR are turned ON, and the wiring is SENSE. The potential (2.0 V) of the charged VCHG wiring is short-circuited between the node A and the node B. Since the first N-type transistor N 1 and the first P-type transistor Ρ 1 constitute an inverter circuit, the IN/OUT of the inverter circuit It will be short-circuited. At this time, the potentials of the node A and the node B eventually reach the potential VS shown by the following equation (for detailed calculation, for example, reference K) Ang Leblebici "CMOS Digital Integrated Circuits" Third Edition P206, etc. [Number 1] VS =
x (WSH - VVSL + Vthp)x (WSH - VVSL + Vthp)
-35- 200905655 在此，Wn:第IN型電晶體N1的通道寬，Ln:第ιΝ 型電晶體N1的通道長，μη:第IN型電晶體N1的移動度 ，Vthn :第1N型電晶體N1的臨界値電壓，Wp :第1P型 電晶體P1的通道寬’ Lp:第1P型電晶體pi的通道長，μρ :第IP型電晶體Ρ1的移動度，Vthp :第IP型電晶體ρ! 的臨界値電壓，因此在本實施例中是計算成VS = 2.5(V)。 另外，配線RST爲High(5V)的期間是第5N型電晶體N5 爲形成ON，第5P型電晶體P5爲形成OFF，因此OUT配 線是〇 V。 一旦RST配線在100μ秒後形成Low(OV)，則復位電 晶體NR會形成OFF，節點A與節點B會被電性切離。此 時，以第1 N型電晶體N 1及第1 P型電晶體P 1所構成的倒 相電路，若節點A的電位比VS低則對節點B輸出比VS 高的電位，若節點A的電位比VS高，則對節點B輸出比 VS低的電位。第2N型電晶體N2與第2P型電晶體P2及第 3N型電晶體N3與第3P型電晶體P3亦分別構成倒相電路 ，同樣若輸入段的電位比VS低，則輸出比VS高的電位 ，若輸入段的電位比VS高’則輸出比VS低的電位。此 時，輸出段的電位與VS的差要比輸入段的電位與VS的 差更大，接近配線VSH的電位VVSH( = + 5V)或配線VSL 的電位VVSL( = 0V)。結果，若節點A的電位比VS低，則 節點D是大致形成VSH配線的電位VVSH( = + 5V)’若節 點A的電位比V S高，則節點D是大致形成V S L配線的 電位VVSL( = 0V)。由於第4N型電晶體N4及弟5N型電晶 -36- 200905655 體N5、第4P型電晶體P4及第5P型電晶體P5是構成NOR 電路，因此在RST配線的電位爲Low(OV)的期間，若節 點D爲High( + 5V)，則將Low(OV)輸出至OUT配線，若 節點D爲Low(OV)，則將High( + 5V)輸出至OUT配線。 亦即，在RST配線的電位爲Low(OV)的期間，若節點A 的電位比VS低，則往OUT配線的輸出是形成Low(OV)， 若節點A的電位比VS高，則往OUT配線的輸出是形成 High(+5V)。 節點A如前述般，配線RST形成Low(OV)，復位電 晶體NR爲OFF，節點A與節點B會被電性切離，但同時 藉由第2電容器C2的結合，和配線RST同時電位下降。在 此若第1電容器C1的電容CCl(=lpF)比第2電容器C2的電 容CC2(=100fF)及第1N型電晶體N1、第1P型電晶體P1、 復位電晶體NR的閘極·汲極間電容（在本實施例皆爲1 0fF 以下）更充分大，且復位電晶體NR的寫入阻抗與第1電容 器C1的電容的積（在本實施例是約1μ秒）要比配線RST的 電位下降期間（在本實施例是1 00η秒）更充分大，則當配線 RST形成Low(OV)時（以下記爲時間t = 0)之節點A的電位（ 以下記爲VA(t))是用以下的式子來表示。-35- 200905655 Here, Wn: the channel width of the IN-type transistor N1, Ln: the channel length of the ι-type transistor N1, μη: the mobility of the IN-type transistor N1, Vthn: the 1N-type transistor The critical 値 voltage of N1, Wp: the channel width of the first P-type transistor P1 'Lp: the channel length of the first P-type transistor pi, μρ: the mobility of the IP-type transistor Ρ1, Vthp: the IP-type transistor ρ The critical 値 voltage is therefore calculated to be VS = 2.5 (V) in this embodiment. In the period in which the wiring RST is High (5 V), the fifth N-type transistor N5 is turned ON, and the fifth P-type transistor P5 is turned OFF. Therefore, the OUT wiring is 〇 V. Once the RST wiring forms Low (OV) after 100 μsec, the reset transistor NR is turned OFF, and the node A and the node B are electrically disconnected. In this case, the inverter circuit including the first N-type transistor N 1 and the first P-type transistor P 1 has a potential higher than VS when the potential of the node A is lower than VS, and the node A outputs a potential higher than VS. If the potential is higher than VS, the node B outputs a potential lower than VS. The second N-type transistor N2 and the second P-type transistor P2, the third N-type transistor N3, and the third P-type transistor P3 also constitute an inverter circuit, respectively. Similarly, if the potential of the input section is lower than VS, the output is higher than VS. The potential, if the potential of the input section is higher than VS, outputs a potential lower than VS. At this time, the difference between the potential of the output section and VS is larger than the difference between the potential of the input section and VS, which is close to the potential VVSH (= + 5V) of the wiring VSH or the potential VVSL (= 0V) of the wiring VSL. As a result, if the potential of the node A is lower than VS, the node D is a potential VVSH (= + 5V) which substantially forms the VSH wiring. If the potential of the node A is higher than VS, the node D is a potential VVSL which substantially forms the VSL wiring (= 0V). Since the 4N-type transistor N4 and the 5N-type transistor-36-200905655 body N5, the 4P-type transistor P4, and the 5P-type transistor P5 constitute a NOR circuit, the potential of the RST line is Low (OV). During the period, if node D is High (+ 5V), Low (OV) is output to the OUT wiring, and if node D is Low (OV), High (+ 5V) is output to the OUT wiring. In other words, when the potential of the RST line is Low (OV), if the potential of the node A is lower than VS, the output to the OUT line is Low (OV), and if the potential of the node A is higher than VS, the line is turned to OUT. The output of the wiring is formed High (+5V). As described above, the wiring RST forms Low (OV), the reset transistor NR is OFF, and the node A and the node B are electrically disconnected, but at the same time, the second capacitor C2 is combined, and the wiring RST is simultaneously lowered. . Here, the capacitance CCl (= lpF) of the first capacitor C1 is larger than the capacitance CC2 (= 100 fF) of the second capacitor C2, and the gates of the first N-type transistor N1, the first P-type transistor P1, and the reset transistor NR. The interelectrode capacitance (10 fF or less in the present embodiment) is sufficiently larger, and the product of the write impedance of the reset transistor NR and the capacitance of the first capacitor C1 (about 1 μsec in this embodiment) is larger than the wiring RST. The potential drop period (100 ns in this embodiment) is sufficiently large, and the potential of the node A when the wiring RST forms Low (OV) (hereinafter referred to as time t = 0) (hereinafter referred to as VA(t) ) is expressed by the following formula.
[數2] VA(i = 0) = VS CC2ca x(WSH-WSL) -37- 200905655 在本實施例是形成VA(t = 0) = 2.0V。此時，施加於受 光感測器3 5 0P-1的偏壓是Vd = -3.0V，施加於遮光感測器 3 5 0D-1的偏壓是Vd = -2.0V。由圖13的説明可明確得知， 此時，構成受光感測器3 5 0P-1與遮光感測器3 5 0D-1的PIN 二極體的熱電流量Ileak的差是以KAxl.O來表示。因此， 在配線SENSE是流動對應於照射至受光感測器3 5 0P-1的 外光之光電流量Iphoto加上電流量KAxl.O的電流。在此 ，若KA<<IPhoto，則流至配線 SENSE的電流量可僅與 Ipho to近似，可除去熱電流的寄與。本實施例是動作保證 温度上限70°C的KA與照度10勒克斯的Iphoto形成相等。 因此，若爲外光照度1 00勒克斯以上，則在動作保證温度 範圍内可有效地除去熱洩漏。 在此，外光與Iphoto的關係是如前述般，在此偏壓 條件下，外光會與照射受光感測器3 5 0P -1的外光照度LX 成比例，不依存於Vd，形成Iphoto = LX.k(k是一定的係 數）。一旦RST配線形成Low(OV)，則節點A爲浮動狀態 ，因此若無視第2電容器C2的電容CC2及第1N型電晶體 N 1、第1 P型電晶體p 1的閘極·源極間電容，則大致實效 性的電容是只形成第3電容器C3的電容CC3，而配線 SENSE的電位VSENSE是變化成以下的式子所示。 [數3] VSENSE {t) = WCHG + —xk CC3 -38- 200905655 另外，在此爲了説明’是無視在受光感測器3 50P-1及 遮光感測器3 50D-1、及引繞配線的附加電容來進行説明。 該等的附加電容部份是只要加算於上述的CC3即可。並且 ，在受光感測器3 50P-1及遮光感測器3 50D-1、及引繞配線 的附加電容爲充分大時，即使無第3電容器C3也可以。因 此，CC3的値是由受光感測器3 5 0P-1及遮光感測器3 5 0D-1 、及引繞配線的附加電容來決定下限。 VA(t)是一但VSENSE(t)變化，則在電容結合下進行 同電位部份變化。因此，節點A的電位VA是用以下那樣 的式子來表不。 [數4]VA(t) = VS- X (VVSH - VVSL) + LX χ CC1 CC3 在此形成VA(t) = VS的時間t0是用以下那樣的式子來 表示 [數5] CC2xCC3 亦即，在時間to，OUT輸出是朝Low(0V) — High(5V) 反轉’由此時間t0容易求取外光照度lx。 -39- 200905655[Equation 2] VA(i = 0) = VS CC2ca x(WSH-WSL) -37- 200905655 In this embodiment, VA(t = 0) = 2.0V is formed. At this time, the bias voltage applied to the photodetector 3500-15-1 is Vd = -3.0 V, and the bias applied to the shading sensor 350D-1 is Vd = -2.0 V. As is clear from the description of Fig. 13, at this time, the difference between the thermal current amount Ileak of the PIN diode constituting the light-receiving sensor 3500P-1 and the light-shielding sensor 3500D-1 is KAxl. Said. Therefore, the wiring SENSE is a current that flows in correspondence with the photocurrent Iphoto of the external light irradiated to the light receiving sensor 3500-1-1 plus the current amount KAx1.O. Here, if KA<<IPhoto, the amount of current flowing to the wiring SENSE can be approximated only to Ipho to, and the transfer of the thermal current can be removed. In the present embodiment, the KA of the operation guarantee temperature upper limit of 70 ° C is equal to the I photo of the illumination 10 lux. Therefore, if the external illuminance is 100 lux or more, heat leakage can be effectively removed within the operation guaranteed temperature range. Here, the relationship between the external light and Iphoto is as described above. Under this bias condition, the external light is proportional to the external illuminance LX of the illumination receiving sensor 3500P-1, and does not depend on Vd, forming Iphoto = LX.k (k is a certain coefficient). When the RST line is formed as Low (OV), the node A is in a floating state. Therefore, if the capacitance CC2 of the second capacitor C2 and the first N-type transistor N 1 and the gate and source of the first P-type transistor p 1 are ignored, In the capacitor, the substantially effective capacitor is formed only by the capacitance CC3 of the third capacitor C3, and the potential VSENSE of the wiring SENSE is changed to the following equation. [Number 3] VSENSE {t) = WCHG + —xk CC3 -38- 200905655 In addition, here, in order to explain 'is ignoring the light-receiving sensor 3 50P-1 and the light-shielding sensor 3 50D-1, and the wiring Additional capacitors are used for illustration. These additional capacitor parts are added to CC3 as described above. Further, when the light-receiving sensor 315P-1, the light-shielding sensor 305D-1, and the additional capacitance of the wiring are sufficiently large, the third capacitor C3 may be omitted. Therefore, the lower limit of CC3 is determined by the light sensor 305P-1 and the light-shielding sensor 305D-1, and the additional capacitance of the wiring. When VA(t) is a change in VSENSE(t), the same potential portion is changed under the combination of capacitance. Therefore, the potential VA of the node A is expressed by the following equation. [Number 4] VA(t) = VS- X (VVSH - VVSL) + LX χ CC1 CC3 The time t0 at which VA(t) = VS is formed is expressed by the following equation [5] CC2xCC3 At time to, the OUT output is inverted to Low (0V) - High (5V). From this time t0 is easy to obtain the external illumination lx. -39- 200905655
檢測電路3 60是RST配線爲Low(OV)的期間’節點A 會形成浮動狀態’在此一旦電磁雜訊進入而節點A的電 位變化，則會錯誤動作。所以，電磁雜訊的防止極重要’ 因此配置屏蔽電極369。 本構成之類的橫向構造的PIN型二極體或PN型二極 體是對於垂直方向的電場而言會有光電流量IPh〇to變化 的問題。配合本實施例具體而言’連接至配線PBT的透 明電極612P-1〜612P-6及背光遮光電極611P-1〜611P-6的 電位（以下稱爲VPBT)會影響受光感測器350P-1〜350P-6 的特性，連接至配線DBT的透明電極612D-1〜612D-6及 背光遮光電極611P-1〜611P-6的電位（以下稱爲 VDBT)會 影響遮光感測器3 5 0D-1〜3 50D-6的特性。 圖15是有關構成受光感測器350P-1〜350P-6及遮光感 測器3 5 0D-1〜3 5 0D-6之二極體的特性，將遮光電極（及透 明電極）-陰極電極間的電位差作爲橫軸，將P IN二極體的 23°C、偏壓Vd = -2.5V、外光1 000勒克斯的條件之陽極·陰 極間電流作爲縱軸時的曲線圖。就本實施例而言，橫軸是 在受光感測器3 5 0P-1〜3 50P-6相當於VPBT-VVSH，在遮 光感測器350D-1〜350D-6相當於VDBT-VSENSE。 實線（A)是在測定顯示峰値電流的橫軸的電壓値爲複 數取樣數中，顯示中央値的取樣結果，點線（B)同樣的是 在測定顯示峰値電流的橫軸的電壓値爲複數取樣測定中， 顯示最大値的取樣結果’虛線（C)是同樣的在測定顯示峰 値電流的橫軸的電壓値爲複數取樣測定中，顯示最小値的 -40- 200905655 取樣結果。可知皆於峰値具有某適當電壓（以下將此光電 流形成峰値的遮光電極（及透明電極）-陰極電極間的電位 差稱爲VMAX)。這是因爲若遮光電極（及透明電極）-陰極 電極間的電位差爲適當電壓，則PIN接合二極體的受光部 (圖8的受光部3 5 0P-1I、受光部3 5 0D-1I相當）會空乏化而 於全域藉由光來激勵載流子，相對的，若遮光電極（及透 明電極）-陰極電極間的電位差比適當電壓更正，則受光部 會N型化，同樣的若比適當電壓更負，則受光部會P型 化，空乏層的寬會變窄，藉由光來激發載流子的面積會被 限制。因此，爲了充分取得光電流，必須適當地控制 VPBT，VDBT，使能夠形成 VMAX點。由圖15的曲線圖 (A)可知，在製造不均的中央値中，最好遮光層及透明電 極的電位是形成從施加於陰極電極的電位低1.4V程度的 電位。但，比較曲線圖（A)、曲線圖（B)及曲線圖（C)可知 ，實際因製造不均，適當電位VMAX會若干偏差。這是 因爲多晶矽薄膜中的缺陷準位或底層絶緣膜·閘極絶緣膜 界面的固定電荷等在製造工程不均所發生的現象。 圖16是表示在同一基板上作成的薄膜電晶體與PIN二 極體的相關之散布圖。將N型薄膜電晶體的臨界値電壓 (VthN)與P型薄膜電晶體的臨界値電壓（VthP)的平均設於 橫軸，將使PIN二極體的光電流形成最大的適當電位 VMAX設於縱軸。由圖16可知一般，薄膜電晶體的臨界値 及使PIN二極體的光電流形成最大的適當電位VMAX是 具有強的正的相關。本實施例，如圖1 6曲線圖（A)所示， -41 - 200905655 遮光電極（及透明電極）相較於陰極電極電位 較低時光電流是顯示最大値（VMAX) ’此時白 晶體的臨界値電壓（VthN)是+1.0V、及P型 臨界値電壓（VthP)是-1.0V ’爲製造不均中 在製造不均下若VthN與VthP的平均爲偏ί 也偏移1 V，顯示大致y = X (點線）的正的相關 以上，在本實施例是使用根據薄膜電 (Vth)來自己補正電壓，對配線PBT及配線 之自己補正電壓電路3 6 1。就本實施例的製 均値而言，VthN = +1.0、VthP = -l.〇，此時自 路3 6 1是對配線P B T施加3 . 6 V，對配線D B T 受光感測器3 5 0P-1〜3 5 0P-6，陰極是與配線 爲5.0V，因此背光遮光電極61 1P-1〜61 1P 612P-1與陰極的電位差是形成-1.4V，此爲 的最適電位（VMAX)。在製造不均下電晶體 ，例如若 VthN = +l .5、VthP = -0.5則在配線 4.1 V，在配線D B T被施加1 . 9 V。同樣地例斑 、VthP = -l .5則在配線PBT被施加3.1 V，在| 加〇 . 9 V。無論哪種情況，皆是一旦電晶體的 則隨之被施加於配線PBT與配線DBT的電 因此經常光電流會大致取得最大。 圖17是表示圖16的自己補正電壓電路3 之第2自己補正電壓電路36Γ的電路圖。第 N31的閘極電極及汲極電極、第8P型電晶體 ，在1.4V程度 5 N型薄膜電 薄膜電晶體的 的平均狀態， 多 1 V 貝!J VMAX 〇 晶體的臨界値 D B T施加電壓 造不均中的平 己補正電壓電 施加1.4V。在 VSH連接， -6及透明電極 可取得光電流 的特性會變動 PBT被施加 】若 VthN = + 0.5 §己線DBT被施 臨界値變動， 位也會變動， 6 1的別的構成 ;8N型電晶體 P 3 1的閘極電 -42- 200905655 極及汲極電極是全部被連接至節點E。並且，節點E也被 連接至第9P型電晶體P41的閘極電極、及第9N型電晶體 N41的閘極電極。第9P型電晶體P41的源極電極是被連接 至配線PBT，汲極電極是被連接至配線VSL。而且，第 10P型電晶體P42的汲極電極是被連接至配線PBT，源極 電極是被連接至配線VSH，閘極電極是被連接至調整電源 配線Voffl。第9N型電晶體N41的源極電極是被連接至配 線DBT，汲極電極是被連接至配線VSH。第10N型電晶體 N42的汲極電極是被連接至配線DBT，源極電極是被連接 至配線VSL，閘極電極是被連接至調整電源配線Voff2。 調整電源配線Voffl及調整電源配線Voff2是經由信號輸 入端子3 20來由外部電源電路7 84所供給的電源，調整電源 配線Voffl是被設定成3.9V，調整電源配線Voff2是被設 定成1.1V。在此，第8N型電晶體N31的通道寬是ΙΟμπι， 第8Ρ型電晶體Ρ3 1的通道寬是ΙΟμπι，第9Ν型電晶體Ν41 的通道寬是ΙΟΟμηι，第10Ν型電晶體 Ν42的通道寬是 ΙΟΟμιη，第9Ρ型電晶體Ρ41的通道寬是ΙΟΟμιη，第10Ρ型 電晶體Ρ42的通道寬是ΙΟΟμιη，全部的Ν型電晶體的通道 長是8 μιη，全部的Ρ型電晶體的通道長是6μιη，全部的Ν 型電晶體的移動度是80cm2/Vsec，全部的Ρ型電晶體的移 動度是60cm2/Vsec。若如以上那樣構成，則由第2自己補 正電壓電路3 6 1'輸出至配線D B T的電壓及輸出至配線Ρ B T 的電壓與薄膜電晶體的臨界値電壓（Vth)的關係是與圖14 的自己補正電壓電路361時完全同様。 -43- 200905655 與圖14的自己補正電壓電路361的構成作比較，圖17 的第2自己補正電壓電路36Γ的構成是在調整調整電源配 線Voffl及調整電源配線Voff2的電位之下，可不變更主 動矩陣基板101來調整輸出至配線DBT的電壓及輸出至配 線PBT的電壓的點爲優點。另一方面，因爲元件數、配 線數、端子數會増大，所以由電路面積的觀點來看形成不 利的構成，因此到底要採用哪一個，只要根據各個的長短 處來任意地決定即可。又，本發明並非限於該等的電路構 成，其他，使用既知的所有電壓電路來取代自己補正電壓 電路361也無妨。又，亦可將配線DBT及配線PBT經由信 號輸入端子320來連接至外部電源電路784，由外部電源電 路784來供給適當的電位。此情況，可將自外部電源電路 784輸出的電位的設定値予以按每個製品寫入EEPR0M等 ，對製品不均進行控制。 另外，在此次的實施例是以連接至受光感測器3 5 OP-1 〜3 5 0 P - 6及遮光感測器3 5 0 D -1〜3 5 0 D - 6的電源配線 V S Η 及電源配線V S L作爲檢測電路3 6 0的驅動電源，但該等亦 可爲別的電源配線。若如此地構成，則配線或端子數會増 大，但另一方面具有檢測電路360的動作雜訊難以對受光 感測器350Ρ-1〜350Ρ-6及遮光感測器350D-1〜350D-6造成 影響的利點。 在本實施例是中央運算電路781會監視端子OUT的信 號’由反轉後的時間to首先取得離散値V 1 0。離散値V 1 0 會被任意的次數取樣，取得其平均値VI 0_。由VI 0_來參 -44 - 200905655 〃照參照表785 ’取得對應於v1〇_的適當的背光單元926的 電壓設定値V20。中央運算電路781會將此V20値送至外 部電源電路784 ’變更背光單元926的亮度。藉此，液晶顯 示裝置910的全白顯示時亮度會變化，對於使用者而言在 抑止過剰的亮度下使視認性提升的同時，可抑止消費電力 的増大。 ΪΪ #實施例’外部光的檢出照度與背光亮度的關係是 如圖18那樣設定。至檢出照度3〇〇(勒克斯）爲止是使背光 的照度緩慢地上升，在30〇勒克斯〇ux)以上是比較增大傾 斜度來提高照度。在檢出照度2000勒克斯下亮度是形成 MAX ’以後是形成相同的狀態。一旦如此地設定，則外光 會在3 00勒克斯以下，周圍會極暗，在使用者的瞳孔打開 時以不刺眼的程度壓制背光，在3〇〇勒克斯〜20〇〇勒克斯 的外光映入液晶面板的區域是配合周圍的明亮度來使亮度 急速上升而使視認性不會降低。 另一方面’如本實施例那樣非透過型，使用半透過型 液晶時只要如圖1 9那樣即可。至外光照度5000勒克斯爲止 是同樣，但就以上而言因爲只要反射部份便可形成充分的 視認性’所以將背光完全地OFF，可節約消費電力，因此 特別是在屋外使用時可大幅度地延長所搭載的電子機器的 電池驅動時間。 當然，此控制曲線（curve)爲一例，亦可按照用途，設 定任何的曲線，爲了抑止閃光，亦可使曲線具有磁滯現象 。又，亦可不是在每次測定進行亮度調整，而是測定複數 -45- 200905655 次數，取平均或中央値來調整亮度。 以光電電晶體來構成受光感測器350P-1〜350P-6及遮 光感測器350D-1〜350D-6時也是基本上如本實施例所述， 最好施加於與受光感測器350P-1〜350P-6及遮光感測器 350D-1〜350D-6平面性重疊的電極之電壓是個別地最適化 。因爲光電電晶體的空乏層的擴大也會受到平面性重疊的 電極影響。 [第2實施形態] 圖20是第2實施例的液晶顯示裝置910B的立體構成圖 (一部份剖面圖）’替代第1實施例的圖1所説明的液晶顯示 裝置9 1 0者。以下，說明與第1實施例的圖1之液晶顯示裝 置9 1 0的差異。 本實施例是取代受光開口部990-1〜990-6，而配置1〇 個的受光開口部991-1〜991-10。在此，受光開口部991-1 〜991-6是被設置於遠離突出部1〇2所對向的周緣部，受光 開口部991-7〜991-10是被設置於與突出部102正交的周緣 部的邊。並且，取代主動矩陣基板101，而使用主動矩陣 基板101B’對向基板912是由對向基板912B取代。在此， 對向基板912B是除了其厚度爲〇.25min以外，與對向基板 9 1 2同様構成。由於其他的點是與第！實施例的圖1沒有不 同，因此賦予同樣的記號而省略説明。 圖2 1是第2實施例的主動矩陣基板1 〇丨b的方塊圖，取 代第1實施例的圖2所説明的主動矩陣基板1 〇 1，以下，以 -46- 200905655 和第1實施例的圖2之主動矩陣基板101的不同點爲中心來 進行説明。本實施例是配線DBT、配線PBT不存在，受 光感測器350P-1〜350P-6是被受光感測器351P-1〜351P· 10所替換，遮光感測器350D-1〜3 50D-6是被遮光感測器 351D-1〜351D-10所替換。在此，受光感測器351P-1〜 35 1P-6及遮光感測器351D-1〜351D-10是被配置於與設有 受光開口部991-1〜991-6的周緣部同邊’受光感測器 351P-1〜351P-6是與受光開口部991-1〜991-6平面性重疊 而配置構成。又，受光感測器351P-7〜351P-10及遮光感 測器351D-7〜351D-10是被配置於與設有受光開口部991-1 〜991-6的周緣部同邊，受光感測器351P-1〜351P-6是與 受光開口部991-1〜991-6平面性重疊而配置構成。受光感 測器351P-1〜351P-10是被連接至配線SENSE及配線VSH ，遮光感測器3 5 1 D -1〜3 5 1 D - 1 0是被連接至配線V S L、配 線S EN S E及配線V C H G。檢測電路3 6 0是被檢測電路3 6 2 所替換。其他的點則是與第1實施例沒有不同，因此賦予 同記號，而省略説明。又，賦予本實施例的配線ν SH的 電位是5.0V，賦予配線 VSL的電位是0.0V，賦予配線 VCHG的電位是2.0V，賦予配線RST的信號是電位振幅〇-5 V的脈衝波，每周期5 1 0m秒，在脈衝長1 〇〇μ秒之間保持 於High電位（5 V)，剩下的5 09.9m秒間是保持於Low電位 (0V)。該等亦與第1實施例沒有不同。 圖22是檢測電路3 62的電路圖，說明與第1實施例的圖 14所示之檢測電路360不同的點。本實施例是配線DBT、 -47 - 200905655 配線PBT不存在，且自己補正電壓電路361亦不存在。取 而代之，將配線V C H G原封不動輸出至遮光感測器3 5 1 D -1 〜351D-10。並且，屏蔽電極369不存在。藉此，相較於第 1實施例，電路的附加電容會變小，可更高速且精度佳動 作，但另一方面電磁雜訊變弱，屏蔽電極3 69的有無是只 要以檢測電路的配置位置等之電磁雜訊的大小來決定即可 。第1電容器C1、第2電容器C2、第3電容器C3的連接及 電容、初期充電電晶體NC、初期充電電晶體NC、第1〜 第5Ν型電晶體Ν1〜Ν5、第1〜第5Ρ型電晶體Ρ1〜Ρ5的構 成、大小、移動度、臨界値電壓（Vth)的設定是全部與第1 實施例同樣，因此省略説明。 圖2 3是受光感測器3 5 1 P -1 (第1光感測器）與遮光感測 器351D-1(第1光感測器）附近的擴大平面圖。一邊與第1實 施例的圖8作比較一邊説明。受光感測器3 5 1 P-1是與受光 開口部990- 1平面性重疊而可被外光照射’藉由受光部 351P-1I、陽極區域351P-1P、陰極區域351P-1N所構成’ 遮光感測器351 D-1是不與受光開口部990- 1平面性重疊’ 藉由受光部351D-1I、陽極區域351D-1P、陰極區域351D-1N所構成。受光部351P-1I、陽極區域351P-1P、陰極區 域351P-1N、受光部351D-1I、陽極區域351D-1P、陰極區 域351D-1N是分別與第1實施例的受光部3 5 0p-U、陽極區 域350P-1P、陰極區域350P-1N、受光部350D-1I、陽極區 域350D-1P、陰極區域350D-1N的構成·尺寸·連接觸等無 任何的改變，因此省略說明。在本實施例中’與受光感測 -48- 200905655 器351P-1重疊的背光遮光電極614P-1是經由中間電極 616P-1來連接至配線VSH，與遮光感測器351D-1重疊的背 光遮光電極614D-1是經由中間電極616D-1來連接至配線 VCHG。並且，重疊於受光感測器351P-1的透明電極615亦 重疊於遮光感測器3 5 1 D-1，互相不分離，因此第1實施例 的透明電極間隙6 1 2G不存在。透明電極6 1 4是配置有被配 置於受光感測器3 5 1 P-1及遮光感測器3 5 1 D-1之接近顯示區 域3 1 0側的共通電位配線3 3 5，賦予共通電位。本實施例是 在共通電位配線33 5施加DC電位，其電位爲4·〇ν。除了 配置的位置·間距·方向以外，受光感測器351 Ρ-2〜35 1Ρ-10與受光感測器351Ρ-1，遮光感測器351D-2〜351D-10與 遮光感測器351 D-1是完全相同，因此省略説明。 本實施例是在受光感測器351 Ρ-1〜35 1Ρ-6的背光遮光 電極614Ρ-1〜614Ρ-6連接與陰極同一的電位VVSH( = 5V)。 另一方面，在遮光感測器3 5 0D-1〜3 5 0D-6的背光遮光電極 614D-1 〜614D-6連接電位 VVCHG( = 2.0V)，RST 信號剛從 High(5V)形成Low(OV)之後是與陰極同一的電位，被輸出 至配線OUT的電位從Low(OV)形成High(5V)的瞬間是陰 極的電位上升至2.5V，因此形成較低0.5V的電位。 圖24是有關構成受光感測器351P-1〜351P-6及遮光感 測器35 1 D-1〜35 1D-6的二極體的特性，將遮光電極-陰極 電極間的電位差設於橫軸，將P IN二極體之2 3 °C、偏壓 Vd = -2.5V、外光1 000勒克斯條件的陽極.陰極間電流設於 縱軸時的曲線圖，取代第1實施例的圖1 5之曲線圖。實線 -49- 200905655 (A)是在測定顯示峰値電流的橫軸的電壓値爲複數取樣數 中’顯示中央値的取樣結果，點線（B)同樣的是在測定顯 示峰値電流的橫軸的電壓値爲複數取樣測定中，顯示最大 値的取樣結果’虛線（C)是同樣的在測定顯示峰値電流的 橫軸的電壓値爲複數取樣測定中，顯示最小値的取樣結果 。與第1實施例作比較’在本實施例是實線（A)、點線(B) 、虛線（C)間的差異少’即使將遮光電極-陰極電極間的電 位差固定於〇〜0.5V也無妨。藉由如此的構成，相較於第 1實施例’具有元件數.配線數可低減的優點。並且，就本 實施例的構成而言，背光遮光電極614P-1及背光遮光電極 6 1 4D-1的電位會與外部電源電路的電源連接，因此亦具有 像第1實施例那樣藉由連接至自己補正電壓電路361來降低 輸出阻抗，提升對電磁雜訊的屏蔽性能之優點。像第1實 施例那樣設置自己補正電壓電路，還是像本實施例那樣不 設置自己補正電壓電路，將固定電位施加於遮光層，是只 要測定製造工程的不均來判斷即可。 又，本實施例，透明電極6 1 5是重疊於遮光感測器 351D-1〜351D-6、受光感測器351P-1〜351P-6雙方，被施 加同電位（共通電位）。本實施例，背光遮光電極614P-1與 作爲受光層的受光部351P-1I之間的每單位面積電容及背 光遮光電極614D-1與作爲受光層的受光部351D-1I之間的 每單位面積電容是2 22 μΡ/μπι2，透明電極61 5與作爲受光 層的受光部3 5 1 Ρ -1 I之間的每單位面積電容及透明電極6 1 5 與作爲受光層的受光部351 D-II之間的每單位面積電容是 -50- 200905655 18μΡ/μηι2。因此，對受光層之電位的影響是背光遮光電 極614Ρ-1、背光遮光電極614D-1要比透明電極615大上12 倍以上。例如，背光遮光電極6 1 4Ρ -1、背光遮光電極 6 1 4D- 1的電位偏移1 V時的影響是等於透明電極6 1 5的電位 偏移12V時的影響。 本實施例，透明電極6 1 5的電位與受光感測器3 5 1 Ρ-1 的陰極區域3 5 1 Ρ -1 Ν間的電位差是-1 . 0 V，透明電極6 1 5的 電位與遮光感測器3 5 1 D -1的陰極區域3 5 1 D -1 Ν間的電位差 是+2.0〜2.5V，雖最大具有3.5V的差異，但若予以換算成 背光遮光電極的電位，則僅些微0.3V程度的差異，可無 視。如此，當與受光層平面性重疊的電極爲複數時，若使 受光層的每單位面積之電容大的一側的電極的電位最適化 ’則受光層的每單位面積之電容小的一側的電位可不一定 要最適化。本實施例是將透明電極614設爲1片的大電極來 與遮光感測器351D-1〜351D-6、受光感測器351Ρ-1〜 351Ρ-6重疊，藉由連接至輸出阻抗（impedance)低的共通電 位電源來使對遮光感測器3 5 1 D-1〜3 5 1 D-6、受光感測器 351P-1〜351P-6之電磁雜訊的屏蔽性能提升。 另外，此次所被揭示的實施形態所有的點爲例示，並 非受限者。本發明的範圍是根據申請專利範圍來表示，且 包含與申請專利範圍均等的意思及範圍内所有的變更。 例如’本實施例雖是將透明電極6 1 4與共通電位配線 3 3 5連接’但只要是輸出阻抗較低的配線，亦可爲其他的 配線，例如亦可與和液晶顯示裝置9 1 0的GND連接的配線 -51 - 200905655 V S L連接。 有關使用主動矩陣基板101B的液晶顯示裝置的實施 例是只將第1實施例的圖1所示的液晶顯示裝置910的主動 矩陣基板101置換成主動矩陣基板101B’因此省略説明。 又，有關使用液晶顯示裝置9 1 0的電子機器亦如第1實施例 的圖4的説明哪樣，因此其詳細省略。 有關受光開口部991-1〜99 1-6的大小，在與配置有該 受光開口部990-1〜990-6的顯示區域310的周緣部的境界 邊平行的方向（以下記爲X方向）是與第1實施例相同爲 10mm。另一方面，受光開口部99 1-7〜991-10的X方向的 大小是考量接近背光單元926的邊温度梯度會變大，而縮 短成7mm。因應於此，受光開口部991-1〜991-6的配置間 距爲20mm，受光開口部991-7〜991-10的配置間距爲14mm 〇 有關與顯示區域310的境界邊正交的方向（以下記爲Y 方向）是對向基板912B的厚度爲0.25mm，因此與第1實施 例相同在〇 . 3 m m迷光會變強，測定精度會降低，因此在受 光開口部991-1〜991-10全體 Y方向是設定成0.2mm的大 小。 如本實施例那樣，若在複數的邊配置受光感測器，則 更可除去手指或小的陰影的影響，因此更爲理想，但從與 光源的位置關係到温度梯度都必須用心。本實施例是在2 邊配置受光感測器，當然亦可在3邊或4邊配置。又，本實 施例是依據邊來改變感測器間距及開口部的大小，但同一 -52- 200905655 邊中若温度梯度顯著不同，則即使在同一邊内改變感測器 間距及開口部的大小也無妨。 另外，本實施例亦可分別連接至以中間電極6 1 6 D -1〜 6 16D-6作爲陰極電極的陰極區域351D-1N〜351D-6N、以 中間電極616P-1〜616P-6作爲陰極電極的陰極區域35ip_ 1N〜35 1P-6N來配置配線VCHG。取如此的構成時的受光 感測器3 5 1 P - 1及遮光感測器3 5 1 D -1的各別平面圖爲圖2 5。 若取如此的構成，則背光遮光電極614P-1〜614P-6與陰極 區域35 1P-1N〜35 1P-6N間的電位差及背光遮光電極614D-1〜614D-6與陰極區域351D-1N〜351D-6N間的電位差是 經常形成0V，因此具有流至受光感測器351P-1〜351P-6與 遮光感測器351D-1〜351D-6的熱電流量Ileak是經常形成 一定的優點，另一方面，背光遮光電極614D-1是被連接至 配線 SENSE，配線 SENSE是在配線 RST的電位爲 Low(OV)的期間未被連接至電位，爲浮動狀態，因此有容 易受電磁雜訊的影響之問題點。到底要選擇哪個是藉由評 價電磁雜訊的影響等來決定即可。 [產業上的利用可能性] 本發明並非限於實施例的形態，即使不是TN模式， 而是利用於垂直配向模式（VA模式）、利用橫電場的ipS 模式、利用邊緣電場的FFS模式等的液晶顯示裝置也無妨 。又，並非限於全透過型，即使爲全反射型、反射透過兼 用型也無妨。又，並非限於液晶顯示裝置，亦可利用於有 -53- 200905655 機EL顯示器、場致發射型顯示器，或利用於液晶顯示裝 置以外的半導體裝置。 又’並非限於本實施例所示那樣配合外光之顯示亮度 的控制’即使利用於測定顯示裝置的亮度或色度後予以反 餽，而無不均或經年變化的顯示裝置也無妨。 【圖式簡單說明】 圖1是本發明的實施例之液晶顯示裝置910的立體圖。 圖2是本發明的第1實施例之主動矩陣基板1〇1的構成 圖。 圖3是本發明的實施例之主動矩陣基板101的畫素電路 圖。 圖4是表示本發明的電子機器的實施例的方塊圖。 圖5是本發明的實施例之主動矩陣基板1 0 1的畫素部的 平面圖。 圖6是沿著圖5A-A'的剖面圖。 圖7是沿著圖5B-B'的剖面圖。 圖8是本發明的第1實施例之受光感測器3 5 0P-1、遮光 感測器3 5 0 D -1的平面圖。 圖9是沿著圖8C-C'的剖面圖。 圖1 〇是沿著圖8 D - D '的剖面圖。 圖1 1是本發明的第1實施例之受光感測器3 5 OP-1〜 3 5 0P-6、遮光感測器3 5 0D-1〜3 5 0D-6的等效電路圖。 圖12是本發明的第1實施例之受光感測器3 5 0P-1〜 -54- 200905655 350P-6、遮光感測器350D-1〜350D-6之簡略化的等效電路 圖。 圖13是表示構成本發明的第1實施例的受光感測器 350P-1 〜350P-6、遮光感測器 350D-1 〜350D-6 之 PIN 二極 體的特性曲線圖。 圖14是本發明的第1實施例之檢測電路3 60的電路圖。 圖15是本發明的第1實施例之PIN二極體的電流與遮 光電極-陰極電極間電位的曲線圖。 圖16是表示本發明的實施例之薄膜電晶體與PIN二極 體的特性相關的散布圖。 圖1 7是表示本發明的第1實施例的別的構成例之第2自 己補正電壓電路3 6 Γ的電路圖。 圖1 8是本發明的實施例之外部光的檢出照度與背光亮 度的設定圖。 圖1 9是半透過液晶顯示裝置用的外部光的檢出照度與 背光亮度的設定圖。 圖20是本發明的第2實施例之液晶顯示裝置9 1 0B的立 體圖。 圖21是本發明的第2實施例之主動矩陣基板101B的方 塊圖。 圖22是本發明的第2實施例之檢測電路3 62的電路圖。 圖23是本發明的第2實施例之受光感測器、遮 光感測器3 5 1 D - 1的平面圖。 圖24是本發明的第2實施例之PIN二極體的電流與遮 -55- 200905655 光電極-陰極電極間電位的曲線圖。 圖25是本發明的第2實施例的別構成例之受光感測器 351P-1、遮光感測器351D-1的平面圖。 【主要元件符號說明】 1 0 1 ’ 1 0 1 B :主動矩陣基板（本發明的「第1基板」、「半 導體裝置」之一例） 1 〇 2 :突出部 201- 1〜201-480 :掃描線 202- 1〜202-1920:資料線 3 〇 1 :掃描線驅動電路 3 02 :資料線驅動電路 320 :信號輸入端子 3 3 0- 1〜3 3 0-2 :對向導通部 3 3 5 :共通電位配線 350P-1〜350P-6’ 351P-1〜351P-6:受光感測器（本發明的 「第1光感測器」之一例） 350D-1〜350D-6’ 351D-1〜351D-6:遮光感測器（本發明 的「第2光感測器」之一例） 3 6 0 ’ 3 6 2 :檢測電路（本發明的「光檢測部」之—例） 3 6 1 ’ 3 6 1 ':自己補正電壓電路（本發明的「電位施加部」 之一例） 611P，611P-1 〜611P-6，611D，611D-1〜611D-6:背光遮 光電極（611P是本發明的「第1電極」、611D是本發明的 -56- 200905655 「第2電極」之一例） 612P > 612P-1 〜612P-6，612D，612D-1 〜612D-6:透明電 極（612P是本發明的「第1電極」、612D是本發明的Γ第2 電極」之一例） 781 :中央運算電路 784 :外部電源電路 9 1 0 :液晶顯示裝置 911:液晶面板（本發明的「面板」之一例） 9 1 2 :對向基板（本發明的「第2基板」之一例） 922 :向列相液晶材料 9 2 3 :密封材 926 :背光單元 927 :導光板 940 :黑矩陣 990-1〜990-6:受光開口部 VPBT:配線PBT的電位（本發明的「第丨電極的電位」之 一例） VDBT.配線DBT的電位（本發明的「第2電極的電位」之 一例） LA :外光、 LB :背光光 -57-The detection circuit 3 60 is in a period in which the RST line is Low (OV), and the node A is in a floating state. Here, when the electromagnetic noise enters and the potential of the node A changes, an error occurs. Therefore, the prevention of electromagnetic noise is extremely important. Therefore, the shield electrode 369 is disposed. A PIN-type diode or a PN-type diode having a lateral structure such as this configuration has a problem that the photoelectric flow rate IPh〇to changes in the electric field in the vertical direction. Specifically, in the present embodiment, the potentials of the transparent electrodes 612P-1 to 612P-6 and the backlight-shielding electrodes 611P-1 to 611P-6 connected to the wiring PBT (hereinafter referred to as VPBT) affect the light-receiving sensor 350P-1. The characteristics of the ~350P-6, the potentials of the transparent electrodes 612D-1 to 612D-6 and the backlight-shielding electrodes 611P-1 to 611P-6 connected to the wiring DBT (hereinafter referred to as VDBT) affect the shading sensor 3 5 0D- 1 to 3 features of 50D-6. Fig. 15 is a view showing the characteristics of the diodes constituting the light receiving sensors 350P-1 to 350P-6 and the light shielding sensors 3 5 0D-1 to 3 5 0D-6, and the light shielding electrode (and the transparent electrode) - the cathode electrode The potential difference between the anode and the cathode is 23 ° C, the bias voltage Vd = -2.5 V, and the external-electrode 1 000 lux is the vertical axis. In the present embodiment, the horizontal axis is equivalent to VPBT-VVSH at the light-receiving sensor 3 0 0P-1 to 3 50P-6, and VDBT-VSENSE is equivalent to the light-shielding sensors 350D-1 to 350D-6. The solid line (A) is a sampling result in which the center 値 is displayed in the voltage 値 which is the horizontal axis of the peak current measured, and the center line B is displayed. The dotted line (B) is the same as the voltage on the horizontal axis of the peak current.値 In the case of the complex sampling measurement, the sampling result showing the maximum enthalpy 'Cross line (C) is the same in the measurement of the voltage 値 of the horizontal axis of the peak current 値 is a complex sampling measurement, showing the smallest 値 -40-200905655 sampling result. It can be seen that the peak 値 has an appropriate voltage (hereinafter, the potential difference between the light-shielding electrode (and the transparent electrode) forming the peak of the photocurrent and the cathode electrode is referred to as VMAX). This is because when the potential difference between the light-shielding electrode (and the transparent electrode) and the cathode electrode is an appropriate voltage, the light-receiving portion of the PIN-bonded diode is equivalent to the light-receiving portion 3 5 0P-1I and the light-receiving portion 3 5 0D-1I in Fig. 8 . The light is excited and the carriers are excited by light in the whole region. If the potential difference between the light-shielding electrode (and the transparent electrode) and the cathode electrode is more positive than the appropriate voltage, the light-receiving portion is N-shaped, and the same ratio is obtained. When the appropriate voltage is more negative, the light receiving portion will be P-type, the width of the depletion layer will be narrowed, and the area of the carrier excited by the light will be limited. Therefore, in order to fully obtain the photocurrent, it is necessary to appropriately control the VPBT and VDBT so that the VMAX point can be formed. As is clear from the graph (A) of Fig. 15, in the central crucible in which unevenness is produced, it is preferable that the potential of the light shielding layer and the transparent electrode is a potential which is about 1.4 V lower than the potential applied to the cathode electrode. However, comparing the graph (A), the graph (B), and the graph (C), it is known that the actual potential VMAX will vary somewhat due to manufacturing unevenness. This is because the defect level in the polycrystalline silicon film or the fixed charge at the interface of the underlying insulating film and the gate insulating film is uneven in manufacturing engineering. Fig. 16 is a scatter diagram showing the relationship between a thin film transistor formed on the same substrate and a PIN diode. The average threshold voltage (VthN) of the N-type thin film transistor and the average threshold voltage (VthP) of the P-type thin film transistor are set on the horizontal axis, and the appropriate potential VMAX for forming the maximum photocurrent of the PIN diode is set to Vertical axis. As is apparent from Fig. 16, in general, the critical 値 of the thin film transistor and the appropriate potential VMAX for maximizing the photocurrent of the PIN diode have a strong positive correlation. In this embodiment, as shown in the graph (A) of Fig. 16.6, the light-shielding electrode (and the transparent electrode) exhibits a maximum 値 (VMAX) when the potential of the shading electrode (and the transparent electrode) is lower than that of the cathode electrode. The critical 値 voltage (VthN) is +1.0V, and the P-type critical 値 voltage (VthP) is -1.0V'. In the case of manufacturing unevenness, the average deviation of VthN and VthP is also offset by 1 V. In the present embodiment, a positive correction voltage of approximately y = X (dotted line) is used. In the present embodiment, the voltage is self-corrected by the thin film power (Vth), and the wiring PBT and the wiring are self-corrected by the voltage circuit 361. For the uniformity of the embodiment, VthN = +1.0, VthP = -l.〇, at this time, the self-channel 3 6 1 is applied to the wiring PBT 3.6 V, and the wiring DBT receives the photo sensor 3 5 0P -1 to 3 5 0P-6, the cathode is 5.0V with wiring, so the potential difference between the backlight shading electrodes 61 1P-1 to 61 1P 612P-1 and the cathode is -1.4V, which is the optimum potential (VMAX). In the case of manufacturing uneven transistors, for example, if VthN = +1.5, VthP = -0.5, wiring is 4.1 V, and wiring is applied at wiring D B T of 1.9 V. Similarly, VthP = -l .5 is applied to the wiring PBT by 3.1 V, and is increased by | 9 V. In either case, once the transistor is applied to the wiring PBT and the wiring DBT, the photocurrent is generally maximized. Fig. 17 is a circuit diagram showing a second self-correcting voltage circuit 36A of the self-correcting voltage circuit 3 of Fig. 16; The average state of the gate electrode and the drain electrode of the N31, the 8P-type transistor, and the 5 N-type thin film electro-film transistor at a level of 1.4 V, the threshold voltage of the 1 V-B! J VMAX 〇 crystal The uneven self-correcting voltage is applied with 1.4V. In the VSH connection, -6 and the transparent electrode can obtain the characteristics of the photocurrent, and the PBT is applied. If VthN = + 0.5 § The DBT is subjected to the critical 値 change, the bit will also change, and the other components of 6 1; 8N type The gate of transistor P 3 1 - 42- 200905655 The pole and drain electrodes are all connected to node E. Further, the node E is also connected to the gate electrode of the ninth P-type transistor P41 and the gate electrode of the ninth N-type transistor N41. The source electrode of the ninth P-type transistor P41 is connected to the wiring PBT, and the drain electrode is connected to the wiring VSL. Further, the drain electrode of the 10P-type transistor P42 is connected to the wiring PBT, the source electrode is connected to the wiring VSH, and the gate electrode is connected to the adjustment power supply wiring Voff1. The source electrode of the ninth N-type transistor N41 is connected to the wiring DBT, and the drain electrode is connected to the wiring VSH. The drain electrode of the 10N-type transistor N42 is connected to the wiring DBT, the source electrode is connected to the wiring VSL, and the gate electrode is connected to the adjustment power supply wiring Voff2. The adjustment power supply line Voff1 and the adjustment power supply line Voff2 are power supplies supplied from the external power supply circuit 784 via the signal input terminal 306. The adjustment power supply line Voff1 is set to 3.9V, and the adjustment power supply line Voff2 is set to 1.1V. Here, the channel width of the 8N-type transistor N31 is ΙΟμπι, the channel width of the 8th-type transistor Ρ3 1 is ΙΟμπι, the channel width of the ninth-type transistor Ν41 is ΙΟΟμηι, and the channel width of the 10th-type transistor Ν42 is ΙΟΟμιη, the channel width of the 9th transistor Ρ41 is ΙΟΟμιη, the channel width of the 10th transistor Ρ42 is ΙΟΟμιη, the channel length of all Ν-type transistors is 8 μηη, and the channel length of all Ρ-type transistors is 6μιη The mobility of all Ν-type transistors was 80 cm 2 /Vsec, and the mobility of all Ρ-type transistors was 60 cm 2 /Vsec. According to the above configuration, the relationship between the voltage outputted from the second self-correcting voltage circuit 3 6 1 ' to the wiring DBT and the voltage output to the wiring BT BT and the critical 値 voltage (Vth) of the thin film transistor is the same as that of FIG. 14 . When you correct the voltage circuit 361 yourself, it is completely the same. -43- 200905655 In comparison with the configuration of the self-correcting voltage circuit 361 of FIG. 14, the second self-correcting voltage circuit 36A of FIG. 17 is configured such that the potential of the power supply wiring Voff1 and the power supply wiring Voff2 are adjusted and adjusted, and the active switching is not required. The matrix substrate 101 has an advantage of adjusting the voltage output to the wiring DBT and the voltage output to the wiring PBT. On the other hand, since the number of components, the number of wirings, and the number of terminals are large, it is disadvantageous in terms of circuit area. Therefore, it is only necessary to use any one of them depending on the length and length of each. Further, the present invention is not limited to these circuit configurations, and it is also possible to use any of the known voltage circuits instead of the self-correcting voltage circuit 361. Further, the wiring DBT and the wiring PBT may be connected to the external power supply circuit 784 via the signal input terminal 320, and the external power supply circuit 784 may supply an appropriate potential. In this case, the setting of the potential output from the external power supply circuit 784 can be written to EEPR0M or the like for each product, and the product unevenness can be controlled. In addition, in this embodiment, the power supply wiring VS is connected to the light-receiving sensor 3 5 OP-1 〜 3 5 0 P - 6 and the light-shielding sensor 3 5 0 D -1 to 3 5 0 D - 6. Η and the power supply wiring VSL are used as the driving power for the detection circuit 306, but these may be other power supply wirings. According to this configuration, the number of wirings or terminals is large, but on the other hand, the operation noise of the detection circuit 360 is difficult for the light-receiving sensors 350Ρ-1 to 350Ρ-6 and the light-shielding sensors 350D-1 to 350D-6. The point of interest. In the present embodiment, the signal that the central processing circuit 781 monitors the terminal OUT' is first obtained by the inverted time to the discrete 値V 1 0. The discrete 値V 1 0 will be sampled a random number of times to obtain its average 値VI 0_. The voltage setting 値V20 of the appropriate backlight unit 926 corresponding to v1〇_ is obtained from VI 0_ to -44 - 200905655. The central processing circuit 781 sends the V20 to the external power supply circuit 784' to change the brightness of the backlight unit 926. As a result, the brightness of the liquid crystal display device 910 is changed during the all-white display, and the user can suppress the increase in visibility while suppressing the excessive brightness. ΪΪ #实施例 The relationship between the detected illuminance of external light and the backlight brightness is set as shown in Fig. 18. The illuminance of the backlight is gradually increased until the illuminance is 3 〇〇 (lux), and the illuminance is increased by increasing the tilt degree at 30 lux or more. In the case where the detected illuminance is 2000 lux, the brightness is formed after the formation of MAX'. Once set in this way, the external light will be below 300 lux, and the surroundings will be extremely dark. When the user's pupil is opened, the backlight will be pressed without glare, and the external light in the 3 lux lux to 20 lux will be reflected. The area of the liquid crystal panel is such that the brightness is rapidly increased in accordance with the brightness of the surrounding area, so that the visibility is not lowered. On the other hand, as in the case of the non-transmissive type as in the present embodiment, the semi-transmissive liquid crystal may be used as long as it is as shown in Fig. 19. The same is true for the external illuminance of 5000 lux. However, since the reflection portion can be sufficiently visible as described above, the backlight can be completely turned off, and the power consumption can be saved, so that it can be greatly used especially when used outdoors. Extend the battery drive time of the electronic equipment installed. Of course, this control curve is an example, and any curve can be set according to the application. In order to suppress the flash, the curve can also have hysteresis. Further, instead of performing brightness adjustment for each measurement, the number of times -45 - 200905655 may be measured, and the average or center 値 may be used to adjust the brightness. When the light-receiving sensors 350P-1 to 350P-6 and the light-shielding sensors 350D-1 to 350D-6 are formed by photoelectric transistors, they are basically as described in the embodiment, and are preferably applied to the light-receiving sensor 350P. The voltages of the -1 to 350P-6 and the light-shielding sensors 350D-1 to 350D-6 planarly overlapping electrodes are individually optimized. Because the expansion of the depletion layer of the photovoltaic cell is also affected by the planar overlapping electrodes. [Second Embodiment] Fig. 20 is a perspective view showing a three-dimensional configuration of a liquid crystal display device 910B according to a second embodiment of the liquid crystal display device 910B of the second embodiment. Hereinafter, the difference from the liquid crystal display device 910 of Fig. 1 of the first embodiment will be described. In the present embodiment, one of the light-receiving opening portions 991-1 to 991-10 is disposed instead of the light-receiving opening portions 990-1 to 990-6. Here, the light-receiving opening portions 991-1 to 991-6 are provided at a peripheral portion that faces away from the protruding portion 1〇2, and the light-receiving opening portions 991-7 to 991-10 are disposed to be orthogonal to the protruding portion 102. The side of the peripheral part. Further, in place of the active matrix substrate 101, the active substrate substrate 101B' is used instead of the counter substrate 912B. Here, the counter substrate 912B is formed in the same manner as the counter substrate 9 1 2 except that the thickness thereof is 〇.25 min. Since the other points are with the first! Fig. 1 of the embodiment is not different, and therefore the same reference numerals are given and the description is omitted. Fig. 21 is a block diagram of the active matrix substrate 1 〇丨b of the second embodiment, in place of the active matrix substrate 1 〇 1 illustrated in Fig. 2 of the first embodiment, hereinafter, -46-200905655 and the first embodiment The difference between the active matrix substrate 101 of FIG. 2 will be described as a center. In this embodiment, the wiring DBT and the wiring PBT are not present, and the light receiving sensors 350P-1 to 350P-6 are replaced by the light receiving sensors 351P-1 to 351P·10, and the light blocking sensors 350D-1 to 3 50D- 6 is replaced by the shading sensors 351D-1 to 351D-10. Here, the light-receiving sensors 351P-1 to 35 1P-6 and the light-shielding sensors 351D-1 to 351D-10 are disposed on the same side as the peripheral portion where the light-receiving openings 991-1 to 991-6 are provided. The light receiving sensors 351P-1 to 351P-6 are arranged to be planarly overlapped with the light receiving openings 991-1 to 991-6. Further, the light-receiving sensors 351P-7 to 351P-10 and the light-shielding sensors 351D-7 to 351D-10 are disposed on the same side as the peripheral portion where the light-receiving openings 991-1 to 991-6 are provided, and the light-receiving feeling is received. The detectors 351P-1 to 351P-6 are arranged to be planarly overlapped with the light receiving openings 991-1 to 991-6. The light-receiving sensors 351P-1 to 351P-10 are connected to the wiring SENSE and the wiring VSH, and the light-shielding sensors 3 5 1 D -1 to 3 5 1 D - 1 0 are connected to the wiring VSL, the wiring S EN SE And wiring VCHG. The detection circuit 306 is replaced by the detection circuit 326. The other points are not different from the first embodiment, and therefore the same reference numerals are given, and the description is omitted. In addition, the potential of the wiring ν SH to which the present embodiment is applied is 5.0 V, the potential applied to the wiring VSL is 0.0 V, the potential applied to the wiring VCHG is 2.0 V, and the signal applied to the wiring RST is a pulse wave having a potential amplitude 〇 -5 V. At a cycle of 5 1 0 m seconds, the pulse is held at a high potential (5 V) for a period of 1 〇〇 μsec, and the remaining 5 09.9 m seconds is maintained at a Low potential (0 V). These are also no different from the first embodiment. Fig. 22 is a circuit diagram of the detecting circuit 362, and illustrates a point different from the detecting circuit 360 shown in Fig. 14 of the first embodiment. In this embodiment, the wiring DBT, -47 - 200905655 wiring PBT does not exist, and the self-correcting voltage circuit 361 does not exist. Instead, the wiring V C H G is output as it is to the shading sensor 3 5 1 D -1 to 351D-10. Also, the shield electrode 369 does not exist. Thereby, compared with the first embodiment, the additional capacitance of the circuit is reduced, and the operation can be performed at a higher speed and with higher precision. On the other hand, the electromagnetic noise is weak, and the presence or absence of the shield electrode 3 69 is as long as the configuration of the detection circuit The size of the electromagnetic noise such as the position can be determined. Connection and capacitance of the first capacitor C1, the second capacitor C2, and the third capacitor C3, the initial charge transistor NC, the initial charge transistor NC, the first to fifth NMOS transistors Ν1 to Ν5, and the first to fifth types The configuration, the size, the mobility, and the threshold voltage (Vth) of the crystals Ρ1 to Ρ5 are all the same as those of the first embodiment, and thus the description thereof is omitted. Fig. 23 is an enlarged plan view showing the vicinity of the light-receiving sensor 35 1 P -1 (first photo sensor) and the light-shielding sensor 351D-1 (first photo sensor). This will be described in comparison with Fig. 8 of the first embodiment. The light-receiving sensor 3 5 1 P-1 is planarly overlapped with the light-receiving opening portion 990-1 and can be irradiated with external light 'by the light-receiving portion 351P-1I, the anode region 351P-1P, and the cathode region 351P-1N'. The light-shielding sensor 351 D-1 is formed so as not to planarly overlap the light-receiving opening portion 990-1 by the light-receiving portion 351D-1I, the anode region 351D-1P, and the cathode region 351D-1N. The light receiving portion 351P-1I, the anode region 351P-1P, the cathode region 351P-1N, the light receiving portion 351D-1I, the anode region 351D-1P, and the cathode region 351D-1N are respectively the light receiving portion 3 0 0p-U of the first embodiment. The configuration, size, and connection of the anode region 350P-1P, the cathode region 350P-1N, the light receiving portion 350D-1I, the anode region 350D-1P, and the cathode region 350D-1N are not changed, and thus the description thereof is omitted. In the present embodiment, the backlight light-shielding electrode 614P-1 overlapping with the light-sensing-sensing-48-200905655 351P-1 is connected to the wiring VSH via the intermediate electrode 616P-1, and is overlapped with the light-shielding sensor 351D-1. The light-shielding electrode 614D-1 is connected to the wiring VCHG via the intermediate electrode 616D-1. Further, the transparent electrode 615 which is superimposed on the photodetector 351P-1 is also overlapped with the light-shielding sensor 3 5 1 D-1 and is not separated from each other. Therefore, the transparent electrode gap 6 1 2G of the first embodiment does not exist. The transparent electrode 6 1 4 is provided with a common potential wiring 3 3 5 disposed on the side closer to the display region 3 1 0 of the light receiving sensor 3 5 1 P-1 and the light blocking sensor 3 5 1 D-1, and is given commonality. Potential. In the present embodiment, a DC potential is applied to the common potential wiring 33 5, and its potential is 4·〇ν. In addition to the position, spacing, and direction of the arrangement, the light-receiving sensors 351 Ρ - 2 to 35 1 Ρ - 10 and the light-receiving sensor 351 Ρ -1, the light-shielding sensors 351D - 2 to 351 D - 10 and the light-shielding sensor 351 D -1 is identical, and therefore the description is omitted. In the present embodiment, the backlight light-shielding electrodes 614Ρ-1 to 614Ρ-6 of the light-receiving sensors 351 Ρ-1 to 35 1Ρ-6 are connected to the same potential VVSH (= 5V) as the cathode. On the other hand, the backlight shading electrodes 614D-1 to 614D-6 of the shading sensors 3 5 0D-1 to 3 5 0D-6 are connected to the potential VVCHG (= 2.0V), and the RST signal just forms Low from High (5V). (OV) is the same potential as the cathode, and the potential output to the wiring OUT is high (5 V) from Low (OV). The potential of the cathode rises to 2.5 V, so that a potential lower than 0.5 V is formed. Fig. 24 shows the characteristics of the diodes constituting the photodetectors 351P-1 to 351P-6 and the shading sensors 35 1 D-1 to 35 1D-6, and the potential difference between the shading electrode and the cathode electrode is set to the horizontal The axis is a graph in which the anode and cathode currents of the P IN diode at 23 ° C, the bias voltage Vd = -2.5 V, and the external light of 1 000 lux are set on the vertical axis, instead of the map of the first embodiment. 1 5 graph. Solid line -49- 200905655 (A) is a sampling result showing the center 値 in the voltage 値 of the horizontal axis indicating the peak current, and the point line (B) is the same as the peak current in the measurement. The voltage 値 on the horizontal axis is the sampling result showing the maximum 値 in the complex sampling measurement. The broken line (C) is the same sampling result in which the voltage 値 on the horizontal axis of the peak 値 current is measured and the minimum 値 is displayed. Compared with the first embodiment, 'the difference between the solid line (A), the dotted line (B), and the broken line (C) is small in the present embodiment, even if the potential difference between the shading electrode and the cathode electrode is fixed at 〇~0.5V. It doesn't matter. With such a configuration, the number of components is smaller than that of the first embodiment, and the number of wirings can be reduced. Further, in the configuration of the present embodiment, the potentials of the backlight-shielding electrode 614P-1 and the backlight-shielding electrode 6 1 4D-1 are connected to the power source of the external power supply circuit, and therefore, by connecting to the same as in the first embodiment The voltage circuit 361 is self-corrected to reduce the output impedance and improve the shielding performance of the electromagnetic noise. In the case where the self-correcting voltage circuit is provided as in the first embodiment, the self-correcting voltage circuit is not provided as in the present embodiment, and a fixed potential is applied to the light-shielding layer, and it is only necessary to measure the unevenness of the manufacturing process. Further, in the present embodiment, the transparent electrodes 615 are superposed on the light-shielding sensors 351D-1 to 351D-6 and the light-receiving sensors 351P-1 to 351P-6, and the same potential (common potential) is applied. In the present embodiment, the capacitance per unit area between the backlight light-shielding electrode 614P-1 and the light-receiving portion 351P-1I as the light-receiving layer, and the unit area between the backlight light-shielding electrode 614D-1 and the light-receiving portion 351D-1I as the light-receiving layer The capacitance is 2 22 μΡ/μπι 2, the transparent electrode 615 and the light-receiving portion 3 5 1 Ρ -1 I as the light-receiving layer have a capacitance per unit area and the transparent electrode 6 1 5 and the light-receiving portion 351 D-II as the light-receiving layer. The capacitance per unit area is -50-200905655 18μΡ/μηι2. Therefore, the influence on the potential of the light receiving layer is that the backlight light-shielding electrode 614Ρ-1 and the backlight light-shielding electrode 614D-1 are more than 12 times larger than the transparent electrode 615. For example, the influence of the backlight shading electrode 6 1 4 Ρ -1 and the potential of the backlight shading electrode 6 1 4D-1 shifted by 1 V is equal to the effect when the potential of the transparent electrode 6 15 is shifted by 12 V. In this embodiment, the potential difference between the potential of the transparent electrode 615 and the cathode region 3 5 1 Ρ -1 受 of the photodetector 3 5 1 Ρ-1 is -1.0 V, and the potential of the transparent electrode 6 1 5 The cathode area of the shading sensor 3 5 1 D -1 3 5 1 D -1 The potential difference between the turns is +2.0 to 2.5 V, and although it has a maximum difference of 3.5 V, if it is converted into the potential of the backlight shading electrode, Only a slight difference of 0.3V can be ignored. When the number of electrodes that are planarly overlapped with the light-receiving layer is plural, if the potential of the electrode having a large capacitance per unit area of the light-receiving layer is optimized, the capacitance per unit area of the light-receiving layer is small. The potential may not necessarily be optimized. In this embodiment, the transparent electrode 614 is provided as a large electrode to overlap the light-shielding sensors 351D-1 to 351D-6 and the light-receiving sensors 351Ρ-1 to 351Ρ-6, and is connected to the output impedance (impedance). The low common-potential power supply improves the shielding performance of the electromagnetic noise of the light-shielding sensors 3 5 1 D-1 to 3 5 1 D-6 and the light-receiving sensors 351P-1 to 351P-6. Further, all points of the embodiments disclosed herein are illustrative and not restrictive. The scope of the present invention is defined by the scope of the claims, and all modifications within the meaning and scope of the claims are included. For example, in the present embodiment, the transparent electrode 614 is connected to the common potential wiring 3 3 5, but any wiring may be used as long as it has a low output impedance, and may be, for example, a liquid crystal display device. GND connection wiring -51 - 200905655 VSL connection. In the embodiment of the liquid crystal display device using the active matrix substrate 101B, only the active matrix substrate 101 of the liquid crystal display device 910 shown in Fig. 1 of the first embodiment is replaced with the active matrix substrate 101B. Further, the electronic device using the liquid crystal display device 910 is also omitted from the description of Fig. 4 of the first embodiment. The size of the light-receiving opening portions 991-1 to 99 1-6 is parallel to the boundary edge of the peripheral edge portion of the display region 310 in which the light-receiving openings 990-1 to 990-6 are disposed (hereinafter referred to as the X direction). It is 10 mm as in the first embodiment. On the other hand, the size of the light-receiving openings 99 1-7 to 991-10 in the X direction is such that the temperature gradient close to the backlight unit 926 becomes larger, and is shortened to 7 mm. In response to this, the arrangement pitch of the light-receiving openings 991-1 to 991-6 is 20 mm, and the arrangement pitch of the light-receiving openings 991-7 to 991-10 is 14 mm, which is a direction orthogonal to the boundary edge of the display region 310 ( In the Y direction, the thickness of the counter substrate 912B is 0.25 mm. Therefore, as in the first embodiment, the 3 mm glare becomes strong, and the measurement accuracy is lowered. Therefore, the light receiving opening portions 991-1 to 991-10 The entire Y direction is set to a size of 0.2 mm. As in the present embodiment, if the light-receiving sensor is disposed on a plurality of sides, it is more preferable to remove the influence of a finger or a small shadow, but it is necessary to be careful from the positional relationship with the light source to the temperature gradient. In this embodiment, the light-receiving sensors are disposed on two sides, and of course, they may be arranged on three sides or four sides. Moreover, in this embodiment, the sensor spacing and the size of the opening are changed according to the side, but if the temperature gradient is significantly different in the same -52-200905655 side, the sensor spacing and the opening size are changed even in the same side. It doesn't matter. In addition, the present embodiment can also be respectively connected to the cathode regions 351D-1N to 351D-6N having the intermediate electrodes 6 1 6 D -1 to 6 16D-6 as the cathode electrodes, and the cathode electrodes 616P-1 to 616P-6 as the cathodes. The wiring VCHG is disposed in the cathode regions 35ip_ 1N to 35 1P-6N of the electrodes. The respective plan views of the light-receiving sensor 3 5 1 P - 1 and the light-shielding sensor 3 5 1 D - 1 when such a configuration is taken are as shown in Fig. 25. With such a configuration, the potential difference between the backlight-shielding electrodes 614P-1 to 614P-6 and the cathode regions 35 1P-1N to 35 1P-6N and the backlight-shielding electrodes 614D-1 to 614D-6 and the cathode region 351D-1N are The potential difference between 351D-6N is often 0V. Therefore, the amount of thermal current Ileak flowing to the light receiving sensors 351P-1 to 351P-6 and the light shielding sensors 351D-1 to 351D-6 often has certain advantages. On the other hand, the backlight shading electrode 614D-1 is connected to the wiring SENSE, and the wiring SENSE is not connected to the potential during the period in which the potential of the wiring RST is Low (OV), and is in a floating state, so that it is susceptible to electromagnetic noise. The problem point. Which one to choose is determined by evaluating the influence of electromagnetic noise. [Industrial Applicability] The present invention is not limited to the embodiment, and is not used in the vertical alignment mode (VA mode), the ipS mode using the horizontal electric field, or the FFS mode using the fringe electric field, even if it is not the TN mode. The display device is also fine. Further, it is not limited to the full transmission type, and may be a total reflection type or a reflection type. Further, the present invention is not limited to the liquid crystal display device, and may be used in an EL display having a -53-200905655, a field emission type display, or a semiconductor device other than the liquid crystal display device. Further, the present invention is not limited to the control of the display brightness of the external light as shown in the present embodiment, and may be used for measuring the brightness or chromaticity of the display device and then feeding back the display device without unevenness or change over the years. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view of a liquid crystal display device 910 according to an embodiment of the present invention. Fig. 2 is a view showing the configuration of an active matrix substrate 1〇1 according to the first embodiment of the present invention. Fig. 3 is a diagram showing a pixel circuit of the active matrix substrate 101 of the embodiment of the present invention. Fig. 4 is a block diagram showing an embodiment of an electronic apparatus of the present invention. Fig. 5 is a plan view showing a pixel portion of the active matrix substrate 110 of the embodiment of the present invention. Figure 6 is a cross-sectional view taken along line A-A' of Figure 5; Figure 7 is a cross-sectional view taken along line BB' of Figure 5B. Fig. 8 is a plan view showing a light-receiving sensor 350-P-1 and a light-shielding sensor 350-D-1 in the first embodiment of the present invention. Figure 9 is a cross-sectional view taken along line 8C-C'. Figure 1 is a cross-sectional view taken along line D - D ' of Figure 8. Fig. 11 is an equivalent circuit diagram of the light-receiving sensors 3 5 OP-1 to 3 5 0P-6 and the light-shielding sensors 3 5 0D-1 to 3 5 0D-6 of the first embodiment of the present invention. Fig. 12 is a simplified equivalent circuit diagram of the light-receiving sensors 3 0 0P-1 to -54- 200905655 350P-6 and the light-shielding sensors 350D-1 to 350D-6 according to the first embodiment of the present invention. Fig. 13 is a characteristic diagram showing the PIN diodes of the light-receiving sensors 350P-1 to 350P-6 and the light-shielding sensors 350D-1 to 350D-6 which constitute the first embodiment of the present invention. Fig. 14 is a circuit diagram of a detecting circuit 3 60 according to the first embodiment of the present invention. Fig. 15 is a graph showing the current between the current of the PIN diode and the potential between the light-shielding electrode and the cathode electrode in the first embodiment of the present invention. Fig. 16 is a scatter diagram showing the characteristics of the thin film transistor of the embodiment of the present invention and the PIN diode. Fig. 17 is a circuit diagram showing a second self-correcting voltage circuit 3 6 别 of another configuration example of the first embodiment of the present invention. Fig. 18 is a diagram showing the setting of the detected illuminance and the backlight luminance of the external light according to the embodiment of the present invention. Fig. 19 is a diagram showing the setting of the detected illuminance and the backlight luminance of the external light for the semi-transmissive liquid crystal display device. Fig. 20 is a perspective view showing a liquid crystal display device 910B according to a second embodiment of the present invention. Fig. 21 is a block diagram showing an active matrix substrate 101B according to a second embodiment of the present invention. Fig. 22 is a circuit diagram of a detecting circuit 3 62 of the second embodiment of the present invention. Figure 23 is a plan view showing a light-receiving sensor and a light-shielding sensor 35 1 D - 1 according to a second embodiment of the present invention. Fig. 24 is a graph showing the current between the PIN diode of the second embodiment of the present invention and the potential between the photoelectrode and the cathode electrode of the -55-200905655. Fig. 25 is a plan view showing a light receiving sensor 351P-1 and a light blocking sensor 351D-1 according to another configuration example of the second embodiment of the present invention. [Description of main component symbols] 1 0 1 '1 0 1 B : Active matrix substrate (an example of "first substrate" and "semiconductor device" of the present invention) 1 〇 2 : protruding portion 201 - 1 to 201-480 : scanning Line 202-1 to 202-1920: data line 3 〇1: scan line drive circuit 3 02: data line drive circuit 320: signal input terminal 3 3 0- 1 to 3 3 0-2: pair of guides 3 3 5 : Common potential wirings 350P-1 to 350P-6' 351P-1 to 351P-6: Light-receiving sensor (an example of "first light sensor" of the present invention) 350D-1 to 350D-6' 351D-1 ～351D-6: Shading sensor (an example of "2nd photo sensor" of the present invention) 3 6 0 ' 3 6 2 : Detection circuit (example of "photodetection unit" of the present invention) 3 6 1 ' 3 6 1 ': Self-correcting voltage circuit (an example of "potential application unit" of the present invention) 611P, 611P-1 to 611P-6, 611D, 611D-1 to 611D-6: backlight light-shielding electrode (611P is the present invention) "First electrode" and 611D are examples of "second electrode" of -56-200905655 of the present invention) 612P > 612P-1 to 612P-6, 612D, 612D-1 to 612D-6: transparent electrode (612P is "First electrode of the present invention" 612D is an example of the second electrode of the present invention.) 781: Central calculation circuit 784: External power supply circuit 9 1 0: Liquid crystal display device 911: Liquid crystal panel (an example of "panel" of the present invention) 9 1 2 : Counter substrate (an example of "second substrate" of the present invention) 922: Nematic liquid crystal material 9 2 3 : Sealing material 926: Backlight unit 927: Light guide plate 940: Black matrix 990-1 to 990-6: Light receiving opening VPBT: potential of the wiring PBT (an example of the potential of the second electrode of the present invention) VDBT. The potential of the wiring DBT (an example of the "potential of the second electrode" of the present invention) LA: external light, LB: backlight -57-