200843049 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種半導體封裝構造，特別係有關 於一種可增進抗溼氣性與避免分層之半導體封裝構造。 【先前技術】 在半導體封裝構造中，特別是球格陣列封裝（Ball Grid Array, BGA)、平墊陣列封裝（Land Grid Array，LGA) 或記憶卡封裝（memory card package)，晶片係設置於基 板上並以例如環氧模封化合物（EMC)之封膠體密封 之，而基板之另一表面係為顯露，可接合複數個銲球或 外接端子，以供接合至其他印刷電路板。通常基板應僅 有單一上表面被封膠體所覆蓋，以避免在基板下表面形 成溢膠污染。然而，在進行濕氣敏感性測試（moisture sensitivity test)或溫度循環測試（temperature cycle test) 時，該基板與該封膠體間易發生分層剝離（delamination) 或爆米花（popcorn)之問題，以致使半導體封裝構造之可 靠度及品質受到影響。 请參閱第1圖所示，一種習知半導體封裝構造1〇〇 主要包含一基板110、一晶片120以及一封膠體130。 该基板110係具有一上表面111、一下表面112以及複 數個設置於該下表面1 1 2之外接墊1 1 3。該晶片1 2 0係 具有複數個銲墊1 2 1，另可藉由一黏晶層1 60將該晶片 120黏設於該基板11〇之該上表面ill，其中該些銲塾 1 2 1係為朝上，以供複數個銲線1 4 0打線接合以電性連 200843049 接至該基板11 0。該封膠體i 3 〇係密封該晶片i 2〇與該 些銲線140。複數個銲球150係設置於該基板n〇之該 些外接墊11 3，以作為該半導體封裝構造丨〇 〇之外導接 部。然而該半導體封裝構造1〇〇在長時間之使用或測試 後’其内部之元件中該基板110與該封膠體13〇之間易 發生分層之現象。請再參閱第1圖所示，濕氣會由該基 板110與該封膠體130之間的界面邊緣，沿著該基板 110之上表面侵入，到達該晶片12〇與該黏晶層16〇， 」 導致分層剝離。特別是，當濕氣侵入該黏晶層1 6 0時， 會有水解現象，又加上該晶片120與該基板11〇的熱膨 脹係數的差異，當越多的濕氣被累積與吸收在黏晶層 160甚至會有爆米花問題。 我國新型專利證號第M3 05962號「球栅陣列封裝結 構」，其技術手段係形成至少一通孔以貫通基板並設置 於晶片之周緣，且封膠體係填滿該通孔。故基板之外周 邊被封膠體覆蓋，可以增加封膠體與基板之接合面積並BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package structure, and more particularly to a semiconductor package structure which can improve moisture resistance and avoid delamination. [Prior Art] In a semiconductor package structure, in particular, a Ball Grid Array (BGA), a Land Grid Array (LGA), or a memory card package, a wafer system is disposed on a substrate. The upper surface of the substrate is exposed and the other solder balls or external terminals are bonded for bonding to other printed circuit boards. Usually the substrate should have only a single upper surface covered by the encapsulant to avoid spillage of the underlying surface of the substrate. However, when performing a moisture sensitivity test or a temperature cycle test, delamination or popcorn is liable to occur between the substrate and the sealant. The reliability and quality of the semiconductor package structure are affected. Referring to FIG. 1, a conventional semiconductor package structure 1 〇〇 mainly includes a substrate 110, a wafer 120, and a gel 130. The substrate 110 has an upper surface 111, a lower surface 112, and a plurality of pads 1 1 3 disposed outside the lower surface 1 1 2 . The wafer 120 has a plurality of pads 1 2 1 , and the wafer 120 is adhered to the upper surface ill of the substrate 11 by a die layer 160, wherein the pads 1 2 1 The upper side is connected to the plurality of bonding wires 140 to be electrically connected to the substrate 11 0. The encapsulant i 3 is used to seal the wafer i 2 and the bonding wires 140. A plurality of solder balls 150 are disposed on the external pads 11 3 of the substrate n as a conductive portion other than the semiconductor package structure. However, the semiconductor package structure 1 is susceptible to delamination between the substrate 110 and the encapsulant 13〇 in the internal components after a long period of use or testing. Referring to FIG. 1 again, moisture enters from the interface edge between the substrate 110 and the encapsulant 130 along the upper surface of the substrate 110 to reach the wafer 12 and the die layer 16 Causes delamination. In particular, when moisture invades the viscous layer 160, there is a phenomenon of hydrolysis, and the difference in thermal expansion coefficient between the wafer 120 and the substrate 11 ,, when more moisture is accumulated and absorbed in the viscous The layer 160 may even have popcorn problems. The new patent certificate No. M3 05962 "ball grid array package structure" is formed by forming at least one through hole through the substrate and disposed on the periphery of the wafer, and the sealing system fills the through hole. Therefore, the periphery of the substrate is covered by the encapsulant, and the bonding area between the encapsulant and the substrate can be increased.
U 避免濕氣入侵。然而該封膠體會經由貫通基板之通孔流 佈在基板之下表面，會有溢膠汙染外接墊之可能。此 外，改變了最終產品的外觀並且基板之線路結構必須重 作設計。 【發明内容】 本發明之主要目的係在於提供一種半導體封裝構 造，藉由基板上具有凹坑之設計，在不改變產品外觀下 增加封膠結合面積與濕氣侵入路徑，達到抗濕氣與耐熱 6 200843049 不剝離之功效。 本發明之次一目的係在於提供一種半導體封裝構 造，可避免基板楂球面之溢膠並且不需要變更基板之線 路設計。 本發明的目的及解決其技術問題是採用以下技術方 案來實現的。依據本發明，一種半導體封裝構造主要包 含一基板、一晶片以及一封膠體。該基板係具有一上表 面以及複數個形成於該上表面之凹坑，該上表面係定義 有一晶片設置區，該些凹坑係位於該晶片設置區外之線 路空白區域且不貫穿該基板。該晶月係設置於該基板之 該上表面且位於該晶片設置區内。該封膠體係形成於該 基板之該上表面’以密封該晶片。 本發明的目的及解決其技術問題還可採用以下技術 措施進一步實現。 在前述的半導體封裴構造中，該些凹坑係可鄰近於 該基板之上表面周邊。 在刖述的半導體封裝構造中，該些凹坑係可具有圓 形、矩形或多邊形之開口。 在刖述的半導體封裝構造中，該些凹坑之深度係可 介於該基板之厚度〇·丨至〇5件。 在刖述的半導體封裝構造中，該些凹坑係可主要分 佈在該基板之該上表面之角隅。 在刖述的半導體封裝構造中，該些凹坑係可為以鑽 孔方式形成之盲孔。 7 200843049 在前述的半導體封裝構造中，該些凹坑係可 射或沖壓方式形成炙盲孔。 在前述的半導體封裝構造中，該基板可另包 防銲層’其係形成於該基板之該上表面並覆蓋 坑。 在前述的半導體封裝構造中，該封膠體係可 該些凹坑。 ^ 在前述的半導體封裝構造中，該晶片係可具 個凸塊並以覆晶方式接合至該基板。 在前述的半導體封裝構造中，可另包含複 線’其係電性連接該晶片與該基板。 在前述的半導體封裝構造中，該基板可另包 數個外接塾，其係形成於該基板之一下表面。 在前述的半導體封裝構造中，可另包含有複 球’其係設置於該基板之該些外接墊。 (j 【實施方式】 依據本發明之第一具體實施例，配合參閱第 圖揭示一種半導體封裝構造。請參閱第2圖所示 半導體封裝構造200主要包含一基板210、一曰曰E 以及一封膠體230。該基板210係具有一上表S 一下表面212以及複數個形成於該上表面211 213°請參閱第2及3圖所示，該上表面211係 一晶片設置區214，以供設置該晶片220。其中 凹*几2 1 3係位於該晶片設置區2 1 4外之線路空白 為以胃 含有一 該些凹 填入於 有複數 數個銲 含有複 數個銲 2及3 :’ 一種 i 片 220 7 211、 之凹坑 定義有 ’該些 區域且 200843049 不貫穿該基板210，故在形成該些凹坑213時不會破壞 該基板2 10怎線路217結構（請參閱第3圖所示）。在本 實施例中，該些凹坑2 1 3係可為以鑽孔方式形成之盲 孔，並以鄰近於該基板210之上表面211周邊為較佳， 換言之，大部份之該些凹坑2 1 3距離至該基板2 1 0之上 表面211周邊比起其距離至該晶片設置區214來得更 短。請再參閱第2圖所示，該基板2 1 0係可包含有一防 銲層215，其係形成於該基板210之該上表面211並覆 Γ、 1 蓋該些凹坑213。該些凹坑213之深度係可介於該基板 210之厚度0.1至0.5倍。 請再參閱第3圖所示，在本實施例中，該些凹坑2 1 3 係可具有圓形之開口。該些凹坑2 1 3係可主要分佈在該 基板2 1 0之該上表面2 1 1之角隅，以局部強化該基板 2 1 0與該封膠體23 0之較弱結合部位。具體而言，該基 板2 1 0可另包含有複數個外接墊2 1 6，其係形成於該基 ^ 板210之該下表面212。 該晶片220係藉由一黏晶層260之黏貼而能設置於 該基板210之該上表面211並且位於該晶片設置區214 内。其中，該晶片220係具有一主動面221以及複數個 形成於該主動面221之銲墊222，並可利用複數個打線 形成之銲線240連接該些銲墊222至該基板210，使該 晶片2 2 0與該基板2 1 0之間形成電性連接。 該封膠體230係形成於該基板21〇之該上表面211， 以密封該晶片2 2 0與該些銲線2 4 0。在本實施例中，該 9 200843049 封膠體230係為一環氧模封化合物（Epoxy Molding Compound，EMC)，以轉移成形方式僅覆蓋於該基板210 之該上表面211。該半導體封裝構造200可另包含有複 數個銲球2 5 0，其係設置於該基板2 1 0之該些外接墊 216 ’故該半導體封裝構造2〇〇係可藉由該些銲球25 〇 接合至一外部印刷電路板。 因此，利用設計有該些凹坑2 1 3之該基板2 1 0，可 1 ^長水氣滲入路徑，因而延長水氣滲入該半導體封裝構 造200之黏晶區之時間。此外，該些凹坑2 1 3可增加該 封膠體230與該基板210之結合面積，進而增加其間之 附著力’以避免該封膠體230與該基板210之間產生分 層’進而提高該半導體封裝構造200之可靠度。再者， μ二凹坑2 1 3係不貫穿該基板2 1 0，不會改變產品外觀 亦不需要變更該基板2丨〇之線路結構，故可避免該基板 2 1 〇 > ^ 、該下表面212溢膠進而汙染該些外接墊216，又 CJ 〜二1^坑213具有形成成本低且不會傷害該基板210之 線路2 1 7結構之功效。 在第一具體實施例中，揭示另一種半導體封裝構 弟4圖係為一半導體封裝構造之截面示意圖。第5 圖係為該半導體封裝構造在封膠前之頂面示意圖。請參 閱第 4圖所示，該半導體封裝構造300主要包含一基板 31G、一晶片320以及一封膠體33〇。該基板310係具 有—卜主 上表面3 1 1、一下表面3丨2以及複數個形成於該上 11之凹i几313’該上表面311係定義有一晶片没 10 200843049 置區3 1 4 ’該些凹坑3 1 3係位於該晶片設 線路空白區域且不貫穿該基板31〇，故不 3 1 0之線路3 1 6結構。在本實施例中，該 可為以雷射方式形成之盲孔。該基板3 1 0 係形成於該基板3 1 0之該上表面3 11並 3 1 3。在本實施例中，該防銲層3 1 5之開 凹坑3 1 3之開口尺寸係為相同。本發明並 坑2 13之開口之形狀。請參閱第5圖所示 、 中，該些凹坑313係可具有矩形或多邊形 請再參閱第5圖所不’該晶片320係 3 1 0之該上表面3 1 1且位於該晶片設置區 實施例中，如第4圖所示，該晶片3 2 0係 凸塊322，其係形成於該晶片320之一主 中該晶片3 2 0係以覆晶方式接合至該基柄 體330係形成於該基板31〇之該上表面3 晶片320。請再參閱第4圖所示，在本實 ϋ 膠體3 3 0係可填入於該些凹坑3 1 3，以加強 與該基板3 1 0之間的結合強度，故可避免 增加產品之可靠度。因此’該半導體封裝 加射膠結合面積與濕氣侵入路徑達到抗 剝離之功效。 在第三具體實施例中，揭示另一種 造。請參閱第6圖所示’該半導體封裝構 含〆基板410、〆晶片420以及一封膠體 置區3 1 4外之 會傷害該基板 些凹坑3 1 3係 之防銲層3 1 5 顯露該些凹坑 孔尺寸與該些 不侷限該些凹 ，在本實施例 ，之開口。 設置於該基板 3 1 4内。在本 可具有複數個 動面321 ，其 .3 1 0。該封膠 1 1，以密封該 施例中，該封 ί該封膠體3 3 0 分層之現象以 構造300可增 濕氣與耐熱不 半導體封裝構 造400主要包 [430。該基板 11 200843049 410係具有一上表面411以及複數個形成於該上表面 411夂凹坑413，該上表面411係定義有一晶片設置區 (圖中未繪出），該些凹坑4 1 3係位於該晶片設置區外之 線路空白區域且不貫穿該基板410。請再參閱第6圖所 示，該基板410可另包含有一防銲層414，其係形成於 該基板4 1 0之該上表面4 1 1並具有複數個開槽4 1 5，以 局部顯露該上表面411。在本實施例中，該些凹坑4i3 係可位於該些開槽4 1 5内並以沖壓方式形成之盲孔。 、 該晶片420係可利用一黏晶層460將該晶片42〇之 主動面421黏著在該基板410之該上表面411，以使該 晶片420對應設置在該晶片設置區内。在本實施例中， 該基板4 1 0係可具有一槽孔4 1 7，且該半導體封裝構造 400另可包含有複數個銲線440，其係通過該槽孔417 並電性連接該晶片 420之複數個銲墊 422至該基板 4 1 0。該封膠體43 0係形成於該基板4 1 0之該上表面 411’以密封該晶片420。具體而言，該半導體封裝構U Avoid moisture intrusion. However, the encapsulant may flow on the lower surface of the substrate through the through hole penetrating the substrate, and there is a possibility that the adhesive may contaminate the external pad. In addition, the appearance of the final product is changed and the circuit structure of the substrate must be redesigned. SUMMARY OF THE INVENTION The main object of the present invention is to provide a semiconductor package structure, which has a design of a pit on a substrate, and increases the sealing area and the moisture intrusion path without changing the appearance of the product, thereby achieving moisture resistance and heat resistance. 6 200843049 The effect of no peeling. A second object of the present invention is to provide a semiconductor package structure that avoids the overflow of the substrate ball and does not require changing the circuit design of the substrate. The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. According to the present invention, a semiconductor package structure mainly comprises a substrate, a wafer, and a gel. The substrate has an upper surface and a plurality of dimples formed on the upper surface, the upper surface defining a wafer placement region, the recess being located in a blank area outside the wafer placement region and not extending through the substrate. The crystal moon is disposed on the upper surface of the substrate and in the wafer setting region. The encapsulation system is formed on the upper surface of the substrate to seal the wafer. The object of the present invention and solving the technical problems thereof can be further realized by the following technical measures. In the foregoing semiconductor package construction, the recesses may be adjacent to the periphery of the upper surface of the substrate. In the semiconductor package construction described above, the dimples may have circular, rectangular or polygonal openings. In the semiconductor package structure described above, the depth of the pits may be between 〇·丨 and 〇5 of the substrate. In the semiconductor package construction described above, the pits may be mainly distributed at the corners of the upper surface of the substrate. In the semiconductor package construction described above, the dimples may be blind holes formed by drilling. 7 200843049 In the aforementioned semiconductor package construction, the dimples are formed by bumping or stamping. In the foregoing semiconductor package structure, the substrate may be additionally provided with a solder resist layer which is formed on the upper surface of the substrate and covers the pit. In the aforementioned semiconductor package construction, the encapsulation system can be recessed. In the foregoing semiconductor package construction, the wafer system may have bumps and be bonded to the substrate in a flip chip manner. In the foregoing semiconductor package structure, a double wire may be further included which electrically connects the wafer to the substrate. In the foregoing semiconductor package structure, the substrate may be additionally provided with a plurality of external turns formed on a lower surface of the substrate. In the foregoing semiconductor package structure, a plurality of bonding balls may be further included in the external pads of the substrate. (Embodiment) According to a first embodiment of the present invention, a semiconductor package structure is disclosed with reference to the drawings. The semiconductor package structure 200 shown in FIG. 2 mainly includes a substrate 210, a 曰曰E, and a The substrate 210 has a top surface S of the upper surface S 212 and a plurality of surfaces 211 213 formed on the upper surface. Referring to FIGS. 2 and 3, the upper surface 211 is a wafer setting area 214 for setting. The wafer 220, wherein the recess *2 1 3 is located outside the wafer setting area 2 1 4, the blank of the line is filled with the concave portion of the stomach, and the plurality of solders are filled with a plurality of solders 2 and 3: The recesses of the i-pieces 220 7 211 are defined as 'these regions and the 200843049 does not penetrate the substrate 210. Therefore, when the pits 213 are formed, the structure of the substrate 2 10 is not damaged (see FIG. 3). In the present embodiment, the dimples 2 1 3 may be blind holes formed by drilling, and preferably adjacent to the periphery of the upper surface 211 of the substrate 210. In other words, most of them The pits 2 1 3 are spaced above the substrate 2 1 0 The periphery of the surface 211 is shorter than the distance from the wafer setting area 214. Referring to FIG. 2 again, the substrate 210 may include a solder resist layer 215 formed on the substrate 210. The surface 211 is covered and covered by the recesses 213. The depth of the pits 213 may be 0.1 to 0.5 times the thickness of the substrate 210. Referring to Figure 3, in this embodiment, The dimples 2 1 3 may have circular openings. The dimples 2 1 3 may be mainly distributed at the corner 该 of the upper surface 21 1 of the substrate 2 10 to locally strengthen the substrate 2 1 0, a weaker bonding portion with the encapsulant 230. Specifically, the substrate 210 may further include a plurality of external pads 2 1 6 formed on the lower surface 212 of the substrate 210. The wafer 220 is disposed on the upper surface 211 of the substrate 210 and is disposed in the wafer mounting region 214 by bonding a bonding layer 260. The wafer 220 has an active surface 221 and a plurality of layers formed thereon. a bonding pad 222 of the active surface 221, and connecting the bonding pads 222 to the substrate 210 by using a plurality of bonding wires 240 formed by wires An electrical connection is formed between the wafer 220 and the substrate 210. The encapsulant 230 is formed on the upper surface 211 of the substrate 21 to seal the wafer 220 and the bonding wires 240. In this embodiment, the 9 200843049 encapsulant 230 is an Epoxy Molding Compound (EMC), and covers only the upper surface 211 of the substrate 210 by transfer molding. The semiconductor package structure 200 can further include a plurality of solder balls 250, which are disposed on the external pads 216 of the substrate 210. Therefore, the semiconductor package structure 2 can be formed by the solder balls 25 The 〇 is bonded to an external printed circuit board. Therefore, by using the substrate 2 1 0 designed with the pits 2 1 3, water can penetrate into the path, thereby prolonging the time during which moisture penetrates into the die bond region of the semiconductor package structure 200. In addition, the recesses 213 can increase the bonding area of the encapsulant 230 and the substrate 210, thereby increasing the adhesion therebetween to avoid delamination between the encapsulant 230 and the substrate 210, thereby improving the semiconductor. The reliability of the package construction 200. Furthermore, the μ 2 dimples 2 1 3 do not penetrate the substrate 2 1 0 , and the circuit structure of the substrate 2 不需要 is not changed without changing the appearance of the product, so that the substrate 2 1 〇> can be avoided. The lower surface 212 overflows and then contaminates the external pads 216, and the CJ~21 pits 213 have the effect of forming a low cost structure and not damaging the structure of the substrate 210. In a first embodiment, another semiconductor package structure 4 is disclosed as a schematic cross-sectional view of a semiconductor package structure. Figure 5 is a top plan view of the semiconductor package structure prior to encapsulation. Referring to FIG. 4, the semiconductor package structure 300 mainly includes a substrate 31G, a wafer 320, and a gel 33 〇. The substrate 310 has a main surface 3 1 1 , a lower surface 3丨2, and a plurality of concave portions 313 ′ formed on the upper surface 11. The upper surface 311 defines a wafer without a 10 200843049 area 3 1 4 ' The pits 3 1 3 are located in the blank area of the chip and do not penetrate the substrate 31 , so the line 3 16 of the 3 10 is not structured. In this embodiment, the blind hole may be formed in a laser manner. The substrate 310 is formed on the upper surface 3 11 and 3 1 3 of the substrate 310. In the present embodiment, the opening size of the dimples 3 1 3 of the solder resist layer 3 15 is the same. The shape of the opening of the pit 2 13 of the present invention. Referring to FIG. 5, the pits 313 may have a rectangular shape or a polygonal shape. Please refer to the upper surface 3 1 1 of the wafer 320 system 3 1 0 in the wafer setting area. In the embodiment, as shown in FIG. 4, the wafer 320 is a bump 322 formed in one of the main bodies of the wafer 320. The wafer is bonded to the base handle 330 in a flip chip manner. The wafer 320 is formed on the upper surface 3 of the substrate 31. Please refer to FIG. 4 again, in which the solid colloid 3 3 0 can be filled in the dimples 3 1 3 to strengthen the bonding strength with the substrate 310 , so that the product can be avoided. Reliability. Therefore, the semiconductor package adhesive bonding area and the moisture intrusion path achieve the effect of resisting peeling. In the third embodiment, another construction is disclosed. Referring to FIG. 6 , the semiconductor package structure includes a germanium substrate 410, a germanium wafer 420, and a solder mask region 3 1 4 which may damage the solder resist layer 3 1 3 of the substrate. The size of the pit holes and the recesses are not limited to those in the embodiment. It is disposed in the substrate 3 1 4 . In this case, there may be a plurality of moving faces 321, which are .3 1 0. The encapsulant 1 1 is used to seal the seal of the sealant in the embodiment, and the structure of the sealant 3 3 0 is structured to form a package of 300 moisture-reinforcing and heat-resistant semiconductor package 400 [430. The substrate 11 200843049 410 has an upper surface 411 and a plurality of recesses 413 formed on the upper surface 411. The upper surface 411 defines a wafer setting area (not shown), and the pits 4 1 3 The line blank area outside the wafer setting area is not penetrated through the substrate 410. Referring to FIG. 6 again, the substrate 410 may further include a solder resist layer 414 formed on the upper surface 41 1 of the substrate 410 and having a plurality of slots 4 15 for partial exposure. The upper surface 411. In this embodiment, the dimples 4i3 are blind holes that can be formed in the slots 4 1 5 and formed by stamping. The wafer 420 can adhere the active surface 421 of the wafer 42 to the upper surface 411 of the substrate 410 by using a bonding layer 460, so that the wafer 420 is correspondingly disposed in the wafer setting region. In this embodiment, the substrate 410 can have a slot 411, and the semiconductor package structure 400 can further include a plurality of bonding wires 440 passing through the slot 417 and electrically connecting the wafer. A plurality of pads 422 of 420 are applied to the substrate 410. The encapsulant 430 is formed on the upper surface 411' of the substrate 410 to seal the wafer 420. Specifically, the semiconductor package
CJ 造4 00可另包含有複數個銲球450，其係設置於該基板 410之複數個外接墊416，其中該些外接墊416係形成 於該基板410之一下表面412。 因此，利用該些凹坑4 1 3之設置位置與組合關係能 增加濕氣侵入路徑，達到抗濕氣，亦可增強該封膠體 4 3 0對該基板4 1 0之結合力，以防止封膠分層及避免引 發爆米花現象。 以上所述，僅是本發明的較佳實施例而已，並非對 12 200843049 本發明作任何形式上的限法丨丨 制’本發明技術方案範圍當依 所附申請專利範圍為準。任柄勃杂丄* 一 仕何热悉本專業的技術人員可 利用上述揭示的技術内容作山 4作出些許更動或修飾為等同 變化的等效實施例，但凡B 4 疋未脫離本發明技術方案的内 容，依據本發明的技術實暂…，& T耳買對以上實施例所作的任何簡 單修改、等同變化與修飾，的 ^ 均仍屬於本發明技術方案的 範圍内。 ΟThe CJ 4 can additionally include a plurality of solder balls 450 disposed on the plurality of external pads 416 of the substrate 410, wherein the external pads 416 are formed on a lower surface 412 of the substrate 410. Therefore, the position and the combined position of the dimples 4 1 3 can increase the moisture intrusion path to achieve moisture resistance, and can also enhance the bonding force of the encapsulant 410 to the substrate 410 to prevent sealing. Glue layering and avoid popping. The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the invention to the invention. The scope of the present invention is defined by the scope of the appended claims.任 勃 丄 丄 一 一 一 热 热 热 热 热 热 热 热 热 热 热 热 热 热 热 热 热 热 热 热 热 热 热 热 热 热 热 热 热 热 热 热 热 热 热 热 热 热 热 热 热 热 热 热 热 本 本The contents of the present invention are in accordance with the technical scope of the present invention, and any simple modifications, equivalent changes and modifications made to the above embodiments are still within the scope of the technical solution of the present invention. Ο
Ci 【圖式簡單說明】 第1圖· -種習知半導體封裝構造之截面示意圖。 第2圖·依據本發明之第—具體實施例，一種半導體封 裳構造之截面示意圖。 第3圖：依據本發明之第一具體實施例，該半導體封裝 構造在封膠前之頂面示意圖。 第4圖：依據本發明之第二具體實施例，另一種半導體 封襄構造之截面示意圖。 第5圖·依據本發明之第二具體實施例，該半導體封裝 構造在封膠前之頂面示意圖。 第6圖·依據本發明之第三具體實施例，另一種半導體 封裝構造之截面示意圖。 【主要元件符號說明】 100半導體封裝構造 110基板 111上表面 112下表面 113外接墊 120晶片 121銲墊 13 200843049Ci [Simple description of the drawing] Fig. 1 - A schematic cross-sectional view of a conventional semiconductor package structure. Fig. 2 is a cross-sectional view showing a semiconductor package structure in accordance with a first embodiment of the present invention. Figure 3 is a top plan view of the semiconductor package construction prior to encapsulation in accordance with a first embodiment of the present invention. Figure 4 is a cross-sectional view showing another semiconductor package structure in accordance with a second embodiment of the present invention. Figure 5 is a top plan view of the semiconductor package prior to encapsulation in accordance with a second embodiment of the present invention. Fig. 6 is a cross-sectional view showing another semiconductor package structure in accordance with a third embodiment of the present invention. [Main component symbol description] 100 semiconductor package structure 110 substrate 111 upper surface 112 lower surface 113 external pad 120 wafer 121 solder pad 13 200843049
ϋ 130 封膠體 140 銲線 150 銲球 160 黏晶層 200 半導體封裝構造 210 基板 211 上表面 212 下表面 213 凹坑 214 晶片設 置 區 215 防銲層 216 外接墊 217 線路 220 晶片 221 主動面 222 銲墊 230 封膠體 240 銲線 250 銲球 260 黏晶層 300 半導體封裝構造 310 基板 311 上表面 312 下表面 313 凹坑 314 晶片設 置 區 315 防銲層 316 線路 320 晶片 321 主動面 322 凸塊 330 封膠體 400 半導體封裴構 造 410 基板 411 上表面 412 下表面 413 凹坑 414 防銲層 415 開槽 416 外接墊 417 槽孔 420 晶片 421 主動面 422 銲墊 430 封膠體 440 銲線 450 銲球 460 黏晶層 14ϋ 130 Sealant 140 Solder wire 150 Solder ball 160 Bonded layer 200 Semiconductor package structure 210 Substrate 211 Upper surface 212 Lower surface 213 Dimple 214 Wafer setting area 215 Solder mask 216 External pad 217 Line 220 Wafer 221 Active surface 222 Pad 230 Sealant 240 Solder wire 250 Solder ball 260 Bonded layer 300 Semiconductor package structure 310 Substrate 311 Upper surface 312 Lower surface 313 Pit 314 Wafer setting area 315 Solder mask 316 Line 320 Wafer 321 Active surface 322 Bump 330 Sealant 400 Semiconductor package structure 410 substrate 411 upper surface 412 lower surface 413 pit 414 solder resist layer 415 slot 416 external pad 417 slot 420 wafer 421 active surface 422 pad 430 sealant 440 wire 450 solder ball 460 bonding layer 14