200842986 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種製作具有金屬閘極之金氧半導體電晶體的 方法’尤指-種製作出具有γ型金屬閘極之金氧料體電晶體的 方法。 【先前技術】 奴著半導體技術不斷進步，目前業界已經能夠製造出45奈米 (nm)之半導體裝置。而現今的金氧半導體場效電晶體 (Metal-Oxide-Semiconductor Field-Effect Transistors; MOSFET)多數 是利用多晶矽(P〇ly_silicon)材料來製作閘極(Gate)。但是，既有之 摻雜多晶矽材料做為閘極結構之方法尚存在多晶矽閘極的空乏效 應(Depletion Effect)及硼穿透(Boron Penetration)至通道區域等問題。 以多晶矽閘極的空乏效應為例，多晶矽閘極在反轉階段 (Inversion)會在多晶石夕鄰近閘極介電質(〇伽Dieiectric)的區域產生 載子(Carrier)空乏的現象。假若此多晶矽閘極發生多晶矽閘極的空 乏效應’則其有效閘極電容(册ectGateCapacitance)會降低。但 疋，良好的電子產品之金氧半導體電晶體卻應該具有高單位的閘 極電容。因為，閘極電容越高時，閘極電容兩邊會累積越多的電 何’所以通道中便可以有更多的電荷累積，故當金氧半導體電晶 體％連接至偏壓時，源極/汲極（s〇urce/Drain)之間的電流流動率會 更良好。 胃 6 200842986 請^考第1⑻圖，第i⑻圖係為習知金氧料體電晶體之示意 圖在第1圖中基底10上方具有一閘極結構12，問極結構^和 基底10之間具有—閘極介電層，且閘極結構u相對應的兩側 之基底ίο中，具有源極/沒極14，而閘極結構12周圍環繞—側壁 子H、中舰結構12與源極級極⑷冓成金氧半導體電晶體 18,且閘極結構12係由多晶々所製作而成。當金氧半導體電晶體 1S發生多晶·極的空乏效應時，帶電荷的載子會累積在間極結 構12與閘極介電層15之間’使得等效閘極介電層的厚度增加。 因此:閘極電容值會隨之下降，進而降低閘極電容的總值，並導 致金氧半導體電晶體驅動能力的衰退。 :、、、、免上述夕曰曰石夕閘極的空乏效應，目前業界多利用金屬問 極取代多晶销極，其相關製程可利用「取代閘極⑽⑻师邮 蛛）」製程來完成。也就是先形成—偽多祕閘極(d_y —n gate) ’接著，再去除此偽多晶石夕間極以形成一凹槽， 並在其簡⑽成-金屬閘極。另外，金屬_和基底之間又常 '、有章€以及间介電常數材料(Wgh-k)介電層，以防止閘極 結構漏電並增加製程的彈性。而這種結構經常被使用於45nm及 乂下一件中以減少多晶石夕耗竭效應，提供較低之熱預算，進 而提尚元件效能。 7 200842986 寬度比，使得沈積阻障層時容易發生阻障層階梯覆蓋(卿_零) 不良的情況。請參考第1(b)圖與第1(c)圖，第1(b)圖與第1(〇圖係 為傳統金氧半導體電㈣之製作方絲意圖。如第_圖所示， 去除偽多晶石夕閘極之後，基底1〇上具有一凹槽22，且凹槽Μ本 身具有-定的深度L與寬度w。沈積於基底1〇上的阻障層％造 成凹槽22開口縮小(overhang)現象，並且導致後續填入金屬形成 ，屬f極26的製程容易產生孔洞㈣)現象，如第⑽圖所示。 這使得後續製程時金私_受到化學損傷(ehemieauttack)而影 響π件特性。有鑑於此，如何製造出無階梯覆蓋不㈣題之阻障 層的金氧半導體電㈣’係半導體業界—猶要課題。 【發明内容】 、一本發日肚要的目的是在於提供—種具有Y型金屬閘極之金氧 半¥體電晶體及其製程以解決上述問題。 入，根據本發明之請求項，本發明提供—種製作具有金屬閘極之 =半導體綱驗，咖纖，基紅方具有間極犧 2换側好隠閘極齡層，_齡層姆兩敗基底内各 ::雜區。接著’於閘極犧牲層、側壁子以絲底上方依序形 =層與介電層。之後，絲部份介電層至曝露出絕緣層，並 =極犧牲層上款絕緣層與閘極犧牲層，鱗麵之側壁子 。其後，在側壁子内形成凹槽。形成阻障層於凹 内J、傾嫌糊崎恤，蝴綱層於凹槽 200842986 • 内、傾斜邊緣以及剩餘之介電層上，以及去除剩餘之介電層上方 之阻障層和導電層，使剩餘之阻障層和導電層得以形成金屬間極。 根據本發明之請求項，本發明提供一種具有γ型金屬閘極之 金氧半導體電晶體，包含基底，γ型金屬閘極位於基底上方，二 摻雜區位於Υ型金屬閘極相對兩側之基底内。 由於本發明之阻障層填入凹槽時，因為凹槽開口處有傾斜邊 緣，所以有效深度/寬度比較先前技術小，因此，本發明不會發生 先前技術中阻障層階梯覆蓋不良的問題。又因為本發明沒有9阻Χ障 層階梯覆蓋不良的問題，所以，金屬閘極可完整填入凹槽中，製 作出口口負良好之具有金屬閘極的金氧半導體電晶體。 【實施方式】 凊參考第2至6®，第2至6圖係為本發明第—實施例之取 、代閘極製作方法的示意圖。如第2圖所*，一基底5〇上具有一間 極、、、。構57 ’閘極結構π包含有一閘極絕緣層52，一閘極犧牲層 54以及-閘極覆蓋層（caplayer)56。其中，基底兄可由石夕基底、 含石夕基底或者石夕I絕緣(Silicon_on_Insulat〇r，s〇l)等半導體材料所 構成。而閘極絕緣層52則可為氧化層(〇xide)、氮氧化物 (Oxy Nitride)層等具有氧原子或者氛原子的介電質以及氧原子和 氮原子組合物的介電材料所構成。另外，在第-實施例中，閘極 犧牲層54係利用多晶石夕材㈣成，閘極覆蓋層兄則可包含有氧 200842986 . 化物層、氮氧化物層或是氮化物層。 於閘極結構57 _之基底％ _成輕摻雜汲極(Lightly D〇PedDrain，LDD ’亦可稱為輕摻雜源極)58以及源極/汲極62。 另外，源極/汲極62之表面又可視製程需要與元件特性等考量，形 成:金屬魏物(silidde)層63。再者，.結構57周關圍繞一 以乳化石夕、氧化石夕或氮化石夕/氧化石夕複合材質之側壁子(叩咖⑽。 而-絕緣材質之接觸孔侧停止層(c_ct —轉如，c亂） 64覆蓋在閘極結構57、側壁子6〇和基底％上方。其中，形成接 觸孔鞋刻止層64的目的’除了使後續的接觸洞侧能有韻刻終 點作為，刻停止層用之外，另外其可產生壓縮或拉伸應力之功、 用’使得閉極結構57下方與源極/汲極62間之通道區域形成應變 、、σ構▲以增進通道之電荷遷移率或電洞遷移率。再者，在接觸孔 侧停止層64上方又具有一内層介電層(Inter_Levei取丨咖， Μ)6^6。其中，接觸孔银刻停止層64可為一氮化石夕層或包含碳、 氟之氮化石夕層等絕緣層，而内層介電層的則可由氧化物或推有 硼、磷之氧化矽等材料所構成。 睛參考第3圖，隨後，利用一化學機械娜⑽咖㈣ echamcal p〇hshmg，CMp)之平坦化製程與一蝕刻製程來曝露閘 芦犧t層％ °例如，先進行—化學機械研磨製程，以接觸孔敍刻 I ' 64作為化學機械研磨製程之研磨終止層，也就是研磨内層 ’丨1 66至接觸孔侧停止層64。或者，此階段亦可藉由 10 200842986 製程先研磨去除一部份内層介電層66，而保留&卩八位於接 刻停止層64上的内層介電層66。接著，進彳千 _ 艰仃—蝕刻製程，去除位 於閑極犧牲層54上方的接觸孔侧停止層64，並使得剩餘的内層 介電層66、接觸孔飯刻停止層64和侧壁+ μ y 卞㈧上形成一傾斜邊緣 68。於本實施射’傾斜邊緣68主要是位於職犧牲層％周圍 的側壁子60、接觸孔朗停止層64、與内層介電層的上。秋而， 傾斜邊緣68的尺寸、位置侧斜肖度_趣槪。於本發明之 其他實施例中，傾斜邊緣68也可以僅位於間極犧牲層％周圍的 側壁子60與接觸孔_停止層64上，而不覆蓋勒層介電層的。 在上述之實施射’形·斜邊緣68 _程可以利用濕 式敍刻或者是乾式_完成。以濕絲刻為例，可對氣化石夕 和氧化層具有高度_選擇比咖濕式钱刻溶液，例如一 碟酸類溶液，侧去除錢切騎⑽接觸孔綱停止層料。 因為濕式蝴是—卿向⑽_输_祕ng)，所以，濕式蝕 d不C α在縱向進行侧，而且也會有橫向的侧效果。再者， 由於内層介電層66的部分被_的速度較純氮切材質的接觸孔 I蝴Τ止層64’所以靠近内層介電層66的接觸孔敍刻停止層 64被細的厚紐纟隨切㈣的接麻侧停止層64少，故會 自然形成傾斜邊緣68。 —又或者作為形細斜邊緣Μ _刻製程 ，可利用 對氣化神氧化層具有高度酬選擇比的乾式侧氣體，例如氯 11 200842986 =’I氣乙说和演化氣混合氣體，針對接觸孔触刻停止層64與部 :内yi電層66進行侧’以蝴出傾斜邊緣⑽。另外，無論是 以咖㈣細斜邊緣’皆可調整侧成分 Λ、斜U 68 A成且去除閘極覆蓋層56之後，請參考第4 凹槽72 =衣”閘極犧牲層54及閘極絕緣層52，以形成- 曰-，凹槽72周圍係為側壁子⑼之 部職有基底去除酿犧牲層5 到溶液作為_溶液。若以硝酸/氣化氣組成之化輪 化氣為主喊體，《去除_=^4除/可_綠或者漠 層的材料並不僅限於多晶石夕，:要5^ =粒意’閉極犧牲 有適當蝕刻選擇比的材麻__ ”要疋和間極絕緣層52相較具 、〇選作為閘極犧牲層54的材料。 姓刻去除閘極絕緣層52的蝕 是乾式蝕刻，若以濕式 Χ 4亦可選擇用濕式蝕刻或者 可選擇使用氣化氯組成石夕材f的開極絕緣層义，則 侧去除，則可使用m 了讀輕液。若以乾式 方式，以去輪絕緣層雜子縣細5吟〜） 後或後續閘極介電層形成叫去除閘極犧牲層54 IΘ %裝程。 200842986 • 請參考第5圖，接著，彻化學氣相沈積方法或者其他沈積 方法，形成一高介電常數(High K)材料層82於該凹槽72内壁，以 及傾斜邊緣68、剩餘内層介電層66上。一般作為高介電常數材料 層82的材料包含有高溫過渡金屬、貴重金屬、稀土金屬等元素以 及其鋁化物、矽化物或含氮氧的鋁化物、矽化物如氮氧矽铪 (HfSiON)、氧化此(Gd2〇3)、氧化鋼(Dy2〇3)等。而一般在形成高介 電常數材料層82之前，會先在高介電常數材料層82與基底5〇間 f 形成一個介面層(未顯示），該介面層(未顯示）包含一個由加熱或是 化學鍵結而形成的氧化矽層、氮氧化矽層或氮化矽層。而完成高 介電常數材料層82的沈積之後，再於高介電常數材料層82表面 形成一阻障層(barrier layer) 84，其形成方法包含有原子層沈積法 (ALD)、化學氣相沈積法(chemical Vapor Deposition，CVD)或者物 理氣相沈積法(Physical vapor deposition，PVD)，且其材料包含有高 溫過渡金屬、貴重金屬、稀土金屬等元素以及其碳化物、氮化物、 碎化物、紹氮化物或氮碎化物，例如氮化鈦(titanium nitride，TiN)、 %, 氮化钽(tantalum nitride, TaN)、碳化钽(tantalum carbide，TaC)、氮 矽化组(tantalum silica-nitride, TaSiN)、鋁默化翻(MoA1N)等材料。 部分阻障層84可以兼具有功函數調節功能如TaC等。在第一實施 例中，在部分無功函數調節功能阻障層84上方又可再形成一功函 數(work function)調整層，其材料可為釕(ruthenium，Ru)等含金屬元 素之材料。 由於本發明之第一實施例中的凹槽72上方具有傾斜邊緣 13 200842986 68 ’所以第-實施例中凹槽72的開口較大，使得凹槽 深度L，與寬度W的比值(L，/w)下降，所以高介電常數材料層u 以及阻障層84填入時，不會發生階梯覆蓋不良的情況，且二 凹槽72的開口產生縮小現象。 t兄 之後，請參考第6圖’阻障層84完成後，形成—導電層(未顯 不)於内層介電層66上並填滿凹槽72和傾斜邊緣68。 層可利用麵、氮化鈦(TiN)、觸_)等金屬材料或人 電層(未顯示）、阻障㈣與高介電常娜層 =進订-平坦f程，彻—化學機械研㈣程暴露 介電層66。而最後位於凹槽72和傾斜邊緣6 高㈣ :職=剩餘_，與剩餘導電層9。即‘ 於第心例中，金屬閘極92係填滿凹槽72和傾斜邊緣姑， =金相極92的剖面結構會約略具有—γ型結構。而金屬間極 62 ㈣氧轉_體。之後， p、舰積介電層，並依序形成所需之金屬内 體元件之製作。 凡取干守 66、二si弟—實施例的變化型中’當第2圖中的内層介電層 6被去除至曝露出接觸蝴停止層⑷夺，亦可利用一離子· =咖去除__4上辕麻侧停止 難龜=得剩餘的内層介電層的、接觸聽刻停止層64和 曰上形成一傾斜邊緣68。而在進行離子雇擊製程的過 200842986 王也可以在同—個機台中同時進行-乾弋蝕 間極覆蓋層56，並調整乾式綱 t式韻刻製程，以去除 形成凹槽72。換句話說，第—實施例;以::圣犧牲層Μ，進而 離子敍相 H i Μ同時進行 後’只需依序職介_刪、轉=緣68㈣槽72。之 例之描作金相極即可，其詳細製程科此實施 請參考第7至10圖’第7至1〇圖 :代間極製作方法示意圖。如第7圖所示，一基二 ::絕，、-閉極犧牲層】。—極覆蓋層(二 "，基底1GG可由錄底或切覆絕緣等半導體材料所構成。 而閑極絕緣層搬則可為氧化層、氮氧化物層等具有氧原子或者 亂原子的料質錢氧原子㈣軒組合物的介紐料所構成。 另外’在第二實施例中，閘極犧牲層1〇4係利用多晶秒材質構成。 於閘極絕緣層102以及閘極犧牲層丨〇4兩側之基底1〇〇内具 有輕摻雜汲極108以及源極/汲極112，另外，源極/汲極112上又 具有金屬矽化物層113。再者，閘極絕緣層1〇2以及閘極犧牲層 1〇4周圍則圍繞一以氮化石夕為材質之側壁子11〇。 接著，沈積一接觸孔蝕刻停止層114覆蓋在閘極犧牲層1〇4、 側壁子110和基底100上方。另外，又沈積一内層介電層116在 接觸孔蝕刻停止層114上方。其中，接觸孔蝕刻停止層114係為 15 200842986 ^的亂化發層或包含碳、氟之氮化補，而内層介電層 1 6默由減層雜_、獻氧化卿減。讀，利用化; 製程熱·㈣曝露閘極犧 : =磨製程研磨去除部份之内層介電層ιΐ6^^^ 刻(etch back)製程部份之内 止層114。之m士日層116直到裸露出接觸孔餘刻停 耗δ周整不同的银刻成分，以去除間極犧牲層 到裸ιΓΓ孔餘刻停止層114，以及閘極覆蓋層(未顯示），直 裸路出夕一材質的間極犧牲層104。 緣居考_ ’侧去除閘極犧牲層W4以及閘極絕 賴辟所^ ^。其卜凹槽⑽係由側壁子⑽的垂 的轉底部則為基底100。其中去除閘極犧_ 去除多肖4式糊或者是乾式闕。若以濕式钱刻 成極犧牲層1〇4，則可選擇使用石肖酸/氣化氣組 氯氣或I /作為餘刻溶液。若以乾式餘刻去除，則可利用 音，、主魏體，財__牲層iG4。在此請注 簡不僅限於多晶石夕，只要是和間極絕 104的材料。I虫列去二4擇比的材料都可選作為閑極犧牲層 峨者1G2 _物村·用濕式 層102目丨/右以濕式侧去除多晶石夕材質的間極絕緣 二-:=,=:==作為，。 «去除_絕緣層102。去除時機可以在去除閉極或 16 200842986 後續閑極介電層形成前•置清潔製程。 月接、參考第9圖’針對凹槽丨 程或蝕刻製程，使得_1ις? V軒轟擊製 刻停止層m被去除，=18:口處的側壁子110和部份接觸触 具有傾斜邊緣m ’ _可=斜邊緣⑽。由於凹槽118周圍 w的比值(LVW)下降。μ使㈣槽m的有效深度L，與寬度 然後’請參考第1〇圖，於凹槽m底部之基底1〇〇上方形成 一閘極介電層132。J：中，鬥托人中兑 数將w… 介魏132可以藉由氧化製程包含 ^子A形成’即對含石夕成份之基底100進行氧化使得部分 132形成於凹槽118底部。接著，利用化學氣相沈積 方法或I、他沈積方法，全面形成一高介電常數材料層（未顯利 於該凹槽m内’以及傾斜邊緣12〇、内層介電層116上。完成高 介電常數材料層（未顯示)的沈積之後，再於高介電常數材料層 (未顯示)表面形成-阻障層（未顯示）。其後，形成一導電層(未顯 示)於内層介電層116上並填滿凹槽m和傾斜邊緣12〇。然後， 利用-化學树磨製程將導電層(未顯示)研磨至暴露出剩餘内 層介電層m、剩餘高介電常數材m 134,與剩餘轉層136,。 最後位於哺m和傾斜邊緣⑽_繼高介料數材料層 m，、剩餘阻障層136，及剩餘金屬材料138即為金屬間極14〇。之 後’可再接續沈積介電層，並依序形成所需的金屬内連線，以完 成功能完整之半導體元件。 17 200842986 一般作為高介電常數材料層（未顯示）的材料包含高溫過渡 ，屬、貴重金屬、稀土金群元素以及翻化物、魏物或含氮 乳_化物、魏物如氮氧雜、氧化乱、氧化鋼。阻障層形成 方法包含有原子層沈積法、化學氣相沈積法或者物理氣相沈積 法，且其材料包含有高溫過渡金屬、貴重金屬、稀土金屬等元素 从其碳化物、缝物、氮化物、魏物、喊化物或氮石夕化物 氮化鈦氮化组、叙化组、銘氮化銷、氮秒化麵等材料。部分 阻障層(未顯示)可以兼具有功函數調節功能如加等。在第二實施 例中’在部分無功函數調節魏阻障層（未顯示)上方又可再形成 -功函數_層’其㈣可為_含金屬元素之材料。 如同本發明第-實施例之優點，由於本發明之第二實施例中 ^凹槽m賴具有傾斜邊請，所以_ 118的有效深度/寬 X比(L—/W)較小，因此’高介電常數材料層（未顯示)以及阻障層 (。未顯不）填^時，不會發生階梯覆蓋不良的情況。其中，導電層 :、烏II化鈦、鎮化鈦等金屬材料構成。由於第二實施例中， 且右恥14G係填滿凹槽118和傾斜邊緣12G，所以金屬閘極140 型結構。而第二實施例中的金氧半導體電晶體係由金屬 ψ/ 和源極/汲極112所構成。由於本發明之阻障層填入凹槽 m·為叫開ϋ處有傾斜邊緣’所財效深度7寬度(l，/w)比先 二’因此’本發明不會發生先前技術中阻障層階梯覆蓋不 二=。又因為本發明沒有阻障層階梯覆蓋不良的問題，所以， 五完整填入凹槽中，以製作出品質良好之具有金屬閘極 18 200842986 . 的金氧半導體電晶體。 以上所述僅為本發明之較佳實施例，凡依本發明申靖專矛# 圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 範 【圖式簡單說明】 第1(a)圖係為習知金氧半導體電晶體之示意圖。 導體電 弟Kb)圖與第1(。)_示的是一般具有金相極的 曰曰體發生開口縮小現象與孔洞現象之示意圖。 基底 閘極結構 源極/>及極 閘極介電層 側壁子 金氧半導體電晶體 閘極絕緣層 阻障層 剩餘阻障層 凹槽 【主要元件符號說明】 10、50、100 12、57 H、62、112 15、 132 16、 60、11〇 18 52、1〇2 84 84,、136， 72 、 118 19 200842986 90 剩餘導電層 92、140 金屬閘極 54、104 閘極犧牲層 56、63、113 金屬石夕化物層 58、108 輕摻雜汲極 64、114 接觸孔#刻停止層 66、116 内層介電層 68、120 傾斜邊緣 82 高介電常數材料層 82,、134， 剩餘高介電常數材料層 138 剩餘金屬材料 L、L， 深度 W 寬度 20200842986 IX. Description of the Invention: [Technical Field] The present invention relates to a method for fabricating a metal oxide semiconductor transistor having a metal gate, in particular, a metal oxide body having a gamma-type metal gate The method of crystals. [Prior Art] Slave semiconductor technology continues to advance, and the industry has been able to manufacture 45 nanometer (nm) semiconductor devices. Most of today's Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) use polysilicon (P〇ly_silicon) materials to make gates. However, the existing doped polysilicon material as the gate structure still has problems such as the depletion effect of the polysilicon gate and the Boron Penetration to the channel region. Taking the depletion effect of the polysilicon gate as an example, the polymorphic gate in the inversion phase will cause carrier depletion in the region adjacent to the gate dielectric (Sega Dieiectric) in the polycrystalline stone. If the polysilicon gate occurs in the polysilicon gate, the effective gate capacitance (the ectGateCapacitance) will decrease. However, a good electronic product MOS transistor should have a high unit of gate capacitance. Because, the higher the gate capacitance, the more electricity will accumulate on both sides of the gate capacitance. Therefore, more charge accumulation can occur in the channel. Therefore, when the MOS transistor is connected to the bias voltage, the source/ The current flow rate between the drains (s〇urce/Drain) will be better. Stomach 6 200842986 Please refer to Figure 1 (8), the i (8) diagram is a schematic diagram of a conventional oxy-oxide body transistor. In the first figure, there is a gate structure 12 above the substrate 10, and between the gate structure and the substrate 10 a gate dielectric layer, and a substrate/zero electrode 14 in the substrate λ of the gate structure u, and a gate structure 12 surrounding the sidewall structure H, the middle ship structure 12 and the source level The pole (4) is formed into a MOS transistor 18, and the gate structure 12 is made of polysilicon. When the MOS transistor 1S undergoes a depletion effect of polycrystals, a charged carrier accumulates between the interpole structure 12 and the gate dielectric layer 15 to increase the thickness of the equivalent gate dielectric layer. . Therefore, the value of the gate capacitance decreases, which in turn reduces the total value of the gate capacitance and causes the degradation of the driving ability of the MOS transistor. :,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, That is, the first dummy-d gate is formed. Then, the pseudo-polycrystal is removed to form a recess, and is simply (10)-metal gate. In addition, the metal _ and the substrate are often ', have a chapter and a dielectric constant material (Wgh-k) dielectric layer to prevent leakage of the gate structure and increase the flexibility of the process. This structure is often used in 45nm and the next to reduce the polycrystalline depletion effect, providing a lower thermal budget and improving component performance. 7 200842986 The width ratio makes it difficult for the barrier layer to cover (clear_zero) when depositing the barrier layer. Please refer to the first (b) and the first (c), the first (b) and the first (the original is the traditional MOS semiconductor (four) to make the square wire intention. As shown in Figure _, remove After the pseudo-polycrystalline slab gate, the substrate 1 has a recess 22 thereon, and the recess Μ itself has a predetermined depth L and a width w. The barrier layer deposited on the substrate 1 造成 causes the opening of the recess 22 The phenomenon of overhang is caused, and the subsequent filling of the metal is formed, and the process of the f-pole 26 is liable to cause the hole (4)), as shown in the figure (10). This causes the chemical process to be chemically damaged (ehemieauttack) and affects the π-piece characteristics. In view of this, how to create a gold-oxide semiconductor (4) semiconductor industry that has no barrier covering the problem of the (4) problem is a major issue. SUMMARY OF THE INVENTION A purpose of the present invention is to provide a gold oxide semiconductor body having a Y-type metal gate and a process thereof to solve the above problems. According to the claims of the present invention, the present invention provides a semiconductor inspection with a metal gate, a coffee fiber, a base red with a pole sacrifice, a side change, and a aging layer. Defeat the base:: Miscellaneous. Then, in the gate sacrificial layer, the sidewalls are sequentially formed with a layer and a dielectric layer. After that, the wire part of the dielectric layer is exposed to the insulating layer, and the sacrificial layer is provided with an insulating layer and a gate sacrificial layer, and the sidewall of the scale surface. Thereafter, a groove is formed in the side wall. Forming a barrier layer in the recess J, implying the smear, the layer on the groove 200842986 • inside, the slanted edge and the remaining dielectric layer, and removing the barrier layer and the conductive layer above the remaining dielectric layer The remaining barrier layer and the conductive layer are formed to form an intermetallic pole. According to the claimed invention, the present invention provides a MOS semiconductor transistor having a gamma-type metal gate, comprising a substrate, a gamma-type metal gate on the substrate, and a second-doped region on opposite sides of the Υ-type metal gate Inside the substrate. Since the barrier layer of the present invention fills the groove, since the groove opening has a slanted edge, the effective depth/width is smaller than that of the prior art, and therefore, the problem of poor barrier layer coverage in the prior art does not occur in the prior art. . Moreover, since the present invention does not have the problem that the barrier layer of the barrier layer is poorly covered, the metal gate can be completely filled into the recess to form a metal oxide semiconductor transistor having a metal gate with a good outlet. [Embodiment] Referring to Figs. 2 to 6®, Figs. 2 to 6 are schematic views showing a method of fabricating a gate electrode according to a first embodiment of the present invention. As shown in Fig. 2, a substrate 5 has an interlayer, and . The structure 57' gate structure π includes a gate insulating layer 52, a gate sacrificial layer 54 and a gate caplayer 56. Among them, the base brother may be composed of a semiconductor material such as a Shi Xi base, a stone-like base or a Si Xi I insulation (Silicon_on_Insulat〇r, s〇l). Further, the gate insulating layer 52 may be composed of a dielectric material having an oxygen atom or an atmosphere atom such as an oxide layer or an Oxy Nitride layer, and a dielectric material of a combination of an oxygen atom and a nitrogen atom. Further, in the first embodiment, the gate sacrificial layer 54 is formed by polycrystalline stone (4), and the gate cap layer may contain an oxygen layer 200842986. a chemical layer, an oxynitride layer or a nitride layer. The base structure of the gate structure 57_ is lightly doped (Lightly D〇PedDrain, LDD' may also be referred to as lightly doped source) 58 and source/drain 62. In addition, the surface of the source/drain 62 can be considered to be a metal silidde layer 63, depending on process requirements and component characteristics. Furthermore, the structure 57 is surrounded by a side wall of a composite material of emulsified stone, oxidized stone or nitrite/oxidized stone etched (10). The contact hole side stop layer of the insulating material (c_ct-turn For example, c chaos 64 covers over the gate structure 57, the sidewalls 6〇 and the substrate %. Among them, the purpose of forming the contact hole shoe layer 64 is to make the subsequent contact hole side have a rhyme end point, engraved In addition to the stop layer, it can also generate the work of compressing or tensile stress, using 'so that the channel region between the bottom of the closed-pole structure 57 and the source/drain 62 is strained, and the σ structure is used to enhance the charge transfer of the channel. Rate or hole mobility. Further, there is an inner dielectric layer (Inter_Levei) 6 6 over the contact hole side stop layer 64. The contact hole silver stop layer 64 may be a nitrogen. The fossil layer may comprise an insulating layer such as carbon or fluorine nitride layer, and the inner dielectric layer may be composed of an oxide or a material such as boron or phosphorous oxide. The eye is referred to Fig. 3, and subsequently, A chemical mechanical Na (10) coffee (four) echamcal p〇hshmg, CMp) flattening process An etch process is used to expose the gate layer. For example, the chemical mechanical polishing process is first performed, and the contact hole is etched as I '64 as the polishing stop layer of the chemical mechanical polishing process, that is, the inner layer of the polishing layer '丨1 66 to The hole side stop layer 64 is contacted. Alternatively, at this stage, a portion of the inner dielectric layer 66 may be first removed by the process of 10 200842986, while the inner dielectric layer 66 on the etch stop layer 64 is retained & Next, the etching process is performed to remove the contact hole side stop layer 64 above the dummy sacrificial layer 54, and the remaining inner dielectric layer 66, the contact hole stop layer 64 and the sidewall + μ A slanted edge 68 is formed on y 八 (eight). In this embodiment, the oblique edge 68 is mainly the sidewall spacer 60 around the sacrificial layer %, the contact hole stop layer 64, and the inner dielectric layer. In autumn, the size of the slanted edge 68 and the position side slanting angle _ interesting. In other embodiments of the invention, the slanted edge 68 may also be located only on the sidewall spacer 60 and the contact hole stop layer 64 around the interlayer sacrificial layer, without covering the dielectric layer. In the above implementation, the shot-shaped oblique edge 68 can be completed by wet quotation or dry _. Taking the wet wire engraving as an example, the gasification stone and the oxide layer can be highly _selected than the coffee wet etching solution, such as a dish of acid solution, and the side is removed by the money cutting (10) contact hole stop layer. Because the wet butterfly is - (G), the wet etch d is not C α in the longitudinal direction, and there is also a lateral side effect. Furthermore, since the portion of the inner dielectric layer 66 is _ faster than the contact hole I of the pure nitrogen cut material, the contact hole near the inner dielectric layer 66 is etched to stop the layer 64 from being thin. The snagging side stop layer 64 is less as it is cut (4), so the inclined edge 68 is naturally formed. - or as a thin-edged edge Μ _ etch process, can use a dry side gas with a high ratio of gas to the oxidation of the oxide layer, such as chlorine 11 200842986 = 'I gas and evolution gas mixed gas, for contact holes The etch stop layer 64 and the portion: the inner y electrical layer 66 performs a side 'to slant the slanted edge (10). In addition, after adjusting the side component Λ, the oblique U 68 A and removing the gate cap layer 56 in the fine edge of the coffee (4), please refer to the 4th groove 72 = clothing "gate sacrificial layer 54 and gate The insulating layer 52 is formed to form - 曰-, and the periphery of the groove 72 is a part of the side wall (9), and the substrate is used to remove the sacrificial layer 5 to the solution as a solution. If the nitric acid/gasification gas is composed of a round gas Shouting body, "Removing _=^4 except / can be _ green or desert material is not limited to polycrystalline stone eve,: to 5 ^ = grain meaning 'closed sacrifice, there is appropriate etching choice ratio of material __" The germanium and the interpole insulating layer 52 are compared and selected as the material of the gate sacrificial layer 54. The etch of the gate insulating layer 52 is a dry etch. If the wet Χ 4 is used, the wet etching or the optional use of vaporized chlorine to form the open insulating layer of the stone material f is removed. Then you can use m to read the light liquid. If the dry-type method is used to remove the gate insulator layer 5 or later, or the subsequent gate dielectric layer is formed to remove the gate sacrificial layer 54 I Θ % process. 200842986 • Referring to Figure 5, followed by a chemical vapor deposition method or other deposition method, a high dielectric constant (High K) material layer 82 is formed on the inner wall of the recess 72, and the inclined edge 68, the remaining inner dielectric On layer 66. Generally, the material of the high dielectric constant material layer 82 includes an element such as a high temperature transition metal, a precious metal, a rare earth metal, and an aluminide, a telluride or a nitrogen-containing aluminide, a telluride such as oxynitride (HfSiON), Oxidize (Gd2〇3), oxidized steel (Dy2〇3), and the like. Generally, before forming the high dielectric constant material layer 82, an interface layer (not shown) is formed between the high dielectric constant material layer 82 and the substrate 5, and the interface layer (not shown) contains a heating or It is a ruthenium oxide layer, a ruthenium oxynitride layer or a tantalum nitride layer formed by chemical bonding. After the deposition of the high dielectric constant material layer 82 is completed, a barrier layer 84 is formed on the surface of the high dielectric constant material layer 82, and the formation method includes an atomic layer deposition method (ALD), a chemical vapor phase. Chemical Vapor Deposition (CVD) or Physical Vapor Deposition (PVD), and its materials include high temperature transition metals, precious metals, rare earth metals and other elements and their carbides, nitrides, and fragments. Nitrogen or nitrogen compound, such as titanium nitride (TiN), %, tantalum nitride (TaN), tantalum carbide (TaC), tantalum silica-nitride (TaSiN) ), aluminum melody (MoA1N) and other materials. The partial barrier layer 84 may have a work function adjustment function such as TaC or the like. In the first embodiment, a work function adjustment layer may be formed over the partial reactive function adjustment function barrier layer 84, and the material thereof may be a metal element containing material such as ruthenium (Ru). Since the groove 72 in the first embodiment of the present invention has the inclined edge 13 200842986 68 ' above the opening of the groove 72 in the first embodiment, the groove depth L is proportional to the width W (L, / w) is lowered, so that when the high dielectric constant material layer u and the barrier layer 84 are filled, the step coverage failure does not occur, and the opening of the two grooves 72 is reduced. After t, please refer to Fig. 6 after the barrier layer 84 is completed, forming a conductive layer (not shown) on the inner dielectric layer 66 and filling the recess 72 and the inclined edge 68. The layer can be made of metal materials such as surface, titanium nitride (TiN), contact _) or human electric layer (not shown), barrier (4) and high dielectric constant layer = binding - flat f-process, thorough - chemical mechanical research (d) The process exposes the dielectric layer 66. And finally located in the groove 72 and the inclined edge 6 is high (four): job = remaining _, with the remaining conductive layer 9. That is, in the first example, the metal gate 92 fills the groove 72 and the inclined edge, and the cross-sectional structure of the metal phase pole 92 will have a -γ-type structure. The intermetallic pole 62 (four) oxygen to _ body. Thereafter, p, the reservoir dielectric layer, and the formation of the desired metal internal components are sequentially formed. Where the defensive 66, the second si brother - the variant of the embodiment - when the inner dielectric layer 6 in Figure 2 is removed to expose the contact butterfly stop layer (4), can also use an ion · = coffee removal _ _4 The ramie side stops the difficult turtle = the remaining inner dielectric layer, the contact hearing stop layer 64 and the sill form a slanted edge 68. In the case of the ion-hiking process, the king may also perform the dry-corrugated interlayer cover 56 in the same machine and adjust the dry-type t-type engraving process to remove the groove 72. In other words, the first embodiment; the:: sacrificial layer Μ, and then the ionic phase H H i Μ simultaneously performed ‘detailed job _ delete, turn = edge 68 (four) slot 72. The example can be described as a metal phase. For detailed implementation of this process, please refer to Figures 7 to 10'. Figure 7 to Figure 1: Schematic diagram of the generation process. As shown in Figure 7, a base two :: absolute, - closed-end sacrificial layer. - the pole cover layer (two ", the base 1GG can be composed of a semiconductor material such as a bottom recording or a cut-off insulation. The idle-pole insulating layer can be a material having an oxygen atom or a chaotic atom such as an oxide layer or an oxynitride layer. In the second embodiment, the gate sacrificial layer 1〇4 is formed of a polycrystalline second material. The gate insulating layer 102 and the gate sacrificial layer are formed by the dielectric material of the composition of the oxygen atom (fourth). The substrate 1 on both sides of the crucible 4 has a lightly doped drain 108 and a source/drain 112. In addition, the source/drain 112 has a metal telluride layer 113. Further, the gate insulating layer 1 〇2 and the sacrificial layer 1〇4 around the gate are surrounded by a sidewall of the nitride material 11〇. Next, a contact hole etch stop layer 114 is deposited over the gate sacrificial layer 1〇4, the sidewall sub-110 and In addition, an inner dielectric layer 116 is deposited over the contact hole etch stop layer 114. The contact hole etch stop layer 114 is a disordered layer or a carbon and fluorine nitriding supplement. And the inner dielectric layer 16 is silently reduced by the layer _, and the oxidation is reduced. Read, Utilization; Process heat · (4) Exposure gate: ● Grinding process removes part of the inner dielectric layer ιΐ6^^^ etch back the inner portion of the process portion 114. The m-day layer 116 until bare The contact hole is stopped for a total of δ weeks of different silver engraving components to remove the interstitial sacrificial layer to the bare ΓΓ hole residual stop layer 114, and the gate cap layer (not shown), straight bare road out of the material The inter-electrode sacrificial layer 104. The edge of the test _ 'side removal of the gate sacrificial layer W4 and the gate is absolutely the best ^ ^. The groove (10) is the bottom of the side wall (10), the bottom of the bottom is the substrate 100. Gate Sacrifice _ Remove the multi-Shaw 4 paste or the dry crucible. If the wet sacrificial layer is used to form the sacrificial layer 1〇4, you can choose to use the lime acid/gasification gas chlorine or I / as the residual solution. If it is removed by dry remnant, you can use the sound, the main Wei body, the financial __ layer iG4. Please note that the description is not limited to the polycrystalline stone eve, as long as it is the material of the extremely thin 104. The materials of the second and fourth choices can be selected as the sacrificial layer of the idle pole. 1G2 _Yusu·use the wet layer 102 mesh/right to remove the polycrystalline stone material from the wet side Pole insulation two -:=, =:== as.. «Remove_Insulation layer 102. The removal timing can be removed before the closed pole or 16 200842986 follow-up of the idle dielectric layer. • Monthly connection, reference 9 Figure 'for the groove process or etching process, so that _1 ς ς V V 轰 轰 制 制 被 = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = (10) Since the ratio (LVW) of w around the groove 118 is decreased, μ makes the effective depth L of the (four) groove m, and the width then 'please refer to the first figure to form a gate above the base 1〇〇 at the bottom of the groove m Electrode layer 132. J: In the case of the bucket holder, the amount of the wafer can be formed by the oxidation process including the formation of the sub-component A, that is, the substrate 100 containing the component is oxidized so that the portion 132 is formed at the bottom of the groove 118. Then, using a chemical vapor deposition method or I, another deposition method, a high dielectric constant material layer is formed (not in the groove m) and the inclined edge 12〇, the inner dielectric layer 116. After deposition of a layer of electrically constant material (not shown), a barrier layer (not shown) is formed over the surface of the layer of high dielectric constant material (not shown). Thereafter, a conductive layer (not shown) is formed on the inner layer. The layer 116 is filled with the groove m and the inclined edge 12A. Then, the conductive layer (not shown) is ground to expose the remaining inner dielectric layer m and the remaining high dielectric constant material m 134 by a chemical tree grinding process. And the remaining transfer layer 136, finally located at the feeding edge and the inclined edge (10) _ following the high dielectric material layer m, the remaining barrier layer 136, and the remaining metal material 138 is the intermetallic pole 14 〇. After that, the splicing can be continued The dielectric layer is deposited and the desired metal interconnects are sequentially formed to complete the functionally complete semiconductor component. 17 200842986 Generally, the material of the high dielectric constant material layer (not shown) contains a high temperature transition, a genus, a precious metal, Rare earth gold group elements and turning compounds , Weiwu or nitrogen-containing milk _ compounds, Wei materials such as nitrous oxide, oxidized disorder, oxidized steel. The barrier layer formation method includes atomic layer deposition, chemical vapor deposition or physical vapor deposition, and the materials thereof include High-temperature transition metals, precious metals, rare earth metals and other elements from their carbides, joints, nitrides, Wei materials, shouts or nitrogen nitriding titanium nitride nitride group, classification group, Ming nitrided pin, nitrogen seconds A material such as a dough, a partial barrier layer (not shown) may have a work function adjustment function such as addition, etc. In the second embodiment, 'the partial reactive function is adjusted over the Wei barrier layer (not shown) and can be reformed again. - Work function _ layer '(4) may be _ metal-containing material. As the advantages of the first embodiment of the present invention, since the second embodiment of the present invention has a slanted edge, so _ 118 The effective depth/width X ratio (L-/W) is small, so that when the high dielectric constant material layer (not shown) and the barrier layer (not shown) are filled, the step coverage failure does not occur. Among them, the conductive layer:, U-titanium titanium, titanium carbide and other metal materials Since the second embodiment, and the right shame 14G is filled with the recess 118 and the inclined edge 12G, the metal gate is of a 140-type structure. The MOS semiconductor crystal system of the second embodiment is composed of a metal ψ/ and a source. The structure of the baffle 112 is formed. Since the barrier layer of the present invention is filled into the groove m· is called a slanted edge at the opening, the depth of the effect is 7 width (l, /w) is greater than the first two 'so the present invention does not In the prior art, the step coverage of the barrier layer is different. Moreover, since the present invention has no problem of poor barrier coverage of the barrier layer, the fifth is completely filled into the groove to produce a metal gate 18 of good quality. The MOS transistor is the only preferred embodiment of the present invention, and all the equivalent changes and modifications made by the present invention are within the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1(a) is a schematic view of a conventional MOS transistor. The conductor Kb) diagram and the first (.)_ show a schematic diagram of the opening reduction phenomenon and the pore phenomenon of the corpus callosum generally having a metal phase. Substrate gate structure source/> and pole gate dielectric layer sidewall MOS transistor transistor gate insulating layer barrier layer residual barrier layer recess [Major component symbol description] 10, 50, 100 12, 57 H, 62, 112 15, 132 16, 60, 11 〇 18 52, 1 〇 2 84 84,, 136, 72, 118 19 200842986 90 Remaining conductive layer 92, 140 metal gate 54, 104 gate sacrificial layer 56, 63, 113 metal lithium layer 58, 108 lightly doped bismuth 64, 114 contact hole # etch stop layer 66, 116 inner dielectric layer 68, 120 inclined edge 82 high dielectric constant material layer 82, 134, remaining High dielectric constant material layer 138 residual metal material L, L, depth W width 20