200841446 九、發明說明： 【發明所屬之技術領域】 本發明係有_-種四方騎無⑽ 平無引腳之半導體。 【先前技術】 p在Γ代!^導麟裝製財，均是將—個已經完成前段製程(Fr〇ntEnd P_S)之』（wafer)統行薄化處理（Thinningpr。⑽），將晶片的厚 =至2〜2() mil之間；然後，再塗佈（_g)或網印⑽一層 ^子=Γ〇㈣於晶片㈣面’此高分子材料可以是—種樹脂 #’將—個可以移除的膠帶一）貼附於半固化狀的高分子 T(tie) (sawin§P^cess)，a 片（die)，最後，就可將一顆顆的晶片與基板連接。 rwf眾多的半導體封裝型態中，四方扁平無引腳（QuadFlatNon-Lead; =)之封裝結構是將引腳内建於封裝體中，故與外部電路板連接時，較 可以有較小的結合厚度’因此_的封裝結構符合當 下對電子，需「輕、薄、短、小」的要求，特別是用在可攜型一& device)之電子產品上，此種具有封「 效的節細。 ，、㈣^ d小」的職構可以有 樓^先’請參考第1a圖’係一中典型的QFN封裝結構，此QFN封裝姓 =曰片U與導線架中的晶片承座15固接，而晶片承座15的四週配； ’此複數個㈣腳12的高度高於晶片承座15使得兩者 ^成一兩度差’並且複數個内引腳12藉由複數條金屬導線13盘晶片主 動面上的複數個金屬接點連接4此封裝結射，複數個㈣腳Η之前端 5 200841446 度易口疋a時在進行金屬導線的打線製程（wke b〇ndi )時 Μ彎’故降低了雜結翻可#度。 谷易破 另外一種典動QFN封震結構，是由美國專利縣5942794所揭露， 其主要疋以導線架為主體，將導線架四端的支撐勒（加㈣16向上， 使，、可以支撐日日片1卜使传晶片u得以升高，可以便於封裝體Μ密封晶 片11及内引腳I2，但此封裳結構會增加封裝體之厚度，且因其内引腳U 係平貼於封裝體的底面，耻請_金屬導線13來連接晶片U與内引 腳12，除了增加電子信訊號的延遲外，還會使用金屬導線η因跨弧太大變 (molding) 5 13 專利第而6另37^f= 吏用，架的QFN封裝結制已揭露於美國 專^弟63,72539射。此專利主要是在金屬基板上以半爛（腿 ΪΜ製程來定義出晶片承座17與引腳群18，然後經由-封膠 ί 1==11 f屬導線13。由於QFN封裝結構很多都使用 it: 產品’故電子產品所產生的熱效應會影響 產加的性ι ’目錄缺㈣㈣課題。此 以改善以導線架為主體的QFN封裝結構之缺 二= =與引腳群18在同一平面上’故其完全平貼二卜= 上，因此散熱性不佳。 【發明内容】 有見於上述QFN封裝結構之缺點與問題，本發明提供一種在晶片基座 ^露面上形成_或凸出之近域何_，藉此來增加卿封裝結構之 政…、面積，以有效解決QFN封装結構散熱性不佳的問題。 6 200841446 爐m本Γ之一主要目的在提供一種可增加散熱面師N封㈣ 構，以有效解決QFN封裝結構散熱性不佳的問題。 封紅 本^之另-主要目的在提供—種可增加散細積_封裝方法 有效解決QFN封裝結構散熱性不佳的問題。 =明之再’目的在提供—種可增加散熱面積_封裝結構，係 1 ^電鑛層包覆曝露之金屬焊塾，可防止被細後的金屬焊塾氧化。 依據上述之目的’本發财先提供—種四耗平鋪腳之半導 ^構，係將主動面上配置有複數個金屬接點的晶片與—個金屬基座之底面固 屬墓^屬基座之第—面上，配置有近似幾何圖案之凹痕；然後以複數條金 屬導線’用以將晶壯的複數個金屬接點與複數個金屬焊墊之第— 最後，再以-個封膠體，包覆晶片、金屬導線、金屬基座之第—面及複數個 金屬焊塾之第-面，並曝露金屬基座之第二面及複數個金屬焊塾之第二面。 本發明接著提供-種四方扁平無引腳之半導體封裝結構，將主動面上 配置有複數個金屬接點的晶片與—個金屬基座之底面固接；然後以複數條金 屬導線’用以將晶片上的複數個金屬接點與複數個金屬焊塾之第一面連接. 然後，再以-個封膠體，包覆晶片、金屬導線、金屬基座之第一面及複數個 金屬焊墊之第-面’並曝露金屬基座之第二面及複數個金屬焊墊之第二面； 最後’再以-個電鍍層HJ接於金屬基座之第二面及複數個金屬焊塾之第二 面，其中金屬基座之第二面上的電鍍層為近似幾何圖案。 本發明接著提供-種四方扁平無引腳之轉體封裝之方法，係提供一 金屬基板，其具有-第-面及相對於該第一面之一第二面；形成一圖案 (pattern)於金屬基板之第-面上，以定義出一金屬基座區及複數個金屬焊 墊，接著，蝕刻金屬基板，以形成該金屬基座區及該複數個金屬焊墊；將一 個主動面上配置複數個金屬接點之半導體晶片貼附於金屬基座區；形成複數 條金屬導線，用以將晶片上的複數個金屬接點與複數個金屬焊墊連接；然 後，以注膜方式（molding)形成封膠體，以覆蓋晶片、金屬導線、金屬基 7 200841446 軸之第一面，並曝露金屬基座之第二面及複數個 刻曝露之金屬基座之第二面及複數個金屬焊塾 2-面’錢金躲座與龍個金屬焊墊關；再 基 =金屬：之第二面上;最後，刻封膠體並將軸案二3封 座'^弟—面上。 【實施方式】 本發明在此所探討的方向為-種QFN職結構及方式，贿_封 • |結構具有較佳的散熱效果。為了能徹底地瞭解本發明，將在下列的描述 中提出詳盡的步驟及其組成。顯然地，本發明的施行並未限定卿封裝之 結構及方式之技藝者所熟習的特殊細節。另一方面， 形 方式以及晶片薄化等後段製程之詳細步驟並未描述於細節中，以避免造^ 本發明不必要之_。_，册本發_健實_，齡詳細描述如 下’然而除了這些詳細描述之外’本發明還可以廣泛地施行在其他的實施 例中，且本發明的範圍不受限定，其以之後的專利範圍為準。 、首先，請參考第2A目至第2K _，其為本發明之一具體實施例之詳細 參 t造過程。請參考第2Α圖，係為一平整之金屬基板i⑻，此金屬基板刚 之材料可岐銅、喊兩者之合金。接著將—個適#_案_於金屬基 板100之表面上（未顯示於圖中），然後進行一個蝕刻程序，將未被圖案遮 蔽的至屬基板100移除；在本實施例中，先以一個近似半餘刻（half etch) 之方式進行，先將沒有被圖案遮蔽的金屬基板1〇〇移除一部份，也就是並 未完全侧穿透，如第2B圖所示。當經過半鍅刻的製程後，就可以依據圖 案定義出金屬基座區102與複數個金屬焊墊區1〇4。接著，可以選擇性地在 金屬焊墊區104上先進行一次的電鍍製程，將一金屬材料沉積於每一個金 屬焊墊區1〇4之上，以形成一金屬層106,而此金屬層106之金屬材料係自 下列族群中選出，包括金、銀、銅、錫、鉍、鈀或其合金；在形成本金屬 8 200841446200841446 IX. INSTRUCTIONS: [Technical Field to Be Invented by the Invention] The present invention is a semiconductor that has a four-way ride without a (10) flat leadless. [Prior technology] p in the dynasty! ^ lead the lining to make money, are all have completed the front-end process (Fr〇ntEnd P_S) (wafer) unified thinning treatment (Thinningpr. (10)), the wafer Thickness = to 2~2 () mil; then, recoat (_g) or screen printing (10) layer ^ sub = 四 (four) on the wafer (four) surface 'this polymer material can be - kind of resin #' will be The removable tape is attached to a semi-cured polymer T (tie), a die, and finally, a single wafer can be connected to the substrate. Among the many semiconductor package types of rwf, the quad flat no-lead (QuadFlatNon-Lead; =) package structure is built into the package, so when connected to an external circuit board, there is a smaller bond. The thickness of the package is therefore in line with the current requirements for "electronic, light, thin, short, and small", especially for portable electronic devices. Fine, , (4) ^ d small" can have a floor ^ first 'please refer to Figure 1a' for a typical QFN package structure, this QFN package surname = 曰 piece U and the wafer holder in the lead frame 15 Fixed, and the wafer holder 15 is surrounded by; 'the height of the plurality of (four) legs 12 is higher than the wafer holder 15 so that the two are two degrees difference' and the plurality of inner pins 12 are made of a plurality of metal wires 13 A plurality of metal contacts on the active surface of the disc wafer are connected to the package 4, and the plurality of (four) ankles are at the front end 5 200841446 degree 疋 a when the metal wire is being wire-bonded (wke b〇ndi) Therefore, the number of miscellaneous knots can be reduced. Gu Yi broke another kind of QFN sealing structure, which was revealed by the US Patent County 5942794. The main part is the lead frame, which supports the four ends of the lead frame (plus (4) 16 upwards, so that it can support the Japanese film. 1 The wafer is raised, which can facilitate the package to seal the wafer 11 and the inner lead I2. However, the sealing structure increases the thickness of the package, and the inner lead U is flat on the package. The bottom surface, shame _ metal wire 13 to connect the wafer U and the inner pin 12, in addition to increasing the delay of the electronic signal, the metal wire η is also used to be too large due to cross-arc. 5 13 Patent No. 6 ^f= 吏 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , 18, then via - sealant ί 1 == 11 f is the wire 13. Since many QFN package structures use it: product 'The thermal effect of the electronic product will affect the production of the property ι ' catalog missing (four) (four) subject. Improve the shortage of QFN package structure with lead frame as the main == and The group 18 is on the same plane, so it is completely flattened, so the heat dissipation is not good. SUMMARY OF THE INVENTION The present invention provides a defect on the exposed surface of the wafer base. _ or bulging the near field _, in order to increase the political structure, area, to effectively solve the problem of poor heat dissipation of the QFN package structure. 6 200841446 One of the main purposes of the furnace m is to provide a Increase the heat sink N seal (four) structure to effectively solve the problem of poor heat dissipation of the QFN package structure. Sealed red this other - the main purpose is to provide - can increase the scattered product _ packaging method to effectively solve the heat dissipation of QFN package structure Poor problem. = Mingzhi's purpose is to provide a kind of heat-dissipating area _ package structure, which is a metal solder joint coated with exposed metallized layer to prevent oxidation of the metal solder after being thinned. The purpose of the present invention is to provide a semi-conducting structure for a four-emission flat-ply foot. The wafer with a plurality of metal contacts on the active surface and the bottom surface of the metal base are fixed to the base of the tomb. On the first side, the configuration is near a dent of a geometric pattern; then a plurality of metal wires 'for a plurality of metal contacts and a plurality of metal pads - and finally, a sealing body, a wafer, a metal wire, a first surface of the metal base and a first surface of the plurality of metal soldering pads, and exposing the second side of the metal base and the second side of the plurality of metal soldering pads. The present invention further provides a quad flat no lead a semiconductor package structure, wherein a wafer having a plurality of metal contacts on an active surface is fixed to a bottom surface of a metal base; and then a plurality of metal wires are used to connect a plurality of metal contacts on the wafer with a plurality of metals The first side of the solder fillet is connected. Then, the first surface of the metal substrate, the first side of the metal base, and the first surface of the plurality of metal pads are covered with a sealant and exposed to the second side of the metal base a second surface of the plurality of metal pads; and finally a second plating layer HJ is attached to the second side of the metal base and the second side of the plurality of metal soldering holes, wherein the second side of the metal base The plating layer is an approximate geometric pattern. The invention further provides a method for a quad flat no-lead swivel package, which provides a metal substrate having a - face and a second face relative to the first face; forming a pattern on a metal substrate region defining a metal pedestal region and a plurality of metal pads, and then etching the metal substrate to form the metal pedestal region and the plurality of metal pads; arranging an active surface a plurality of metal contacts of the semiconductor wafer are attached to the metal pedestal region; forming a plurality of metal wires for connecting the plurality of metal contacts on the wafer with the plurality of metal pads; and then, by filming Forming an encapsulant to cover the first side of the wafer, the metal wire, the metal base 7 200841446 shaft, and exposing the second side of the metal base and the second side of the plurality of exposed metal bases and the plurality of metal soldering holes 2 - Face 'Qian Jin hide seat and dragon metal pad off; re-base = metal: the second side; finally, engrave the colloid and the axis case 2 3 seat '^ brother - face. [Embodiment] The invention is directed to a QFN job structure and mode, and the structure of the bribe_seal has a better heat dissipation effect. In order to thoroughly understand the present invention, detailed steps and compositions thereof will be set forth in the following description. Obviously, the practice of the present invention is not limited to the specific details familiar to those skilled in the art. On the other hand, the detailed steps of the shape and the thinning process such as wafer thinning are not described in detail to avoid unnecessary invention. _, booklet_compact_, age is described in detail below 'however, in addition to these detailed descriptions, the invention may be widely practiced in other embodiments, and the scope of the invention is not limited, The scope of the patent shall prevail. First, please refer to the 2A to 2K_, which is a detailed construction process of one embodiment of the present invention. Please refer to the second drawing, which is a flat metal substrate i (8). The material of the metal substrate can be copper or alloy. Then, a method is applied to the surface of the metal substrate 100 (not shown in the drawing), and then an etching process is performed to remove the substrate 100 that is not masked; in this embodiment, In a manner of a half etch, the metal substrate 1 that is not masked is first removed, that is, it is not completely side-pierced, as shown in FIG. 2B. After a half-etch process, the metal pedestal region 102 and the plurality of metal pad regions 1 〇 4 can be defined according to the pattern. Then, a metal plating process may be selectively performed on the metal pad region 104 to deposit a metal material on each of the metal pad regions 1 to 4 to form a metal layer 106. The metal material is selected from the following groups, including gold, silver, copper, tin, antimony, palladium or alloys thereof; in forming the metal 8 200841446
層106後，可以使得後續在進行金屬導線焊接時，較容易形成焊接點，如 第2C圖所示。再接著，將一個半導體晶片2〇〇經由一黏著層（未顯示於圖 中）固接於金屬基板100之金屬基座區1〇2上，此黏著層之目的在接合半 導體晶片200與金屬基座1〇2,因此，只要是具有此一功能之黏著材料，均 為本發明之實施態樣，例如：膠膜（die attached ftlm)或是半固化膠（即 B Stage膠）’如弟2D圖所示。然後，進行一打線製程（wireb〇n(jing)，以 複數條金屬導線1G8來將轉體⑼上的複數個金屬接點（未顯示於 圖中）與金屬基板100之複數個金屬焊墊區1〇4電性連接；如前所述，金 屬導線108可直接焊接於複數個金屬焊墊區1〇4上，也可以是焊接於金屬 焊墊區104之金屬層1〇6上，如第2E圖所示。再接著，隨即進行一封膠製 程（encapsulatePr〇cess)，以注模方式（m〇lding)將一高分子材料或一樹脂 材料所形成之封膠層300來將晶片2〇〇、金屬導線log、金屬基座之第 一面及複數個金屬焊塾1〇4之第一面覆蓋並固化成一體，如帛2F圖所示。 在此要強調，本發明上述之過程係以一個半導體晶片綱的單元來描 述’其主要目的在揭示本發明之特徵，而實際之製造過程是將_整片的金 屬基板loo以一圖案進行蝕刻，來形成複數個金屬基座區1〇2與複數個金 屬焊墊區ι〇4 ’因此半導體晶片2〇0也是依序貼附於金屬焊墊區1〇4上，故 在完成封膠製程後，是在整片的金屬基板励上形成複數侧膠體。因 此，在形成封膠體300的另一面仍然是平整的金屬層。 接著，將上述之整片完成封膠製程的金屬基板1〇〇進行另一次的侧 程序，以將封膠體3GG的另-_金屬層移除，由於先前的伟刻製程已 移除-部份的金屬而形成金屬基座區1〇2與複數個金屬焊墊區1〇4,因此當 另一面（第二面）的金屬層移除後，自然會將已先被半侧的部份侧穿 透（etchmgthrough)，使得金屬基座區1〇2與複數個金屬焊墊區1〇4完全分 離，同時複數個金屬焊墊區1〇4之間也形成各自獨立的焊塾，請參考第2G 3很月,、、、員地，g弟一次的钱刻完成後，金屬基座區與複數個金屬焊 9 200841446 塾區104之第二面1〇5並未被封縣300所覆蓋，也就是直接裸露或曝露 出金屬層。最後，再將-個具有近似幾何圖案4〇1的隔離層*⑽貼附於金 屬基座區102之曝露面’如帛2H圖所示。然後，再進行—次餘刻製程，將 近似幾何圖案咖侧於金屬基座區1()2之第二面上，如第圖所示。此 近似幾何Μ可以是平行錄、同傾、平行之料鱗或是其他規則及 不規則之Β料。㈣臟，此輸刻後的凹賴案可明加與空氣的接 觸面積’故當蘭賴構置於-可翻之電腦（ΝΒ)時，可藉縣增加qfn 封裝結構之散熱面積，以有效解決QFN封裝結構散熱性不佳的問 在上述形成本發明之實施_過財，為了使第二次的網過程能夠 確實將金屬基座區102與複數個金屬焊墊區1()4及複數個金屬焊塾區ι〇4 之間完全被蚀刻穿ϋ，因此會多敍刻-段時間，藉由過#刻（〇veretehing) 來確保完全被蝕刻穿透。故為了能使複數個金屬焊墊區1〇4之間能保持平 整的共平面，故也可以選擇性地在進行一次電鍍的製程，以將一金屬電鍍 層500形成在複數個金屬焊墊區104之第二面1〇5上，如第2K圖所示。^ 此，除了可以將蝕刻後的金屬焊墊區104保持平整的共平面，也能防止被 餘刻後曝露的複數個金屬焊墊區104發生氧化的情形；此外，金屬電锻層 5〇〇也具有一定之厚度，故當此QFN封裝結構與外部電路板接合時，可^ 使得金屬基座區102不與外部電路板接觸，使得整個金屬基座區ι〇2及其 上的近似幾何圖案600與外部電路板有一間距，故可進一步的增加散熱的 效果。當然’也可以選擇在金屬基座區102的近似幾何圖案6〇〇上，养由 此電鍍製程也電鍍上一金屬電鍍層500，在此本發明並不加以限制。 第2Κ圖所示為一理想化之示意圖，在實施的製程中，因為選擇使用溼 蝕刻（wetetching)製程，因此在蝕刻後，會有非等向性的蝕刻所形成之下 切（under-cut)痕跡，如第2L圖所示。然而，因金屬基板1〇〇並非很厚， 因此下切痕跡在巨觀之下並不明顯，特別是在幾何圖案的蝕刻深度不是报 大時，下切痕跡更不明顯。同時此下切痕跡為溼蝕刻製程必然有的現象， 200841446 而且也非本發明之特徵所在，故在此並未詳細說明。 ^ 接下來，請參考第3A圖至第3E圖，係本發明之另一具體實施例之較 簡化之製程示意圖。本實施例在將一金屬基板100進行不同圖案的蝕刻， ‘ 以定義出金屬基座區102與複數個金屬焊墊區104;以及可以選擇性地在金 屬焊墊區104之第一面上先進行一次的電鍍製程，將一金屬材料沉積於每 個金屬焊塾區1〇4之第一面之上，以形成一金屬層，然後將一個半導 體晶片200經由一黏著層固接於金屬基板1〇〇之金屬基座區1〇2之第一面 上’接著，以複數條金屬導線1〇8來將半導體晶片2〇〇上的複數個金屬接 • 點與金屬基板10()之複數個金屬焊墊區104電性連接，以上過程均與第2 圖相同。 再接著，沿著複數個金屬焊墊104之側邊以注模方式（麵lding)將〆 南分子材料或一樹脂材料所形成之封膠層300來將晶片200、金屬導線 1⑽、金屬基座102之第一面及複數個金屬焊墊104之第一面覆蓋並固化成 一體’如第3A圖所示。接著，將上述之整片完成封膠製程的金屬基板1〇〇 進仃另一次的蝕刻程序，將金屬基板1〇〇已先被半蝕刻的部份蝕刻穿透 (etdimg through)，使得金屬基座區1〇2與複數個金屬焊墊區1〇4完全分 魯 離门時複數個金屬焊塾區104之間也形成各自獨立的焊墊，如第3B圖所 一、很月顯地，當弟二次的鍅刻完成後，金屬基座區102與複數個金屬焊 墊區104之第二面1〇5及第三面1〇7並未被封膠體3〇〇所覆蓋，也就是複 數個金屬焊塾區1()4之第二面⑽及第三面1σ?是直接裸露或曝露出金屬 層，並且金屬焊墊區104之第二面1〇5及第三面1〇7是連接在一起。最後， 再將一個具有近似幾何圖案4〇1的隔離層400貼附於金屬基座區1〇2及複 數個金屬焊塾區刚之第二面1〇5之曝露的部份，如第3c圖所示。然後， 再進行一次餘刻製程，將近似幾何圖案_鍅刻於金屬基座區搬之第二 2上，如第3D圖所示。此近似幾何圖案可以是平行直線、同心圓、平行之 ^曲線或疋其他規則及不規則之圖案等。很明顯地，此被儀刻後的凹痕 200841446 圖案可以增加與空氣的接觸面積，可藉此來增加QFN封裝結構之散熱面 積，以有效解決QFN封裝結構散熱性不佳的問題。 在上述形成本發明之實施例的過程中，為了使第二次的侧過程能夠 ‘ 雜將金屬基座區102與複數個金屬烊墊區104及複數個金屬焊塾區1〇4 之間完全被餃刻穿透，因此會多餘刻一段時間，藉由過侧來確保完全被 侧穿透。故為了能使複數個金屬焊墊區1〇4之間能保持平整的共平面， 故也可以選擇性地在進行一次電鍍的製程，以將一金屬電鍛層形成在 複數個金屬焊墊區104之第二面1〇5上，如第3E圖所示。如此，除了可以 參 雜刻後的金屬焊塾區刚保持平整的共平面，也能防止被钱刻後曝露的 複數個金屬焊墊區1〇4發生氧化的情形；此外，金屬電鐘層也具有一 定之厚度，故當此QFN封裝結構與外部電路板接合時，可以使得金屬基座 區102不與外部電路板接觸，使得整個金屬基座 1〇2及其上的近似幾何 圖案6G0與外部電路板有一間距，故可進一步的增加散熱的效果。當然， 也可以選擇在金屬基座區1〇2的近似幾何圖案_上，藉由此電鑛製程也 電鍍上一金屬電鍍層500，在此本發明並不加以限制。 請繼續參考第4A圖及第4B圖，係本發明之另一具體實施例之簡化之 • 製程示意圖。本實施例係在完成前述之第2A圖至第2G圖的步驟後，並不 再使用钕刻製程來將近似幾何圖案侧在金屬基座1〇2上，而是以一層具 有近似幾何圖案彻及金屬焊塾層圖案402之隔離層彻直接貼附^屬 基座區102與複數個金屬焊墊區104之曝露面上，如第4a圖所示。然後直 接進行電鍍製程，將電鍍層500形成於複數個金屬焊墊區1〇4之上，並且 在金屬基座102上形成電鍍之近似幾何圖案咖，如第4B圖所示。此近似 幾何圖案可以是平行錢、同心圓、平行之„轉或是其他規則及不規 則之圖案等。㈣顯地，由電鍍製程所形成之凸起的幾何圖翻樣可以增 加與空氣的接觸面積，故可藉此來增加QFN封裝結構之散熱面積，以有效 解決QFN封裝結構散熱性不佳的問題。 、 ^ 12After the layer 106, it is possible to make it easier to form a solder joint later when the metal wire is soldered, as shown in Fig. 2C. Then, a semiconductor wafer 2 is fixed to the metal pedestal region 1 〇 2 of the metal substrate 100 via an adhesive layer (not shown) for bonding the semiconductor wafer 200 and the metal substrate. The seat is 1〇2, therefore, as long as it is an adhesive material having such a function, it is an embodiment of the present invention, for example, a film attached (die attached ftlm) or a semi-cured adhesive (ie, B Stage glue) The figure shows. Then, a wire bonding process (wireb〇n (jing), using a plurality of metal wires 1G8 to a plurality of metal contacts on the rotating body (9) (not shown) and a plurality of metal pad regions of the metal substrate 100 1〇4 electrical connection; as described above, the metal wire 108 may be directly soldered to the plurality of metal pad regions 1〇4, or may be soldered to the metal pad layer 〇6 of the metal pad region 104, such as 2E is shown. Then, an adhesive process (encapsulatePr〇cess) is performed, and a polymer material or a sealing material 300 formed of a resin material is used to mold the wafer 2 by injection molding. The first surface of the metal wire log, the first side of the metal base and the plurality of metal soldering holes 1〇4 are covered and solidified, as shown in FIG. 2F. It is emphasized here that the above process of the present invention is The main purpose of the invention is to disclose the features of the present invention. The actual manufacturing process is to etch the entire metal substrate loo in a pattern to form a plurality of metal pedestal regions. 2 with a plurality of metal pad areas ι〇4 'so half The bulk wafer 2〇0 is also sequentially attached to the metal pad region 1〇4, so after completing the sealing process, a plurality of side colloids are formed on the entire metal substrate. Therefore, in forming the encapsulant 300 The other side is still a flat metal layer. Next, the metal substrate of the entire encapsulation process is subjected to another side process to remove the other metal layer of the encapsulant 3GG, due to the previous The etch process has removed - part of the metal to form the metal pedestal area 1 〇 2 and the plurality of metal pad areas 1 〇 4, so when the metal layer of the other side (second side) is removed, it will naturally It has been etchmgthrough by the side of the half side, so that the metal pedestal region 1〇2 is completely separated from the plurality of metal pad regions 1〇4, and a plurality of metal pad regions 1〇4 are also formed. For the independent welding boring, please refer to the 2G 3 month, month, 、, 、,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, It has not been covered by Fengxian 300, that is, it is directly exposed or exposed to metal layers. Finally, it will be The isolation layer * (10) of the approximate geometric pattern 4 〇 1 is attached to the exposed surface of the metal pedestal region 102 as shown in Fig. 2H. Then, the process is repeated, and the approximate geometric pattern is placed on the metal pedestal. The second side of the area 1 () 2, as shown in the figure. This approximate geometry can be parallel recording, same tilting, parallel scales or other rules and irregular materials. (4) dirty, this inscription After the recessed case can clearly increase the contact area with the air', so when Lan Lai is placed in the -turnable computer (ΝΒ), the county can increase the heat dissipation area of the qfn package structure to effectively solve the heat dissipation of the QFN package structure. Poorly asked to form the implementation of the present invention in the above-mentioned, in order to enable the second network process to reliably connect the metal pedestal region 102 with a plurality of metal pad regions 1 () 4 and a plurality of metal soldering regions ι 〇4 is completely etched through the ϋ, so it will be more than a period of time, by the #刻 (〇 veretehing) to ensure that the etch is completely etched. Therefore, in order to maintain a flat coplanarity between the plurality of metal pad regions 1 〇 4, it is also possible to selectively perform a plating process to form a metal plating layer 500 in a plurality of metal pad regions. On the second side of 104, 1〇5, as shown in Fig. 2K. ^ This, in addition to maintaining a flat coplanarity of the etched metal pad region 104, can also prevent oxidation of the plurality of metal pad regions 104 exposed by the remnant; in addition, the metal forging layer 5〇〇 It also has a certain thickness, so when the QFN package structure is bonded to the external circuit board, the metal base region 102 can be prevented from contacting the external circuit board, so that the entire metal base region ι〇2 and the approximate geometric pattern thereon The 600 has a spacing from the external circuit board, so that the heat dissipation effect can be further increased. Of course, it is also possible to select an approximate geometric pattern 6 of the metal pedestal region 102, and the plating process is also plated with a metal plating layer 500, which is not limited herein. Figure 2 shows an idealized schematic diagram. In the process of implementation, because of the wet etching process, there is an under-cutting of the anisotropic etch after etching. Traces, as shown in Figure 2L. However, since the metal substrate 1 is not very thick, the undercut trace is not obvious under the macroscopic view, especially when the etching depth of the geometric pattern is not large, the undercut trace is less noticeable. At the same time, this undercut is a phenomenon that is inevitable in the wet etching process, and is not a feature of the present invention, and thus is not described in detail herein. ^ Next, please refer to Figures 3A through 3E, which are simplified schematic illustrations of another embodiment of the present invention. In this embodiment, a metal substrate 100 is etched in different patterns, to define a metal pedestal region 102 and a plurality of metal pad regions 104; and optionally on the first side of the metal pad region 104. Performing a plating process, depositing a metal material on the first surface of each of the metal pad regions 1 to 4 to form a metal layer, and then fixing a semiconductor wafer 200 to the metal substrate via an adhesive layer 1 On the first side of the metal pedestal region 1〇2', then a plurality of metal wires 1〇8 are used to connect the plurality of metal contacts on the semiconductor wafer 2 to the plurality of metal substrates 10() The metal pad region 104 is electrically connected, and the above process is the same as in the second drawing. Then, the wafer 200, the metal wire 1 (10), and the metal base are placed along the side of the plurality of metal pads 104 by injection molding to form a sealant layer 300 formed of a southern molecular material or a resin material. The first side of 102 and the first side of the plurality of metal pads 104 are covered and cured into one body as shown in FIG. 3A. Then, the metal substrate 1 of the entire encapsulation process is further etched into another etching process, and the portion of the metal substrate 1 that has been first half-etched is etched through to make a metal base. When the seat area 1〇2 and the plurality of metal pad areas 1〇4 are completely separated from the door, a plurality of metal pad sides 104 are also formed with independent pads, as shown in FIG. 3B, which is very lucrative. After the second engraving of the younger brother, the metal base region 102 and the second surface 1〇5 and the third surface 1〇7 of the plurality of metal pad regions 104 are not covered by the encapsulant 3〇〇, that is, The second surface (10) and the third surface 1σ of the plurality of metal soldering regions 1 () 4 are directly exposed or exposed metal layers, and the second surface 1〇5 and the third surface 1〇7 of the metal pad region 104 It is connected together. Finally, an isolation layer 400 having an approximate geometric pattern 4〇1 is attached to the exposed portion of the metal base region 1〇2 and the second surface of the plurality of metal soldering regions, such as the 3c. The figure shows. Then, a further engraving process is performed, and the approximate geometric pattern is engraved on the second 2 of the metal pedestal area, as shown in Fig. 3D. The approximate geometric pattern may be a parallel straight line, a concentric circle, a parallel curve or other regular and irregular patterns, and the like. Obviously, the indented post 200841446 pattern can increase the contact area with air, which can increase the heat dissipation area of the QFN package structure to effectively solve the problem of poor heat dissipation of the QFN package structure. In the above-described process of forming an embodiment of the present invention, in order to enable the second side process to be completely mixed between the metal pedestal region 102 and the plurality of metal ruthenium regions 104 and the plurality of metal ferrule regions 1 〇 4 It is pierced by the dumplings, so it will be extra for a period of time, and the side will be ensured to be completely penetrated by the side. Therefore, in order to maintain a flat coplanarity between the plurality of metal pad regions 1 〇 4, it is also possible to selectively perform a plating process to form a metal wrought layer in a plurality of metal pad regions. On the second side of 104, 1〇5, as shown in Fig. 3E. In this way, in addition to the coplanar surface of the metal soldering area that can be etched, it is also possible to prevent oxidation of the plurality of metal pad regions 1〇4 exposed by the money; in addition, the metal clock layer is also Having a certain thickness, when the QFN package structure is bonded to the external circuit board, the metal pedestal region 102 can be prevented from contacting the external circuit board, so that the entire metal pedestal 1 〇 2 and the approximate geometric pattern 6G0 and the external The circuit board has a spacing, so that the heat dissipation effect can be further increased. Of course, it is also possible to select an approximate metal pattern on the metal pedestal region 1 〇 2, by which a metal plating layer 500 is also plated, which is not limited herein. Please continue to refer to Figures 4A and 4B, which are simplified schematic illustrations of another embodiment of the present invention. In this embodiment, after the steps of FIGS. 2A to 2G are completed, the etching process is no longer used to place the approximate geometric pattern on the metal base 1〇2, but the layer has an approximate geometric pattern. The isolation layer of the metal solder layer pattern 402 is directly attached to the exposed surface of the pedestal region 102 and the plurality of metal pad regions 104, as shown in FIG. 4a. Then, the plating process is directly performed, and the plating layer 500 is formed over the plurality of metal pad regions 1〇4, and an approximate geometric pattern of plating is formed on the metal base 102, as shown in Fig. 4B. The approximate geometric pattern can be parallel money, concentric circles, parallel turns or other regular and irregular patterns, etc. (4) Explicitly, the raised geometrical pattern formed by the electroplating process can increase the contact with the air. The area can be used to increase the heat dissipation area of the QFN package structure to effectively solve the problem of poor heat dissipation of the QFN package structure.
200841446 同理’也可以將本實施例係在完成前述之第3B圖的步驟後，也是直接 以-層具有近似幾何圖案4()1及金屬焊墊層圖案4〇2之隔離層_直接貼 附在金屬基舰102與概個金麟Μ 104之曝露面上；紐直接進行 電鑛製程，將電鍍層500形成於複數個金屬焊塾㊣1〇4之上，並且在金屬 基座=2上形成魏之近似幾何圖案_，如第5圖所示。此近似幾何圖案 可以是平行絲、同心W、平行之f曲鱗或是其他簡及不規則之圖案 等。很明’由電鍍製顧«之凸起_何圖案_可明加與空氣 的接觸面積，故可藉此來增加QFN封裝結構之散熱 封裝結概雛不__。 ^ 屬声=明Γ的’本發明的特徵相較於先前技術，係將先前技術中的寬大金 實=14^獻在微金屬鮮驗置作不同的配置。舰地，依照上面 1二=二本發明可能有許多的修正與差異。因此需要在其附加的 读求項之賴内加㈣解，除了上述詳細的描料，本酬還可以廣 泛地在其他的實施例中施行。上述僅為每 兴 成的等效改變或修飾，均應包含在下述申請專利範圍内。料下所疋 【圖式簡單說明】 第1A〜1C圖係先前技術之QFN封裝結構之示意圖； 第2A〜2L圖係本義之_封裝轉之製造過程示意圖； 第3A侧係本發明之另一 _封裝結構之製造過程示意圖； f犯_她♦⑽繼㈣物示意圖；以及 弟5圖係本發明之P QFN封裝結構之製造難示意圖。 13 200841446 【主要元件符號說明】 10 QFN封裝結構（先前技術） 11 晶片 12 内引腳 13 金屬導線 14 封膠體 15 晶片承座 16 凸起之承座 17 晶片承座200841446 Similarly, this embodiment can also be directly attached to the layer 3B with the approximate geometric pattern 4 () 1 and the metal pad layer pattern 4 〇 2 after the step of the above FIG. 3B is completed. Attached to the exposed surface of the metal base ship 102 and the general Jinlin Μ 104; New Zealand directly carries out the electric ore process, and the plating layer 500 is formed on the plurality of metal welding 塾1〇4, and the metal base = 2 The approximate geometric pattern _ of Wei is formed on it, as shown in Fig. 5. The approximate geometric pattern may be parallel filaments, concentric W, parallel f-curves or other simple and irregular patterns. It is very clear that the bumps from the electroplating system can increase the contact area with the air, so that the heat dissipation of the QFN package structure can be increased. ^Acoustic = Alum' The features of the present invention are compared to the prior art in that the prior art is provided in a different configuration for the micro-metal. Shipyard, according to the above 1 2 = two inventions may have many corrections and differences. Therefore, it is necessary to add a (four) solution to its additional reading requirements. In addition to the above detailed description, the present reward can be widely implemented in other embodiments. The above-mentioned equivalent changes or modifications are intended to be included in the following claims. The following is a schematic diagram of the QFN package structure of the prior art; the 2A to 2L drawings are schematic diagrams of the manufacturing process of the package conversion; the 3A side is another of the present invention. _ Schematic diagram of the manufacturing process of the package structure; f _ her ♦ (10) followed by (four) object schematic; and brother 5 is a schematic diagram of the manufacturing of the P QFN package structure of the present invention. 13 200841446 [Explanation of main component symbols] 10 QFN package structure (prior art) 11 Wafer 12 Inner leads 13 Metal wires 14 Sealant 15 Wafer holder 16 Raised socket 17 Wafer holder
18 引腳群 100 金屬基板 102 金屬基座區 104 金屬焊墊區 105 焊墊區之第二面 106 金屬層 107 金屬焊墊區之第三面 108 金屬導線 200 晶片 300 封膠體 400 隔離層 401 幾何圖案 402 金屬焊墊層圖案 500 電鍍層 600 幾何圖案18 pin group 100 metal substrate 102 metal pedestal area 104 metal pad area 105 second side of pad area 106 metal layer 107 third side of metal pad area 108 metal wire 200 wafer 300 encapsulant 400 isolation layer 401 geometry Pattern 402 Metal Pad Pattern 500 Plating Layer 600 Geometric Pattern