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TW200841431A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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Publication number
TW200841431A
TW200841431A TW096143567A TW96143567A TW200841431A TW 200841431 A TW200841431 A TW 200841431A TW 096143567 A TW096143567 A TW 096143567A TW 96143567 A TW96143567 A TW 96143567A TW 200841431 A TW200841431 A TW 200841431A
Authority
TW
Taiwan
Prior art keywords
substrate
substrates
semiconductor device
sealing resin
manufacturing
Prior art date
Application number
TW096143567A
Other languages
Chinese (zh)
Other versions
TWI382501B (en
Inventor
Fujio Kanayama
Tomoshi Ohde
Mitsuru Adachi
Tetsunori Niimi
Hidetoshi Kusano
Yuuji Nishitani
Original Assignee
Sony Corp
Sony Computer Entertainment Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp, Sony Computer Entertainment Inc filed Critical Sony Corp
Publication of TW200841431A publication Critical patent/TW200841431A/en
Application granted granted Critical
Publication of TWI382501B publication Critical patent/TWI382501B/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

To provide a method for manufacturing a semiconductor device, capable of reducing damage in the end of a thinned substrate. Semiconductor chips 30 are respectively flip-flop mounted on a plurality of substrates 20 with an insulating layer and a wiring layer laminated therein. The size of the substrate 20 is larger than a stipulated size. Sealing resins 40 are molded in a state where the plurality of substrates 20, where the semiconductor chips 30 are mounted, respectively, is aligned in one direction. The molding regions of the sealing resins 40 are made to be larger than the outer shapes of a sealing resin layers to be molded in the respective substrates 20. Then, surplus regions R are cut by using a dicing device, etc., so as to meet the prescribed dimension, and the respective substrates 20 are made into single pieces.

Description

200841431 九、發明說明： 【發明所屬之技術區域】 本發明係關於一種基板上安裝有半導體晶片之半導體裝 置之製造方法。 【先前技術】 伴隨著近年來電腦、手機、PDA(個人數位助理（personai Digital Assistance))等電子機器之小型化、高性能化及高 速化，人們亦越要求裝載有此種電子機器的iC(積體電 籲 路）、LSI(大型積體電路）等半導體晶片之半導體裝置進一 步小型化、高速化及高密度化。 隨著半導體裝置之小型化，多層配線基板變得薄型化。 作為薄型化進展之多層配線基板，已知有譬如將以絕緣樹 脂層與配線層交錯形成之增層（bulid up)為主體，且未具備 芯基板之無芯基板（參照專利文獻！)。 [專利文獻1]曰本專利公開公報特開2004-1 86265號 【發明内容】 •[發明所欲解決之問題] 如無芯基板，當多層配線基板薄型化進展時，於半導體 • 裝置之製造或檢查過程中受到來自外部之衝擊時，多層配 線基板易於受到損傷。即便係於多層配線基板上成形有密 封樹脂之封裝構造，與多層配線基板之外形相比，密封樹 脂之外形較小，且若為多層配線基板之端部延伸超出密封 樹脂之構造時，多層配線基板之端部受損便成為一個問 題。故而，需要-種可讓密封樹脂之外形與多層配線基板 126592.doc 200841431 之外形相對合之構造。然而，在基板單體進行之密封，由 於模具偏移，故不易讓密封樹脂之外形與多層配線基板之 外形對合。 本發明係有鑑於前述課題而創作完成者，其目的在於提 : 丨一種可減輕薄型化基板其端部之損冑料導體裝置之製 造方法。 [解決課題之手段] 本發明之—樣態，係半導體裝置之製造方法。該半導體 凌置之製造方法之特徵係包含有以下步驟，即：安裝步 驟，係於複數個基板上分別安料導體晶片；配設步驟， 係配設複數個基板，以使安裝有半導體晶片之各基板的至 > 一邊與其他基板的邊相接觸；密封步驟，係讓密封樹脂 成开7在較可形成於複數個基板上之密封樹脂層其外形更大 的區域，並連結相鄰之基板群；及單片化步驟，係將各基 板及各基板上的密封樹脂按預定尺寸進行切割，使各基板 φ 單片化。上述配設步驟中，亦可讓將前述複數個基板朝一 方向並列放置。 依據此樣態，可讓薄型化之基板外形與密封樹脂之外形 • 一致，因此可大幅度降低外力作用於基板端部之可能性。 ： 藉此，在半導體裝置之製造過程與檢查步驟中，可減低傷 及基板端部之可能性，提高半導體裝置之製造成品率。 【實施方式】 以下將本發明係依較佳態樣加以說明。當然此係說明本 發明之較佳形態，並無法據此限縮本發明之範圍。 126592.doc 200841431 參照圖式說明實施形態之半導體裝置之製造方法。 圖1係顯示實施形態之半導體裝置製造方法所使用之基 板的構造圖。基板20具有層間絕緣膜與配線膜交錯層積且 不含芯基板之多層配線構造。更詳細言之，複數個配線層 22係挾層間絕緣膜24而加以層積。配線層22係譬如採用 銅。為不同層的配線層22之間，係藉由設置於層間絕緣膜 24上之導通孔插塞26而電性連接。基板20背面之配線層 22a周圍，係形成有由耐熱性良好的樹脂材料組成之焊料 掩膜28，且熔焊至基板20時，為避免焊料附著於必要區域 以外的其他區域，係對最下層之層間絕緣膜24a進行塗 層。又，接合有BGA球50之球區部29係呈陣列狀地多數配 ό又於基板20之为面。各球區部29之表面上係覆蓋有有機表 面保護塗覆材料（〇SP)21。另一方面，藉由電解鑛敷而形 成之鎳（Ni)、鉛（Pd)、金（Au)或其等之合金所組成的電極 塾25，係呈陣列狀地多數配設於安裝有半導體晶片側之基 板20表面上，且各電極墊25之上，設有由錫、鉛、或其等 之合金所組成之C4(控制崩潰接片接合（c〇ntr〇iied c〇iiapSe Chip Connection))凸塊 27。 基板20之製造方法並無特別限定，可藉由組合眾所周知 的微影製程、蝕刻、鍍敷、積層等技術而獲致。作為獲得 無芯基板之方法，可例舉在鋼等金屬板上形成由層間絕緣 膜與配線層電解所構成之增層後，對金屬板進行蝕刻戋剝 離等手法。 / 且基板20之外形宜使用大於半導體裝置預先設定好的尺 126592.doc 200841431 寸。譬如半導體裝置所使用之基板的尺寸為45 mm角時， 將基板20各邊之長度較45 mm再多取1 mm程度。 準備多數個基板20，如圖2(A)所示，將LSI(大型積體電 路）等半導體晶片30安裝至基板20。具體言之，在將設有 半導體晶片30之外部電極端子的表面朝下狀態，藉由熔焊 各焊接凸塊32及與其相對應的C4凸塊27，進行半導體晶片 3〇之覆晶安裝。 其次，如圖2(B)所示，將填充料7〇填充至半導體晶片3〇 與基板20之間。由此，焊料結合部分所產生的壓力加以分 散，故可改善半導體裝置丨〇之耐溫度變化特性，並可抑制 半導體裝置10的彎曲。 對多數個基板分別進行如上述之半導體晶片安裝程序 後’如圖3(A)及圖3(B)所示，配設多數個基板2〇，以使各 基板20的至少一邊與其他基板2〇的邊相接觸。本實施形態 中，係將4個基板20朝同一方向排列放置。此時，在相鄰 接之基板20間，宜使基板2〇的上方面高度保持一致。 其次，如圖4(A)及圖4(B)所示，藉由傳遞模塑法於並列 放置的各基板20上成形密封樹脂4〇。此時，傳遞模塑裝置 所使用之上模，並非與各半導體裝置之密封樹脂的設計形 狀相吻合的模，而是使用較該模大者。本實施形態中，為 使各半導體晶片30之背面露出，係使用與半導體晶片3〇周 邊相分離，且相鄰接之基板2〇上的密封樹脂4〇為相連的上 模，並於多數個基板20上進行密封樹脂注塑。藉由讓經模 塑後之猎封樹脂形狀大於設計形狀，可避免設計區域内產 126592.doc 200841431 生渣料毛邊等之毛刺。又，藉由密封樹脂4〇硬化而讓各基 板20加以連接，故可作為多數個基板2〇的集合體而進行處 理。再者，由於可在產品區域外的基板上設置注入密封樹 脂之閘口，故無需開發特別的模具，可降低模具所需的費 用。 其次，如圖5(A)及圖5(B)所示，使用切割裝置等的切削 器械，並依預定之製品尺寸將基板20單片化。藉由切割加 工，對各基板20及其上的密封樹脂4〇將超出製品尺寸的部 分R切除。 各基板20單片化後，如圖6所示，將BGA球5〇安裝至設 於各基板20上之球區部29(參照圖1)。藉由以上步驟，獲致 將半導體晶片30覆晶安裝於基板2〇上，且密封樹脂4〇成形 於與半導體晶片30周邊相分離的位置上之半導體裝置1〇。 更具體言之，熔焊設置於半導體晶片3〇上之凸塊32，以及 與該等凸塊32相對應而設於基板2〇上的C4凸塊27，並將填 充料70填充至半導體晶片3〇與基板2〇之間。 依以上說明之半導體裝置之製造方法，可讓薄型化之基 板外形與密封樹脂之外形一致，故可大幅度降低外力作用 於基板端部之可能性。由此，可降低半導體裝置之製造過 程以及檢查過程中，基板端部受損之可能性，提高半導體 裝置之產品成品率。 又由於模塑時係在基板上形成大於設計形狀之密封樹 脂，故在基板上可能因模塑而產生殘渣毛刺之處係在製品 區域之外侧。製品區域之外侧因可藉由切割等而加以切 126592.doc 200841431 除，故進行成品所得之半導體裝置上不會殘留有殘潰毛刺 等。由此，可提高半導體裝置之產品品質。 再者’使用密封樹脂而讓半導體襄置封裝化的方法，並 不限於使用模塑裝置來讓導人孔内之密封樹脂熱硬化之手 法亦可採用如下述方法，即，並非於最後才進行模塑裝 置之熱硬化’而可自中途開始，如圖7所示，使用簡易構 造的熱硬化裝置完成熱硬化處理。 熱硬化裝置100係包含有下側板11〇、上側板12〇、加壓 設備（圖式未標注）以及加熱設備（圖式未標注）。下侧板110 包含有與半導體裝置之基板20之底面相連接之平面。另一 方面，上側板120包含有與半導體裝置之密封樹脂4〇之頂 面相連接之平面。下側板11〇與上側板12〇上分別設有加熱 器等加熱設備，下侧板110與上側板12〇係藉由加熱設備而 將半V體裝置所用的密封樹脂40加熱至其硬化溫度。又， 下側板110與上侧板120之間所挾有之複數個基板2〇之集合 體，係藉由加壓設備而以預定之壓力進行押壓。藉由使用 如上述之熱硬化裝置1〇〇，可將複數個基板2〇之集合體保 持於加熱至預定溫度的下側板i丨〇與上側板1 2 〇之間，故可 於抑制彎曲的同時，完成密封樹脂40之硬化。 參知圖8(A)說明使用上述熱硬化裝置而讓半導體裝置封 裝化之程序。將欲封裝化之複數個基板之集合體（以下稱 為基板集合體）依次以PI，P2，P3…表示。將預定溫度下 至硬化所需時間表示為標準硬化時間T1。首先，對於基板 集合體P1 ’令模塑裝置所進行的熱硬化以T1的一半時間 126592.doc 200841431 (、1)進行其後，將基板集合體p 1設置於熱硬化裝 置並將八後可進行封裝化之基板集合體p2設置於模塑裝 置。接著，令熱硬化裳置對基板集合體？1所進行之熱硬化 XTl的半時間⑽⑺）進行，與之同時，對於基板集合200841431 IX. Description of the Invention: [Technical Area to Which the Invention Is Ascribed] The present invention relates to a method of manufacturing a semiconductor device in which a semiconductor wafer is mounted on a substrate. [Prior Art] With the recent miniaturization, high performance, and high speed of electronic devices such as computers, mobile phones, and PDAs (personai Digital Assistance), people are increasingly required to load iCs with such electronic devices ( The semiconductor device of a semiconductor wafer such as an integrated circuit or an LSI (large integrated circuit) is further reduced in size, speed, and density. As the size of the semiconductor device is reduced, the multilayer wiring substrate is made thinner. For example, a coreless substrate in which a bulk layer formed by interleaving an insulating resin layer and a wiring layer is formed and a core substrate is not provided (see Patent Document) is known. [Patent Document 1] Japanese Laid-Open Patent Publication No. 2004-1 86265 [Draft of the Invention] [Problems to be Solved by the Invention] For a coreless substrate, when a multilayer wiring substrate is made thinner, a semiconductor device is manufactured. The multilayer wiring board is susceptible to damage when subjected to an impact from the outside during the inspection. Even if it is a package structure in which a sealing resin is formed on a multilayer wiring board, the sealing resin is smaller in shape than the outer shape of the multilayer wiring substrate, and if the end portion of the multilayer wiring substrate extends beyond the structure of the sealing resin, the multilayer wiring Damage to the end of the substrate becomes a problem. Therefore, it is necessary to have a configuration in which the sealing resin is shaped to face the multilayer wiring substrate 126592.doc 200841431. However, since the sealing of the substrate alone is performed due to the offset of the mold, it is difficult to make the outer shape of the sealing resin and the outer shape of the multilayer wiring substrate. The present invention has been made in view of the above problems, and an object thereof is to provide a method for manufacturing a damaged conductor device capable of reducing the end portion of a thinned substrate. [Means for Solving the Problem] The present invention is a method of manufacturing a semiconductor device. The manufacturing method of the semiconductor device includes the following steps: a mounting step of respectively mounting a conductor wafer on a plurality of substrates; and a step of disposing a plurality of substrates to mount the semiconductor wafer. The side of each substrate is in contact with the side of the other substrate; the sealing step is such that the sealing resin is opened 7 in a region having a larger outer shape than the sealing resin layer which can be formed on the plurality of substrates, and is connected adjacent thereto The substrate group and the singulation step are performed by cutting the sealing resin on each of the substrates and the respective substrates by a predetermined size to singulate each of the substrates φ. In the above arrangement step, the plurality of substrates may be placed side by side in one direction. According to this aspect, the shape of the thinned substrate can be made uniform with the shape of the sealing resin, so that the possibility of external force acting on the end portion of the substrate can be greatly reduced. Therefore, in the manufacturing process and the inspection step of the semiconductor device, the possibility of damage to the end portion of the substrate can be reduced, and the manufacturing yield of the semiconductor device can be improved. [Embodiment] Hereinafter, the present invention will be described in terms of preferred embodiments. It is a matter of course that this is a preferred form of the invention and is not intended to limit the scope of the invention. 126592.doc 200841431 A method of manufacturing a semiconductor device according to an embodiment will be described with reference to the drawings. Fig. 1 is a structural view showing a substrate used in a method of manufacturing a semiconductor device of an embodiment. The substrate 20 has a multilayer wiring structure in which an interlayer insulating film and a wiring film are alternately laminated and which does not include a core substrate. More specifically, a plurality of wiring layers 22 are laminated by laminating the interlayer insulating film 24. The wiring layer 22 is made of, for example, copper. The wiring layers 22 of different layers are electrically connected by via via plugs 26 provided on the interlayer insulating film 24. A solder mask 28 made of a resin material having good heat resistance is formed around the wiring layer 22a on the back surface of the substrate 20, and when soldering to the substrate 20, the solder layer is prevented from adhering to other regions than necessary regions, and the lowermost layer is formed. The interlayer insulating film 24a is coated. Further, the ball portion 29 to which the BGA balls 50 are joined is arranged in a plurality of rows and is disposed on the surface of the substrate 20. The surface of each of the ball portions 29 is covered with an organic surface protective coating material (〇SP) 21. On the other hand, the electrode crucible 25 composed of nickel (Ni), lead (Pd), gold (Au) or the like formed by electrolytic mineral deposition is mostly arranged in an array and mounted with a semiconductor. On the surface of the substrate 20 on the wafer side, and on each of the electrode pads 25, C4 composed of an alloy of tin, lead, or the like is provided (control collapse joint bonding (c〇ntr〇iied c〇iiapSe Chip Connection) ) bump 27. The method of manufacturing the substrate 20 is not particularly limited, and can be obtained by a combination of well-known techniques such as photolithography, etching, plating, and lamination. As a method of obtaining a coreless substrate, a method of forming a layer formed by electrolysis of an interlayer insulating film and a wiring layer on a metal plate such as steel, and then etching and stripping the metal plate may be mentioned. And the shape of the substrate 20 is preferably larger than the predetermined size of the semiconductor device 126592.doc 200841431 inch. For example, when the size of the substrate used in the semiconductor device is 45 mm, the length of each side of the substrate 20 is about 1 mm more than 45 mm. A plurality of substrates 20 are prepared, and as shown in Fig. 2(A), a semiconductor wafer 30 such as an LSI (large integrated circuit) is mounted on the substrate 20. Specifically, the flip-chip mounting of the semiconductor wafer 3 is performed by welding the solder bumps 32 and the corresponding C4 bumps 27 with the surface of the external electrode terminals on which the semiconductor wafer 30 is provided facing downward. Next, as shown in Fig. 2(B), the filler 7 is filled between the semiconductor wafer 3A and the substrate 20. Thereby, the pressure generated by the solder joint portion is dispersed, so that the temperature change characteristic of the semiconductor device can be improved, and the bending of the semiconductor device 10 can be suppressed. After performing the semiconductor wafer mounting process as described above for each of the plurality of substrates, as shown in FIGS. 3(A) and 3(B), a plurality of substrates 2 are disposed so that at least one side of each substrate 20 and the other substrate 2 are provided. The sides of the cockroach are in contact. In the present embodiment, four substrates 20 are arranged in the same direction. At this time, it is preferable that the heights of the upper sides of the substrate 2 are kept uniform between the adjacent substrates 20. Next, as shown in Fig. 4 (A) and Fig. 4 (B), a sealing resin 4 is formed on each of the substrates 20 placed side by side by transfer molding. At this time, the upper mold used in the transfer molding apparatus is not a mold which conforms to the design shape of the sealing resin of each semiconductor device, but uses a larger one than the mold. In the present embodiment, in order to expose the back surface of each semiconductor wafer 30, the sealing resin 4 〇 on the adjacent substrate 2 is separated from the periphery of the semiconductor wafer 3, and the upper mold is connected to each other. Sealing resin injection molding is performed on the substrate 20. By allowing the shape of the molded resin to be larger than the design shape, it is possible to avoid burrs such as burrs of raw materials in the design area. Further, since each of the substrates 20 is joined by curing the sealing resin 4, it can be handled as an aggregate of a plurality of substrates 2A. Furthermore, since the gate for injecting the sealing resin can be provided on the substrate outside the product area, it is not necessary to develop a special mold, and the cost required for the mold can be reduced. Next, as shown in Fig. 5 (A) and Fig. 5 (B), a cutting instrument such as a cutting device is used, and the substrate 20 is singulated in accordance with a predetermined product size. By the dicing process, the portion R of the substrate 20 and the sealing resin 4 on it is cut beyond the size of the article. After the respective substrates 20 are singulated, as shown in Fig. 6, the BGA balls 5 are attached to the ball portion 29 provided on each of the substrates 20 (see Fig. 1). By the above steps, the semiconductor wafer 30 is flip-chip mounted on the substrate 2, and the sealing resin 4 is formed on the semiconductor device 1 at a position separated from the periphery of the semiconductor wafer 30. More specifically, the bumps 32 disposed on the semiconductor wafer 3 are soldered, and the C4 bumps 27 disposed on the substrate 2 corresponding to the bumps 32 are filled, and the filler 70 is filled to the semiconductor wafer. 3〇 and the substrate 2〇. According to the method of manufacturing a semiconductor device as described above, the shape of the thinned substrate can be made to conform to the shape of the sealing resin, so that the possibility of external force acting on the end portion of the substrate can be greatly reduced. Thereby, the possibility of damage to the end portion of the substrate during the manufacturing process of the semiconductor device and the inspection process can be reduced, and the product yield of the semiconductor device can be improved. Further, since a sealing resin having a shape larger than the design shape is formed on the substrate during molding, the residue on the substrate due to molding may be on the outer side of the product region. The outer side of the product area can be cut by cutting or the like. 126592.doc 200841431 Except, the burr or the like does not remain on the semiconductor device obtained by the finished product. Thereby, the product quality of the semiconductor device can be improved. Further, the method of encapsulating the semiconductor device using the sealing resin is not limited to the method of using the molding device to thermally harden the sealing resin in the conductor hole, and the method may be employed as follows, that is, not at the end The heat hardening of the molding apparatus can be started from the middle, and as shown in Fig. 7, the heat hardening treatment is performed using a heat curing device of a simple structure. The heat curing device 100 includes a lower side plate 11A, an upper side plate 12A, a pressurizing device (not shown), and a heating device (not shown). The lower side plate 110 includes a plane that is connected to the bottom surface of the substrate 20 of the semiconductor device. On the other hand, the upper side plate 120 includes a plane which is connected to the top surface of the sealing resin 4 of the semiconductor device. The lower side plate 11A and the upper side plate 12 are respectively provided with heating means such as a heater, and the lower side plate 110 and the upper side plate 12 are heated by the heating means to heat the sealing resin 40 used for the half V body device to the hardening temperature. Further, the assembly of the plurality of substrates 2 挟 between the lower side plate 110 and the upper side plate 120 is pressed by a predetermined pressure by a pressurizing device. By using the thermal curing device 1 as described above, the assembly of the plurality of substrates 2 can be held between the lower side plate i 加热 and the upper side plate 1 2 加热 heated to a predetermined temperature, so that the bending can be suppressed. At the same time, the hardening of the sealing resin 40 is completed. Fig. 8(A) shows a procedure for sealing a semiconductor device using the above-described thermosetting device. The aggregate of a plurality of substrates to be encapsulated (hereinafter referred to as a substrate assembly) is sequentially represented by PI, P2, P3, .... The time required to cure at a predetermined temperature is expressed as a standard hardening time T1. First, for the substrate assembly P1', the thermal hardening performed by the molding apparatus is performed at half time T1 of 126592.doc 200841431 (1), and then the substrate assembly p1 is placed on the heat curing device and eight The packaged substrate assembly p2 is placed in a molding apparatus. Next, let the heat hardening be placed on the substrate assembly? 1 part of the thermal hardening XTl is carried out for half time (10) (7)), at the same time, for the substrate assembly

體P2 ’令_塑裝置所進行之熱硬化以T1的一半時間⑽X T1)進行。即，對於不同的基板集合體，係並行藉由模塑 裝置所進^了之熱硬化，以及藉由熱硬化裝置所進行之熱硬 化。依此，如圖8(B)所示，與僅採用模塑裝置並依次讓基 板集合體封裝化的情況下所需時間相&，封裝化所需時間 可減半，可提兩半導體裝置之生產性能。再者，與模塑裝 置相比，熱硬化裝置係構造簡單，故價格較為低廉，與保 有兩台模塑裝置的情況相比，可抑制投資所需費用。 更具體言之，密封樹脂係採用T1為6〇秒的習知態樣之環 氧樹脂時，每一個基板集合體所需之熱硬化處理的工作時 間可約為30秒。又，即便與先前態樣相比而需較長之τι 時，熱硬化處理之工作時間亦可減半。如，T1為i2〇秒 時’每一個基板集合體所需的熱硬化處理之工作時間可約 為60秒。 再者，熱硬化裝置100之下側板110或/及上側板12〇，亦 可配合基板集合體之彎曲特性，而為可將與基板集合體連 接的面做成矯正彎曲之形狀。據此，可更進一步抑制基板 集合體之彎曲。 又’上述之封裝化程序中，係將T1二等分，惟，亦可藉 由使用2台以上的熱硬化裝置而將T1三等分，於包含模塑 126592.doc -12· 200841431 裝置與多數個熱硬化裝置的3處以上並行地進行熱硬化處 理。 本發明並不限於上述實施方式，亦可依當業者之學識而 施加各種設計變更等之變形，且如此種施加變形後之實施 方式仍包括在本發明内。 如圖2(A)中，半導體晶片3〇係覆晶安裝於基板2〇上，惟 半導體晶片30亦可藉由打線接而合與基板2〇進行電性連 接。The body P2' is subjected to thermal hardening by a plastic device at half time (10) X T1) of T1. Namely, for different substrate assemblies, the heat hardening by the molding apparatus in parallel and the heat hardening by the heat hardening means are performed. Accordingly, as shown in FIG. 8(B), the time required for the encapsulation can be halved, and the time required for the encapsulation can be halved, and the two semiconductor devices can be lifted, in the case where only the molding apparatus is used and the substrate assembly is sequentially packaged. Production performance. Further, compared with the molding apparatus, the thermosetting apparatus has a simple structure and is relatively inexpensive, and the cost of investment can be suppressed as compared with the case of holding two molding apparatuses. More specifically, when the sealing resin is a conventional epoxy resin having a T1 of 6 sec., the working time of the heat hardening treatment required for each of the substrate assemblies may be about 30 seconds. Moreover, even if a longer τι is required than in the previous aspect, the working time of the thermosetting treatment can be halved. For example, when T1 is i2 〇 second, the working time of the heat hardening treatment required for each substrate assembly can be about 60 seconds. Further, the lower side plate 110 or/and the upper side plate 12 of the thermosetting apparatus 100 may have a curved shape in which the substrate assembly is connected, and the surface to be connected to the substrate assembly may be formed into a shape to be corrected and curved. According to this, the bending of the substrate assembly can be further suppressed. In the above-mentioned encapsulation procedure, T1 is halved, but T1 can be equally divided by using two or more thermal curing devices, including the molding of 126592.doc -12·200841431 device and More than three of the plurality of thermosetting devices are thermally hardened in parallel. The present invention is not limited to the above-described embodiments, and variations of various design changes and the like may be applied depending on the knowledge of the practitioner, and such an embodiment after the application of the deformation is still included in the present invention. As shown in Fig. 2(A), the semiconductor wafer 3 is flip-chip mounted on the substrate 2, but the semiconductor wafer 30 can be electrically connected to the substrate 2 by wire bonding.

又，圖3(A)及圖3(B)中，複數個基板2〇為同一方向並列 放置，惟亦可讓複數個基板2〇縱橫二次元並列。 再者，圖4(A)及圖4(B)中，密封樹脂糾係設置於各半導 體晶片30之周it，且各半導體晶片3〇的背面露出，惟密封 樹月曰40之形狀亦可為任意，可藉由密封樹脂扣而整個披覆 住各半導體晶片30。 【圖式簡單說明】 圖1係表μ於半導體裝置製造上之基板的構造圖。 圖⑽、⑻係表示半㈣晶片之安裝步㈣❹圖。 ，圖3:圖3(Α)係表示載置基板之步驟的平面圖。圖3(B) 係表示圖3(A)之Α_Α，線上的剖面圖。 圖4(B)係表示 圖4 :圖4(A)係表示模塑步驟之平面圖 圖4(A)之Α-Α，線上的剖面圖。 圖 5(B) 圖：圖5(A)係表示基板單片化步驟之平面圖 係表示圖5(A)之α_Α，線上的剖面圖。 圖6係表示焊球安裝步驟圖。 126592.doc 200841431 圖7係表示以簡易構造的熱硬化裝置進 的形成方法圖。 成形樹脂層 【主要元件符號說明】 圖8 :圖8(A)係表示使用熱硬化裝置而硬化半導體裝置 之成形樹脂層的流程圖。圖8(B)係表示僅使用模塑裝置而 硬化半導體裝置之成形樹脂層的流程圖。 20 基板 21 脂塗層材料 22 配線層 22a 背面配線層 24 層間絕緣膜 24a 最下層層間絕緣膜 25 電極塾 26 導通孔插塞 27 凸塊 28 焊料掩膜 29 球區部 30 半導體晶片 32 焊接凸塊 40 密封樹脂 50 BGA球 70 填充材料 100 熱硬化裝置 110 上侧板 doc -14 - 200841431 120 下側板 P1，P2 基板集合體Further, in Fig. 3 (A) and Fig. 3 (B), a plurality of substrates 2 are arranged side by side in the same direction, but a plurality of substrates 2 may be arranged in parallel with each other. In addition, in FIG. 4(A) and FIG. 4(B), the sealing resin is provided in the periphery of each semiconductor wafer 30, and the back surface of each semiconductor wafer 3 is exposed, but the shape of the sealing tree moon 40 may be Optionally, each semiconductor wafer 30 can be entirely covered by a sealing resin clasp. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a structural view showing a substrate on a semiconductor device. Figures (10) and (8) show the installation steps (4) of the half (four) wafer. Fig. 3: Fig. 3 (Α) is a plan view showing a step of placing a substrate. Fig. 3(B) is a cross-sectional view showing the line Α_Α of Fig. 3(A). Fig. 4(B) is a view showing Fig. 4: Fig. 4(A) is a plan view showing a molding step. Fig. 4(A) is a cross-sectional view taken along line Α-Α. Fig. 5(B) Fig. 5(A) is a plan view showing the step of singulating the substrate. Fig. 5(A) is a cross-sectional view taken along line α_Α of Fig. 5(A). Fig. 6 is a view showing a step of mounting a solder ball. 126592.doc 200841431 Fig. 7 is a view showing a method of forming a thermosetting device with a simple structure. [Forming Resin Layer] [Explanation of Main Element Symbols] Fig. 8: Fig. 8(A) is a flow chart showing the curing of the molding resin layer of the semiconductor device using a thermosetting device. Fig. 8(B) is a flow chart showing the curing of the formed resin layer of the semiconductor device using only a molding apparatus. 20 substrate 21 lipid coating material 22 wiring layer 22a back wiring layer 24 interlayer insulating film 24a lowermost interlayer insulating film 25 electrode 塾 26 via plug 27 bump 28 solder mask 29 ball portion 30 semiconductor wafer 32 solder bump 40 sealing resin 50 BGA ball 70 filling material 100 heat curing device 110 upper side plate doc -14 - 200841431 120 lower side plate P1, P2 substrate assembly

126592.doc 15-126592.doc 15-

Claims (1)

200841431 十、申請專利範圍： 1 · 一種半導體裝置之製造方法，其特徵係包含有以下步 驟： 安裝步驟’係於複數個基板上分別安裝半導體晶片； 配設步驟，係配設前述複數個基板，以使安裝有半導 1 體晶片之各基板的至少一邊與其他基板的邊相接； 密封步驟’係讓密封樹脂成形至較應形成於前述複數 個基板上之密封樹脂層其外形更大的區域，連結相鄰之 基板群；及 單片化步驟，係將各基板及各基板上的密封樹脂按預 定尺寸進行切割，使各基板單片化。 2·如請求項1之半導體裝置之製造方法，其中前述配設步 驟中’係讓複數個基板朝一方向並列放置。 ，員1或2之半導體裝置之製造方法，其中前述複數 個基板為多層配線基板。 φ 4·如請求項3之半導體裝置之製造方法，其中前述多層配 、線基板為無芯基板。 126592.doc200841431 X. Patent application scope: 1 . A method for manufacturing a semiconductor device, characterized in that the method comprises the steps of: mounting a step of mounting a semiconductor wafer on a plurality of substrates; and disposing a plurality of substrates; So that at least one side of each substrate on which the semiconductor wafer is mounted is in contact with the side of the other substrate; the sealing step 'shapes the sealing resin to a sealing resin layer which is formed on the plurality of substrates to have a larger outer shape The region is connected to the adjacent substrate group; and the singulation step is to cut the sealing resin on each substrate and each substrate by a predetermined size to singulate each substrate. 2. The method of manufacturing a semiconductor device according to claim 1, wherein in the arranging step, a plurality of substrates are placed side by side in one direction. The method of manufacturing a semiconductor device according to the first or second aspect, wherein the plurality of substrates are multilayer wiring substrates. The manufacturing method of the semiconductor device of claim 3, wherein the multilayer wiring and the line substrate are coreless substrates. 126592.doc
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