200841306 九、發明說明·· 【發明所屬之技術領域】 本發明係有關於液晶顯示器（liquid crystal display，LCD )，尤 指一種用來驅動液晶顯示面板（LCDpanel)之裴置與方法。 【先前技術】BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display (LCD), and more particularly to a device and method for driving a liquid crystal display panel (LCD panel). [Prior Art]
請參考第1圖，第1圖為習知用來驅動一液晶顯示面板（LCDPlease refer to FIG. 1 , which is a conventional diagram for driving a liquid crystal display panel (LCD).
panel)之裝置1〇〇的示意圖，其中裝置100包含一灰階電壓產生 電路110與一源極驅動電路120。灰階電壓產生電路11()包含兩組 緩衝放大器112-1與112-2，分別接收一第一組參考電壓 VREF—P(l)、VREF P(2)、...、VREFJ>(N-1)、與 VREF P(N)以及 一第二組參考電壓 VREF—N(1)、VREF—N(2)、…、VREF一N(N-l)、 與VREF_N(N)，以進行緩衝處理並於各個緩衝放大器之輸出端分 別產生相對應的緩衝處理後之參考電壓（buffered reference voltage) ’其中該第一組參考電壓對應於正極性，而該第二組參考 縣對應於負極性。灰階電壓產生電路11〇3包含兩組灰階電阻 114-1 與 114-2 可一組夂哨龟阻包含有M個串聯之分壓電阻， 中各個電阻之軒均可輸$輕。於是，第—組紐電阻队 依據第-組緩衝放大器咖所輸㈣緩衝處理後之參考電壓, 產生第-組候選灰階電壓VP(〇)、VP⑴、、w(M_小與_ 依據第二_放A11112_2所輪出的 处Y彡考電絲產生第二組候選灰階電壓频⑼、 VN(1)、…、VN(M-l)、與 γ^Μ)。 200841306 ^ 如第1圖所示，灰階電壓產生電路110另包含切換單元116-0、 116-1、〜、與116以，每一切換單元1164(卜〇、1、.、]^)分 別依據極性反轉控制訊號POL及其反向訊號PQLB於候選灰階電 壓VP(M -1)與VN(i)當中選擇一候選灰階電壓作為相對應之灰階 電壓V(i)。如此，這兩組候選灰階電壓（即第一組候選灰階電壓 VP⑼、VP(1)、…、VP(M-l)、與VP(M)以及第二組候選灰階電壓 VN(0) > VN(1)、…、VN(M-l)、與vn(M))當中之一組候選灰階 • 電壓係依據極性反轉控制訊號p〇L所代表之極性被選為灰階電壓 V(〇)、V(l)、…、與V(M)，以供傳送至該液晶顯示面板之各顯示 單元之源級驅動電路，例如：源級驅動電路^^’其中^^“代表 源級驅動電路120所驅動的顯示單元之等效電容。 另外，源級驅動電路120包含一解碼器124與一緩衝器128, 其中解碼器m依據顯示資料（display data)，於灰階電壓V⑼、 φ V(1).....與V(M)當中選擇並輸出一灰階電壓，再透過緩衝器128 進行緩衝處理，以驅動該液晶顯示面板中之姆應負載，即上述 之專效電容Cload。 第2圖為第1圖所示之第一組候選灰階電壓仰(〇)、^1)(1)、 VP_)、與W⑽對顯示資料的函數fw之曲線的示意圖，而第 3圖則為第1圖所示之第二組候選灰階電壓w⑼、w⑴、·· VN(m)、與w⑽對顯示資料的函數fvN之曲線的示意圖，盆中 fw(1)，(M 〇且 fw㈣(i) (i = 〇、i、..、M)。在這個例子 9 200841306 -函射vp之曲線與函數_之曲線形狀相仿、方向相反。另外， 刀別如第2圖與第3圖所示，顯示資料〇於函數&之曲線與函數 之曲線中77別對應至正極性之最小灰階電壓VP(M)與負極性之 最大雄賴VN⑼，且顯示資料M於函數&之曲線與函數f· 之曲線中刀別對應至正極性之最大灰階電壓仰⑼與負極性之最 小灰階電壓VN〇VQ。 ' ⑩ 由上述可知，在灰階電壓之產生過程中，各個切換單元116-i C 〇 1 ···、Μ)於極性反轉時所切換之候選灰階電壓Vp(M _ 〇 ::⑴之兒壓切換範圍（v〇lta§eswing)過大，因此需要在解碼 為124中设置大量的傳輸閘（transmissi〇n糾;依據典型的實施 方式，每一傳輸閘具有—P型金屬氧化半導體電晶體（pM〇s tranSiStW)與—N型金屬氧化半導體電晶體（NMOS transistor)。 然而’在同一時間點，該P型金屬氧化半導體電晶體與該N型金 ⑩屬氧化半‘體電晶體當中可能只有—個主要作用，*另—個卻是 處於次要的地位。亦即，在同一時間點，解碼器124中約有一半 的電路面積並未被有效地利用。 【發明内容】 因此本發明之目的之-在於提供用來驅動液晶顯示面板之裝 置與方法，以解決上述問題。 本發明之另一目的在於提供用來轉液晶顯示面板之裝置與 10 200841306 • 方法，喊少灰階電壓之產生過程中之電墨切換範圍（v〇itage swing) ’藉此可產生相較於習知技術更穩定的灰階電壓，並可進 一步增進切換速度。 本發明之又一目的在於提供用來驅動液晶顯示面板之裝置與 方法，以於解碼顯示資料時避免使用傳輸間（tra_issi〇n gate )， 藉此可將解碼顯示資料時所使用之電晶體的數量減少為習知技術 φ 所需之一半，以節省電路面積。 本發明讀佳魏射提供—_來_ —液關示面板之 裝置。•亥裝置包含有：一灰階（gray level)電壓產生電路，用來 產生分別對應複數個灰階之複數個灰階電壓，並依據一極性反轉 控制喊決賴魏做階t壓是额由彻（Μ·)—第一組 參考電壓或一第二組參考電壓來產生，其中該灰階電壓產生電路 春依據該極性反轉控制訊號，決定一灰階電壓是否藉由利用該第一 組參考賴巾之最高電壓或娜二組參考龍巾之最高電壓來產 生，並決定另一灰階電壓是否藉由利用該第一組參考電壓中之最 低電壓或該第二組參考電壓中之最低電壓來產生；以及一源極 (S〇_)，_路，_至該雄賴產生，絲依據顯示 2或該顯示資料之反向資料（inverteddata)從該複數個灰階電 壓當中選擇-灰階電壓，以驅動該液晶顯示面板之—顯示單元之 ，源極#巾該源極_電路依據該極性反轉控制訊號決定該灰階 電壓疋否藉由利用該顯示資料或該反向資料來選出。 11 200841306 • 本㈣概供上述裝置之_，㈣應地提供-觀來驅動一 液晶顯涵板之綠。财法包含有：產生分麟應複數個灰階 之複數個灰階賴，並依據—極性轉蝴峨蚊該複數個灰 p白電壓疋否藉由利用一第一組參考電壓或一第二組參考電壓來產 生。決定該複數個灰階電壓是否藉由利用該第一組參考電壓或該 第一組參考電縣產生之步驟另包含有：依據該極性反轉控制訊 號，決定一灰階電壓是否藉由利用該第一組參考電壓中之最高電 ❿壓或該第二組參考電壓中之最高電壓來產生；以及依據該極性反 轉控制峨，蚊另-灰階領是雜_職第—組參考電壓 中之最低電壓或該第二組參考電壓中之最低電壓來產生。該方法 另包含有：依據顯示資料或該顯示資料之反向資料從該複數個灰 階電壓當帽擇-灰階電壓以驅動該液晶顯示面板之—顯示單元 之源極，以及依據該極性反轉控制訊號來決定該灰階電壓是否藉 由利用該顯示資料或該反向資料來選出。 【實施方式】 請參考第4圖，第4圖為依據本發明一實施例所提供之一種用 來驅動一液晶顯示面板（LCDpanel)之裝置200的示意圖，其中 裝置200包含一灰階電壓產生電路21〇與一源極驅動電路22〇，且 本實施例之該液晶顯示面板係為應用薄膜電晶體液晶顯示器 (TFT-LCD)技術之顯示面板。另外，本實施例之灰階電壓產生 ， 電路210包含上述之兩組緩衝放大器112_丨與112_2、上述之兩組 灰階電阻114-1與114-2、以及切換單元216-〇、216-1、…、與216-M。 200841306 ^ 依據本實施例，第一組緩衝放大器1124緩衝處理第一組參考 電壓 VREF—P(l)、VREF—P(2)、·· ·、VREFJP(N-1)、，VREFJ>(N) 以於第一組緩衝放大器112-1之輸出端產生第一組緩衝處理後之 參考電壓（buffered reference voltage)，而第二組緩衝放大器112-2 緩衝處理第二組參考電壓VREF_N(1)、VREF_N(2)、…、 VREF一N(N-l)、與VREF—N(N)，以於第二組緩衝放大器112-2之 輸出端產生第二組緩衝處理後之參考電壓，其中某一緩衝放大器 _ 所緩衝處理後之參考電壓實質上（substantially)等於同一個緩衝 放大器所接收之參考電壓。另外，第一組灰階電阻114-1係彼此串 聯且麵接至第一組緩衝放大器112_1，並可依據該第一組緩衝處理 後之參考電壓來產生第一組候選灰階電壓VP(〇)、ΥΡ0)、…、 VP(M-l)、與VP(M>。相仿地，第二組灰階電阻114-2係彼此串聯 且麵接至第二組緩衝放大器112_2，並可依據該第二組緩衝處理後 之參考電壓來產生第二組候選灰階電壓^(〇)、VN^)、…、 φ VN^1)、與VN(M)。如前面所述，兩組灰階電阻114-1與11Φ2 中之每一組灰階電阻包含有M個串聯之分壓電阻，其中各個電阻 之端子均可輸出電壓。依據本實施例，（M+1)>N，所以這些分壓 電阻之間的節點當巾有些節點並沒有直接連接至—緩衝放大器。 於本實施例中，第-組灰階電阻⑴心所輸出之第一組候選灰 階電壓VP(0)、VP⑴、…、vp(M-1)、與vp(M)對顯示資料的函 ， 數fw之曲線係如第2圖所示，而第二組灰階電阻⑽2所輪出之 第二組候選灰階電壓VN⑼、VN⑴、…、VN(M-l)、與物㈣ 13 200841306A schematic diagram of a device of the panel, wherein the device 100 includes a gray scale voltage generating circuit 110 and a source driving circuit 120. The gray scale voltage generating circuit 11 () includes two sets of buffer amplifiers 112-1 and 112-2, respectively receiving a first set of reference voltages VREF-P(l), VREF P(2), ..., VREFJ> -1), with VREF P(N) and a second set of reference voltages VREF-N(1), VREF-N(2), ..., VREF-N(Nl), and VREF_N(N) for buffering And correspondingly generating buffered reference voltages at the output ends of the respective buffer amplifiers, wherein the first set of reference voltages corresponds to positive polarity, and the second set of reference counts corresponds to negative polarity. The gray scale voltage generating circuit 11 〇 3 includes two sets of gray scale resistors 114-1 and 114-2. One set of whistle turtle resistors includes M series voltage dividing resistors, and each of the resistors can be converted to light. Therefore, the first-group resistance team generates the first-group candidate gray-scale voltages VP(〇), VP(1), and w(M_small and _ according to the second reference voltage according to the buffer voltage of the first-group buffer amplifier. The second set of candidate gray scale voltages (9), VN(1), ..., VN(Ml), and γ^Μ) are generated by the Y-test wire that is rotated by A11112_2. 200841306 ^ As shown in FIG. 1, the gray scale voltage generating circuit 110 further includes switching units 116-0, 116-1, 〜, and 116, and each switching unit 1164 (di, 1, . , ] ^) respectively A candidate gray scale voltage is selected as the corresponding gray scale voltage V(i) among the candidate gray scale voltages VP(M-1) and VN(i) according to the polarity inversion control signal POL and its reverse signal PQLB. Thus, the two sets of candidate gray scale voltages (ie, the first set of candidate gray scale voltages VP(9), VP(1), ..., VP(M1), and VP(M), and the second set of candidate gray scale voltages VN(0) > ; a set of candidate gray scales among VN(1), ..., VN(Ml), and vn(M)) • The voltage is selected as the gray scale voltage V according to the polarity represented by the polarity inversion control signal p〇L ( 〇), V(l), ..., and V(M) for transmission to the source-level driving circuits of the display units of the liquid crystal display panel, for example, source-level driving circuits ^^' where ^^" represents the source level The equivalent capacitance of the display unit driven by the driving circuit 120. In addition, the source driving circuit 120 includes a decoder 124 and a buffer 128, wherein the decoder m is based on the display data for the gray scale voltage V(9), φ. V(1)... and V(M) select and output a gray scale voltage, and then buffer processing through the buffer 128 to drive the load in the liquid crystal display panel, that is, the above-mentioned special effect capacitor Cload. Fig. 2 is a diagram showing the curves of the first set of candidate gray scale voltages (〇), ^1) (1), VP_), and W(10) versus the function fw of the displayed data, as shown in Fig. 1. The third graph is a graph of the curves of the second set of candidate gray scale voltages w(9), w(1), ··· VN(m), and w(10) versus the function fvN of the displayed data shown in Fig. 1, fw(1) in the basin, (M 〇 and fw(4)(i) (i = 〇, i, .., M). In this example 9 200841306 - the curve of the function vp is similar to the shape of the function _, and the direction is opposite. As shown in Fig. 3, the data shown in the function & curve and function curve 77 correspond to the minimum gray scale voltage VP(M) of the positive polarity and the maximum negative polarity VN(9) of the negative polarity, and the data M is displayed. In the curve of the function & the curve of the function f· corresponds to the maximum gray scale voltage of the positive polarity (9) and the minimum gray scale voltage of the negative polarity VN〇VQ. '10 From the above, the generation of the gray scale voltage In the process, each switching unit 116-i C 〇1 ···, Μ) selects the candidate gray scale voltage Vp when the polarity is reversed (M _ 〇:: (1) the child pressure switching range (v〇lta§eswing) Too large, so it is necessary to set a large number of transmission gates in decoding 124 (transmissi〇n correction; according to a typical implementation, each transmission gate has -P Metal oxide semiconductor transistor (pM〇s tranSiStW) and —N type metal oxide semiconductor transistor (NMOS transistor). However, 'at the same time point, the P-type metal oxide semiconductor transistor and the N-type gold 10 oxidized half' There may be only one main function in the body transistor, and the other one is in a secondary position. That is, at the same time point, about half of the circuit area of the decoder 124 is not effectively utilized. SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide an apparatus and method for driving a liquid crystal display panel to solve the above problems. Another object of the present invention is to provide a device for rotating a liquid crystal display panel and a method for squeezing a lower gray scale voltage during the generation of an ink switching range (v〇itage swing) The conventional technology has a more stable gray scale voltage and can further increase the switching speed. It is still another object of the present invention to provide an apparatus and method for driving a liquid crystal display panel to avoid use of a transmission space (tra_issi〇n gate) when decoding display materials, thereby enabling decoding of a transistor used for displaying data. The number is reduced by one and a half of the conventional technology φ to save circuit area. The invention of the invention provides a device for providing a liquid-display panel. The hex device includes: a gray level voltage generating circuit for generating a plurality of gray scale voltages respectively corresponding to the plurality of gray scales, and according to a polarity reversal control Is generated by the first set of reference voltages or a second set of reference voltages, wherein the gray scale voltage generating circuit determines whether a gray scale voltage is utilized by using the first The group is generated by referring to the highest voltage of the towel or the highest voltage of the reference group of the towel, and determining whether another gray level voltage is utilized by using the lowest voltage of the first group of reference voltages or the second group of reference voltages The lowest voltage is generated; and a source (S〇_), _ way, _ is generated by the singularity, and the wire is selected from the plurality of gray scale voltages according to the display 2 or the inverted data of the display data (inverted data) - a gray scale voltage for driving the display unit of the liquid crystal display panel, and the source _ circuit determines the gray scale voltage according to the polarity inversion control signal by using the display data or the reverse data Come to choose. 11 200841306 • This (4) is intended to provide the above-mentioned device, and (4) to provide a view to drive the green of a liquid crystal display panel. The financial method includes: generating a plurality of gray scales of a plurality of gray scales, and determining whether the plurality of gray-white voltages are based on the first set of reference voltages or a second The group reference voltage is generated. Determining whether the plurality of gray scale voltages are generated by using the first set of reference voltages or the first set of reference voltages includes: determining whether a gray scale voltage is utilized by using the polarity inversion control signal The highest voltage of the first set of reference voltages or the highest voltage of the second set of reference voltages is generated; and according to the polarity inversion control, the mosquito-grey-level collar is in the miscellaneous-group reference voltage The lowest voltage or the lowest of the second set of reference voltages is generated. The method further includes: selecting, according to the display data or the reverse data of the display data, the source of the display unit from the plurality of gray scale voltages to drive the liquid crystal display panel, and according to the polarity The control signal is rotated to determine whether the gray scale voltage is selected by using the display data or the reverse data. [Embodiment] Please refer to FIG. 4, which is a schematic diagram of an apparatus 200 for driving a liquid crystal display panel (LCD) according to an embodiment of the invention. The apparatus 200 includes a gray scale voltage generating circuit. 21〇 and a source driving circuit 22〇, and the liquid crystal display panel of the embodiment is a display panel using a thin film transistor liquid crystal display (TFT-LCD) technology. In addition, in the gray scale voltage generation of the embodiment, the circuit 210 includes the two sets of buffer amplifiers 112_丨 and 112_2, the two sets of gray scale resistors 114-1 and 114-2, and the switching units 216-〇, 216- 1, ..., and 216-M. 200841306 ^ According to the embodiment, the first group of buffer amplifiers 1124 buffers the first set of reference voltages VREF-P(l), VREF-P(2), ···, VREFJP(N-1), VREFJ> A first set of buffered reference voltages is generated at the output of the first set of buffer amplifiers 112-1, and a second set of reference voltages VREF_N(1) is buffered by the second set of buffer amplifiers 112-2 VREF_N(2), ..., VREF_N(Nl), and VREF_N(N), for generating a second set of buffered reference voltages at the output of the second group of buffer amplifiers 112-2, one of which Buffer amplifier _ The buffered reference voltage is substantially equal to the reference voltage received by the same buffer amplifier. In addition, the first set of gray scale resistors 114-1 are connected in series to each other and to the first group of buffer amplifiers 112_1, and can generate a first set of candidate gray scale voltages VP according to the first set of buffered reference voltages. ), ΥΡ0), ..., VP(Ml), and VP(M>. Similarly, the second set of gray scale resistors 114-2 are connected in series to each other and to the second group of buffer amplifiers 112_2, and may be in accordance with the second The group buffers the processed reference voltage to generate a second set of candidate gray scale voltages ^(〇), VN^), ..., φ VN^1), and VN(M). As described above, each of the two sets of gray scale resistors 114-1 and 11Φ2 includes M series voltage dividing resistors, wherein the terminals of the respective resistors can output voltage. According to this embodiment, (M+1) > N, so the nodes between these voltage dividing resistors are not directly connected to the buffer amplifier. In the present embodiment, the first set of candidate gray scale voltages VP(0), VP(1), ..., vp(M-1), and vp(M) outputted by the first set of gray scale resistors (1) are used to display data. The curve of the number fw is as shown in Fig. 2, and the second set of candidate gray scale voltages VN(9), VN(1), ..., VN(Ml), and (4) 13 of the second set of gray scale resistors (10) 2
3 對顯示資料的函數fvN之曲線係如第3圖所示，其中fw(〇 = VP(M i)且 fVN(i) = VN(i)(卜 〇、1、…、μ) 〇 依據本實施例，每一切換單元216-i (i = 0、1、…、Μ)係耦 接至候選灰階電壓VP(i)與VN(i)，以依據極性反轉控制訊號Pol 及其反向訊號POLB於候選灰階電壓vP(i)與VN(i)當中選擇一候 選灰階電壓作為相對應之灰階電壓V①。於是，本發明於本實施 • 例所提供之裝置200及其方法可依據極生反轉控制訊號POL決定 第4圖所示之複數個灰階電壓ν(〇)、ό)、…、與v(M)是否藉由 利用（utilize)第一組參考電壓vrefJP⑴、VREFJP(；2)、…、 VREF P(N-1)、與VREF—P(N)或第二組參考電壓VREF N⑴、 VREF一N(2)、…、VREF—N(N-1)、與 VREFJ^(N)來產生，其中灰 階電壓產生電路210依據極性反轉控制訊號P〇L，決定一灰階電 壓V(0)是否藉由利用第一組參考電壓⑴、 修 VREF-P⑵、…、VREF—P(N-1)、與VREF—P(N)中之最高電壓 VREF P⑴或第二組參考電壓VREF N⑴、VREF_N(；2；)、…、 VREF_N(N_1)、與 VREF一N(N)中之最高電壓 VREF_N(1)來產生， 並決定另一灰階電壓V(M)是否藉由利用第一組參考電壓 VREF P(l)、VREF P(2)、…、VREFJP(N-1)、與 VREFJ>(N)中之 最低電壓VREF_P(N)或第二組參考電壓VREF N(l)、 VREF一N(2)、…、VREF一N(N-l)、與 vreF_n(N)中之最低電壓 VREF—N(N)來產生。另外，灰階電壓產生電路21〇亦可依據極性 反轉控制訊號POL，決定該複數個灰階電壓v(0)、V(l)、···、與 14 200841306 . V(M)中之一特定灰階電壓是否藉由利用第一組參考電壓 VREFJP⑴、VREF P(2)、.··、、與 p⑼中之 一弟一電壓或弟一組參考電壓VREF_N(1)、VREF 、…、 VREF-N(N-l)、與VREF—N(N)中之一第二電壓來產生；於本實施 例中，該第-電壓實質上等於該第二電壓。例如··該特定灰階電 壓、該第一電壓、與該第二電壓係分別為灰階電壓v(1)、參考電 壓VREF_P(2)、與參考電壓⑺。 請注意，依據第2圖所示之函數fw之曲線以及第3圖所示之 函數fvN之曲線，每一切換單元216-i於一極性（於本實施例係為 正極性）所選擇之候選灰階電壓VP①與同一切換單元216_丨於另 極性（於本實施例係為負極性）所選擇之候選灰階電壓νκ① 疋非〶接近的，尤其於本實施例中，正極性之候選灰階電壓Vp⑴ 實質上等於負極性之候選灰階電壓VN(i)。因此，相較於習知技 _ 術，本發明於本實施例所提供之裝置2〇〇及其方法可將灰階電壓 之產生過程中之電壓切換範圍（v〇ltageswing)減少至非常小，藉 此可產生相較於習知技術更穩定的灰階電壓，並可進一步增進切 換速度。 依據本貫施例，這兩組候選灰階電壓中之一組候選灰階電壓係 依據極性反轉控制訊號POL所代表之極性被選為灰階電壓v(〇)、 V(l)、…、與V(M)，以供傳送至該液晶顯示面板之各顯示單元之 源級驅動電路，例如··源級驅動電路220，其中Cload代表源級驅 15 200841306 動電路220所驅動的顯示單元之等效電容 本實施例之源級驅動電路220包含一顯示資料控制電路迎、 -解碼器224、與上述之緩衝器128 ’其中解碼器、124依據顯示資 料（display data)，於灰階電壓v⑼、v⑴、...、與v(m)當中選 擇並輸出-灰階電壓（於本實施例即第4圖所示之灰階電^ 、 dec〇DEr_out)，再透過緩衝器128進行緩衝處理，以驅動該液 #晶顯示面板中之相對應負載’即上述之等效電容。另外，顯 示資料控制電路222之運作係對應於切換單元2职（㈣小、 M)麵接至候選灰階電壓w_聰(〇之輕接方式來設計。於本 實施例中，顯示資料控制電路222可依據極性反轉控制訊號p〇L 決定是否反向（invert)細示資料以產生該顯示資料之反向資料、 或旁通（bypass)該顯示資料。例如：若該顯示資料之二進位值等 於nun ’則該反向資料之二進位值等於〇〇〇〇〇〇。 依據本實施例，若極性反轉控制訊號p〇L4於一高位準dew) (在此代表邏輯值1 )，此時反向訊號_處於-低位準，則顯 不貝枓控制電路222所輸出之輸出資料D為該顯示資料之反向資 料。相反地，若雜反轉㈣職pQL處於—低辦（在此代表 =值〇)，此喊向喊_祕—高位準，職示資料控制 “路222所輪出之輸出資料D仍為該顯示資料。於是，顧示資料 控制電路222對應於極性反轉控制訊號p〇L及其反向訊號 POLB ’輸出該顯示資料或該反向資料作為輸出資料〇，所以解瑪 16 200841306 翁 • 器224就可依據輸出資料D (在此即該旁通之顯示資料或該反向 資料），從複數個灰階電壓當中選擇並輸出該灰階電壓（於本實施 例即第4圖所示之灰階電壓DEC〇DER_〇UT)。如此，即可產生 與第1圖所示裝置100相同的解碼結果。 第5圖為第4圖所示之解碼器224的示意圖，其中D(0)、 D(l)、…、與D(X)代表輪出資料D之(χ+1)個位元，而DB⑼、 • 加⑴、…、與DB(X)分別代表該(x+1)個位元之反向位元。例如： 若位tgD(O)之邏輯值為1，則其反向位元DB(〇)之邏輯值為〇。依 據本實施例中之各切換單元216_〇、以心丨.....與216-M的耦接 方式，由於灰階電壓V⑼、V⑴、…、與V(M)中之每一個灰階電 壓於極性切換時的之電壓切換範圍都很小，而解碼器224上半部 之第一組電晶體均用來解碼較高電壓（於本實施例係為v(〇)、 V(l)、···、與VRM·；!)/】)），且解碼器224下半部之第二組電晶體 % 均用來解碼較低電壓（於本實施例係為V((M+l)/2)、 V((M+3)/2)、…、與V(M)) ’故解碼器224上半部的第一組電晶體 可採甩p型金屬氧化半導體電晶體（PM〇Stransist〇r)，且解碼器 似下半部的第二組電晶體可採用N型金屬氧化半導體電晶體 fNMOS transistor) ’如第5圖所示。於是，本實施例於解竭顯示 資料時不會如習知技術使用到傳輸閘（transmissi〇ngate)，因此^ 將解碼顯示資料時所使用之電晶體的數量減少為習知技術所需之 . 一半，以節省電路面積。 17 200841306 器124中所需設置之 例如：若M = 63，則第1圖所示之解碼 傳輸閘的數量至少為： (32+16 + 8 + 4 + 2+1) *2 = 63 *2 = 126 ； 〜中每傳輸閘具有- P型金屬氧化半導體電晶體與一 n型金屬 氧化半導體電晶體。相較於第1圖所示之解碼器124，若心63， 則解碼ϋ224上半部共省略了 &㈣型金屬氧化半導體電晶體， 且解石馬器故下半部共省略了 03個ρ型金屬氧化半導體電晶體。 依據本實施例之一變化例，每一切換單元216以㈣、！、、 Μ)係_至候選灰階賴W(M _丨)與倾⑽_丨），以依據極性反 轉控制峨PQL及狀向城PQLB練駄階輕仰） 與顧⑹)當中選擇一候選灰階電壓作為相對應之灰階電壓 V(i)。依據本變化例’絲性反轉控制減舰處於—高位準， 此時反向訊號POLB處於一低位準，則顯示資料控制電路從所 輸出之輸出貞料D仍為鋪示資料。減地，絲性反轉控制訊 號=OL處於-低位準，此時反向訊號p〇LB處於一高位準:則顯 不資料控制電路222所輸出之輸出資料D為該顯示資料之反向資 料。其餘相似之處不再重複贅述。 、 依據本實施例之另一變化例， 可在佈局（layout)整合成一單一 源極驅動電路220之至少—部分 模組。例如：顯示資料控制電路 18 200841306 • 222、解碼器224、及緩衝器128當中之兩元件或全部元件在佈局 可整合成一單一模組。 第6圖為依據本發明另一實施例所提供之一種用來驅動一液 晶顯示面板之裝置300的示意圖。本實施例係為第4圖所示之實 施例的變化例，其中切換單元316-卜316-2、..、、316|1)、與 316 Ν η又置的位置緊鄰於该兩組參考電壓，以於該兩組參考電壓當 ⑩中直接選擇一組參考電壓，因此本實施例只需要一組緩衝放大器 112以及一組灰階電阻114。其餘相似之處不再重複贅述。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範 圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖為習知用來驅動一液晶顯示面板（LCDpanel)之裝置的示 • 意圖。 第2圖與第3圖為第1圖所示之候選灰階電壓對顯示資料的函數 之曲線的示意圖。 第4圖為依據本發明一實施例所提供之一種用來驅動一液晶顯示 面板之裝置的示意圖。 第5圖為第4圖所示之解碼器的示意圖。 第6圖為依據本發明另一實施例所提供之一種用來驅動一液晶顯 示面板之裝置的示意圖。 19 200841306 【主要元件符號說明】 100, 200, 300 裝置 110, 210, 310 灰階電壓產生電路 112-1， 112-2,312 緩衝放大器 1144, 114-2, 314 灰階電阻 116-0, 116-1，…，Π6-Μ， 216_0, 216-1，…，216-M， 3164 , 316-2, . . .，:316-(N-1)， 316-N 切換單元 120, 220 源極驅動電路 124, 224 解碼器 128 緩衝器 222 顯示資料控制電路 Cload 顯示單元之等效電容 D 輸出資料 D⑼，D⑴，"·，Ό(Χ) 輸出資料之各個位元 DB(0)? DB(1)5 ... 5DB(X) 輸出資料之各個位元之 反向位元 fvP5 fvN 候選灰階電壓對顯示資料的 函數 POL 極性反轉控制訊號 POLB 極性反轉控制訊號之 20 200841306 反向訊號 VREFJ^l)，VREF_JP(2)，…， VREF P(N-1)? VREF P(N) 第一組參考電壓 VREF—N(l)，VREF一N(2)，…， VREF_N(N-1)5 VREF_N(N) 第二組參考電壓 VP(0)，VPW，".5VP(M-1)， VP(M) 第一組候選灰階電壓 VN(0)，VN(1)，···，VN(M-1)， VN(M) 第二組候選灰階電壓 V(0)，V(1)，."，V(M-1)，V(M)， DECODER OUT 灰階電壓 213 The curve of the function fvN showing the data is as shown in Fig. 3, where fw(〇= VP(M i) and fVN(i) = VN(i)(di, 1,..., μ) In an embodiment, each switching unit 216-i (i = 0, 1, ..., Μ) is coupled to the candidate gray scale voltages VP(i) and VN(i) to control the signal Pol according to the polarity inversion and its inverse Selecting a candidate gray scale voltage from the candidate gray scale voltages vP(i) and VN(i) as the corresponding gray scale voltage V1 to the signal POLB. Thus, the apparatus 200 and the method thereof provided by the present invention Whether the plurality of gray scale voltages ν(〇), ό), ..., and v(M) shown in Fig. 4 can be utilized by utilizing the first set of reference voltages vrefJP(1) according to the polarity inversion control signal POL, VREFJP(;2),..., VREF P(N-1), and VREF-P(N) or the second set of reference voltages VREF N(1), VREF-N(2),..., VREF-N(N-1), And VREFJ^(N) is generated, wherein the gray scale voltage generating circuit 210 determines whether a gray scale voltage V(0) is determined by using the first set of reference voltages (1), and repairing VREF-P(2) according to the polarity inversion control signal P〇L. ,..., VREF—P(N-1), and VREF—P(N) The highest voltage VREF P(1) or the second set of reference voltages VREF N(1), VREF_N(;2;),..., VREF_N(N_1), and the highest voltage VREF_N(1) of VREF-N(N) are generated, and another gray is determined. Whether the step voltage V(M) utilizes the lowest voltage VREF_P(N) of the first set of reference voltages VREF P(l), VREF P(2), ..., VREFJP(N-1), and VREFJ>(N) Or a second set of reference voltages VREF N(l), VREF-N(2), ..., VREF-N(Nl), and a lowest voltage VREF-N(N) of vreF_n(N). In addition, the gray scale voltage generating circuit 21 can also determine the plurality of gray scale voltages v(0), V(l), . . . , and 14 200841306 . V(M) according to the polarity inversion control signal POL. Whether a particular gray scale voltage is utilized by utilizing a first set of reference voltages VREFJP(1), VREF P(2), . . . , and p(9), or a set of reference voltages VREF_N(1), VREF, ..., A second voltage of VREF-N(N1) and one of VREF-N(N) is generated; in this embodiment, the first voltage is substantially equal to the second voltage. For example, the specific gray scale voltage, the first voltage, and the second voltage system are a gray scale voltage v(1), a reference voltage VREF_P(2), and a reference voltage (7), respectively. Note that, according to the curve of the function fw shown in FIG. 2 and the curve of the function fvN shown in FIG. 3, each switching unit 216-i is selected as a candidate for a polarity (positive polarity in this embodiment). The gray scale voltage VP1 is close to the candidate gray scale voltage νκ1 另 selected by the same switching unit 216_丨 in another polarity (in this embodiment, the negative polarity), especially in the embodiment, the candidate gray of the positive polarity The step voltage Vp(1) is substantially equal to the candidate gray scale voltage VN(i) of the negative polarity. Therefore, the device 2 〇〇 and the method provided by the present invention in the present embodiment can reduce the voltage switching range (v〇ltageswing) during the generation of the gray scale voltage to a very small level, compared to the conventional technique. Thereby, a gray scale voltage which is more stable than the conventional technique can be generated, and the switching speed can be further improved. According to the present embodiment, one of the two sets of candidate gray scale voltages is selected as the gray scale voltages v(〇), V(l), ... according to the polarity represented by the polarity inversion control signal POL. And V(M) for transmitting to the source driver circuit of each display unit of the liquid crystal display panel, for example, the source driver circuit 220, wherein Cload represents the display unit driven by the source driver 15 200841306 The equivalent-level capacitor of the present embodiment includes a display data control circuit, a decoder 224, and a buffer 128', wherein the decoder, 124 is based on display data, and is at a gray scale voltage. Between v(9), v(1), ..., and v(m), a grayscale voltage (in the present embodiment, that is, the grayscale electric power, dec〇DEr_out shown in FIG. 4) is selected and buffered by the buffer 128. Processing to drive the corresponding load in the liquid crystal display panel, that is, the equivalent capacitance described above. In addition, the operation of the display data control circuit 222 corresponds to the switching unit 2 ((4) small, M) face to the candidate gray scale voltage w_ Cong (the light connection mode is designed. In this embodiment, the display data control The circuit 222 can determine whether to invert the data according to the polarity inversion control signal p〇L to generate reverse data of the display data, or bypass the display data. For example, if the display data is two The carry value is equal to nun ', and the binary value of the reverse data is equal to 〇〇〇〇〇〇. According to this embodiment, if the polarity inversion control signal p 〇 L4 is at a high level dew) (here represents a logical value of 1) At this time, the reverse signal _ is at the low level, and the output data D outputted by the display control circuit 222 is the reverse data of the displayed data. On the contrary, if the misinversion (four) job pQL is in the low office (in this case = value 〇), this shouting shouts _ secret - high level, job information control "the output data D of the road 222 is still the same The data is displayed. Therefore, the data control circuit 222 outputs the display data or the reverse data as the output data corresponding to the polarity inversion control signal p〇L and its reverse signal POLB ', so the solution 16 200841306 Weng 224, according to the output data D (here, the bypass display data or the reverse data), select and output the gray scale voltage from the plurality of gray scale voltages (in the fourth embodiment of the present embodiment) The gray scale voltage DEC 〇 DER_ 〇 UT). Thus, the same decoding result as that of the apparatus 100 shown in Fig. 1 can be generated. Fig. 5 is a schematic diagram of the decoder 224 shown in Fig. 4, where D(0) , D(l), ..., and D(X) represent (χ+1) bits of the rounded data D, and DB(9), • plus (1), ..., and DB(X) represent the (x+1) respectively. The inverse bit of the bit. For example: If the logical value of the bit tgD(O) is 1, the logical value of the inverted bit DB(〇) is 〇. According to the embodiment The switching unit 216_〇, the heart 丨..... and the 216-M coupling mode, since the gray scale voltages V(9), V(1), ..., and V(M) The voltage switching range is very small, and the first group of transistors in the upper half of the decoder 224 are used to decode the higher voltage (in this embodiment, v(〇), V(l), ..., and VRM·;!)/])), and the second group of transistors % in the lower half of the decoder 224 are used to decode the lower voltage (in this embodiment, V((M+l)/2), V) ((M+3)/2), ..., and V(M)) 'The first group of transistors in the upper half of the decoder 224 may be p-type metal oxide semiconductor transistors (PM〇Stransist〇r), And the second group of transistors of the lower half of the decoder can adopt an N-type metal oxide semiconductor transistor fNMOS transistor as shown in FIG. 5. Therefore, the present embodiment does not have the conventional technology when the data is exhausted. The transfer gate (transmissi〇ngate) is used, so the number of transistors used in decoding the display data is reduced to half that required by the prior art to save circuit area. 17 200841306 Required settings in the device 124 For example, if M = 63, the number of decoding transmission gates shown in Figure 1 is at least: (32 + 16 + 8 + 4 + 2 + 1) * 2 = 63 * 2 = 126 ; Having a P-type metal oxide semiconductor transistor and an n-type metal oxide semiconductor transistor. Compared to the decoder 124 shown in FIG. 1, if the core 63, the upper half of the decoding ϋ224 is omitted from the & The oxide semiconductor transistor is oxidized, and the 03 p-type metal oxide semiconductor transistors are omitted in the lower half of the solution. According to a variant of this embodiment, each switching unit 216 is (four), ! , Μ) _ to the candidate gray level 赖 W (M _ 丨) and tilt (10) _ 丨), according to the polarity reversal control 峨 PQL and shape to the city PQLB training step light and Yang ()) The candidate gray scale voltage is used as the corresponding gray scale voltage V(i). According to the variation of the present invention, the silk reversal control is at the high level, and when the reverse signal POLB is at a low level, the display data control circuit outputs the data from the output D. The ground reduction control signal = OL is at the low level, and the reverse signal p 〇 LB is at a high level: the output data D outputted by the data control circuit 222 is the reverse data of the display data. . The rest of the similarities will not be repeated. According to another variation of the embodiment, at least a portion of the modules of the single source driver circuit 220 can be integrated in the layout. For example, the display data control circuit 18 200841306 • 222, the decoder 224, and the buffer 128 can be integrated into a single module in the layout. Figure 6 is a schematic illustration of an apparatus 300 for driving a liquid crystal display panel in accordance with another embodiment of the present invention. This embodiment is a modification of the embodiment shown in FIG. 4, wherein the switching unit 316-b 316-2, .., 316|1), and 316 Ν η are placed next to the two sets of references. The voltage is such that the two sets of reference voltages directly select a set of reference voltages in 10, so this embodiment requires only one set of buffer amplifiers 112 and a set of gray scale resistors 114. The rest of the similarities will not be repeated. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should fall within the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is an illustration of a conventional device for driving a liquid crystal display panel (LCD panel). Fig. 2 and Fig. 3 are diagrams showing the curves of the candidate gray scale voltages as shown in Fig. 1 as a function of the displayed data. Figure 4 is a schematic illustration of an apparatus for driving a liquid crystal display panel in accordance with an embodiment of the present invention. Figure 5 is a schematic diagram of the decoder shown in Figure 4. Figure 6 is a schematic illustration of an apparatus for driving a liquid crystal display panel in accordance with another embodiment of the present invention. 19 200841306 [Description of main component symbols] 100, 200, 300 Devices 110, 210, 310 Gray scale voltage generating circuits 112-1, 112-2, 312 Buffer amplifiers 1144, 114-2, 314 Gray scale resistors 116-0, 116-1 ,...,Π6-Μ, 216_0, 216-1,...,216-M, 3164, 316-2, . . .,:316-(N-1), 316-N switching unit 120, 220 source drive circuit 124, 224 Decoder 128 Buffer 222 Display data control circuit Cload Display unit equivalent capacitance D Output data D(9), D(1), "·,Ό(Χ) Output bits of each bit DB(0)? DB(1) 5 ... 5DB(X) Reverse bit of each bit of the output data fvP5 fvN Function of the gray scale voltage pair display data POL polarity reversal control signal POLB polarity reversal control signal 20 200841306 Reverse signal VREFJ^ l), VREF_JP(2),..., VREF P(N-1)? VREF P(N) The first set of reference voltages VREF-N(l), VREF-N(2),..., VREF_N(N-1) 5 VREF_N(N) The second set of reference voltages VP(0), VPW, ".5VP(M-1), VP(M) The first set of candidate grayscale voltages VN(0), VN(1),·· ·, VN(M-1), VN(M) The second set of candidate grayscales Voltage V (0), V (1), "., V (M-1), V (M), DECODER OUT gray scale voltage 21