200847288 九、發明說明： 【發明所屬之技術領域】 本發明係與半導體技術領域有關，更詳而言之是 指一種具備電性絕緣底層之金氧半電晶體之製法者。 【先前技術】 按，積體電路係往較大晶片與較小之線寬來演進 的，此等趨勢可使相同尺寸之積體電路功能增強並降 低其使用成本。而對積體電路中之金氧半場效應電晶 體（Metal-Oxide-Semiconductor Field-Effect Transistor，MOSFET)而言，當尺寸越小時通道之長度 亦隨之縮短，因此操作速度將加快。不過，當金氧半 電晶體元件往小型化發展時，常因通道縮短而使得源/ 没極之空乏層（Depletion layer)與通道產生重疊之 情形，且，通道越短，其與源/汲極之空乏層產生重疊 之比例就越高，如此將縮短通道之實質長度，謂「短 通道效應」（Short Channel Effect，SCE)。 習知解決短通道效應之作法係形成淺摻雜汲極區 (Lightly Doped Drain，LDD)，或使用較高劑量（濃度） 之源極 / 没極區（Source/Drain Extension，S/D)來取 代淺摻雜汲區，相關技術之專利案甚多，此處不另一 一贅述。 不過，習知金氧半電晶體元件製作過程中，由於 200847288 源極/汲極植入基底而形成源極/汲極區後，須再進行 熱製程（回火），使得源極/汲極區會產生侧面擴散 (Lateral Diffusion)與接面深度（Juncti〇rl Depth) 變大之現象’不僅會加重短通道效應、使次臨限漏電 之現象更為嚴重；而且，因為PN接面之接面電容亦將 增大，也會導致元件之操作速度、操作效能 (Performance)均無法有效提升。 最後利用熱製程使絕緣離 層，獲致切斷次臨限漏電 斜角方式進行絕緣離子植 上侧並未受到任何保護層 入動作之傷害。 為解決前述次臨限漏電之問題，如中華民國發明 第535237號「金氧半電晶體的製造方法」專利案所示， 其主要係以斜角方式進行絕緣離子植入矽基底，而在 靠近通道侧的淡摻雜區域下方形成絕緣離子摻雜區， 子摻雜區反應而形成絕緣 之效果。不過，該專利案以 入時，其閘極電極之兩側及 之保護，易受到絕緣離子植 【發明内容】 本發明之主要目的即在提供 之具備電性絕緣底芦之鮮决别揭缺失 在源極/汲極區與基底 、 ^ - 接面附近形成一電性絕緣 您層，俾可切斷次 d 效能。 丨“黾，而具備更加省電的操作 6 200847288 本發明之另一目的在於提供一且爺 層之金氧半電晶體製法，其藉由形成電性絕緣底^底 ::大幅降㈣接面之接合電容，俾提升元件之㈣ 緣是，為達成前述之目的，本發明係提供 備電性絕緣底層之金氧半電晶體之製法，至少包含； 以下步驟：a)以淺溝渠隔離技術使一基底形成若： 渠區與井區；b)閘極堆疊’依序由下而以該井區^ 形成-閘極氧化層、―閘極電極與—硬罩幕；◦沉積 與回餘刻’使朗極氧化層、閘極電極與硬罩幕外侧 壁形成-間隙壁；d)對該井區進行斜肖度方式高濃产 :緣離子植入；及e)進行一回火製程，使該閘極電極 底侧形成一電性絕緣層。 曰進一步地，本發明具備電性絕緣底層之金氧半電 晶體之製法更包含有一 f)步驟，係移除該硬 隙壁。 進一步地，本發明具備電性絕緣底層之金氧半電 晶體之製法更包含有—g)步驟，係施以淡離子植入， 以在該閘極電極外侧之井區二侧形成一淡摻雜區域。 進一步地，本發明具備電性絕緣底層之金氧半電 晶體製法更包含有一 h)步驟，係施以濃離子植入，以 形成與該淡摻雜區域重疊之一濃摻雜區域，而構成源 極/没極區。 " 200847288 進一步地，本發明具備電性絕緣底層之金氧半電 晶體之製法更包含有—〇步，驟，係利用熱製程以調 整源極/汲極延伸區的接合深度與摻雜輪廓。 【實施方式】 以下，茲舉本發明一較佳實施例，並配合圖式做 進一步之詳細說明如後·· 請參閱各圖所示，本發明一較佳實施例具備電性 絕緣底層之金氧半電晶體之製法，其第一步驟：係以 習知電性絕緣之淺溝渠隔離技術（Shal 10W Trench kolation ’ STI)於一基底（矽，Si)12上形成數淺溝 渠區22與井區（N/p—Wei 1 )24 (或通道）。 本發明之第二步驟：係閘極堆疊，依序由下而上 地於該井區24上形成一閘極氧化層（Gate 〇χ)26、一 閘極電極（Gate EleCte)28與一硬罩幕（SiNx hard mask)30。該閘極氧化層26係經乾（或濕）氧化製程所 形成，而該閘極電極28係利用臨場摻雜（in—situ)之 化學氣相沉積法（Chemical Vapor Deposition，CVD)， 並以例如石夕甲烧（SiΗ4)等作為反應氣體所沉積而成的 摻雜複晶矽層當作材料，再施以非等向性蝕刻步驟定 義而成，該硬罩幕30係氮化矽材質（亦可為氧化矽材 質）。 本發明之第三步驟：係沉積與該硬罩幕3〇材質相 200847288 同之薄膜（氮化矽），繼而利用乾式電漿回蝕刻 (Etching back)之技術，使該閘極氧化層26、閘極電 極28與硬罩幕30外侧壁形成一間隙壁32。該間隙壁 32係氮化石夕材質（亦可為氧化石夕材質）。又，沉積薄 膜與回蝕刻係習知形成間隙壁之技術，此處不予贅述 其詳細實施内容及等效替代技術。 本發明之第四步驟：係對該井區24進行斜角度 (如45斜角）方式高濃度絕緣離子植入，此高濃度絕 緣離子可為氧⑼或氮〇〇，其中以氧較佳。該閉極電 極28有硬罩幕30與間隙壁32之保護，因此，植入高 浪度絕緣離子之動作不會傷及閘極電極28。 本發明之第五步驟··係進行一習知回火製程，使200847288 IX. INSTRUCTIONS OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention relates to the field of semiconductor technology, and more particularly to a method of fabricating a gold-oxygen semi-transistor having an electrically insulating underlayer. [Prior Art] According to the fact that the integrated circuit is evolved toward a larger wafer and a smaller line width, these trends can enhance the function of the integrated circuit of the same size and reduce the cost of its use. For the Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) in the integrated circuit, the length of the channel is shortened as the size is smaller, so the operation speed is accelerated. However, when the gold-oxygen semi-transistor element is developed to be miniaturized, the depletion layer of the source/depolarization overlaps with the channel due to the shortening of the channel, and the shorter the channel, the source/汲The higher the proportion of the vacant layer that overlaps, the shorter the actual length of the channel, which is called the Short Channel Effect (SCE). It is customary to solve the short channel effect by forming a Lightly Doped Drain (LDD) or using a higher dose (concentration) source/Drain Extension (S/D). Replacing the shallow doped sputum area, there are many patents related to the technology, and there is no other description here. However, in the fabrication of conventional MOS semi-transistor components, after the source/drain regions are formed by the 200847288 source/drain implant substrate, a thermal process (tempering) is required to make the source/drain The phenomenon that the lateral diffusion (Lateral Diffusion) and the joint depth (Juncti〇rl Depth) become larger will not only aggravate the short channel effect, but also make the phenomenon of sub-limit leakage more serious. Moreover, because the PN junction is connected The surface capacitance will also increase, and the operating speed and performance of the components will not be effectively improved. Finally, the thermal separation process is used to separate the insulation layer, and the secondary leakage current oblique angle is obtained to perform the insulation ion implantation. The upper side is not damaged by any protective layering action. In order to solve the problem of the aforementioned secondary leakage current, as shown in the patent case of the Republic of China Invention No. 535237 "Manufacturing Method of Golden Oxide Semi-Crystals", the main purpose is to implant the insulating ion implant into the base by oblique angle, and close to An insulating ion doped region is formed under the lightly doped region on the channel side, and the sub doped region reacts to form an insulating effect. However, in the case of the patent, the protection of the two sides of the gate electrode and the protection of the electrodes are susceptible to the insulation ion implantation. [The present invention] The main object of the invention is to provide a reliable alternative to the electrical insulation An electrical insulation layer is formed in the source/drain region adjacent to the substrate and the ^- junction to cut off the secondary d performance.黾“黾, with more power-saving operation 6 200847288 Another object of the present invention is to provide a gold-oxide semi-transistor method for forming a layer of electrical insulation, which is formed by electrically insulating the bottom of the substrate: a substantially lower (four) junction The bonding capacitance, the (four) edge of the 俾 lifting element, is to provide a method for preparing a gold-oxide semi-transistor of an electrically insulating underlayer for at least the foregoing purposes, at least comprising the following steps: a) using shallow trench isolation technology A base is formed: a channel area and a well area; b) a gate stack is formed in the order from the bottom to the gate area ^ gate oxide layer, a gate electrode and a hard mask; 'Making the polar oxide layer, the gate electrode and the outer side wall of the hard mask form a gap; d) performing a high oblique yield on the well region: edge ion implantation; and e) performing a tempering process, Further, the bottom side of the gate electrode is formed with an electrical insulating layer. Further, the method for fabricating a gold-oxygen semi-electrode having an electrically insulating underlayer further comprises a step f) of removing the hard-spaced wall. The invention has the structure of a gold-oxide semi-transistor with an electrically insulating underlayer Further comprising the step (g), applying a light ion implantation to form a lightly doped region on both sides of the well region outside the gate electrode. Further, the present invention is provided with an electrically insulating underlayer of gold oxide semi-electricity The crystal preparation method further comprises a step h), wherein the concentrated ion implantation is performed to form a concentrated doped region overlapping the lightly doped region to form a source/no-polar region. "200847288 Further, the present invention The method for fabricating a gold-oxygen semi-transistor having an electrically insulating underlayer further includes a step of using a thermal process to adjust the bonding depth and doping profile of the source/drain extension region. [Embodiment] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS OF THE INVENTION A preferred embodiment of the present invention will be described in detail with reference to the drawings. Referring to the drawings, a preferred embodiment of the present invention has a method for fabricating a gold-oxide semi-transistor having an electrically insulating underlayer. The first step is to form a shallow trench area 22 and a well area (N/p-Wei) on a substrate (矽, Si) 12 by a conventional shallow insulation isolation technique (Shal 10W Trench kolation 'STI). 1) 24 (or channel). Step: stacking the gates, sequentially forming a gate oxide layer 26, a gate electrode (Gate EleCte) 28 and a hard mask (SiNx hard) on the well region 24 from bottom to top. Mask) 30. The gate oxide layer 26 is formed by a dry (or wet) oxidation process, and the gate electrode 28 is subjected to in-situ chemical vapor deposition (CVD). And using a doped polysilicon layer deposited as a reactive gas such as Shiqijia (SiΗ4) as a material, and then defined by an anisotropic etching step, the hard mask 30 is Barium nitride material (can also be yttria). The third step of the present invention is to deposit a thin film (tantalum nitride) with the hard mask 3〇 material phase 200847288, and then use the dry plasma etching back etching technique to make the gate oxide layer 26, The gate electrode 28 forms a spacer 32 with the outer sidewall of the hard mask 30. The spacer 32 is made of a nitride stone material (which may also be an oxidized stone material). Further, the deposition film and the etch back are conventionally known as the technique of forming the spacer, and the detailed implementation and equivalent replacement techniques are not described herein. The fourth step of the present invention is to implant the well region 24 with a high concentration of insulating ions at an oblique angle (e.g., 45 oblique angle). The high concentration of the insulating ions may be oxygen (9) or nitrogen argon, of which oxygen is preferred. The closed pole electrode 28 is protected by the hard mask 30 and the spacer 32, so that the action of implanting high-wavelength insulating ions does not damage the gate electrode 28. The fifth step of the present invention is to perform a conventional tempering process so that
々又滑洗液C如磷酸，H3P〇4)淮弁n制〜 酸，H3P〇4)進行清洗製程， ’即可去除 200847288 該虱化矽材質之硬罩幕30與間隙壁32 (若硬罩幕30 與間隙壁32係氧化石夕材質則以氫氟酸作為清洗液）。 本發月之弟七步驟··係施以淡離子植入，以在該 閘極電極28外側之井區24二側形成-淡摻雜區域 (Lightly D0ped Drain，LDD)36。淡離子可為例如磷 (P)或砷（As)等五價的n型離子（n_)。 本發明之第八步驟：係在該閘極電極28的侧壁形 成一間隙壁38。 本發明之第九步驟：係施以濃離子植入，以形成 與該淡摻雜區域36重疊之—濃摻雜區域4()，而構成 源極/汲極區（SQurce/Drain⑽，s/d)。濃離 子（n+)使用的植入能量及劑量皆較該淡摻雜區域36之 離子植入步驟還大。 本發明之第九步驟··係利用熱製程，以調整該源 極/汲極區的接合深度與摻雜輪廓。 本實施例係以_S電晶體為例，惟本發明並不限 於此’亦可適用於_電晶體，亦即在_ 底或N型井區形成p型之源極/沒極的情況。 - 藉此，本發明具備電性絕緣底層 之製法，其特色及效果如下·· 虱+電B曰體 本發明先於該間極電極28頂側堆疊罩 外侧形成間_32，使得對該㈣Μ進幕^； 漠度絕緣離子植人步驟時，不會㈣= 10 200847288 傷害，且，藉由熱製程（回火）後在源極/汲極區與基底 之PN接面附近形成該電性絕緣底層34，俾當飽和電 流（Saturation CUrrent)產生時，該電性絕緣底層34 可切斷並阻絕次臨限漏電，進而提升金氧半電晶^元 件之效能。 其次，本發明藉由形成該電性絕緣底層34，更可 減少源極/汲極區之侧面擴散區域，俾可降低接面電 容、提升元件之操作速度。，亦即，本發明更可適用於 積集度高、通道極短之金氧半電晶體之製作者。 雖然本發明已以較佳實施例揭露如上，然其並非 用以限定本發明，任何熟悉此項技藝者，在不脫離本 發明之精神和範圍内，當可作更動與潤飾，因此本發 明之保護範圍當視後附之申請專利範圍所界定者為 準。 【圖式簡單說明】 圖一至圖六係本發明一較佳實施例製造流程之剖 面示意圖。 【主要元件符號說明】 基底12 淺溝渠區22 井區24 閘極氧化層26閘極電極28 硬罩幕3〇 間隙壁32 電性絕緣底層34淡摻雜區域36 間隙壁38 濃摻雜區域40 11々Slip-on washing liquid C such as phosphoric acid, H3P 〇 4) Huai 弁 n system ~ acid, H3P 〇 4) for the cleaning process, 'can remove 200847288 the hard mask material 30 and the spacer 32 (if hard The mask 30 and the partition 32 are made of oxidized stone and the hydrofluoric acid is used as the cleaning liquid. The seventh step of this month is to apply a light ion implantation to form a Lightly D0ped Drain (LDD) 36 on both sides of the well region 24 outside the gate electrode 28. The pale ion may be a pentavalent n-type ion (n_) such as phosphorus (P) or arsenic (As). The eighth step of the present invention is to form a spacer 38 on the sidewall of the gate electrode 28. The ninth step of the present invention is to apply concentrated ion implantation to form a heavily doped region 4() overlapping the lightly doped region 36 to form a source/drain region (SQurce/Drain(10), s/ d). The implantation energy and dose used for the concentrated ion (n+) is greater than the ion implantation step of the lightly doped region 36. The ninth step of the present invention utilizes a thermal process to adjust the bonding depth and doping profile of the source/drain regions. In this embodiment, the _S transistor is taken as an example, but the present invention is not limited thereto. It can also be applied to a _ transistor, that is, a source/no pole of a p-type is formed in a _ bottom or N-type well region. - In this way, the present invention has a method for manufacturing an electrically insulating underlayer, and its characteristics and effects are as follows: · 虱 + electric B 曰 body The present invention forms a space _32 before the top side of the stacking cover of the interpole electrode 28, so that the (four) Μ Into the screen ^; Moisture insulation ion implantation step, does not (4) = 10 200847288 damage, and, by the hot process (tempering) after the source / drain region and the base PN junction to form the electrical The insulating bottom layer 34, when the saturation current (Saturation CUrrent) is generated, the electrical insulating bottom layer 34 can cut off and block the secondary leakage current, thereby improving the performance of the gold-oxygen semiconductor device. Secondly, by forming the electrically insulating underlayer 34, the present invention can further reduce the side diffusion regions of the source/drain regions, thereby reducing the junction capacitance and the operating speed of the lifting elements. That is, the present invention is more applicable to a maker of a gold-oxygen semiconductor transistor having a high degree of integration and a very short channel. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and the invention may be modified and retouched without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application attached. BRIEF DESCRIPTION OF THE DRAWINGS Figures 1 through 6 are schematic cross-sectional views showing a manufacturing process of a preferred embodiment of the present invention. [Main component symbol description] Substrate 12 Shallow trench area 22 Well area 24 Gate oxide layer 26 Gate electrode 28 Hard mask 3〇 Gap 32 Electrically insulating underlayer 34 Lightly doped region 36 Gap 38 Concentrated doped region 40 11