200847231 2005-0101 22657twf.doc/p 九、發明說明： 【發明所屬之技術領域】 種導且特別是有關於-【先前技術】 Ο c200847231 2005-0101 22657twf.doc/p IX. Description of the invention: [Technical field to which the invention pertains] The species is guided and particularly relevant - [Prior Art] Ο c
件大隨體Γ路的積集度要求愈來愈高，整個半導體元 在_=被迫往尺寸不停縮小的方向前進。一般來 :大製程中’將元件與導線的尺寸縮小J 說，元的的微影製程來達成，也就是 的。、¥_尺奴由曝光顯影後的絲圖案來決定 高解析度的微影製程由於亦風 較為困難而且成本也較為昂責2 、、…因此技術 波長為193nm的ArF雷射作貝==術已經發展到使用 是下一世代的微影製程也正乍在^；^!呈的曝光光源，甚至 其他提高解析度的技術，對於193研九°絲，即使結合 形成％ mn以下的光阻随仍^11 =製程來說，要 物理極限，且料的製作與紐者，波長具有其 在，使得微影製程還會面臨解析^料擇亦有其限制所 佳等問題。 又不南、光阻圖案品質不 口此§半導體製程技街對積隹# 上 何解決上述製程中會遭遇的種種門:度f求日益提升，如 展的重點之一。 Θ靖’疋目前業界積極發 【發明内容】 200847231 2005-0101 22657twf.doc/p ^本發明提供—種導體結構的製作方法，可以突破原來 微影製程所能形成之最小尺寸的限制，以縮小導體結構的 尺寸。 -本發明另提供-種硬罩幕層的製作方法，能夠縮小硬 罩幕層的尺寸，以提升元件的積集度。 …本發明提出-種導體結構的製作方法，先提供其上已 形成有導體層之基底。於基底上形成多_案化罩幕芦。 Ο c 然後’於圖案化罩幕層之侧壁形成多俯猶壁，JL中I有 ，隙壁之__案化罩幕層之間具有間隙。接著，ς美 ==幕層，填入此間隙，硬罩幕層的尺寸小“ ^匕罩幕層的尺寸。隨之，移除贿化罩幕層叹間隙壁。 後’以硬罩幕層為罩幕’移除暴露巾 導體結構。 增以形成 ，本發明之—實施财，上述之硬罩幕層的形成 圖上形成硬罩幕材料層，硬罩幕材料層覆蓋 隙辟為_二=_壁。接者’以圖案化罩幕層以及間 |糸土為蝕刻終止層，移除部份硬罩幕材料層。 在本發明之一實施例中，導體結構的 移除部份硬罩幕材料層至完全暴露出間隨的上部。匕 及間例中’上述之移除圖案化罩幕層以 曰 1隙土的方法例如是進行第一 案化罩幕斧ϋ H 峨刻製&，以移除圖 壁。罩幕I Μ ’進㈣二濕式軸燦程，以移除間隙 在本發明之一實施例中，導體結構的製作方法更包括 6 200847231 2005-0101 22657twf.doc/p 於形成該導體結構之後，移除硬罩幕層。 在本發明之一實施例中，上述之硬罩幕層與導體層、 硬罩幕層與圖案化罩幕層以及硬罩幕層與間隙壁例如曰1 有不同之蝕刻選擇性。 疋/、 、 在本發明之一實施例中，上述之導體結構例如是導 在本發明之一實施例中，上述之導體結構例如是 Ο u 在本發明之一實施例中，上述之導體層由下而上 例如是多晶吩層以及石夕化金屬層。 在本發明之一實施例中 如是已形成有一介電層。 在本發明之一實施例中 金屬、多晶矽或是矽化金屬 在本發明之一實施例中 例如是多晶矽。 在本發明之一實施例中 氮化石夕。 在本發明之一實施例中 是硼磷矽玻璃。 ’上述之基底與導體層之間例 ’上述之導體層的材料例如是 Ο ，上述之_化轉層的材料 ’上述之間隙壁的材料例如是 ’上述之硬罩幕層的材料例如 本發明另提出-種硬罩幕層的製作方法，包括下列步 查。首先，於基底上形成多個圖案化罩幕層。然後，於圖 案化罩幕層之側㈣成多姻_，其巾具有間隙壁之兩 目鄰圖案化罩幕層之間具有_。接著，於基底上形成硬 Ο ο 200847231 2005-0101 22657twf.doc/p 罩幕材料層，覆蓋圖案化罩幕層與間隙壁。然後，ρ u 化罩幕層與間隙壁為蝕刻終止層，移除部份硬罩 層。之後，移除圖案化罩幕層以及間隙壁，以形成 料 層，硬罩幕層的尺寸小於圖案化罩幕層的尺寸。/ 幕 在本發明之一實施例中，硬罩幕層的製作方法更包 移除部份硬罩幕材料層至完全暴露出間隙壁的上部。匕 在本發明之-實施例中，上述之硬罩幕材料層與圖安 化罩幕層以及硬罩幕材料層與間隙壁例如是再有不 一 刻選擇性。 /、 σ之蝕 在本發明之一實施例中，上述之硬罩幕材料層的 例如是蝴碟;5夕玻璃。 ^本發明之—實施射，上狀圖案化罩幕層的材料 例如是多晶石夕。 "在本發明之-實施例十，上述之間隙壁的材料例如 氮化石夕。 ~ 本發明利用在圖案化罩幕層之側壁形成間隙壁，再於 f間隙壁之兩相鄰圖案化罩幕層之間的間隙中填入硬罩 2罢=將圖案化罩幕層以及間隙壁移除，並以硬罩幕 :=„具有較小尺寸的導體結構。因此，此種 告“二ΐ突？目前的微影製程所能形成之最小尺寸的限 明^ ΐ到縮小導體結構的尺寸之功效。也就是說，本發 ==的元件尺寸，來增一^ 此外’本發明可以藉由控制間隙壁形成的寬度，來調 8 200847231 2005-0101 22657twf.doc/p 控間隙的大小，使得形成於間隙中的硬罩幕層之尺寸可以 小於利用微影製程所製作的圖案化罩幕層之尺寸。因此， 士發明可藉㈣易的流程達成縮小元件尺寸的目的，而不 而進仃額外的微影製程，可有助於節省製程中的成本。 為讓本發明之上述特徵和優點能更明顯易懂，下文特 舉較佳實施例，並配合所附圖式，作詳細說明如下。、 【實施方式】 〇 圖至圖1F為依照本發明之一實施例之導體結構的 製作流程剖面圖。 首先，請參照圖1A，提供一基底100。基底1〇()中例 如已形成有導體層（未繪示）、介電層（未繪示)或是一般熟知 的半導體元件(未繪示）。之後，於基底刚上形成導體廣 。導體層102的材料例如是金屬、多晶矽或是矽化金 ，。導體層102的形成方法例如是先於基底100上形成多 晶石夕層102a。隨之，再於多晶石夕層斷上形成石夕化金屬 層l〇2b，而矽化金屬層1〇2b的材料例如是矽化鎢。導體 ° 層ι〇2的形成方法例如是進行化學氣相沈積法或物理氣相 沈積法。在本實施例中，導體層102例如是由多晶矽層102a 以及矽化金屬層102b所構成的雙層結構，然而本發明之導 體層102的材料以及膜層數並不侷限於本實施例中所繪 不，於此技術領域具有通常知識者可視其需求進行調整。 接著，請繼續參照圖1A，於導體層102上形成罩幕 層104。罩幕層1〇4的材料例如是多晶矽，其形成方法例 如疋化學氣相沈積法。然後，於罩幕層上形成圖案化光p旦 200847231 2UU^U101 22657twf.doc/p 層106,以覆蓋住部分 成方法例如是先於罩fa G4圖木化光阻層106的形 示），之後再進行曝& θ 上㈣—層光阻層（未繪 程所形成的圖案化先先阻:：的^ 圖案之間的間距相同。'、3案尺寸例如是與兩相鄰 之後’睛參照圖岡安 進行乾編m程層1G6為罩幕， Ο 移除。4’。隨之，將圖案化光阻層106 二阻層106的方法例如是乾式去光阻法 或濕式去先阻法。接下來，於導體層搬 ，104，。，壁材料層π〇的材料例如是氮化 成方法例如是化學氣相沈積法。 在-實施例中，圖案化罩幕層104，之尺寸wi例如是 90 rnn’且兩相鄰圖案化罩幕㉟刚，之間的圖案間距例如 是 90 nm。 接著，請參照圖1C，進行非等向性敍刻製程，移除 部分間隙壁材料層110,以於圖案化罩幕層刚，的侧壁形 成間隙壁11G’。此時’於具有間隙壁11G，之兩相鄰圖案化 罩幕層104’之間具有間隙1〇8。此外，由於進行非等向性 蝕刻製程時，亦會對垂直方向的間隙壁材料層11〇造成損 耗’於之後所形成的間隙壁11〇,之上部p因而會有圓化現 象(rounding)的產生。一般而言，可以藉由控制先前所沈積 的間隙壁材料層110之厚度與蝕刻條件等參數，視製程需 200847231 2005-0101 22657twf.doc/p 求對間隙壁110’底部之寬度W2進行調整，進而控制間隙 108的寬度，以符合元件設計的需求。 承上述’在一實施例中，間隙壁110’底部之寬度W2 例如是15 nm。由於兩相鄰圖案化罩幕層1〇4,之間的圖案 間距例如是90 nm，因此具有間隙壁110,之兩相鄰圖案化 罩幕層104’之間的間隙1〇8的寬度則例如是6〇nm。 然後，請繼續參照圖1C，於導體層102上形成硬罩 Ο ο 幕材料層112。硬罩幕材料層112覆蓋住圖案化罩幕層1〇4, 以及間隙壁110,，並填入間隙108中。硬罩幕材料層112 的材料例如是硼磷矽玻璃，其形成方法例如是化學氣相沈 積法。 接著，請參照圖1D，移除部份硬罩幕材料層112，以 =間隙1〇8中形成硬罩幕層m，。移除部份硬罩幕材料層 ^方法例如是⑽躲，如乾絲駭或濕絲刻 法。值付h狀，硬罩幕㈣層112 於移除硬罩幕材料層112 # 罩幕材料層m例如是移除至：入f見象’因此移除硬 部p，使硬罩幕層112,頂部之==_上 避免於後績進行飿刻製程時，^索 、致以 在一實施财，形成於_ 1GY巾的乡=。 11 200847231 2005-0101 22657twf.doc/p 上述移除硬罩幕材㈣112i完全暴露出間 部Ρ之後，硬罩幕層112,之尺寸W3例如是6〇nm。 請餐照® 1E，將圖案化罩幕層1〇4，移除 化罩幕層刚，的方法例如是濕式_法 = 硝酸與氫_組成之混合溶液來進行 j == 壁·。移除間隙壁110,的方法例如是^^除， 如是使用經加熱的磷酸來進行。 人4 z、例 Ο Ο 之後，睛茶照圖1F，以硬罩幕芦 露出的導體層1〇2,以形成導曰為罩幕，移除暴 除方法例如先移除暴露出的魏金屬層舰b = 暴露出的多晶矽層102a 接耆再移除 晶砍層_的方法例如是乾以及多 導體結構114形成之後,實施财，於 程，將硬罩幕層112,移除。 少2-擇性地進仃蝕刻製 —^W3^6〇 之 值得注意的是，由於問隙 層104,之尺寸W1，而、/、 的九度小於圖案化罩幕 而形成於間隙1 〇8中的麻罢| 之尺寸W3亦會小於圖二厲中的硬罩幕層112, 是說，以舜¥萁β Ί案化罩幕層1〇4,之尺寸W1。冰魷 疋兄以硬罩幕層〗〗2,為罩幕所彬士憎碰^ 也就 W4會小於圖案化罩幕層]04，之°構114之尺寸 ⑴之尺寸W4可以 ^尺寸W卜因此’導體結構 尺寸的限制。 ㈤n讀程所能形成之最小 尺寸-例如是2 2為罩幕所形成導體結構丨14 12 200847231 2005-0101 22657twf.doc/p 利用上述方法所形成的導體結構114 -實施例中，於基底⑽與導體層102j=閘極。在 層介電層（未繪示），以作為閘極氧化層。^ 成― 材料例如是二氧化矽’其形成方法例如是化乂= 塞，於此技術領域具有通常知二 線或是插 Ο ο 另-方面’本發明並不揭限於將導見髓=。=。 製作導體結構m。本發明可更進—=02圖案化以 層，以縮小待钕刻層上的圖宰尺寸;^用於製作硬罩幕 施例中，導體層搬可是說，在其他實 料層例如是多晶㈣、介電層、全、tffD’材 壁不舰於上述實==㈡ 。也就是說’材料層與硬罩幕層m’、圖 罩幕=104、間隙壁11〇，例如是具有不同之钱刻選擇性， 即可應用上逑方法來定義具有較小尺寸之材料層。詳 流程為此技術領域中具有通常知識者當可知其翻，故於 此不再費述。 、 、綜上所述，本發明利用圖案化罩幕層以及間隙壁 成，以於間隙中形成硬罩幕層，再藉由移除圖案化罩幕/ 以及間隙壁，以硬罩幕層為罩幕㈣作導體結構。由3 罩幕層之尺寸小於圖案化光阻層之圖案尺寸，因此，利用 本發明能夠克服目前微影製程解析度的限制，製作出具 較小尺寸的閘極、導線、插塞或是其他導體結構。、 13 200847231 2005-0101 22657twf.doc/p 此外，利用上述的方法製作出的硬罩幕層具有較小的 士、:更可以於任何待钱刻的材料層上定義較小的圖案尺 寸，來增加積體電路的積集度。 • 另—方面’本發明可以藉由控制間隙壁的寬度，使得 =間隙巾的硬罩幕層之尺寸小於利賴影製程所製作的 I、化罩幕層之尺寸。也就是說，在不更換機台的前提之 I此種方法可以突破微影製程中機台與光阻的限制，而 f) 尺寸較小、品質較佳的圖案及結構。因此，本發明藉 簡易的就可以達到縮小尺寸的功效，進而提升元件 ，集度與製程n使得製程困難度降低，可有助於節省 製造成本。 —雖然本發明已以較佳實_減如上，然其並非用以 限定本發明’任何所屬技術領域中具有通常知識者 脫離本發明之精神和範圍内，當可作些許之更動與潤 因此本發明之保護範圍當視後附之申請專利範圍所界 為準。 又节 1) 【圖式簡單說明】 圖1A至圖1F為依照本發明之一實施例之導體鈐 製作流程剖面圖。 "的 【主要元件符號說明】 100 :基底 102 :導體層 102a ·多晶砍層 102b :矽化金屬層 14 200847231 2005-0101 22657twf. doc/p 104 :罩幕層 104’ ：圖案化罩幕層 106 :圖案化光阻層 108 :間隙 110 :間隙壁材料層 110’ ：間隙壁 112 :硬罩幕材料層 112’ ：硬罩幕層 114 :導體結構 P :上部 W卜W3、W4 :尺寸 W2 :寬度The demand for the large-scale body-carrying circuit is getting higher and higher, and the entire semiconductor element is forced to move toward the size of the _=. Generally speaking: in the large process, the size of the component and the wire is reduced. J says that the lithography process of the element is achieved, that is. , _ 尺 奴 by the exposure of the developed silk pattern to determine the high-resolution lithography process because the wind is more difficult and costly more blame 2, ... so the technical wavelength of 193nm ArF laser for shell == surgery Has been developed to use the next generation of lithography process is also in the ^; ^! exposure light source, and even other techniques to improve the resolution, for the 193 research nine ° wire, even if combined with the formation of photoresist below % mn Still ^11 = process, the physical limit, and the production and materials of the material, the wavelength has its own, so that the lithography process will also face the problem of the choice of materials and its limitations. It is not south, the quality of the photoresist pattern is not § § Semiconductor process technology street against the accumulation of # 上 How to solve the various processes that will be encountered in the above process: degree f seeking increasing, such as one of the focus of the exhibition. Θ靖'疋 is currently active in the industry [invention] 200847231 2005-0101 22657twf.doc/p ^ The present invention provides a method for fabricating a conductor structure that can break through the limitations of the minimum size that can be formed by the original lithography process to reduce The size of the conductor structure. - The present invention further provides a method of fabricating a hard mask layer capable of reducing the size of the hard mask layer to enhance the integration of components. The present invention proposes a method of fabricating a conductor structure by first providing a substrate on which a conductor layer has been formed. Forming a multi-case mask on the substrate. Ο c then 'forms the sidewalls of the patterned mask layer to form a multi-dip wall, JL has I, and there is a gap between the mask walls. Next, ς美==the curtain layer, fill in the gap, the size of the hard mask layer is small "^ 匕 匕 幕 。 。 。 。 。 。 。 。 。 随之 随之 随之 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除The layer is a mask 'removing the exposed towel conductor structure. The invention is formed, and the hard mask layer is formed on the formation of the hard mask layer, and the hard mask material layer covers the gap _ The second = _ wall. The splicer layer and the smear layer are used as an etch stop layer to remove a portion of the hard mask material layer. In one embodiment of the invention, the removed portion of the conductor structure The hard mask material layer is completely exposed to the upper portion. In the above example, the method of removing the patterned mask layer to remove the soil is, for example, performing the first case mask axe H engraving System & to remove the wall. The mask I Μ 'into (four) two wet shaft can be removed to remove the gap in one embodiment of the invention, the conductor structure is further included 6 200847231 2005-0101 22657twf .doc/p After forming the conductor structure, the hard mask layer is removed. In one embodiment of the invention, the hard mask described above The layer and conductor layers, the hard mask layer and the patterned mask layer, and the hard mask layer have different etch selectivity from the spacers, such as 曰1. 疋/, In one embodiment of the invention, the conductor structure described above For example, in one embodiment of the present invention, the conductor structure described above is, for example, Ο u. In one embodiment of the invention, the conductor layer is, for example, a polycrystalline phenary layer and a stellite metal layer from bottom to top. In one embodiment of the invention, a dielectric layer has been formed. In one embodiment of the invention, the metal, polysilicon or deuterated metal is, for example, a polysilicon in one embodiment of the invention. In one embodiment of the present invention, borophosphonium bismuth glass is used. The material of the conductor layer described above between the substrate and the conductor layer is, for example, Ο, the material of the above-mentioned conversion layer The material of the spacer is, for example, the material of the hard mask layer described above, for example, the method for fabricating the hard mask layer, which includes the following steps. First, a plurality of patterned mask layers are formed on the substrate. Of course On the side of the patterned mask layer (4) into a plurality of marriages, the towel has a gap between the two adjacent patterned patterned mask layers. Then, a hard Ο is formed on the substrate. 200847231 2005-0101 22657twf.doc /p mask material layer covering the patterned mask layer and the spacer. Then, the pudding mask layer and the spacer are etch stop layers, and part of the hard mask layer is removed. Thereafter, the patterned mask layer is removed. And a spacer to form a layer of material, the size of the hard mask layer being smaller than the size of the patterned mask layer. / Curtain In one embodiment of the invention, the method of fabricating the hard mask layer further includes removing a portion of the hard mask The curtain material layer is completely exposed to the upper portion of the spacer. In the embodiment of the present invention, the hard mask material layer and the patterned mask layer and the hard mask material layer and the spacer are, for example, A moment of selectivity. /, σ etch In one embodiment of the present invention, the above-mentioned hard mask material layer is, for example, a butterfly disc; The material of the present invention, which is a topographically patterned mask layer, is, for example, polycrystalline. < In the tenth embodiment of the present invention, the material of the above-mentioned spacer is, for example, nitrided. ~ The present invention utilizes a spacer formed on the sidewall of the patterned mask layer, and then fills the gap between the two adjacent patterned mask layers of the f-spacer into the hard mask 2; the patterned mask layer and the gap The wall is removed and the hard mask is: =„The conductor structure has a smaller size. Therefore, this kind of slogan “two conflicts? The minimum size that can be formed by current lithography processes is limited to the size of the conductor structure. That is to say, the size of the component of the present invention is increased by one. Further, the present invention can adjust the size of the gap by controlling the width of the spacer wall, so that the size of the gap is controlled. The size of the hard mask layer in the gap can be smaller than the size of the patterned mask layer made by the lithography process. Therefore, the inventor can use the (four) easy process to achieve the purpose of reducing the size of the component, and not to enter an additional lithography process, which can help to save the cost in the process. The above described features and advantages of the present invention will become more apparent from the following description. [Embodiment] FIG. 1F is a cross-sectional view showing a manufacturing process of a conductor structure according to an embodiment of the present invention. First, referring to FIG. 1A, a substrate 100 is provided. For example, a conductor layer (not shown), a dielectric layer (not shown), or a generally well-known semiconductor component (not shown) has been formed in the substrate. After that, a large conductor is formed on the substrate. The material of the conductor layer 102 is, for example, metal, polycrystalline germanium or gold telluride. The conductor layer 102 is formed by, for example, forming a polycrystalline layer 102a on the substrate 100. Subsequently, a shihua metal layer l〇2b is formed on the polycrystalline slab layer, and the material of the bismuth metal layer 〇2b is, for example, tungsten telluride. Conductor ° The formation method of the layer ι 2 is, for example, a chemical vapor deposition method or a physical vapor deposition method. In the present embodiment, the conductor layer 102 is, for example, a two-layer structure composed of a polysilicon layer 102a and a deuterated metal layer 102b. However, the material of the conductor layer 102 and the number of layers of the layer of the present invention are not limited to those depicted in this embodiment. No, those skilled in the art can adjust to their needs. Next, referring to FIG. 1A, a mask layer 104 is formed on the conductor layer 102. The material of the mask layer 1 〇 4 is, for example, polycrystalline germanium, and its formation method is, for example, bismuth chemical vapor deposition. Then, a patterned light pdan 200847231 2UU^U101 22657twf.doc/p layer 106 is formed on the mask layer to cover the portion forming method, for example, the pattern of the photoresist layer 106 before the mask fa G4 is applied) Then, the exposure & θ is applied to the (four)-layer photoresist layer (the pattern formed by the unpatterned first-resistance:: the spacing between the patterns of the ^ is the same. ', the size of the 3 case is, for example, after two adjacent' The eye is etched with reference to Tugangan, and the mG layer 1G6 is used as a mask, and Ο is removed. 4'. Accordingly, the method of patterning the photoresist layer 106 of the photoresist layer 106 is, for example, a dry photoresist method or a wet method. Next, in the conductor layer, 104, the material of the wall material layer π 例如 is, for example, a nitridation method such as chemical vapor deposition. In the embodiment, the size of the mask layer 104 is patterned. Wi is, for example, 90 rnn' and the pattern spacing between two adjacent patterned masks 35 is, for example, 90 nm. Next, referring to FIG. 1C, an anisotropic etching process is performed to remove a portion of the spacer material layer. 110, in order to pattern the mask layer, the sidewalls of the mask layer form a gap wall 11G'. At this time, the spacer wall 11G is provided. There is a gap 1〇8 between the two adjacent patterned mask layers 104'. In addition, due to the anisotropic etching process, the spacer material layer 11 in the vertical direction is also damaged. The spacers 11〇, the upper portion p thus has a rounding effect. Generally, the parameters such as the thickness and etching conditions of the previously deposited spacer material layer 110 can be controlled, and the process requires 200847231. 2005-0101 22657twf.doc/p The width W2 of the bottom of the spacer 110' is adjusted to control the width of the gap 108 to meet the requirements of the component design. In the above embodiment, the bottom of the spacer 110' The width W2 is, for example, 15 nm. Since the pattern spacing between two adjacent patterned mask layers 1 〇 4 is, for example, 90 nm, there is a spacer 110 between the two adjacent patterned mask layers 104 ′. The width of the gap 1 〇 8 is, for example, 6 〇 nm. Then, referring to Fig. 1C, a hard mask 幕 ο οf material layer 112 is formed on the conductor layer 102. The hard mask material layer 112 covers the patterned mask layer 1 〇4, and the spacer 110, and fill in the room 108. The material of the hard mask material layer 112 is, for example, borophosphon glass, and the forming method thereof is, for example, chemical vapor deposition. Next, referring to FIG. 1D, a part of the hard mask material layer 112 is removed to = gap A hard mask layer m is formed in 1〇8. The method of removing part of the hard mask material layer is, for example, (10) hiding, such as dry silk or wet silk carving. The value is h-shaped, and the hard mask (four) layer 112 is Removing the hard mask material layer 112 # The mask material layer m is, for example, removed until: the intrinsic image is seen, so the hard portion p is removed, so that the hard mask layer 112, the top of the ==_ is avoided. When engraving the process, ^ cable, to the implementation of a wealth, formed in the township of _ 1GY towel =. 11 200847231 2005-0101 22657twf.doc/p After removing the hard mask material (4) 112i completely exposing the internal crucible, the hard mask layer 112 has a size W3 of, for example, 6 〇 nm. Please take the meal photo 1E, pattern the mask layer 1〇4, remove the mask layer, for example, wet_method = mixed solution of nitric acid and hydrogen _ to make j == wall ·. The method of removing the spacers 110 is, for example, a removal, such as using heated phosphoric acid. After 4 z, the case Ο ,, the tea is shown in Figure 1F, with the conductor layer 1〇2 exposed by the hard mask, to form the guide as a mask, and the removal method is removed, for example, the exposed Wei metal is removed first. After the layered ship b = the exposed polysilicon layer 102a and then the chipped layer is removed, for example, after the dry and multi-conductor structure 114 is formed, the hard mask layer 112 is removed. Less than 2 - selective etching process - ^ W3 ^ 6 〇 It is worth noting that due to the gap layer 104, the size W1, and /, nine degrees is smaller than the patterned mask formed in the gap 1 〇 The size W3 of the 8th is also smaller than the hard mask layer 112 of Fig. 2, which means that the size W1 of the mask layer 1〇4 is 舜¥萁β. Bing Xiong brother with a hard mask layer〗 〖 2, for the mask to touch the 憎 ^ ^ ^ W4 will be smaller than the patterned mask layer] 04, ° ° structure 114 size (1) size W4 can ^ size W Bu Therefore 'the size of the conductor structure is limited. (5) The minimum size that n read can be formed - for example, 2 2 is the conductor structure formed by the mask 丨 14 12 200847231 2005-0101 22657twf.doc / p The conductor structure 114 formed by the above method - in the embodiment, on the substrate (10) And the conductor layer 102j = gate. A layer of dielectric (not shown) is used as the gate oxide layer. The material is, for example, cerium oxide, which is formed, for example, by phlegm = plug, which is generally known in the art as a second-line or plug-in. The invention is not limited to the invention. =. Fabricate the conductor structure m. The invention can be further advanced - =0 patterned into layers to reduce the size of the pattern on the layer to be etched; ^ used in the manufacture of the hard mask embodiment, the conductor layer can be said to be, for example, in other solid layers Crystal (4), dielectric layer, full, tffD' material wall is not in the above real == (two). That is to say, 'material layer and hard mask layer m', mask = 104, spacer 11 〇, for example, have different cost selectivity, then the upper 即可 method can be applied to define a material layer with a smaller size. . The detailed process is known to those of ordinary skill in the art and will not be described here. In summary, the present invention utilizes a patterned mask layer and spacers to form a hard mask layer in the gap, and by removing the patterned mask/gap, with a hard mask layer The cover (4) is used as a conductor structure. The size of the mask layer is smaller than the pattern size of the patterned photoresist layer. Therefore, the present invention can overcome the limitations of the current lithography process resolution and produce gates, wires, plugs or other conductors having a smaller size. structure. , 13 200847231 2005-0101 22657twf.doc/p In addition, the hard mask layer produced by the above method has a smaller taxi, and can define a smaller pattern size on any material layer to be engraved. Increase the accumulation of integrated circuits. • Another aspect] The present invention can control the width of the spacer wall such that the size of the hard mask layer of the gap mask is smaller than the size of the mask layer produced by the photo processing process. That is to say, in the premise of not changing the machine, this method can break through the limitation of the machine and the photoresist in the lithography process, and f) the pattern and structure with smaller size and better quality. Therefore, the present invention can achieve the effect of downsizing by simple means, thereby improving the components, the degree of assembly and the process n, which makes the process difficulty less, and can help to save manufacturing costs. </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; The scope of the invention is defined by the scope of the appended claims. Further Section 1) [Schematic Description of the Drawings] Figs. 1A to 1F are cross-sectional views showing a manufacturing process of a conductor 依照 according to an embodiment of the present invention. "Main component symbol description] 100: Substrate 102: Conductor layer 102a Polycrystalline chopped layer 102b: Deuterated metal layer 14 200847231 2005-0101 22657twf. doc/p 104: Mask layer 104': Patterned mask layer 106: patterned photoresist layer 108: gap 110: spacer material layer 110': spacer 112: hard mask material layer 112': hard mask layer 114: conductor structure P: upper Wb W3, W4: size W2 :width
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