200845865 九、發明說明： 【發明所屬之技術領域】 本發明係關於薄膜陶瓷冬 其是闕於適於作為探針卡的及錢造方法’尤 膜陶瓷多層佈線板及爱穿』1^木夕層佈線板之高積集薄 曰日片專之南頻模組 【先前技術】 ，年，動通訊技術的發展已朝 細小化、多功能化、模组化 /丁树％迷地 技術中，對於消費者的高要求，於此類 陶兗多層佈線板。 一㈣冋或低溫共燒 訊、微波連接器、境線動通 換。之，利用半導體裝置(例 裝置近來在舰與尺杜進行料。料财/之== 增加’且被微型化並具有多個接腳。t—個板具有内建^ 接腳小尺寸半導體裝置，則已提供了彻建構方法 佈線板。 夕曰 於此類多層佈線板中，利用如玻璃纖維銅包覆層疊板 之強化材料作為核心層。絕緣層與佈線層選擇性地形成於 核〜層之任一表面。同時，形成精細佈線層於多層佈線板 上’使得兩積集半導體裝置可安裝於精細佈線層上。 高溫共燒陶瓷多層佈線板(HTCCJVILC)藉由150(rc 200845865 =高的溫度熱處理而形成。高溫共燒陶❹層佈線板之 材料_ 94%或更高的礬土(alumina)作為主成分，而 /里的矽土(silica)作為添加劑，且可於高溫塑形夂鎢(W) 主要作為電導體。高溫共燒陶莞多層佈線板具有絕佳的機 f固性與化學抗性，因而相於有薄膜導線形成於其上的 尚積木封裝。然而，咼溫塑形之鑛導體的導電率低於銀(入幻 或，(Cu)的‘電率，使付咼溫共燒陶莞多層佈線板有不良 『 的高頻特性。此外，熱膨脹係數約為矽半導體裝置的兩倍， 在需要熱膨脹係數匹配的應用領域成為嚴重的問題。 另一方面，低溫共燒陶瓷多層佈線板(LTCC—MLC)藉 由1000 C或更低的溫度熱處理而形成。因此使用大量的低 熔點矽土與相對少量的礬土。當塑形於1000°C或更低的溫 度時，用銀或銅作為導電材料。此外，被動元件如電阻、 電感、電各态(condenser)安裝於板中。因此，此板廣泛地 用於微型化、多功能化、模組化、以及供容納高頻電子元 ί, 件。 _ 然而’低溫共燒陶兗多層佈線板之表面含有大量的二 氧化石夕(Si〇2)，因此在利用強酸物質(例如氬氟酸(HF))或強 鹼物質(例如氳氧化鉀(KOH))之蝕刻程序中容易被蝕刻。 一種解決此問題的方法揭露於韓國專利公開第 10_2007_0013063號，名稱為「多層佈線基板及其製造方法 (Multi-layered Wire Substrate and Method of Manufacturing 7 200845865 the Same)」。 ^此專利余開案揭示一種解決在利用強酸物質(例如氫 氟酸(HF))或強鹼物質（例如氫氧化鉀(K〇H》之蝕刻程序 中，谷易蝕刻表面含有矽化合物之低溫共燒陶瓷多層佈線 板之問題的技術，其係因為作為低溫共燒陶兗多層佈線板 表面之第一絕緣結構含有大量的二氧化矽(Si〇2)。 ( 尤其是，為解決上述問題，第一蜱緣結構完全地被抗 蝕刻劑之第一絕緣結構覆蓋與保護，蝕刻劑包含強酸物質 (例如氳氟酸(HF))與強鹼物質(例如氳氧化鉀(K〇H))。 如圖1所示，多層佈線板主體1000a包含第一導電結 構1〇〇與第-絕緣結構200。第一導電結構1〇〇包含至少: ， —導，圖案10與至少一導電接觸20。第-絕緣結構2〇〇 包圍第-導電結構1〇〇，以暴露第一導電結構励之一部 份1(^，且包含於麵歧低溫燒把低溫共燒陶究材 料第、、、邑緣結構2〇〇之上表面與第一導電結構刚之部 份^的:L表面置於相同水平。於多層佈線板主體l〇〇〇a 置苐$龟結構如〇以電連接第一導電結構1〇〇之 部份10卜此外，設置包圍第二導電結構3〇〇與多 板主體1000a之第二絕緣結構4〇〇，以 :、 2構膨於透過第二絕緣結構400被暴露以 構表面上，形成導電塗佈膜以保護第二導電結構跡 8 200845865 另，例之多層佈線板及其製造方法揭露於韓國專利 公開弟 2007-0028246 號(2007 年 3 月 12 日）。200845865 IX. INSTRUCTIONS: [Technical field of the invention] The present invention relates to a thin film ceramic winter which is suitable for use as a probe card and a method of making money, a special film ceramic multilayer wiring board and a love wearing one The high-density layer of the wiring board is designed for the south frequency module of the thin film. [Previous technology], the development of the mobile communication technology has been reduced to a small, multi-functional, modular/Dingshu% technology. For the high demands of consumers, in this kind of ceramic multilayer wiring board. One (four) 冋 or low temperature co-firing, microwave connector, and dynamic line switching. In this case, a semiconductor device is used (for example, the device has recently been used to carry out materials in the ship and the ruler. The material is increased by == and is miniaturized and has a plurality of pins. The t-board has a built-in pin-sized small-sized semiconductor device. In the case of such a multilayer wiring board, a reinforcing material such as a glass fiber copper-clad laminate is used as a core layer. The insulating layer and the wiring layer are selectively formed on the core to the layer. At the same time, a fine wiring layer is formed on the multilayer wiring board' so that the two integrated semiconductor devices can be mounted on the fine wiring layer. The high temperature co-fired ceramic multilayer wiring board (HTCCJVILC) is 150 (rc 200845865 = high) It is formed by heat treatment at a temperature. The material of the high-temperature co-fired ceramic layer wiring board _ 94% or more of alumina is used as a main component, and the silica is used as an additive and can be shaped at a high temperature. Tungsten (W) is mainly used as an electrical conductor. High-temperature co-fired ceramic multilayer wiring boards have excellent mechanical properties and chemical resistance, and thus are formed in a block package with thin film wires formed thereon. Shaped ore conductor The electric rate is lower than that of silver (into the illusion or (Cu)'s electric rate, so that the high-frequency characteristics of the ceramic board of the ceramics are poor. In addition, the coefficient of thermal expansion is about twice that of the semiconductor device. In the field of application requiring thermal expansion coefficient matching, it becomes a serious problem. On the other hand, low-temperature co-fired ceramic multilayer wiring board (LTCC-MLC) is formed by heat treatment at a temperature of 1000 C or lower. Therefore, a large amount of low-melting bauxite is used. With a relatively small amount of alumina, silver or copper is used as the conductive material when it is shaped at 1000 ° C or lower. In addition, passive components such as resistors, inductors, and electrical condensers are mounted in the board. This board is widely used for miniaturization, multi-functionalization, modularization, and for accommodating high-frequency electronic components. _ However, the surface of the low-temperature co-fired ceramic enamel multilayer wiring board contains a large amount of dioxide dioxide ( Si〇2) is therefore easily etched in an etching process using a strong acid substance such as argon fluoride (HF) or a strong alkali substance such as potassium oxyhydroxide (KOH). A method for solving this problem is disclosed in Korean Patent Public No. 10_2007_0013063, The name is "Multi-layered Wire Substrate and Method of Manufacturing 7 200845865 the Same". ^ This patent publication discloses a solution to the use of strong acid substances (such as hydrofluoric acid (HF)) or A technique for a problem of a low-temperature co-fired ceramic multilayer wiring board in which a high-alkali substance (for example, a low-temperature co-fired ceramic multilayer wiring board containing a ruthenium compound is etched on a surface of a potassium hydroxide (K〇H)) The first insulating structure of the surface contains a large amount of cerium oxide (Si 〇 2). (In particular, in order to solve the above problem, the first rim structure is completely covered and protected by the first insulating structure of the etch resist, and the etchant contains a strong acid substance (for example, fluoric acid (HF)) and a strong alkali substance (for example, ruthenium). Potassium Oxide (K〇H)) As shown in Fig. 1, the multilayer wiring board main body 1000a includes a first conductive structure 1〇〇 and a first insulating structure 200. The first conductive structure 1〇〇 includes at least: , a guide, a pattern 10 and at least one conductive contact 20. The first insulating structure 2 〇〇 surrounds the first conductive structure 1 〇〇 to expose one of the first conductive structures 1 (^, and is included in the surface low temperature firing low temperature co-firing The surface of the ceramic material, the upper surface of the 邑 结构 structure and the first conductive structure is the same as the surface of the first conductive structure: the L surface is placed at the same level. The body of the multilayer wiring board l〇〇〇a is placed at $ turtle structure For example, a portion 10 of the first conductive structure 1 is electrically connected. Further, a second insulating structure 4 surrounding the second conductive structure 3 and the multi-plate main body 1000a is provided to: The second insulating structure 400 is exposed on the surface to form a conductive coating film to protect the second conductive junction STRUCTURE 8 200845865 Another example of a multilayer wiring board and a method of manufacturing the same are disclosed in Korean Patent Publication No. 2007-0028246 (March 12, 2007).
圖2為於專利公開案揭露之多層佈線板之截面圖。如 多層佈線板包含依序由下而上堆疊之強化佈線 ^1〇3、弟一絕緣層104、互連105、第二絕緣層應、互 連⑽、第三絕緣層107、互連110、第四絕緣層1〇9、以 及互連112。焊料_ 102形成於第一絕緣層耐之下表 面上’而焊料._ 12〇形成於第四絕緣層1G9之上表面上。 1的絕緣層104、106、107、與_係由具熱固性之環 氧树脂形成。互連1G5由介胁塞部1G5a姻案 =5b構成。介層栓塞部1〇Sa形成於形成在第一絕緣層辦 之開口内’而圖案互連部lG5b形成於第一絕緣層川4 之上表面上。 上述專利公開案揭露的技術具有以下缺點：製造方法 I 複雜，且报難實施於高密度佈線板。此乃因網板印刷製程 技使得第二絕緣結構並不覆蓋在第—絕緣結構中的第 結構之輸出墊，而形成的第二導電結構連接輸出塾 十利用電漿喷灑方法形成第二絕緣結構，以完全地覆蓋 ^ -絕緣結構與第二導電結構而具有Qlmm至1Q_之 厚，第二絕緣結構的兩表面依序搭接(laPPed)以暴露第 一導電結構之輸出墊。於此，根據第二導電結構與搭接製 9 η υ 200845865 程條件，搭接的第二絕緣結構的厚度與絕緣特性可有不同 變化，且需要額外的製程管理以維持穩定的品質。 此外，於搭接程序完成後，再次形成薄膜導電結構於 暴露的第二導電結構，因此使得製造程序更加複雜。 【發明内容】 本發明用以解決上述問題，且本發明目的之一為提供 種薄膜陶瓷多層佈線板，其係適用於微型化、多功能化、 杈組化與當發展行動通訊技術時使用較高頻之 ^ ’且其具雜學祕，尤其是錢㈣_f(例如氣 或強鹼物質(例如氫氧化鉀(koh》之 中’同時提供製造此薄膜陶究多層佈線板之方法。 的圖案。 幻表化耘序且可輕易地實施精細 !之_陶❹層佈線板及其製造方法， 獲得以下的效果 可 結構二：方2接第-導電結構與第二導電 :導電結構可輕易地實‘二ΐ具電結構之第 度。 、圖木，而忐輕易達到高積集 10 200845865 此外，利用物理沉積方法，例如電子束或濺鍍，形 由氧化鋁構成的第二絕緣結構於含有實質量氧化矽之第一 絕緣結構上，因此不會暴露第一絕緣結構於強酸物質(例如 氳氟酸(HF))或強鹼物質(例如氫氧化鉀(K〇H))。因此，可 輕易地製造具有良好化學抗性之陶瓷多層佈線板。 為達成上述目的，本發社—方面提供—種薄膜陶究 多層佈線板，其包含··第一導電結構與包圍第一導電結構 之第-絕緣結構，此兩者構成一多層佈線板主體、包^ -絕緣結構之第二絕緣結構、以及形成於第 ^塾上之第二導電結構。於此，第二導電結構 性電鑛銅(Cu)、鎳㈣、以及金(Au)而形成。 谇 以 第二導電結構可形成於第—導電結構之輸出墊上， 具有大於第一導電結構之輸出墊之直徑。 第二絕緣結構可形成為G.3至3//m之厚度。 第-導電結構之輸出墊可由一基底金屬層形成，且美 底金屬層可藉由依序沉積鈦(Tl)、摩)以及銅(cu)而形^ 基底金屬層可形成為仏3至3_之厚度。 本發明另-方面提供—種製造多層佈線板之方法，包 11 200845865 二·=成一多層佈線板主體，其包含第一導電結構與第〜 且第—絕緣結構包圍第-導電結構以暴露第〜 =電、、、°構之一部份；形成一光阻層於多層佈線板主體之兩 上；曝光及顯影光阻層以形成一光阻保護層於第一導 y構之輸出墊上；於光_護層戦的狀訂，形成— 搂γΓ緣結構；以及移除光_護層並形成—第二導電处 構於苐_導電結構之輸出墊上。 ° 光阻層可利用光學微影技術形成。· 光阻層可沉積為30至50微米（㈣之厚度。 光阻ίίΐίΓ層之步驟’可施加一黏著增強劑，其增永 先層與夕層佈線板主體間之黏著強度。 至50//m之厚度 光阻保護層可沉積為30 光阻保護層可形成為具有大於 之直徑。 ' 第一 導電結構之輸出墊 第二絕緣結構可形成為G.3至3⑽之厚度。 光阻保賴可_轨瓣設備移除。 12 200845865 第—導電結構可於移除光轉護層之後碱，並形成 基底金屬層。 基底金屬層可藉由依序沉積鈦㈤、把㈣以及銅(Cu) 而形成為約〇·3至3//m之厚度。 /A第—導電結構可藉由依序電鑛銅(Cu)、鎳(Ni)以及金 (Au)而形成。 【實施方式】 、，本务明上述及其他目的、特徵與優點配合圖式與以下 詳細說明將更加鮮明。 爾後，本發明組態將參考伴隨圖式說明。 於圖式巾類似的參考符號表示類似的元件，且此類 元件將僅說明一次。 、 圖3為根據本發明示範性實施例之薄膜陶究多層佈線 板之截面圖。 如圖3所示，根據本發明示範性實施例之薄膜陶瓷多 層佈線板^含：—第—導電結構1與包圍第-導電結構1 之-第-絕緣結構2，兩者構成—多層佈線板主體；包圍 第-絕緣結構2之—第二絕緣結構3 ;以及形成於第一導 13 200845865 迅名。構1之一輸出墊上之一第二導電結構4。於此，第二 導電結構4藉由選擇性電鍍銅(Cu)、鎳(Ni)、以及金(Au) 而形成。 此外，第二導電結構4形成於第一導電結構1之輸出 墊上係大於第一導電結構之直徑(見圖9)。 (:)2 is a cross-sectional view of a multilayer wiring board disclosed in the patent publication. For example, the multilayer wiring board includes the reinforced wirings sequentially stacked from bottom to top, the first insulating layer 104, the interconnect 105, the second insulating layer, the interconnect (10), the third insulating layer 107, the interconnect 110, The fourth insulating layer 1〇9, and the interconnect 112. Solder_102 is formed on the surface under the resistance of the first insulating layer' and solder._12 is formed on the upper surface of the fourth insulating layer 1G9. The insulating layers 104, 106, 107, and _ of 1 are formed of a thermosetting epoxy resin. The interconnection 1G5 is composed of a damaging plug 1G5a marriage = 5b. The via plug portion 1A is formed in the opening formed in the first insulating layer' and the pattern interconnect portion 1G5b is formed on the upper surface of the first insulating layer 4. The technique disclosed in the above patent publication has the following disadvantages: the manufacturing method I is complicated, and it is difficult to implement it in a high-density wiring board. This is because the screen printing process technology makes the second insulating structure not cover the output pad of the first structure in the first insulating structure, and the formed second conductive structure connects the output to the tenth to form the second insulating by the plasma spraying method. The structure is configured to completely cover the insulating structure and the second conductive structure and has a thickness of Q1mm to 1Q_, and the two surfaces of the second insulating structure are sequentially laminated (laPPed) to expose the output pad of the first conductive structure. Here, according to the second conductive structure and the lap joint condition, the thickness and insulation characteristics of the lapped second insulating structure may vary, and additional process management is required to maintain stable quality. In addition, after the lap process is completed, the thin film conductive structure is again formed on the exposed second conductive structure, thus making the manufacturing process more complicated. SUMMARY OF THE INVENTION The present invention is to solve the above problems, and one of the objects of the present invention is to provide a thin film ceramic multilayer wiring board, which is suitable for miniaturization, multi-functionalization, grouping, and when developing mobile communication technology. High-frequency ^ 'and its miscellaneous secrets, especially money (four) _ f (such as gas or strong alkaline substances (such as potassium hydroxide (koh) 'while providing the method of manufacturing this film ceramic multilayer board. The illusion order can be easily implemented and the fineness of the ❹ ❹ ❹ layer wiring board and its manufacturing method can obtain the following effects. Structure 2: square 2 connection first conductive structure and second conductive: conductive structure can be easily implemented '二ΐ has the electrical structure of the first degree., 图木, and 忐 easily reach the high accumulation 10 200845865 In addition, using physical deposition methods, such as electron beam or sputtering, the second insulation structure composed of alumina contains substance The first insulating structure of the cerium oxide is exposed, so that the first insulating structure is not exposed to a strong acid substance (for example, hydrofluoric acid (HF)) or a strong alkali substance (for example, potassium hydroxide (K〇H)). Manufacturing A chemically resistant ceramic multilayer wiring board. In order to achieve the above object, the present invention provides a thin film ceramic multilayer wiring board comprising: a first conductive structure and a first insulating structure surrounding the first conductive structure, The two constitute a multi-layer wiring board main body, a second insulating structure of the insulating structure, and a second conductive structure formed on the second surface. Here, the second conductive structural electric copper (Cu), Nickel (four), and gold (Au) are formed. The second conductive structure may be formed on the output pad of the first conductive structure, having a diameter larger than the output pad of the first conductive structure. The second insulating structure may be formed as G.3 To the thickness of 3 / / m. The output pad of the first conductive structure can be formed by a base metal layer, and the bottom metal layer can be formed by sequentially depositing titanium (Tl), aluminum, and copper (cu) It can be formed into a thickness of 仏3 to 3_. Another aspect of the present invention provides a method for manufacturing a multilayer wiring board, package 11 200845865 2·= into a multilayer wiring board main body, which comprises a first conductive structure and a first and a first An insulating structure surrounds the first conductive structure to expose a part of the first layer of the plurality of wiring boards; a photoresist layer is exposed and developed to form a photoresist layer on the output pad of the first conductive structure In the shape of the light _ 护 layer, forming a 搂 Γ Γ edge structure; and removing the light _ sheath and forming - the second conductive structure is formed on the output pad of the 苐 _ conductive structure. ° The photoresist layer can utilize optical micro The formation of the shadow technology. The photoresist layer can be deposited to a thickness of 30 to 50 microns ((4). The step of the photoresist layer can be applied with an adhesion enhancer which increases the adhesion strength between the first layer and the main layer of the wiring board. The photoresist protective layer to a thickness of 50/m may be deposited as 30. The photoresist layer may be formed to have a diameter greater than that. 'The output pad of the first conductive structure The second insulating structure may be formed to a thickness of G.3 to 3(10). The photoresist can be removed from the rail device. 12 200845865 The first conductive structure can be used to remove the base after the light transfer layer and form a base metal layer. The base metal layer can be formed to a thickness of about 〇3 to 3/m by sequentially depositing titanium (f), (iv), and copper (Cu). The /A first-conducting structure can be formed by sequentially electroplating copper (Cu), nickel (Ni), and gold (Au). [Embodiment] The above and other objects, features and advantages of the present invention will become more apparent. Hereinafter, the configuration of the present invention will be described with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements, and such elements will be described only once. 3 is a cross-sectional view of a thin film multilayer wiring board in accordance with an exemplary embodiment of the present invention. As shown in FIG. 3, a thin film ceramic multilayer wiring board according to an exemplary embodiment of the present invention includes: a first conductive structure 1 and a first insulating structure 2 surrounding the first conductive structure 1, which constitute a multilayer wiring board a body; a second insulating structure 3 surrounding the first insulating structure 2; and a first name formed in the first lead 13 200845865. One of the output pads 1 is one of the second conductive structures 4 on the pad. Here, the second conductive structure 4 is formed by selectively electroplating copper (Cu), nickel (Ni), and gold (Au). Further, the second conductive structure 4 is formed on the output pad of the first conductive structure 1 to be larger than the diameter of the first conductive structure (see Fig. 9). (:)
再者，於根據本發明示範性實施例之薄膜陶瓷多層佈 線板中，第二絕緣結構3形成為〇·3至3#m之厚度。 此外，如圖9所示，第一導電結構1之輸出墊由一基 底金屬層碱，其储由依序賴鈦(Ή)、婦邮及銅㈣ 而形成，且可具有約〇·3至3之厚度。 製造如圖3所示之薄膜陶竟多層佈線板之程序將參考 圖4至14於下描述。 溽膜闹瓷多層佈線板係藉由以下程序形成：製 造生片（green sheets)，形成介層洞於生片，以金屬填夷^ ^洞，印刷導線圖案於設計的生片上，_加熱與加^層 ，其上印刷有導電圖案之生片，於設計的溫度同時塑形層 疊的生片’且研磨設計多層佈線板之兩表面以調^ 該板的平坦度與厚度。透過此程序，可得到如圖4所示晨 露第-導電結構〗之輸出墊5之結構。由於此程序採用: 習知相同的技術，將省略此程序的詳細說明。換言之，圖 14 200845865 2所不之絕緣層與互連可輕易由已知技術形成。於此，個 別的生片與介相可麵鱗_導電結構卜而為個別互 連形成的絕緣層可絲為第—絕緣結構2。本發明之薄膜 陶瓷佈線板並不限於圖4所示的三層結構。 、 …d而根據本發明’第_絕緣結構2並不暴露於例如 ^酸(HF)之強酸物質或例如氫氧化娜〇h)之強驗物 貝。在沉積可抗此類化學物之第二絕緣結構3前，利用半 ‘體製私所帛之絲微影方法沉積乾絲劑(_出坤為 至50#m之厚度，如圖5所示，因而形成光阻層&。光 阻層6利用—般層疊設備堆疊於該板的兩表面。 、:後，曝光與顯影光阻層6以具有如圖6所示之圖案。 尤其疋’具有厚度約3〇至5Q//m之細保護層7形成於 該板的兩表面，使得第二絕緣結構3不覆蓋第-導電結構 1之輸出墊5。 於，，為增加乾感光劑之沉積層6與陶瓷多層佈線板 間之，著強度，可使用黏著增強劑。光阻保護層7之直徑 大於第―導電結構1之輸岭5之直徑。 土接著，於光阻保護層7形成的狀態下，利用如物理沉 知技術之電子束真空沉積或錢鍍技術，形成具冑0.3至3 厚度之第二絕緣結構3，如圖7所示。 15 200845865 兩表面之輸出墊5 接著，利用光阻剝除設備移除光阻保護層7，如圖8 所示。於此，可同時地且輕祕就暴露於第_導電結構工 〃本發明細製程技術，且免除習知網板印刷方法开 第二導電結構4之程序與依序搭接第三_結構3兩表面 以暴露第二導電結構4之程序，因而簡化程序。尤其是，Furthermore, in the thin film ceramic multilayer wiring board according to an exemplary embodiment of the present invention, the second insulating structure 3 is formed to have a thickness of 〇3 to 3#m. In addition, as shown in FIG. 9, the output pad of the first conductive structure 1 is formed of a base metal layer alkali, and the storage is formed by sequential titanium (Ή), Fu Mail, and copper (4), and may have about 〇·3 to 3 The thickness. The procedure for manufacturing a thin-film ceramic multilayer board as shown in Fig. 3 will be described below with reference to Figs. The enamel film multi-layer wiring board is formed by the following procedures: manufacturing green sheets, forming a layer of holes in the green sheets, filling the holes with metal, and printing the conductive patterns on the designed green sheets, _heating and A layer is formed on which a green sheet of a conductive pattern is printed, and the laminated green sheets are simultaneously molded at a design temperature and both surfaces of the multilayer wiring board are ground to adjust the flatness and thickness of the board. Through this procedure, the structure of the output pad 5 of the morning-first conductive structure shown in Fig. 4 can be obtained. Since this procedure uses the same techniques as the prior art, a detailed description of this procedure will be omitted. In other words, the insulating layers and interconnections of Figure 14 200845865 2 can be easily formed by known techniques. Herein, the individual green sheets and the dielectric layers may be surface-type conductive structures, and the insulating layers formed by the individual interconnections may be the first insulating structure 2. The thin film ceramic wiring board of the present invention is not limited to the three-layer structure shown in Fig. 4. And d according to the present invention, the first insulating structure 2 is not exposed to a strong acid such as acid (HF) or a strong analyte such as hydrazine hydride. Before depositing the second insulating structure 3 which is resistant to such chemicals, the dry silking agent is deposited by a semi-institutional private silk lithography method (the thickness is up to 50#m, as shown in FIG. 5, Thus, a photoresist layer is formed. The photoresist layer 6 is stacked on both surfaces of the board by a general lamination apparatus. After that, the photoresist layer 6 is exposed and developed to have a pattern as shown in FIG. 6. A thin protective layer 7 having a thickness of about 3 〇 to 5 Q//m is formed on both surfaces of the board such that the second insulating structure 3 does not cover the output pad 5 of the first conductive structure 1. Therefore, in order to increase the sink of the dry sensitizer The adhesion between the laminate 6 and the ceramic multilayer wiring board can be increased by using an adhesion enhancer. The diameter of the photoresist layer 7 is larger than the diameter of the ridge 5 of the first conductive structure 1. The soil is then formed on the photoresist layer 7. In the state, a second insulating structure 3 having a thickness of 0.3 to 3 is formed by electron beam vacuum deposition or money plating technique such as physical deposition technology, as shown in Fig. 7. 15 200845865 Two-surface output pad 5 Next, use The photoresist stripping device removes the photoresist protection layer 7, as shown in Fig. 8. Here, at the same time, simultaneously Lightly secreted to the first conductive structure of the present invention, and the conventional screen printing method is omitted to open the second conductive structure 4 and sequentially overlap the third surface of the third structure to expose the second conductive The procedure of Structure 4, thus simplifying the program. In particular,
因為第二導電結構4的輸出塾不是_網板印刷=形 成，而使紐集歧計絲可能，且謂造絲集薄膜陶 甍多層佈線板。 接著，依據圖9至14完成圖3所示之薄膜佈線板。 尤其是參考圖9 ’形成薄膜互連之基底金屬層8。利用 如物理沉積技術之濺鍍技術，於高真空反應室，形成基底 金屬層8於該板的兩整個表面，其係於兩表面藉由依^沉 積基底金屬如鈦(Ti)、鈀(Pd)以及銅(Cu)而形成且厚度約α5 βτη〇 而後如圖10與11所示，感光劑沉積於該板的兩表面， 且利用曝光與顯影程序形成互連與墊。 而後如圖12所示，利用電鍍方法依序沉積銅(Cu)、鎳 (Ni)以及金(Au)而形成墊。 16 ♦200845865 圖13顯示移除感光劑後之程序，且參考圖μ，依序 蝕刻由Cu、Pd與Ti形成之非必要基底金屬層。 藉由上述程序，完成了如圖3所示之第二導電結構4。 根據本發明所示之薄膜陶瓷多層佈線板，利用光學微 影方法選擇性沉積第二絕緣結構3為〇·3至3 # m之厚度， 因而免除額外的搭接程序。此外，因為第二導電結構4是 利用薄膜墊形哞製程而非網板印刷方法之墊形成製程來形 成，可簡化整個程序且亦可設計高積集佈線板。再者，具 有，佳導電率之銀(Ag)或銅(Cu)用以作為陶瓷多層佈線板 之導電結構，使該板尤其適用於高頻與高積極度。 本發明可刺於適於作為探針卡的高積集多層佈線板 之，膜陶舒層佈線板，探針卡係測試行動通訊、微波連 接态、纜線組件、半導體晶片等之高頻模組。 ^雖然本發明以參照特定示範性實施例說明與顯示，然 =熟此技術領域者應明瞭在不悖離本發明申請專利範圍界 定之精神與範疇下可有各種修改及變化。 【圖式簡單說明】 圖1為習知多層佈線板之截面圖； 圖2為另一習知多層佈線板之截面圖； 圖3為根擄本發明示範性實施例之薄膜陶瓷多層佈線 200845865 板之截面圖；以及 圖4至14為根據本發明示範性實施例顯示製造圖3 所示之薄膜陶瓷多層佈線板之方法之截面圖。 【主要元件符號說明】 1第一導電結構 2第一絕緣結構 3第二絕緣結構 (4第二導電結構 5輸出墊 6光阻層 7光阻保護層 8基底金屬層 10 導電圖案 20 導電接觸 100 .第一導電結構 101 第一導電結構之部份 102、102A 焊料阻劑 103 強化佈線層 104 第一絕緣層 105 互連 105a介層栓塞部 105b圖案互連部 106 第二絕緣層 107 第三絕緣層 18 200845865 108、108a、108b 互連 109 第四絕緣層 110、110a、110b 互連 112、112a、112b 互連 120、120A 焊料阻劑 200 第一絕緣結構 300 第二導電結構 400 第二絕緣結構 500 導電塗佈膜 1000、1000a 多層佈線板主體Since the output of the second conductive structure 4 is not formed by the stencil printing, it is possible to make the dynamometer wire, and the wire-forming film is a multilayer wiring board. Next, the film wiring board shown in Fig. 3 is completed in accordance with Figs. In particular, the base metal layer 8 forming the thin film interconnection is formed with reference to Fig. 9'. Using a sputtering technique such as physical deposition technique, a base metal layer 8 is formed on both surfaces of the plate in a high vacuum reaction chamber, which is deposited on both surfaces by depositing a base metal such as titanium (Ti) or palladium (Pd). And copper (Cu) is formed and has a thickness of about α5 βτη〇 and then as shown in FIGS. 10 and 11, a sensitizer is deposited on both surfaces of the board, and interconnects and pads are formed by exposure and development processes. Then, as shown in Fig. 12, copper (Cu), nickel (Ni), and gold (Au) are sequentially deposited by a plating method to form a pad. 16 ♦ 200845865 Figure 13 shows the procedure after removal of the sensitizer, and with reference to Figure μ, the unnecessary underlying metal layers formed of Cu, Pd and Ti are sequentially etched. By the above procedure, the second conductive structure 4 as shown in FIG. 3 is completed. According to the thin film ceramic multilayer wiring board shown in the present invention, the second insulating structure 3 is selectively deposited by the optical lithography method to a thickness of 〇·3 to 3 # m, thereby eliminating an extra lap process. Further, since the second conductive structure 4 is formed by a pad forming process using a film pad type process instead of the screen printing method, the entire process can be simplified and a high build wiring board can also be designed. Further, silver (Ag) or copper (Cu) having good conductivity is used as the conductive structure of the ceramic multilayer wiring board, making the board particularly suitable for high frequency and high positivity. The invention can be used for the high-accumulation multi-layer wiring board which is suitable as a probe card, the membrane ceramic layer wiring board, the probe card is a high-frequency module for testing mobile communication, microwave connection state, cable assembly, semiconductor wafer and the like. While the invention has been shown and described with reference to the specific embodiments of the embodiments of the present invention, it will be understood that various modifications and changes can be made without departing from the spirit and scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view of a conventional multilayer wiring board; FIG. 2 is a cross-sectional view of another conventional multilayer wiring board; FIG. 3 is a thin film ceramic multilayer wiring 200845865 board according to an exemplary embodiment of the present invention. FIG. 4 to FIG. 14 are cross-sectional views showing a method of manufacturing the thin film ceramic multilayer wiring board shown in FIG. 3 according to an exemplary embodiment of the present invention. [Main component symbol description] 1 first conductive structure 2 first insulating structure 3 second insulating structure (4 second conductive structure 5 output pad 6 photoresist layer 7 photoresist protective layer 8 base metal layer 10 conductive pattern 20 conductive contact 100 The first conductive structure 101 is a portion of the first conductive structure 102, 102A, the solder resist 103, the reinforcing wiring layer 104, the first insulating layer 105, the interconnect 105a, the via plug portion 105b, the pattern interconnect portion 106, the second insulating layer 107, the third insulating layer. Layer 18 200845865 108, 108a, 108b interconnect 109 fourth insulating layer 110, 110a, 110b interconnect 112, 112a, 112b interconnect 120, 120A solder resist 200 first insulating structure 300 second conductive structure 400 second insulating structure 500 conductive coating film 1000, 1000a multilayer wiring board main body