200832680 • Δ1 /UOLWI.uOC/006 九、發明説明： 【發明所屬之技術領域】 本發明是有關於一種半導體裝置及其製造方法，且特 別疋有關於一種電阻式隨機存取記憶體（resistanCe ran(J〇ni access memory，RRAM)裝置及其製造方法。 【先前技術】200832680 • Δ1 /UOLWI.uOC/006 IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor device and a method of fabricating the same, and in particular to a resistive random access memory (resistCe ran (J〇ni access memory, RRAM) device and method of manufacturing the same. [Prior Art]
RRAM疋使用電阻特性根據外界影響而變化的材料 的圮fe裝置。由於電源斷開後電阻不變，所以是非 揮發性（non-volatile)記憶裝置。 跟其他記憶裝置—樣的是，RRAM包括多個記憶胞 (me腑ycell)，每個記憶胞耦接至一條字元線（—he) 與-條位兀線（bit line)。RRAM胞可包括—底電極（b〇tt〇m 用於位元線連接；一頂電極（邮咖伽屻， 於子兀線連接；以及—電阻膜（resistive film)，作為底 (variaWe --,.;;it* r；r:^ (resistance-determined st n 夕 私阻預疋狀態 元資料。為了具有多重電胞中儲存多位 電阻值以使得此記憶體可具有更要提供高RRAM疋 uses a material whose resistance characteristics vary according to external influences. It is a non-volatile memory device because the resistance does not change after the power is turned off. As with other memory devices, the RRAM includes a plurality of memory cells, each of which is coupled to a word line (-he) and a bit line. The RRAM cell may include a bottom electrode (b〇tt〇m for bit line connection; a top electrode (postal gamma, connected to the sub-wire; and a resistive film) as the bottom (variaWe) ,.;;it* r;r:^ (resistance-determined st n). In order to have multiple resistance values stored in multiple cells, this memory can have a higher supply.
Wrmd〇W)來執行多位元記憶操作。 自（〇Peratl〇n 【發明内容】 本發明的-範例提供一種記憶體，這種記憶體包括第 5 200832680 j..vJ〇C/〇〇6 位;第二方向上的多條位元線，每條 接取少—條字元線；以及多個記憶 ^己^元件耗接到—條字蠄一 — 包括-頂電極，連接;=元線。每個記憶元件 對應的位元線;—t二應-底電極，連接到 :;)電極=:端具有電—^Wrmd〇W) to perform multi-bit memory operations. The present invention provides a memory including a 5th 200832680 j..vJ〇C/〇〇6 bit; a plurality of bit lines in the second direction; Each of the pick-ups is less than a word line; and a plurality of memory elements are consumed by the ------including the top electrode, the connection; = the element line; the bit line corresponding to each memory element; —t二应—bottom electrode, connected to:;) electrode=: terminal has electricity—^
例^ ’―種製造記憶體的方法包括提供第— Μ心夕條字元線；提供第二方向上的多條位元線；形 成了、電極以連铜對應的字元線；形成底電_連接對應 的位碰；在底電極上形成電阻層；以及形成至少兩個^ 立的襯墊’每個襯㈣兩端具有電阻材料，且每個襯塾輕 接於頂電極與電阻層之間。 、本發明的另一範例提供一種製造記憶體的方法，這種 方法包括提供第H的多條字元線；提供第二方向上 的多條位元線；形成底電極；在此底電極上沈積氧化層； 在此氧化層上形成絕緣層；圖案化（pattern)此絕緣層、 氧化層以及底電極，從而使底電極的一部分不被覆蓋，且 氧化層的側面被曝露；在未覆蓋的底電極上以及沿著氧化 層之曝露侧面形成兩個獨立的襯墊；在每個襯墊的兩端形 成％阻材料，以及在未覆蓋的底電極上形成電阻層。 為讓本發明之上述特徵和優點能更明顯易懂，下文特 舉實施例，並配合所附圖式，作詳細說明如下。 【實施方式】 200832680 zi/uorwi.aoc/006 請參照圖1，記憶胞100可形成於積體電路基底 (integrated circuit substrate) 102 上。此記憶胞 可包 括一底電極104與一頂電極106。電阻層ι36形成於底電 極104的部分上。在底電極104與頂電極1〇6之間，有一 氧化層108與一電阻結構。此電阻結構可包括兩個l形襯 墊120，這兩個L形襯墊120被氧化層114以及一金屬或 金屬氧化材料的層112隔開。每個L形概塾12〇可包括第 一氧化襯墊122、金屬襯墊124以及第二氧化襯墊126。每 個L形概墊120的金屬概墊124具有兩個電阻端132及 134’母個電阻端132或134既可以由相同的電阻材料製成 也可以由不同的電阻材料製成。 電阻材料可包括硫屬化物合金（chalc〇genide all〇y) 材料、磁阻（magnetroresistive )材料以及聚合物（p〇lymer ) 材料。利用加熱，硫屬化物合金材料可在晶態（crystamne state )與非晶態（amorphous state )之間變化。在高溫下， 例如超過60(TC，此硫屬化物變為液體。一旦冷卻下來， 則凝固成非晶玻璃態（amorphous glass_like state)，且其 電阻很高。另一方面，藉由將此硫屬化物加熱至其結晶點 (crystallization point)與其熔點（mdtingp〇int)之間的 溫度，此硫屬化物可轉變為具有相當低電阻的晶態。由於 硫屬化物合金材料的晶態與非晶態可根據其不同的電阻值 來進行_，所以就形成了資料被儲存的基礎。舉例來說， 非晶態、高阻態可用來表示二進位〗，且日日日態、低阻態表 不二進位〇。硫屬化物合金材料可由鍺（germanhim)、銻 7 200832680 217U6twt.doc/006 (antimony)以及碲（tellurium)混合而成，又稱為GST。 硫屬化物合金材料可在1 mTorr到100 mTorr的壓力下利 用活性氣體（例如Αγ、Ν2或He)藉由物理氣相沈積（physical vapor deposition，PVD)濺鏡（sputtering)或磁控錢鏡 (magnetron-sputtering)法經沈積而形成。此沈積過程可 在室溫下執行。高寬比（aSpect ratio)為1到5的準直儀 (collimator)可用來改善瑱入（flll-in)性能。此外，要 改善填入性能，也可使用數十伏特至數百伏特的直流偏壓 (DC bias)。利用真空或％環境進行後期沈積退火 (annealing)處理可改善硫屬化物合金材料的晶化狀態。 退火處理的溫度可介於l〇〇°C至40CTC範圍内，時間短於 30分鐘。 應用磁場，磁阻材料可具有可變的磁化方向。由於磁 穿隧效應（magnetic tunnel effect )，磁阻材料的電阻根據 磁化方向而變化。因此，使用這種材料的記憶胞可藉由磁 化狀態來儲存資料，且儲存於其中的資料可藉由測量此胞 的阻末感測。磁阻材料可包括巨磁阻式（c〇l〇ssal magnet〇 resistive, CMR)薄膜以及具有鈣鈦礦結構（Per〇vskite structure)的氧化薄膜。CMR薄膜可在1 mT〇rr到1〇〇 mT〇rr 的壓力下利用活性氣體（例如Ar、N2、〇2或He)藉由pVD ’賤鍍或磁控錢鍍法而形成。根據後期沈積處理條件，沈積 溫度可介於室溫到60(TC範圍内。高寬比為i到5的準直 儀可改善填入性能。此外，數十伏特到數百伏特的直流偏 壓也可用來改善填入性能。再者，可施加數十高斯（gauss) 8 200832680 二 1 / w^wjL.doc/006 到特斯拉（Tesla)的磁場來改善磁晶化狀態。利用真空或 N2環境或02/N2混合環境執行後期沈積退火處理可改善 CMR材料的晶化狀態。此外，在CMR材料沈積之前，可 沈積厚度為30 nm到200 nm的YBaCu03缓衝層（buffer layer)，以改善CMR材料的晶化。同樣地，具有舞鈦礦 結構的氧化薄膜可藉由上述的相同方法沈積而成，或者藉 由以下所述的氧化過程而形成。 0 應用電場’聚合物材料可具有可變的極化狀態 (polarization state)。由於聚合物的電阻是根據此聚合物 的極化導向而變化，所以使用聚合物材料的記憶胞中儲存 的資料可藉由測量此胞的電阻來感測。聚合物材料可包括 四氰基對醌二甲烷（tetracyanoquinodimethane，TCNQ)或 [6,6]_本基 C61 丁酸甲酯（[6,6]-phenyl C61_butyric acid methyl ester，PCBM)。聚合物材料可藉由熱蒸發（thermal evaporation)、電子束蒸發（e_beam evap〇rati〇n)或分子 束磊晶（molecular beam epitaxy，MBE )蒸發而形成。固態 肇 TCNQ與球狀摻雜物被放入一個反應室一起蒸發，並且混 合沈積在晶圓（wafer)上。此過程可能沒有化學反應或氣 體，沈積過程可在1〇_4 Torr到HM0 Torr的壓力下執行， 晶圓度可介於室溫到2〇〇它範圍内。利用真空或n2環境 進行後期沈積退火處理可改善聚合物材料的成分。退火處 理的溫度可介於室溫到3〇〇ΐ範圍内，時間短於1小時。 此外，聚合物材料可藉由以小於1〇〇 _的轉速來旋塗 (SpinC〇ating)摻有雜質的TCNQ溶液而形成。 200832680 # wtvyj..d〇C/006 圖2至圖7是-種非揮發性記憶胞的截面圖，纷示為 製造圖1所示之§己憶胞的示範性方法。請參照圖2，導電 材料沈積在基底102上，且經圖案化以形成底電極綱屯 以用於位it線連接。在-範例中，此導電材料是可被氧化 的金屬’例如A1、W、Ti、Ni或Cu。然後執行金屬間電 介質沈積’以藉由化學機械平坦化（chemical職㈣㈤ planarization)來用一層氧化層1〇8覆蓋底電極ι〇4。隨後 -絕緣材料層202形成於氧化層⑽上，例如在—範例中 此絕緣材料為氮化⑨。圖2所示之結構是藉由蒸發來圖幸 化以形成圖3所示之結構，在圖3所示之結構中底電極刚 的部分沒被覆蓋，且氧化们〇8的側面被曝露。 irvi 〇月參,Ί4 ’藉由氧化概墊沈積，於未覆蓋的底電極 “上且沿著氧化層108的曝露側面形成氧化概塾122。接 Ϊ 行金屬襯墊沈積’以在氧化襯墊122上形成金屬襯 ϋ例巾’此金屬缝是由可被氧化的金屬（例 =、；"、Τί、Μ或㈤製成。然後藉由另-氧化襯墊 ^積，在此金屬襯塾124上形成第二氧化襯塾126。隨後， =irrUblanket etehing)蒸發，以形成l形襯墊 120的結構。 明’、、\圖5 ’在每個金屬襯墊124的兩端以及底電極 帝士的未伋盍邛分上形成電阻材料。在金屬襯墊I%及底 =刚是由被氧化的金屬所製成的範例中，金屬的表面 二在電阻端132及134兩端形成金屬氧化物，且 在未復盍的底電極1G4上形成金屬氧化層（電阻層136)。 200832680 zi /uoiwi.uoc/006 氧化過程可在幾mTorr的壓力到i個大氣壓下利用純〇2 或N2/〇2混合氣體，藉由例如溫度介於2〇〇〇c到7〇〇。〇範圍 内的熱氧化來完成。氧化過程的另一範例是電漿氧化 (plasma oxidation)。在電漿氧化中，在 i mT〇rr 到 1〇〇 =Τ〇π^的壓力下，利用純a或Αγ/〇2混合氣體或Ar/N2/〇2 混合，體，射頻（RadioFreqency’RF)或直流電源電漿可 用來氧化金屬表面。根據電漿氧化的程度，氧化溫度可介 於室溫到300°C範圍内。 請參照圖6，一金屬層或金屬氧化物的層112沈積在 金，氧化層（電阻層136)上。然後藉由化學機械平坦化， 一氧化層114形成於層112上。接著，可藉由習知的氧化 CMP (平坦化氧化層114、氧化層，然後是被清除的金屬 概塾U4)來清除絕緣層（氧化襯墊122)及金屬襯墊 的電阻端132。 請參照圖7，可再次執行氧化過程，以在每個金屬槪 124的電阻端132形成金屬氧化物。由於氧化過程是在 不同的環境中進行，所以電阻端132的金屬氧化物的特性 了不同於電阻端134的金屬氧化物的特性。然後，導電材 料（例如金屬材料）可沈積在圖7所示之結構上來連接字 元線以形成圖1所示之結構。 ♦利用圖1所示之結構，每個電阻端132與134形成— =器（R132’R134)，此電阻器由於面積小，所以可提 =向電阻。此電阻器R132及R134相互串聯，合起來鱼另 —對電阻器R132及R134並聯。此外，電阻層136也形 11 200832680 i〇c/〇〇6 一電阻器R136，與電阻器R132及R134之組合串聯。如 果層Π2是由電阻材料製成，那麼此層n2也可提供—電 阻器Rl12，此電阻器R112串聯於電阻器R136與電阻= R132及R134組合之間。由於電阻端132及134的面積非 =小，所以它們可提供高電阻，這樣則導致更多的操^视 窗來執行多位元記憶體讀與寫操作。Example ^ 'The method for manufacturing a memory includes providing a first-to-be-shaped word line; providing a plurality of bit lines in the second direction; forming a word line corresponding to the copper with the electrode; forming the bottom electricity _ connecting the corresponding bit bump; forming a resistive layer on the bottom electrode; and forming at least two spacers' each of the linings (four) having a resistive material at both ends, and each lining is lightly connected to the top electrode and the resistive layer between. Another example of the present invention provides a method of fabricating a memory, the method comprising: providing a plurality of word lines of a Hth; providing a plurality of bit lines in a second direction; forming a bottom electrode; and forming a bottom electrode thereon Depositing an oxide layer; forming an insulating layer on the oxide layer; patterning the insulating layer, the oxide layer, and the bottom electrode such that a portion of the bottom electrode is not covered and the side of the oxide layer is exposed; Two separate pads are formed on the bottom electrode and along the exposed side of the oxide layer; a % resist material is formed on both ends of each pad, and a resistive layer is formed on the uncovered bottom electrode. The above described features and advantages of the present invention will be more apparent from the following description. [Embodiment] 200832680 zi/uorwi.aoc/006 Referring to FIG. 1, a memory cell 100 may be formed on an integrated circuit substrate 102. The memory cell can include a bottom electrode 104 and a top electrode 106. A resistive layer ι36 is formed on a portion of the bottom electrode 104. Between the bottom electrode 104 and the top electrode 1?6, there is an oxide layer 108 and a resistor structure. The resistive structure can include two l-shaped pads 120 separated by an oxide layer 114 and a layer 112 of metal or metal oxide material. Each L-shaped profile 12 can include a first oxidized liner 122, a metal liner 124, and a second oxidized liner 126. The metal pad 124 of each L-shaped pad 120 has two resistor ends 132 and 134'. The female resistor terminals 132 or 134 may be made of the same resistive material or of different resistive materials. The resistive material may include a chalcantium alloy (chalc〇genide all〇y) material, a magnetoresistive material, and a polymer (p〇lymer) material. With heating, the chalcogenide alloy material can vary between a crystalline state (crystamne state) and an amorphous state. At high temperatures, for example, more than 60 (TC, this chalcogenide becomes a liquid. Once cooled, it solidifies into an amorphous glass_like state, and its electrical resistance is high. On the other hand, by this sulfur The genus is heated to a temperature between its crystallization point and its melting point, which can be converted into a crystalline state with a relatively low electrical resistance. Due to the crystalline and amorphous state of the chalcogenide alloy material The state can be based on its different resistance values, so the basis for storing the data is formed. For example, the amorphous state and the high resistance state can be used to represent the binary, and the daily and low resistance states. The chalcogenide alloy material can be a mixture of germanium, 锑7 200832680 217U6twt.doc/006 (antimony) and tellurium, also known as GST. Chalcogenide alloy material can be used at 1 mTorr Deposition by reactive vapor deposition (PVD) sputtering or magnetron-sputtering using a reactive gas (eg, Αγ, Ν2, or He) to a pressure of 100 mTorr This deposition process can be performed at room temperature. A collimator with an aspect ratio of 1 to 5 can be used to improve the inflection (flll-in) performance. In addition, to improve the filling performance, A DC bias of tens of volts to hundreds of volts can also be used. Post-deposition annealing treatment using vacuum or % environment can improve the crystallization state of the chalcogenide alloy material. In the range of l〇〇°C to 40CTC, the time is shorter than 30 minutes. With the magnetic field, the magnetoresistive material can have a variable magnetization direction. Due to the magnetic tunnel effect, the resistance of the magnetoresistive material depends on the magnetization direction. Therefore, the memory cell using the material can store data by the magnetization state, and the data stored therein can be measured by measuring the end of the cell. The magnetoresistive material can include giant magnetoresistance (c 〇l〇ssal magnet〇resistive, CMR) films and oxide films with a perovskite structure. CMR films can utilize reactive gases at pressures from 1 mT〇rr to 1〇〇mT〇rr (eg Ar N2, 〇2 or He) is formed by pVD '贱 plating or magnetron plating. According to the post-deposition treatment conditions, the deposition temperature can be from room temperature to 60 (TC range). The aspect ratio is i to 5. The collimator improves the filling performance. In addition, DC bias voltages of tens of volts to hundreds of volts can also be used to improve fill performance. Furthermore, a magnetic field of tens of gauss 8 200832680 2 1 / w^wjL.doc/006 to Tesla can be applied to improve the magnetic crystallization state. Performing post-deposition annealing treatment in a vacuum or N2 environment or a 02/N2 mixed environment improves the crystallization state of the CMR material. In addition, a YBaCu03 buffer layer with a thickness of 30 nm to 200 nm can be deposited to improve the crystallization of the CMR material prior to deposition of the CMR material. Similarly, an oxide film having a spectacles structure can be deposited by the same method as described above or by an oxidation process as described below. 0 Applying an electric field 'Polymer material can have a variable polarization state. Since the electrical resistance of the polymer varies depending on the polarization orientation of the polymer, the data stored in the memory cell using the polymeric material can be sensed by measuring the electrical resistance of the cell. The polymeric material may include tetracyanoquinodimethane (TCNQ) or [6,6]-phenyl C61_butyric acid methyl ester (PCBM). The polymer material can be formed by thermal evaporation, electron beam evaporation (e_beam evap〇rati〇n) or molecular beam epitaxy (MBE) evaporation. The solid state 肇 TCNQ is evaporated with a spherical dopant in a reaction chamber and mixed and deposited on a wafer. There may be no chemical reactions or gases in this process, and the deposition process can be performed at pressures from 1 〇 4 Torr to HM0 Torr, with wafers ranging from room temperature to 2 〇〇. Post-deposition annealing treatment in a vacuum or n2 environment improves the composition of the polymer material. The annealing treatment can be carried out at temperatures ranging from room temperature to 3 Torr for less than one hour. Further, the polymer material can be formed by spin-coating a TCNQ solution doped with impurities at a rotational speed of less than 1 Torr. 200832680 # wtvyj..d〇C/006 Figures 2 through 7 are cross-sectional views of a non-volatile memory cell, exemplified by an exemplary method of fabricating the § cell shown in Figure 1. Referring to Figure 2, a conductive material is deposited on substrate 102 and patterned to form a bottom electrode profile for a bit-to-wire connection. In the example, the electrically conductive material is a metal that can be oxidized, such as A1, W, Ti, Ni or Cu. Then, inter-metal dielectric deposition is performed to cover the bottom electrode ι 4 with an oxide layer 1 〇 8 by chemical mechanical planarization (chemical planarization). Subsequently, an insulating material layer 202 is formed on the oxide layer (10), for example, in the example, the insulating material is nitride 9. The structure shown in Fig. 2 is fortunate by evaporation to form the structure shown in Fig. 3. In the structure shown in Fig. 3, the portion of the bottom electrode is not covered, and the sides of the oxides 8 are exposed. Irvi 〇月参, Ί4' is deposited by oxidizing the blanket, forming an oxidation profile on the uncovered bottom electrode "and along the exposed side of the oxide layer 108. Connecting the metal liner deposition" to the oxide liner Forming a metal lining on the 122' This metal seam is made of a metal that can be oxidized (example =,; ", Τ, Μ or (5). Then the metal lining is formed by another oxidized liner. A second oxide liner 126 is formed on the crucible 124. Subsequently, =irrUblanket etehing) is evaporated to form the structure of the l-shaped liner 120. The ',, and FIG. 5' are at both ends of each metal liner 124 and the bottom electrode The resistive material is formed on the top of the emperor. In the example where the metal liner I% and the bottom = just made of oxidized metal, the surface 2 of the metal forms a metal at both ends of the resistor ends 132 and 134. Oxide, and a metal oxide layer (resistive layer 136) is formed on the unrecovered bottom electrode 1G4. 200832680 zi /uoiwi.uoc/006 The oxidation process can utilize pure 〇2 or N2 at a pressure of several mTorr to i atm. /〇2 mixed gas, for example, with a temperature ranging from 2〇〇〇c to 7〇〇. Oxidation is done. Another example of the oxidation process is plasma oxidation. In plasma oxidation, pure a or Αγ/〇 is used at a pressure of i mT〇rr to 1〇〇=Τ〇π^. 2 Mixed gas or Ar/N2/〇2 mixed, bulk, radio frequency (RadioFreqency'RF) or DC power plasma can be used to oxidize the metal surface. Depending on the degree of plasma oxidation, the oxidation temperature can range from room temperature to 300 °C. Referring to Fig. 6, a metal layer or metal oxide layer 112 is deposited on the gold, oxide layer (resistive layer 136). Then, by chemical mechanical planarization, an oxide layer 114 is formed on the layer 112. Next, The insulating layer (oxidation pad 122) and the resistance end 132 of the metal pad can be removed by conventional oxidation CMP (planarization oxide layer 114, oxide layer, and then removed metal profile U4). 7. The oxidation process can be performed again to form a metal oxide at the resistance end 132 of each of the metal crucibles 124. Since the oxidation process is performed in a different environment, the characteristics of the metal oxide of the resistance terminal 132 are different from those of the resistance end. The characteristics of the metal oxide of 134. Thereafter, a conductive material (e.g., a metal material) may be deposited on the structure shown in Fig. 7 to connect the word lines to form the structure shown in Fig. 1. ♦ With the structure shown in Fig. 1, each of the resistor terminals 132 and 134 is formed - = (R132'R134), this resistor can reduce the resistance to the resistance due to the small area. The resistors R132 and R134 are connected in series with each other, and the fish are connected in parallel to the resistors R132 and R134. In addition, the resistor layer 136 is also Shape 11 200832680 i〇c/〇〇6 A resistor R136, in series with a combination of resistors R132 and R134. If layer 2 is made of a resistive material, then this layer n2 can also be provided with a resistor Rl12, which is connected in series between resistor R136 and resistor = R132 and R134. Since the areas of the resistor terminals 132 and 134 are not = small, they provide high resistance, which results in more operation windows for performing multi-bit memory read and write operations.
雖然本發明已以實施例揭露如上，然其並非用以限定 本發明，任何所屬技術領域中具有通常知識者，在不脫離 本發明之精神和範圍内，當可作些許之更動與潤飾，因此 ^發明之保護範圍當視後附之申請專利範圍所界定者為 【圖式簡單說明】 圖1是根據本發明所提出的示範性記憶胞的截面圖。 ，圖2至圖7疋-種非揮發性記憶胞的截面圖，繪示 製造圖1所示之記憶胞的示範性 … 【主要元件符號說明】 / 100 :記憶胞 102 :基底 104 :底電極 106 :頂電極 108、114 :氧化層 112 :層 120 :襯墊 122、126 :氧化襯墊 12Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a cross-sectional view of an exemplary memory cell proposed in accordance with the present invention. FIG. 2 to FIG. 7 are cross-sectional views showing a non-volatile memory cell, and an exemplary embodiment of the memory cell shown in FIG. 1 is illustrated. [Main component symbol description] / 100: Memory cell 102: Substrate 104: Bottom electrode 106: top electrode 108, 114: oxide layer 112: layer 120: pad 122, 126: oxidized pad 12
Joc/006 200832680 124 :金屬襯墊 132、134 :電阻端 136 :電阻層 202 :絕緣材料層Joc/006 200832680 124 : Metal gasket 132, 134 : Resistor terminal 136 : Resistance layer 202 : Insulating material layer