TW200830539A - Memory device and method of operating and fabricating the same - Google Patents

Abstract

A memory transistor including a substrate, a tunnel insulating pattern on the substrate, a charge storage pattern on the tunnel insulating pattern, a blocking insulating pattern on the charge storage pattern, and a gate electrode on the blocking insulating pattern, the blocking insulating pattern surrounding the gate electrode and methods of operating and fabricating the same. A nonvolatile memory may further include a plurality of memory transistors in series and a plurality of auxiliary structures between each of the plurality of unit transistors in series. Each of the plurality of auxiliary structures may be a dummy mask pattern or an assistant gate structure.

Description

200830539 2611 Opif IX. Invention Description: This case is based on the 35U application of the US Patent Law (the case number is (10)06_0=8 t ^, claiming that the country is 3 months old) and the Korean patent application is slaughtering (Zai 2: Qingyi Mine) February 13th, 2007 - Two tigers are 〇-2〇〇7-〇01ton 9, Shen 锖 ^ ^ ^, Liang Yuanquan, all of these two Korean specialties

The content of the (1) month case is added to the case and is not redundant. I

[Technical field to which the invention pertains]

= Examples are related to material devices, such as non-volatile and lightning-sensitive semiconductor memory devices, and their operation and manufacturing methods, such as flash 3 匕丨 / 3⁄4 body.先前Previous technology] Non-volatile memory can even keep the suffocation stored in its memory during power failure. Examples include masked R〇M, EpR〇M, and EEPROM. Non-volatile memory is widely used in various electronic products, such as personal computers, persinai digitd assistants (PDAs), cellular mobile phones (cejQuiar rushing 116), digital sdlls (digital sdll) Camera), digital video camera, video game player, memory card, and other electronic devices. The memory card type may include a multimedia card (MMC), a secure digital (SD) card, a compact flash card, a memory stick, a SM smart card, and an xD memory card (extreme). Digital(xD)picture card). 5 200830539 26110pif Flash memory is widely used in non-volatile memory devices. The connection structure of the flash memory based on the cell (cel丨) and the bit line can be classified into a Not-OR (NOR) type and a Not-AND (NAND) type. Since the read speed is faster and the write operation is slower, the NOR type flash memory can be used as the code memory. Since the writing speed is fast and the price per unit area is low, the NAND type flash memory can be used as a large-capacity storage device.

NOR flash memory can be used in the BIOS/network of a pc, router or hub, or in a telecommunications switch. Flash memory can also be used to store code or data for cellular mobile phones, personal digital assistants (PDAs), POS or PCA. K4ND type (4) Memory is used in mobile computers, digital cameras, digital cameras, CD-quality sound recorders, rugged and reliable storage, such as solid-state hard drives (s〇lid_state by memory card. NOR Type, the stylized method of memory is hot carrier injection plus t earner mJecti〇n), and the stylized method of NAND flash memory is worn by Fowler-Nordheim (FN). & Advances in consumer electronics have produced a high-density record for manufacturing to meet this demand (four) set of efforts to pass the lions and reduce or minimize the attention between the pole structure, the power (four) channel length The effects of reduction, secret and secret on the open field and potential in the channel area increase. This situation is called the short channel effect. # 6 200830539 26110pif Other related questions include trap_assisted leakage ecurrent. As shown in FIG. 3, in a conventional charge tmp memory device, the substrate 12 includes an insulating pattern i4, a charge storage pattern 16, a resistive insulating pattern 18, and a conductive pattern 2〇. For example, electrons e- leak from the charge storage pattern 16 through the blocking insulating pattern 18 to the conductive pattern 20 due to blocking one or more defects D in the insulating layer.

Conventional technical publications have investigated the characteristics of non-overlapping MOSFETs and reported suppressing performance degradation by using short non-overlapping distances (e.g., less than 10 nm). These results indicate that non-overlapping structures are actually applicable. Reference is now made to the prior art device of the U.S. Application Serial No. 11/643,022, filed on November 20, 2006, which is incorporated herein by reference in its entirety in its entirety in its entirety in the the the the the the the The marginal electric field 90, the inversion layer 410, and the inversion layer located at the source/;; reverse polarity region 430. As shown, a 5 V pass voltage is applied to the memory transistors ΜΤ^ and ΜΤη+, and a selection voltage Vsel is applied to the memory transistor ΜΤΩ. The marginal electric field 9 产生 generated by the cell gate potential causes the source/drain to reverse, which enables the channel region to conduct charge. "Vr_pass" indicates the turn-on voltage. "Hungry ^, "Milk ~ and the heart of the factory mark the word line. Now refer to Figure 3 9 to dry the cover ρη宙%Child's 夭国寻利第7,081,651 of the conventional I straight, patterned gate guide bud闰安~& / ton leg) The first formation in the "a" and the cell array area (4) and at least in the external _ _ "t intersecting multi-element line 140, b" on the second active area 203 Extreme 240. The component symbol 1〇 is set up as a gate. 1 108 and 2Q2 respectively indicate the device isolation layer. 7 200830539 26110pif (device isolation layer), stack insulation layer, gate insulation layer. The a surname is gated by the conductive pattern while the third insulation pattern between the plurality of word lines 140 is exposed by the plasma excessively etched or attacked. Thus, a defect defect site is generated in the third insulating pattern 1?6 near the edge of the word line 14?. Follow-up, through the defect site

And there is a trap-to-trap tunneling. The charge stored in the post-formed electrical storage pattern is then discharged to the gate electrode, which has an undesirable effect on device operation. Referring now to FIG. 40, the 1/day lead volume circuit device of the U.S. Patent No. 6,674,122 includes a non-volatile memory cell, each memory cell-memory transistor TMC, and a two-switch transistor Tsw 5 Note that the transistor TMC includes a memory gate electrical connection 7 connected to the word line 5. The switching transistor Tsw includes switching gate electrodes 6-1 and 6-2, respectively, by applying a voltage to the switching gate electrodes 6-1 and 6_2 at the switching gate electrode 6-1 and the inversion layer 2 of the lower = j (M and 20) -2, the inversion layers 20-1 and 20_2 are used as the source or the drain of the bulk transistor Tmc. The component symbols i and 2 are respectively the plate and the gate insulating film. [Summary of the Invention] Or maximizing device performance. Embodiments can overcome short channel effects and/or defect-assisted leakage currents. Embodiments are related to a memory transistor that includes a vial on a substrate. An insulating pattern; an electrically visible pattern on the tunnel insulating pattern; a blocking insulating pattern on the charge storage pattern; and a gate electrode on the barrier of 8200830539 26110pif, the barrier insulating pattern surrounding the inter-electrode. The non-volatile memory may further comprise a series of meristor transistors and a plurality of subsidiary structures located between the plurality of memory cells in the series; mask= ❿ In an embodiment, each virtual mask pattern may be The non-volatile memory may further include electric (four) located at each end of the plurality of memory cells, and a partition wall between each selected lightning cell, the selection transistor package In the embodiment, the substrate may further comprise a doped region under the partition wall. The age η, non-volatile memory may be selected as the gate electrode. Further, a virtual selection transistor (d coffee ys fine tranistor) which is pure at each end of the polycrystal, the f-selective transistor includes a blocking insulating _ and a dummy selection gate electrode, and the resistance = edge image pure о virtual selection f f pole; Selecting a transistor for the virtual selection transistor: the selection transistor includes a barrier insulating pattern and a gate electrode, and the impurity insulation capping electrode is disposed between each of the dummy transistors and the plurality of memory transistors a first partition wall; and a second partition wall of each of the dummy, the electrified crystal and each of the selected transistors. In the embodiment only, the ground substrate further includes doped regions on the first and second partition walls In the embodiment, each of the plurality of subsidiary structures may be Auxiliary interpole structure. 200830539 26U0pif Ιΐ:: Each auxiliary interpole structure can be a conductor and a secondary electrode. 'Each auxiliary opening structure can include blocking insulating pattern bit 13 , i non-volatile memory can be included The plurality of single-pattern inter-selective transistors' includes a barrier insulating layer and is disposed at each of: two of the barrier insulating patterns surround the selected dummy electrode; and: Γ a partition wall between the plurality of unit transistors. The substrate may further comprise a doping region of a bit (4) spacer. The dummy μ of each end of the unit transistor is located in the occlusion blocking insulating pattern, and the virtual selection gate electrode is selected by the virtual selection transistor; The 嫂 嫂 绝缘 绝缘 绝缘 绝缘 廷 廷 廷 廷 廷 廷 廷 廷 廷 廷 廷 廷 廷 廷 廷 廷 廷 廷 廷 廷 廷 廷 廷 廷 廷 廷 廷 廷 廷 廷 廷 廷 廷 廷 廷 廷 廷 廷 廷 廷 廷And a second and between the plurality of single selected transistors and a doped region located in each of the dummy select transistors and in the embodiment, the substrate may be whiter. The crucible is located under the first and second partition walls. In a common embodiment, a stacked plurality of vertically stacked 圮_body-iso-volatile memory structures may include between the bodies and the plurality of verticals. The memory of the heap 4 is in the embodiment, a system that externally transmits the interface of the data; "two poor, and outputs to the user the data of the data". The complex reverses the data and controls the I' Control of the operation of the system 200830539 26110pif the non-volatile memory of the instructions executed by the controller; and for transferring data between interfaces, I/O skirts, controllers and non-volatile memory The embodiment is directed to a non-volatile memory comprising at least one memory cell structure and at least one auxiliary gate cell structure, wherein when the at least one memory cell and the structure are in a state of being pr〇 The grammec| siate), the at least one auxiliary gate cell structure is in a stylized state. In the embodiment, the at least one auxiliary gate cell structure is biased by a positive voltage during the stylization and reading operations. In the example, in the program During the state and the read state, the die = 辋 gate cell structure is biased by a voltage, the auxiliary gate cell structure t voltage is greater than a bias voltage equal to at least one memory cell structure, or At least one auxiliary gate cell structure is floating. ~ The embodiment is a method for stylizing non-volatile memory, which is singularized to the memory cell structure and at least - the auxiliary gate cell structure is at least The memory cell structure and the at least-assisted gate cell structure are simultaneously in a stylized state. The embodiment is a method for manufacturing a unit transistor, including providing a substrate on the substrate, a thin film, and a tunnel insulating pattern. The upper shape ^: He Jiancun pattern, the resistive insulation pattern is formed on the charge storage pattern; the gate electrode is formed on the barrier insulating layer to make the (four) insulating gate electrode. w B 曰曰 In the case of the shell, the subtraction method The method further includes forming a plurality of unit cells in series, and forming a plurality of subsidiary 200830539 26110pif structures between the plurality of unit transistors in series. In an embodiment, each of the plurality of subsidiary structures may be In the embodiment, each dummy mask pattern may include a lower mask pattern and an upper mask pattern. In an embodiment, each dummy mask pattern may be an insulator. In an embodiment, the method may be further Forming a selection transistor at each end of the plurality of unit transistors, including forming a barrier insulating pattern and selecting a gate electrode 5 such that a resist pattern surrounds the selection gate electrode; and selecting a transistor and the plurality of unit transistors in each of the plurality of unit transistors Forming a partition wall therebetween. In an embodiment, the method may further include forming a dummy selection transistor at each end of the plurality of unit transistors, including forming a barrier insulating pattern and a dummy selection gate electrode such that the barrier insulating pattern surrounds the dummy selection a gate electrode; forming a selection transistor at each end of the dummy selection transistor, comprising: forming a barrier insulating pattern and selecting an open electrode such that the blocking insulating pattern surrounds the selection gate electrode; and each of the dummy selection transistors and the plurality of unit transistors Forming a first partition wall therebetween; forming a second partition wall between each of the dummy selection transistors and each of the selection transistors. In an embodiment, each of the plurality of accessory structures may be an auxiliary gate structure. In an embodiment, each of the auxiliary gate structures may be a conductor. In an embodiment, each of the auxiliary gate structures may include a blocking insulating pattern and an auxiliary gate electrode. In an embodiment, the method may further include forming a selection transistor at each end of the plurality of unit transistors, including forming a barrier insulating pattern and selecting a gate electrode such that the blocking insulation pattern surrounds the selection gate electrode; and selecting the electricity 12 200830539 A partition wall is formed between the 26U0pif crystal and the unit cell. : The formation of Jingdian crystal: method: the case and the selection of the gate electrode, ώ / into the resistance of the uncle, the edge of the picture pole; on each side of the electrical interval volume only * 々 point. Between the Japanese and Japanese versions, a second _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The above-mentioned contents, other features and examples of the examples in the original shuttle zone are more clear and easy to understand. [Embodiment] An embodiment of a fine function. However, the 'specific structural and/or functional' is an embodiment for I. However, the scope of application for patents. ° 夕 ', his form is implemented and should not be construed as being limited to this implementation C: when the component is called "located, "connected to" or called "the traitor exists in the middle part. On the contrary, when a part ;" Directly connected to "Wei" "directly linked to" 13 200830539 26110pif On the other part, there is no intermediate part. As understood in this application, although the terms "first" and "second" "~_ describe different elements, components, regions, layers, and/or parts*, -", two," are used: parts, regions, layers, and / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Thus, the fourth member, component, region, layer, and/or portion, discussed below, may be a second component, component, region, layer, and/or portion, without departing from the embodiments. ~ Spatial relative terms, such as "below", "below, "^ ry ^ call", Bu", W = "," "up" and similar terms are used in this application for the purpose of describing the attached __ Μ, the characteristic relationship with another _ component or feature. It is to be understood that the relative terms described in the figures are intended to include different orientations of the device in use or operation. The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. The singular <RTI ID=0.0>"a" </ RTI> </ RTI> as used in this application is intended to mean a plurality of forms 5 unless otherwise clearly indicated in the context. It is to be understood that the terms "including" and "or" are used in the context of the application to indicate the presence of the features, integers, steps, operations, and/or components, but do not exclude the presence or addition of one or more Other features as a whole, steps, operations, components and/or components. Unless otherwise defined, all terms (including technical and/or scientific terms) used herein have the same meaning as commonly understood by those skilled in the art. The language (for example, M in the general-language industry, =% of the arts) makes the meaning of the technique used in the statement the same and should not be interpreted in an idealized form, unless it is explicitly defined in the text.

The embodiments are shown in the drawings, in which the reference numerals indicate similar components. The embodiments of the present invention are not limited to the shape of the special money domain illustrated by these points, and the shape deviation of the raw material is to be =. For example, a rectangular plant is shown with a rounded or curved feature and/or a dense implant instead of a discontinuous change from the implanted region to the non-implanted region. In the same way, the buried area formed by the intrusion can produce a certain degree of implanting in the area between the buried area and the implantation. Thus, the regions of the present invention are illustrative in nature and their shapes are not intended to limit the scope of the invention. Figure 1 illustrates a unitary transistor (unh transistor) in accordance with an embodiment. As shown in FIG. 1, the unit transistor 1A includes a substrate ι5, a tunnel insulating pattern 110, a charge storage pattern 115, and a barrier insulating pattern (8). ^% insulating pattern) 135a, control gate electrode (e_r〇1 gaie electrode) 140 and/or source/nomogram region 150. As shown! As shown, the resistive insulating pattern 135a includes a control gate electrode 140. Fig. 2 illustrates a non-volatile memory 200 comprising a plurality of unit transistors 100]···100Ν (where N&gt;1) are connected in series, according to an embodiment. As shown in Fig. 2, an auxiliary structure 142 is located between each unit transistor of the plurality of series unit transistors 200830539 26110pif 100ρ··100Ν. In an embodiment, the accessory structure 142 can be an insulator. In other embodiments, the accessory structure 1.42 can be a conductor. In an embodiment, the accessory structure 142 can be a dummy mask pattern. In other embodiments, the attachment structure 142 can be an auxiliary gate structure. The various examples will be discussed in more detail below. 3 illustrates a non-volatile memory 300 including select transistors 102, 1022 located at respective ends of a series unit transistor 1〇〇1··.1. Similar to the unit transistor 1〇〇]····1〇〇ν, each of the selection transistors = 2], 1022 includes a barrier insulating pattern 135b and a selection gate electrode ι45. In the second example, the cheek is like a unit transistor 1〇〇]···1〇〇ν, and the blocking insulating pattern 135b surrounds the selection gate electrode 145. The non-volatile memory 300 may further comprise a partition wall W0 spaced apart between each of the selected transistors 1 and 2 and the first layer 1: crystal ΙΟΟ^. 3 more common partition walls. . Fig. 4 shows in more detail a virtual mask pattern 130 as an attached zen body. As shown, each of the dummy mask patterns may include a lower mask pattern 12A and an upper mask pattern 125, respectively. The substrate 1 〇匕 may further include extension and miscellaneous regions located under each of the dummy mask patterns and each of the partition walls 1 (8). The substrate 105 may further include a channel 155a. Figure 4 also shows a selective transistor 1022 located at each end of the string % unit transistor 1〇〇ι,··1〇〇ν. The non-volatile memory 5〇〇 is shown, which includes select transistors m2], 1〇22, and dummy select transistors _, 1G42 located at each end of the serial cell 16 200830539 26110pif bit transistor 100. Similar to the unit cell break, each of the dummy transistors 104, 1042 includes a blocking insulating _135a and a dummy gate electrode 14G. In the embodiment, similar to the unit transistors 100] ... 100N, the blocking insulating pattern l35a surrounds the dummy selection gate electrode.

In the embodiment shown in FIG. 3 to FIG. 5, the plurality of unit transistors 1 〇〇 . . . . 100 Ν are used as storage cells, which are arranged along a plurality of word lines, and the number of control gates 140 can be According to the desired change in memory cell density. Selecting electricity, 1 (^1022 is used to select the plurality of unit transistors 1〇〇ι..·1〇〇: in the embodiment, the plurality of virtual mask patterns η〇 are formed in the word Between the lines. In the embodiment shown in FIG. 5, the dummy selection transistors 10^, 1〇42 cannot be used for data storage, but the selection gate electrodes for selecting the transistors 1〇2!, 1〇4 and In the embodiment where the unit transistor 10〇1...1 knows the control gate electrode is 0 々-tel :), the substrate 1〇5 includes one or more of the spacers 160. The doped area below. In other embodiments, the non-volatile memory includes a plurality of unit transistors 100]...100N, which respectively include a source region and a drain electrode in the substrate, and are located in the source region and the drain region. Multiple virtual mask patterns above. Figure 6 illustrates in more detail a non-volatile § memory _ including an auxiliary gate structure 128 as a structure M2. As shown, each of the auxiliary idlers 128 includes a second blocking insulating pattern t 122 and an auxiliary gate electrode 27. In the embodiment shown in Figure 6, the auxiliary gate structure is a conductor. 17 200830539. Similar to Fig. 4, the selection transistors 102], 1022 are provided at the respective ends of the plurality of unit houses. The selection transistor 丨〇 2], 1 〇 22 includes a blocking insulating pattern 135b and a selection gate electrode 145, wherein the blocking insulating pattern lb surrounds the selection gate electrode 145. The non-volatile memory 6 (8) may further include a partition wall 160 between each of the selection transistors 1〇2], 1〇22, and a plurality of unit transistors 10〇1..100Ν. The 3 ton base plate 105 may further include doped regions located under each of the auxiliary gate structures 128 and the respective spacers 1 〇 0. The substrate 105 may further include a channel 155a. And a burst memory 700, which includes a selection transistor located at each end of the series single-n-N, 02, war, and virtual:; ^:=41, 1 () 42. Similar to the unit transistor job.. With the transistor 104〗, i0 winter can be white and virtual selection P thunder gas: one. One d fine 'bar 10 iwa 】 〇〇)..'l〇〇k two ΓΓ two . . In the long-term embodiment, similar to the unit transistor, the insulating pattern 135 & surrounds the dummy selection gate electrode (10). (10)]...1, can be used as storage•, V; 夕” early only transistor control gate 14〇# &lt; ^ 夕 个 sub-element configuration, and crystal _, 1 〇 = set according to the desired memory blister density Variety. Selecting electricity 1 1022 is used to select between the plurality of clamps, and the plurality of auxiliary gates are between the two. Formed in the embodiment shown by the plurality of character edges 2, the virtual suppression gate = barren storage, but the selection port can be lowered: crystal 104], 1 〇 42 non-gate electrode and unit θ θ In the embodiment shown by the selection of a day 1〇2], 1022, and a *4 irj ^, its uncle a, ^ storm plate l (b can be located, in Fig. (9): = 3...1 Control the electrode. 200830539 261I0pif doped regions below the barrier wall 160. In other embodiments, the non-volatile memory includes the body 100]...1〇〇Μ' which includes the early position in the substrate The electro-crystals are located above the source and the non-polar regions: the regions and the non-polar regions are shown in the description of the example operation as shown in Fig. 8, 8] and the heart indicates the substrate 1〇5, (3) the circuit. Control the gate electrode, for example, the control gate shown in Fig. 6_Fig. 7 = two solid or a plurality of meters, one level of the auxiliary gate electrode, for example, Figure 6_Fig. 7 _ 1 commits 1, pole I2.7. Capacitance 0] And c:z represents the gate capacitance of the control gate electrode and the substrate C3 represents the capacitance between the control gate electrode and the auxiliary electrode: In the first method, the auxiliary gate electrode SG _ That is to say, the voltage applied to it does not work in the first state. During the stylization/reading operation, the auxiliary gate electrode commits a voltage state. The second turn-on voltage is similar to the turn-on voltage. During the simmering operation, the auxiliary gate electrode SG is in a dry state, and the charge is stored in the second voltage state;; =; pressure! lTf (repulsive force) ^! ί 兀 (for example, The multiple units of electricity (four) 1 〇〇].. period ^ ΐ 5 5 ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ When the structure is in a stylized state, the blister structure is also in a stylized state. ^Reading, (4) The method of morphing the memory includes: the cell structure and at least one auxiliary gate cell structure, so that the auxiliary gate structure of 19 200830539 is at the same time The 'auxiliary gate cell structure is stylized by the at least one memory cell structure and the at least one auxiliary horse. As a result, in this method, the charge is stored to assist the memory cell structure. As described in the above embodiment, when The at least - memory cell structure is not

The at least one memory cell structure migrates. Figure 9 is a diagram showing the method of forming a memory transistor (e.g., the memory transistor of Figure 4) according to an embodiment. As shown in Fig. 9, a tunnel insulating pattern tea no and a charge storage pattern m are formed on the substrate 1〇5. A plurality of virtual opacity maps b0 are formed on the charge storage pattern n5. The plurality of virtual occlusion patterns 130 include a lower mask pattern 12A and an upper mask pattern 125. As shown in Fig. 10, the barrier insulating layers 135a, 135b and the conductive layers 140, 14 are sequentially formed between the plurality of dummy mask patterns 13A. For example, the partial conductive layers 140, 14 and the partial blocking insulating layers 135a, 135b are removed by exposure to a Chemical-Mechanical Polishing Process (CMP) or a back-up process (4). Virtual mask layer. In an embodiment, the blocking insulating layers 135 &amp; 135b may be formed simultaneously by the same layer or by different layers at different times. Similarly, in embodiments the conductive layers 140 and 145 may be formed simultaneously from the same layer or from different layers at different times 2008 28539 26110 pif. One side As shown in Fig. 12, the obtained substrate 105 β is subjected to ion implantation to remove the mask pattern 130 region 150. /成#杂区', for example, source/drainage, as shown in Fig. 13, one or both sides of the partition wall 102], 1022. Fig. 14- Fig. 16 shows the phase of the memory cell edge pattern no and the charge ^= method of the memory thunder body of Fig. 5. (4) 14 The sneaker pattern 130 includes a lower hood: the sub-picture I15. The plurality of imaginary bffl U π cases 2 and the upper mask pattern 12 are as shown in FIG. 14 and the blocking insulating layers u5a, 140 And 145 are sequentially formed on the plurality of dummy masks, for example, a by chemical mechanical grinding, such as layer _, (4) and insulation f ^, returning the partial conductive layer 135a, 135b until Exposing the dummy mask layer. In the shell example, the 'blocking insulating layer 13% and U5b can be formed by different layers at the same time by the same person. Similarly, in the embodiment, the electric layers 140 and 145 can be simultaneously formed by the same layer. Or formed by different layers at different times. As shown in Fig. 15, it can be selectively removed on the side or both sides of the selection transistor 1〇2i, i〇22 and the virtual selection transistor, _ side or both sides The virtual mask pattern on the top 13 21 21 200830539 26110pif as shown in Figure 15, can be removed by the base of the virtual mask pattern i3 Ion implantation in the plate 105 forms a doped region, such as a source/drain region. As shown in FIG. 16, the spacer insulating pattern 160 may be formed on one or both sides of the selective transistor 102], 1022. Upper or virtual selection of one or both sides of the transistor 1〇41,1〇7.

Figure 17 Figure 20 illustrates a method of forming a memory transistor (e.g., a 5 丨 丨 思 思 体 体 体 体 体 体 体 体 体 体 体 体 体 体 体 体 体 体As shown in Fig. $, a tunnel insulating pattern 110 and a charge storage pattern 115 are formed on the substrate 1'5. A plurality of auxiliary gate structures 128 are formed on the charge storage map 115. The plurality of auxiliary gate structures 128 include a second NMOS 122 and an auxiliary gate. As shown in FIG. 17, the blocking insulating layers 135a, (10) and the conductive layers 140, (4) may be sequentially formed on the multi-side helper gate structure. Between 128. ^ By the chemical mechanical polishing process (CMp) or back (four) ^ layers 135a, 135b, until the exposed embodiment, the blocking insulating layer 135a and the coffee can be simultaneously formed by different layers. Similarly, in the embodiment, the formation may be formed by the same layer or at the same time, a sub-==_body-drain region 15〇. (4) Sub-implantation to form a region, for example, source/22 200830539 26110pif As shown in Fig. 20, the spacer insulating pattern 160 is formed on one side or both sides of the selection transistors 102, 1 22 . 21-24 illustrate a method of forming a memory transistor (e.g., the memory transistor of FIG. 7) in accordance with an embodiment. As shown in Fig. 21, a tunnel insulating pattern 110 and a charge storage pattern t 115 are formed on the substrate 1〇5. A plurality of auxiliary gate structures 128 are formed on the charge storage pattern 115. Make multiple

The dummy mask pattern 130 includes a second blocking insulating pattern 122 and an auxiliary gate electrode 127. As shown in FIG. 21, barrier insulating layers 135a, 135b and conductive layers 14A, 145 are sequentially formed between the plurality of auxiliary gate structures 128. A portion of the conductive layers 140, 145 and a portion of the barrier insulating layers 135a, (10) are removed by, for example, a chemical mechanical polishing process (CMp) or an etch back process until the dummy cap layer is exposed. In the embodiment, the barrier insulating layers 135a and 35b may be formed of the same layer at the same time or by the suppression layer at the time of Μ. Subtractively, in the embodiment, the bristles 140 and 145 may be formed by the same layer at the same time or at different layers. The field as shown in Fig. 22 can selectively remove the auxiliary gate structure 128 on the selected transistor l〇2l, 1〇22 = or on both sides or virtual selection of the transistor just ι, 谢r 2 . 4, as shown in FIG. 23, the grounding region 105 is performed in the substrate 105. The doping region can be formed by implanting the auxiliary gate structure 128, for example, the source/drain is as shown in FIG. The partition insulating pattern 160 may be formed on one side or both sides of the selective power 23 200830539 26110pif crystal 102 1022 or on one side or both sides of the dummy selection transistors 1〇4i, 1〇42. It is not explicitly shown in Figures 9-24 described above, but it is apparent that the source and drain regions of the plurality of unit transistors can be formed prior to forming the subsidiary structure, and subsequently in the plurality of unit transistors An auxiliary gate structure can be formed on the source region and the drain region. Figure 25 depicts an example of a stacked memory transistor (8). In the various embodiments set forth above (eg, non-volatile memory 1, 200, 300, 400, 500, 600, and/or 700) may be stacked in N stacks, where n&gt ;1. As shown in FIG. 25, the memory transistor stack may include a common source line (CSL) 20A, a bit line contact window (C〇ntact) 210, a layer 丨曰] pen's mussel (ILD) 220, Bit line 230 and/or dielectric 240. In the case of the shell k, the material of the CSL 200 may be iinTiN, TaN, Cu, and a mixture thereof from the group consisting of: the material of the bit line contact window 210 may be selected from the group consisting of: w, WN, TiN, TaN, Cu, and mixtures thereof. The material of the interlayer dielectric (ILD) 22 可 can be selected from the group consisting of: materials of low dielectric constant dielectric, BPSG, HDp, and mixtures thereof. The material of the bit line 230 can be selected from the group consisting of: w, wn, • TaN Cu, and mixtures thereof. The material of the dielectric material 240 can be selected from the group consisting of Si〇2 and low dielectric dielectric materials, BPSG, HDP and mixtures thereof. As explained above, in the embodiment shown in FIGS. 1-25, the gate structure is a chargetrap gate structure including a charge storage layer on the tunnel insulating layer 11G of 200830539 26U0pif. On the electrode located on the upper electrode: the barrier insulating layer 135a and the dielectric constant of the barrier insulating layer insulating layer no ((4) c〇nstam) may be larger than in the embodiment, the tunnel insulating layer 11 is packaged = two : Kind or multiple. In the embodiment, one or more of the charge ^ 夕 虱, 虱 发 、, ^ 氧化 氧化 氧化 silicon silicon silicon silicon silicon silicon silicon silicon silicon silicon silicon silicon silicon silicon silicon silicon silicon silicon silicon silicon silicon silicon silicon In the implementation of == 绝 = layer 135a includes - a metal oxide or a metal nitride of the quaternary element of the periodic table or the scorpion. In an embodiment, the barrier insulating layer gamma comprises a doped metal oxide or a compound, wherein the metal oxide is doped with a first difficulty of Menddeef. In an embodiment, one or more of blocking insulating layer 135 - Γ; Al2° 3' La2° 3: ZK &gt; 2, zrKsll'xc &gt; 2, Zf-Si NOx, and combinations thereof. The work-function of the metal layer of the gate electrode 140 is, for example, to &gt;, 4 eV. The metal layer includes titanium, titanium nitride, nitride group, sister, crane, give, sharp, turn, oxidized, indium nitride, bismuth, sui, chrome, oxidized, ,, (Ti3A1) A type of Ti2AlN, le, tungsten nitride (^^), tungsten (dioxide), a dream chain, or a combination thereof. In other real hoods, the electric ridge structure can be 〇n〇 25 200830539 26110pif structure. In an embodiment, the germanium structure can include a first oxide layer, a nitride layer only on the first oxide layer, and a second oxide layer on the nitride layer. - In other embodiments as described above, the gate structure can be a floating gate structure. With regard to the gate structure, the contents of U.S. Patent Application No. 2004/0169238, filed on March 8, 2004, is incorporated herein by reference. Figure 26 depicts a top view of a NAND flash memory cell in accordance with an embodiment. As shown in the figure, the NAND flash memory cell includes an isolation region 112A, a selection gate 180S, a word line (or gate pattern) 180w, a bit line contact window 1210, a bit line 1230, a common source line CSL, and / or active area ACT. Each of the NAND flash memory cells illustrated in FIG. 26 is implemented in the form of any of the non-volatile memories 100, 200, 300, 400, 500, 600, and/or 700 of FIGS. Figure 27 depicts a NAND flash memory in accordance with an embodiment. As shown, the NAND flash memory can include a memory cell array 310, a page buffer block 320, a Y-gating circuit 330, and/or a memory cell storing data. Control/decoder circuit 340 for controlling the operation of memory array 310, page buffer block 320, and Y-gate control circuit 330. The control/decoder circuit 34 receives the command signal and the address and generates control signals for controlling the memory array 310, the page buffer block 320, and the Y-gate circuit 330. FIG. 28 illustrates an example of a portion of a memory array 310 in accordance with an embodiment. As shown, the memory array 310 can include a plurality of bit lines B/Le, β/Lo, where "e" and "〇" represent even and odd bit lines. 26 200830539 The 26110 pif s-cell array 310 can include a plurality of cell Stings connected to the bit line in the bit line and the tendon, respectively. Each cell string in the illustrated example is formed by a string selection transistor SST (e.g., select transistor 1 〇 21, 1 〇 22 described above) connected to a corresponding bit line, connected to a common source line A ground selection transistor GST on the CSL (for example, the selection transistor 1G2 described above, 1G22) and a plurality of memory cells connected in series between the string selection transistor SST and the ground selection transistor GST, such as the above unit turtle crystal . Each of the string selection transistors, the ground selection, the transistor GST, and the memory cells M1_Mm are formed in accordance with an embodiment of the above embodiment. Although not shown in Figure 28, multiple strings can be connected to the bit line. Each line can be connected to the corresponding page of the page buffer block 32〇. "GSL" indicates the ground selection line. rSSL" marks the string selection line. "ST1" and "ST2" indicate the selection of the transistor. "WL1", "Muscle 2", "WL3" and "WLm" indicate word lines. The page buffer block 320 can include a plurality of page buffers that are read from the memory array 310 and written to the memory array 31 based on control signals from the control/decoder circuitry 34A. The Y-gate control circuit 330 can select a page buffer in the page buffer block 32A based on the control signal from the control/decoder circuit 340 to input data or output data. Since the structure and operation of the page buffer block 32, the gate circuit 330, and the control/decoder circuit 34 are well known, the structure and operation of these elements are not described in detail for the sake of brevity. In other instances, U.S. Patent No. 7,042, 770, which is incorporated herein by reference, is incorporated by reference. Moreover, it should be understood that the embodiments are not limited to application to NAND flash memory having the architecture described with respect to 27 200830539 26110 pif Figures 26-28. Rather, the embodiments are applicable to cell arrays of various NAND flash memory architectures. Figure 29 illustrates another embodiment. As shown, Figure 32 includes a memory 510 coupled to the brother memory controller 520. Memory 510 can be the NAND flash memory discussed above. However, the memory 510 is not limited to these memory architectures and may be any memory architecture having memory cells formed in accordance with an embodiment. The memory controller 520 supplies an input signal for controlling the operation of the memory 510. For example, in the case of the NAND flash memory of Figures 27-28, the memory controller 520 supplies the command CMD and the address signal. It should be appreciated that the memory controller .520 can control the memory 510 based on the received control signals (not shown). Figure 30 illustrates another embodiment. As shown, Figure 3() includes a memory 510 coupled to interface 515. The memory 51 can be the NAND flash memory discussed above. However, the memory 51 is not limited to these memory architectures, and may be any memory architecture having a memory cell formed by the embodiment. . The interface 515 is available for input signals (e.g., externally generated signals) that control the operation of the memory 5! For example, in the case of the nand flash memory of Figures 27-28, the interface 515 supplies the command CMD and the address, number. It will be appreciated that interface 515 controls memory element 51 (e.g., an externally generated but not illustrated signal) based on the received control signal. Figure 31 illustrates another embodiment. Figure 31 is similar to Figure 29 except that it is implemented in the form of 28 200830539 26110 pif = Body Controller 5 Heart Card 53q. For example, ^ can be 疋, recall cards, such as flash memory cards. In other words, the card can be used to satisfy the cost of a computer such as a digital camera: the card that uses the red industry standard. It should be understood that the memory controller does not: control the memory 510 from another device (e.g., an external device) by the card W.

Figure 32 depicts another embodiment. Figure Magic represents a portable device _ : The portable device can be a 3 player, a __ state, a wishing and audio combination player, and the like. As shown, the portable dock 6000 includes an @memory 510 and a memory controller 52A. The portable device 6000 can include an encoder and an arbitrator 61, and a presentation component a. And interface 630. The tribute (video, audio, etc.) can be input or outputted to the memory 51 by the encoder and decoder (EDc) 6i. The data may be directly input from the EDC 610 to the memory 51A and/or directly from the memory 510 to the EDC 610, as indicated by the broken line in FIG. The EDC 610 can encode the data for storage in the memory 51. For example, the EDC 610 can MP3 encode the audio material for storage in the memory 510. In addition, the EDC 610 can perform MPEG encoding (eg, MPEG2, MPEG4, etc.) on the video material for storage in the memory 510. In addition, EDC 610 can include multiple encoders to encode different data types based on different data formats. For example, EDC 610 may include an MP3 encoder for audio material and an MPEG encoder for video data.

The EDC 610 decodes the output of the memory 510. For example, EDC 29 200830539 26110pif 610 performs MP3 decoding on the audio data output of the memory. In addition, the EDC 610 can perform MPEG decoding (e.g., MPEG2, MPEG4, etc.) on the video material output of the memory 510. In addition, EDC 610 includes a plurality of decoders that decode different types of data according to different/1 bucket formats. For example, EDC 61 includes an Mp3 decoder for audio data and an MPEG decoder for video data. ...should know this, EDC 610 only includes the decoder. For example, the encoded material is transmitted to the memory controller 52A and the domain memory 510 by the EDC 61. The EDC 610 can receive data via the interface 630 for encoding or receiving encoded data. Interface 630 follows conventional standards (e.g., firewire (standard for transmitting compressed image files), USB, etc.). Interface 630 can also include multiple gauges. For example, interface 630 can include a firewire interface, a USB interface, and the like. The data from the memory 51〇 is also output via the interface 630. Presentation component 620 can present the data output from the memory and/or encoded by EDC 610 to the user. For example, presentation component 62A may include a ra-p eight jack for outputting audio material, a display screen for outputting video data, and/or other means. Figure 33 depicts another embodiment. As shown, the memory 51 is connected to the main system 7000. The main system 7000 can be a processing system such as a personal computer, a digital camera, or the like. The main system 7000 can use the memory 510 as a removable storage medium. As should be appreciated, the main system 7000 is available for input signals that control the operation of the memory 510. For example, in the case of the NAND flash memory of Figures 27-28, the 30 200830539 26110pif host 7000 supplies the command CMD and the address signal. Figure 34 illustrates an embodiment in which main system 70 (8) is coupled to card 530 of Figure 31. In the % example, the main system 7 can apply a control signal to the card 53 to cause the memory controller 520 to control the control of the memory 51.

Figure d is not a good example of other embodiments. As shown, the memory 51 is coupled to a central processing unit (cpu) 81 in the computer system 8000. For example, the computer system 8000 can be a personal computer, a personal data assistant, or the like. The memory 510 is directly connected to the CPU 810 or connected via a bus bar. It should be understood that for the sake of clarity, Figure 35 does not depict all of the auxiliary components that may be included in the computer system 8A. Figure 36 depicts other embodiments. As shown, the system 9 includes a controller 910, an input/output device 92 (eg, a keypad, a keyboard and/or display, a memory 93G, and/or an interface 94). In an embodiment, Each system component is coupled to each other via 徘 950. Technology y10 may include one or more microprocessors, digital signal emptators, or any processor similar to the above. Memory (4), run by controller 91 〇 The instruction. Any memory described in the memory example. The data is transmitted. The system can be used in another system (such as 'communication network) to transfer the board _ tablet), "Bu / such as PDA, portable computer, Networked memory card, etc. music player, _ part. It is apparent that these embodiments can be varied in many ways, although some embodiments are described 200830539 26110pif. These variations are not to be considered as a departure from the embodiment, and all modifications are intended to be included within the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 illustrates a unit transistor according to an embodiment. 2 illustrates a non-volatile memory including a plurality of tandem unit ray s carvings in accordance with an embodiment.脰, - Figure 3 depicts a non-volatile memory of the electret transistors at each end of a series unit transistor, in accordance with an embodiment. A non-volatile memory including a dummy pattern as an auxiliary node according to an embodiment is illustrated. (d) f f * The non-volatile memory of the domain embodiment of the serial unit transistor at each end of the bulk and virtual selection of the transistor. The enthalpy volatile memory including the auxiliary gate structure is illustrated in accordance with an embodiment. , Ma Rong &quot; 括 】 】 ^ ^ ^ ^ ^ ^ ^ ^ ^ 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 在 在 在 在 在 在 在 在 在 在 在 在 在 在The road 5% is not based on the method of implementing the equivalent electric method of the touch surface method to Fig. 13! The method of forming the memory electric body ® 14 to Fig. 16; 7 ία a - according to the embodiment is shown. The formation of a memory transistor in accordance with the embodiment of the present invention is shown in Figs. 17 to 20, which illustrate a method of forming a memory device 32 200830539 26110pif according to an embodiment. 21 through 24 illustrate a method of forming a memory transistor in accordance with an embodiment. Figure 25 depicts an example of a stacked memory transistor in accordance with an embodiment. Figure 26 depicts a top view of a NAND flash memory cell in accordance with an embodiment. Figure 27 depicts a NAND flash memory in accordance with an embodiment. Figure 28 depicts an example of a portion of a memory array in accordance with an embodiment. - Figure 29 depicts another embodiment including a memory controller in accordance with an embodiment. Figure 30 illustrates another embodiment including an interface in accordance with an embodiment. Figure 31 depicts an example memory card in accordance with an embodiment. Figure 32 depicts an example portable device in accordance with an embodiment. Figure 3 3 shows the example of the main system according to the example. Figure 34 depicts an example memory card and host system in accordance with an embodiment. FIG. 35 depicts an example computer system in accordance with an embodiment. Figure 36 illustrates a conventional example in accordance with an embodiment. Figure 37 depicts a conventional charge extraction type memory device including a defect assisted leakage current. 38 to 40 illustrate a conventional memory device. [Main component symbol description] 5: Word line 33 200830539 261 lOpif 6-1: Switching gate electrode 6-2: Switching gate electrode 7: Memory gate electrode 10 Substrate 12 Substrate 14 Insulation pattern 16 Charge storage pattern 18 Block Insulation pattern 20 Conductive pattern 20-1: Inversion layer 20-2: Inversion layer 90: Marginal electric field 100: Unit transistor 102 1 : Select transistor 102: 2: Select transistor 103: First active area 1〇7 : Select transistor 1 〇 42 : Select transistor 105 : Substrate 106 : Third insulation pattern 110 : Tunnel insulation pattern 115 : Charge storage pattern 120 : Lower mask pattern 122 : Second blocking insulation pattern 34 200830539 26110pif 125 : Top cover Cover pattern 127: auxiliary gate electrode 128: auxiliary gate structure 130: dummy mask pattern 135a: blocking insulating pattern 135b: blocking insulating pattern 140: word line/control gate electrode 142: subsidiary structure 145: selection gate electrode 150 · source Pole/&gt; and polar region 155a: channel 160: partition wall: series unit transistor 180S: selection gate 180W: word line/gate pattern 200 non-volatile memory 210 bit line contact window 220 interlayer dielectric 230 Element 240 Gate Electrode/Dielectric 300 Non-volatile Memory 310 Memory Array 320 Page Buffer Block 330 Y-Gate Control Circuit 200830539 26110pif 340 400 410 β 430 40cC 500 : 510 : • 520 : 530 : 600 : 610 : 620 : 630 : 700 : 810 : 900 : • 910 : 920 : 930 : 940 : 950 : 1120 1210 1230 Control / decoder circuit non-volatile memory inversion layer source /; and polar region inversion layer : channel region Non-volatile memory memory memory controller card non-volatile memory encoder and decoder presentation component interface non-volatile memory central processing unit system controller input/output device memory interface busbar isolation region bit line contact Window bit line 36 200830539 26110pif 6000 : Portable device 7000 : Main system 8000 : Computer system a: Cell array area b : Peripheral circuit area D : Defect e : Electronic ACT : Active area C1 : Control gate electrode and substrate Capacitor C2 · Control the gate electrode and: Capacitor C3 between the Qin board · Control the capacitance between the gate electrode and the auxiliary _ electrode CG: Control the gate electrode CSL: Common source

Sj : Substrate S2 · Storm plate SG : Auxiliary gate electrode ΜΤ ^ : Memory transistor ΜΤ η : Memory transistor ΜΤ η +1 : Memory transistor B / Le : Even bit line B / Lo : Odd bit line BL Direction : bit 谤 c direction WL direction · · word line direction TSW : switching transistor 37 200830539 26110pif TMC : memory transistor

38

Claims (1)

200830539 26110pif X. Patent Application Range: 1 . A memory transistor comprising: a substrate; a tunnel insulation pattern on the substrate; a charge storage pattern on the track insulation pattern; on the charge storage pattern a blocking insulating pattern; and a gate electrode on the blocking insulating pattern, the blocking insulating pattern surrounding the gate electrode. 2 - a non-volatile memory comprising: a plurality of memory transistors as described in claim 1 in series; and an attachment between the plurality of memory transistors in the series structure. 3. The non-volatile memory of claim 2, wherein each of the plurality of subsidiary structures is a dummy mask pattern. 4. The non-volatile memory of claim 3, wherein each of the dummy mask patterns is an insulator. 5. The non-volatile memory of claim 3, further comprising: a selection transistor located at each end of the plurality of memory transistors, the selection transistor comprising a barrier insulating pattern and a selection gate electrode, The blocking insulation pattern surrounds the selection gate electrode; and a partition wall between each of the selection transistors and the plurality of memory transistors. 39. The non-volatile memory of claim 5, wherein the substrate further comprises a doped region under the partition wall. The non-volatile memory of claim 3, further comprising: a virtual selection transistor located at each end of the plurality of memory transistors, the dummy selection transistor comprising a barrier insulating pattern and a virtual Selecting a gate electrode, the blocking insulating pattern surrounding the dummy selection gate electrode; _ a selection transistor located at each end of the dummy selection transistor, the selection transistor including a barrier insulating pattern and a selection gate electrode, the blocking insulation pattern Surrounding the selection gate electrode; a first partition wall between each of the dummy selection transistors and the plurality of memory transistors; and between each of the dummy selection transistors and each of the selection transistors The second partition wall. 8. The non-volatile memory of claim 7, wherein the substrate further comprises a doped region under the first and second barrier walls. 9. The non-volatile memory of claim 2, wherein each of the plurality of subsidiary structures is an auxiliary gate structure. 10. The non-volatile memory of claim 9, wherein each of the auxiliary gate structures is a conductor. 11. The non-volatile memory of claim 10, wherein each of the auxiliary gate structures comprises a barrier insulating pattern and an auxiliary gate electrode 0 12 - non-volatile as described in claim 9 Memory, 40 200830539 26110pif, the selection of the ends of the plurality of memory f crystals, the I-day court electrification sundial includes blocking the insulated electric iliac limb, the edge pattern encasing the selection gate electrode; The barrier is located at each of the selected transistors and the partition walls. ^ between the body transistors $ two: as described in the scope of claim 12, the non-#H includes the memory layer located below the partition wall, and further includes: #料1_第九相相_龟记忆,逑 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择Selecting the respective ends of the transistor, the Thunderbolt electric power includes a blocking insulation pattern and m, the selection pattern surrounding the selection gate lightning pole, and the barrier insulation is located in each of the virtual selections a first-partition wall; ^ - a plurality of memory transistors located in each of the virtual selection f crystals and the second spacer. Between the crystals of the ^ 冤 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. 13. Doping 16 under f J - Heap in a non-volatile memory structure, including ... 200830539 26110pif multiple vertically stacked memory as described in claim 2; and in each of the plurality of vertically stacked Insulator between memories. 17. A system comprising: an interface for receiving data for the system and transmitting data to an external portion of the system; an I/O device for receiving input data from a user and outputting output data to the user; a controller for controlling operation of the system; a non-volatile memory as described in claim 2, storing instructions executed by the controller; and causing data to be in the interface, A busbar transmitted between the I/O device, the controller, and the non-volatile memory. 18-- a non-volatile memory comprising: at least one memory cell structure; and at least one auxiliary gate cell structure, wherein the at least one auxiliary gate is when the at least one memory cell structure is in a stylized state The polar structure is in a stylized state. 19. The non-volatile memory of claim 18, wherein the at least one auxiliary gate cell structure is biased by a positive voltage during a stylizing and reading operation. 20. The non-volatile memory 5 of claim 18, wherein the at least one auxiliary gate cell structure is biased by a voltage, and the bias voltage of the auxiliary gate cell structure is greater than or equal to the at least A memory cell structure 42 200830539 26110pif bias voltage l or the at least 21 .- species is floating. Stylized at least one memory structure and body method, including: The more at least one of the billions of structures and the =, the auxiliary between the two structures, while in a stylized state. a core at least one auxiliary gate cell structure 22 - a substrate for manufacturing a unit transistor; 仏 'including: forming a via insulating on the substrate to form on the tunnel insulating pattern to be stored in the charge storage case Formed on. = Fig. f; s &, % edge pattern is formed on the barrier insulating pattern; and the pattern surrounds the gate electrode. , and the gate electrode makes the barrier insulating insulation. 23. As in the patent application scope, the force method further includes: , the formation unit of the transistor, the formation of a plurality of unit butterflies in series. , electricity day and day. 3⁄4, and the structure. Multiple singles. The version, the day] form a plurality of subsidiary nodes. 24. For example, the method of applying for a patent crystal, wherein each of the above-mentioned =========================================================== A method of crystals wherein the manufacturing unit mask pattern described in each of said covers is an insulator. For example, the method of applying for the scope of the profit-seeking body, the towel of each of the above-mentioned units. The cover case includes a lower mask pattern and an upper mask. FIG. 43 200830539 26110pif 27 The method for manufacturing a unit transistor according to claim 24, further comprising: each of the plurality of early-stage transistors Forming the selection transistor 5 includes forming a barrier insulating pattern and a selection gate electrode such that the barrier insulating pattern surrounds the selection gate electrode; and forming a partition wall between each of the selection transistor and the plurality of unit transistors . The method of manufacturing a unit transistor according to claim 24, further comprising: forming a dummy selection transistor at each end of the plurality of unit transistors, including forming a barrier insulating pattern and a dummy selection gate electrode, Forming the blocking insulating pattern to surround the dummy selection gate electrode; forming a selection transistor at each end of the dummy selection transistor, including forming a blocking insulation pattern and selecting a gate electrode such that the blocking insulation pattern surrounds the selection gate electrode Forming a first partition wall between each of the dummy selection transistors and the plurality of unit transistors; and forming a second partition wall between each of the dummy selection transistors and each of the selection transistors. The method of manufacturing a unit cell according to claim 23, wherein each of said plurality of subsidiary structures is an auxiliary gate structure. The method of manufacturing a unit cell according to claim 29, wherein each of said auxiliary gate structures is a conductor. The method of manufacturing a unit cell according to claim 30, wherein the auxiliary gate structure comprises a barrier insulating pattern and an auxiliary gate electrode. 32. The method of manufacturing a unit transistor according to claim 29, further comprising: forming a selection transistor at each end of the plurality of unit transistors, including forming a barrier insulating pattern and selecting a gate electrode, such that a blocking insulating pattern surrounding the selection gate electrode; and a partition wall formed between each of the selection transistor and the plurality of unit transistors. The method of manufacturing a unit transistor according to claim 29, further comprising: forming a dummy selection transistor 5 at each end of the plurality of unit transistors: forming a barrier insulating pattern and a dummy selection gate electrode, Forming the blocking insulating pattern to surround the dummy selection gate electrode; forming a selection transistor at each end of the dummy selection transistor, including forming a barrier insulating pattern and a selection gate electrode such that the blocking insulation pattern surrounds the selection gate a first spacer is formed between each of the dummy selection transistors and the plurality of unit transistors; and a second barrier is formed between each of the dummy selection transistors and each of the selection transistors . 34. A non-volatile memory comprising: a substrate; a plurality of unit transistors, each unit transistor including a source region and a > polar region located in the substrate 45 200830539 251iUpif, and a plurality of auxiliary gates The structure 'is located above the source region and the wave region 46