200830520 UMCD-2006-0167 21623tw£doc/e 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種半導體元件，且特別是有關於一 種晶片堆疊封裝結構（multi-chip package )。 【先前技術】 在半導體產業中，積體電路（integrated circuits，1C) 的生產主要可分為三個階段：積體電路的設計（Ic design)、積體電路的製作（ic process)及積體電路的封 裝（IC package )。 在積體電路的製作中’晶片（chip )是經由晶圓（wafer ) 製作、形成積體電路以及切割晶圓（wafer sawing)等步驟 而完成。晶圓具有一主動面（active surface)，其泛指晶 圓之具有主動元件（active element)的表面。當晶圓内部 之積體笔路元成之後，晶圓之主動面更配置有多個接塾 (bonding pad)，以使最終由晶圓切割所形成的晶片可經 由這些接墊而向外電性連接於一承載器（carrier)。承載 ί 器例如為一導線架（leadframe)或一封裝基板（package substrate )。晶片可以打線接合（wire b〇nding )或覆晶接 合（flip chip bonding)的方式連接至承載器上，使得晶片 之這些接墊可電性連接於承載器之接點，以構成一晶片封 裝結構。 就覆晶接合技術（flip chip bonding technology )而言， 通常在晶圓之主動面上形成這些接墊之後，會在各個接墊 上進行製作一銲料凸塊（solderbump)，以作為晶片電性 200830520 UMCD-2006-0167 21623twf.doc/e 連接外部封裝基板之用。由於這些銲料凸塊通常以面陣列 排列於晶片之主動面上，使得覆晶接合技術適於運 用在向接點數及高接點密度之晶片封農結構，例如已普遍 ，應用於半㈣縣產業巾的覆晶/球格_式封裝（flip e由一㈣°料，她純線接合技術， S1：些日凸^可提供晶片與承载器之間較短的傳輪路徑， 合技術可提升晶片封裳結構之電性效能 (electrical performance )。 盘積ΐί路業對於電性效能最大化、低成本 統上且gration)等的要求下，上述傳 產業的要求吉構已無法完全滿足現今電子 得多個晶片堆疊以形成2接合技術或覆晶接合技術使 力的方向。 ' 曰曰片堆豐封裝結構將是值得努 之間是以焊結構的這些晶片與基板 線的密度有一定制 為電性連接的媒介，但是焊 性連接的晶片的高度增加長銲:在隨著與基板電 積亦將逐漸增加。因此，敕=下，知枓凸塊所佔據的體 凸塊作為電性連接的媒介不論是以焊線或鲜料 的體積都較大。 白知技術之晶片堆疊封裝結構 【發明内容】 有的目的是提供—種W堆疊縣結構，其所具 200830520 UMCD-2006-0167 21623twf.doc/eBACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a semiconductor device, and more particularly to a multi-chip package. [Prior Art] In the semiconductor industry, the production of integrated circuits (1C) can be mainly divided into three stages: design of integrated circuits (Ic design), fabrication of integrated circuits (ic process), and integrated circuits. Circuit package (IC package). In the fabrication of an integrated circuit, the "chip" is completed by a process of fabricating, forming an integrated circuit, and wafer sawing. The wafer has an active surface that generally refers to the surface of the wafer having an active element. After the integrated chip inside the wafer is formed, the active surface of the wafer is further provided with a plurality of bonding pads, so that the wafer finally formed by the wafer cutting can be electrically connected via the pads. Connected to a carrier. The carrier \\ is, for example, a leadframe or a package substrate. The wafer can be connected to the carrier by wire bonding or flip chip bonding, so that the pads of the wafer can be electrically connected to the contacts of the carrier to form a chip package structure. . In the case of a flip chip bonding technology, after forming these pads on the active surface of the wafer, a solder bump is formed on each of the pads to serve as a wafer electrical 200830520 UMCD. -2006-0167 21623twf.doc/e For connecting external package substrates. Since these solder bumps are usually arranged in an array of planes on the active surface of the wafer, the flip chip bonding technique is suitable for wafer sealing structures using the number of contacts and high junction density, for example, has been commonly applied to semi-four counties. The flip-chip/ball grid of the industrial towel (flip e is made of one (four) ° material, her pure wire bonding technology, S1: some day convex ^ can provide a short transfer path between the wafer and the carrier, Improve the electrical performance of the wafer sealing structure. Under the requirements of the disk industry for the maximization of electrical performance, low cost and gration, the requirements of the above-mentioned industry can not fully meet the requirements of today. The electrons are stacked in a plurality of wafers to form the direction of the force by the 2 bonding technique or the flip chip bonding technique. The 曰曰 堆 堆 封装 package structure will be worthwhile between the soldered structure of these wafers and the density of the substrate line has a custom-made electrical connection medium, but the height of the solder-joined wafer is increased by long solder The electric product with the substrate will also gradually increase. Therefore, under the 敕 =, the body bumps occupied by the knuckles are used as the medium for electrical connection, regardless of the volume of the wire or the fresh material. The wafer stacking package structure of Baizhi Technology [Summary] It is an object to provide a W-stacked county structure, which has the structure of 200830520 UMCD-2006-0167 21623twf.doc/e
本發明之另-目的是提供一種晶片堆疊 内部晶片所具有的接點密度較高。 為達上述或是其他目的，本發賴出—種晶片堆 裝結構，其包括-基板、一第一晶片、多個導^體 (concave body )、一第二晶片與多個導紐（_du咖e ―)。基板具有一第一表面，而第—晶片配置於第―表 面上且於第-表面上形成一第一正投影（〇rth〇g〇nai projection)。這些導電體配置於且電性連接於第一曰片與 第二表面^間。第二晶片配置於第—表面上且於第:表面 上形成一第二正投影，其中至少部分第一晶片是介於第二 ，片與基板之間，且第-正投影與第二正投影至少部分重 豐（ovedap)。此外，這些導雜配置於且電性連接 二晶片與第一表面之間。 在本發明之一實施例中，上述之基板更可具有一凹陷 (cavity)，其位於第一表面上，其中第一晶片位於凹陷處。 e、$在本發明之一實施例中，上述這些導電柱的材質例如 是選自於銅、銘、金、#、鈦、該等之組合及該等之合金 所組成族群中的一種材質。 在本發明之一實施例中，上述這些導電體可為導電凸 塊（conductive bump )。 ^在本發明之一實施例中，上述這些導電體的外型可與 =些‘電柱的外型相同。此外，這些導電體的材質例如是 k自於銅、鋁、金、鉑、鈦、該等之組合及該等之合金所 組成族群中的一種材質。 200830520 UMCD-2006-0167 21623twf.doc/e 在本發明之一實施例中，上述之晶片堆疊封裝結構更 包括一黏著層（adhesive layer)，其配置於第一晶 # 二晶片之間。 89 、第 在本發明之一實施例中，上述之晶片堆疊封裝結 包括一底膠層（underfill layer)，其至少包覆這此 與這些導電柱。 ~ 在本發明之一實施例中，上述之晶片堆疊封裝結 ( 包括多個焊球（s〇lder ball)，其配置於基板之相對於 表面的一第二表面上。 、一 為達上述或是其他目的，本發明提出一種晶片 裝結構，其包括一基板、一第一晶片、多個導電體、:第 =右多，第導電柱、一第三晶片與多個第二導電柱。 fn弟-表面，而第_晶片配置於第—表面上且於 一 ί投影。這些導電體配置於且電性 連接於弟-曰曰片與弟-表面之間。第二晶片配置於第 第一 ί面上形成一第二正投影，其中至少部分第 曰曰片疋介於第二晶片與基板之間，並— 二正投影至少部分重疊，而這此 ^〜一弟 =㈣片與第，=第 -曰表面上形成—第三正投影，其中至少部分第 一日曰片疋介於第三晶片與基柘 # 〇 # 一 三正投影至少部分重疊，;二弟二^投影與第 連接於第三晶片與第-表面^弟—¥電柱配置於且電性 在本發明之-實_巾，上述之基板更可具有一凹 8 200830520 UMCD-2006-0167 21623twf.doc/e P日二位於第一表面上，其中第—晶片位於凹陷處。 初„一實施例中，上述這些第-導電柱的材質 =疋咖銅、銘、金、銘、鈦、該等之組合及該等之 &至所組成族群中的一種材質。 mi例中’上述這些第二導電柱的材質 =疋選自於銅、銘、金、鈾、鈦、該等之組合及該等之 合金所組成族群中的一種材質。 Ρ 在本發明之一貝施例中，上述這些導電體可為導電凸 塊。 、丄f本1明之、„ ’上述這些導電體的外型可與 k些第-導電柱或&些第二導電柱的外型相同。 些導電體的㈣例如是選自於銅、紹、金、始、欽、該等 之組合及该專之合金所組成族群中的一種材巧 、 在本發明之-實施例中，上述之晶片^封裝 包括-第-黏著層，其配置於第_晶片與第二1 林發明之-實施财，上述之晶騎疊封以= 包括-第二黏著層，其配置於第二晶片與第三^ 在本發明之-實施例中，上述之晶片堆 t 包括-底膠層，其至少包覆這些導電體、這 更 與這些第二導電柱。 一 ¥电枝 在本發明之一實施例中，上述之S 包括多個焊球，其配置於基板之相對於第一=面裝結構更 表面上。 、—弟二 為達上述或疋其他目的，本發明提出一種曰片堆、 9 200830520 UMCD-2006-0167 21623twf.doc/e f結構，其包括—基板、_第_晶片、_第二晶片、多個 第厂導電體與多個第-導電柱。基板具有—第—表面，而 f曰，置於第—表面上且於第—表面上形成一第一正 ^。=晶片配置於第_表面上且於第—表面上形成一 3 ϋ〔其t部分ϊ 一晶片是介於第二晶片與基板之 二、曾^掷弟I投影與第二正投影至少部分重疊。這些第 連接於第一晶片與第二晶片之間。 表面=第—導電柱配置於且電性連接於第二晶片與第 ^本發明之—實施财，上叙基板更可具有一凹 於弟—表面上，其中第—晶片位於凹陷處。 例如實施例中，上述這些第—導電柱的材質 例如疋選自於銅、鋁、金、鉑、 合金所組成族群_的一種材質。寺之H亥專之 電凸ΐ本發明之—實施财，上述這些第一導電體可為導 ( 可與施例中，上述這些第—導電體的外型 ㈣質例如是選自於銅、紹、金、翻“= 該等之合金所組成族群巾的—種材質。…、’且口 包括ίΐίΓΐ實施例中，上述之晶片堆疊封褒結構更 粘者層，其配置於第一晶片與基板之間。 包括^㈣片堆疊封裝結構更 岭廣I至少包覆這些第一導電體與這些第一導 200830520 UMCD-2006-0167 21623twf.doc/e 電柱。 在本發明之-實施例中，上述之 包括多個焊球’其配置於基板之相對於第一;結籌更 表面上。 乐表面的一第二 在本發明之一實施例中，上述晶 括-第三晶片、多個第二導電體與多個第二導=構，包 ί片Γί:第:表面上且於第-表面上形成:第 正投影與第三正投影至少部分重疊間、1亚且 酉己置於且電性連接於第—晶片與第三晶片之體 導電柱配置於且電性連接於第二 廷二弟一 外’這些第二導電权二:：=:表面之間。此 裝結構，其包括—基 ^種s曰片堆疊封 ( 基板具有一第—表面，而第 「曰曰上與夕個導電柱。 第一表面上形成—第一正投影曰。曰這_^ 一表面上且於 ，連接於第—晶片與第_表面之間置於且 導電懸配置於且電性影’而這些第二 影，其中第-1片:第且日於第一表面上形成-第三正； 間亚且弟二正投影分別與第-正投影以及^與基板之 仅〜以及弟二正投影至 200830520 UMCD-2006-0167 21623twf.doc/e 少部分重疊，而這些導電柱配置於且電性連接於第三曰 與第一表面之間。 在本發明之—實施例中’上述之基板更可具有兩凹 陷，其位於第—表面上，其中第—晶片與第二日日日片分 於這些凹陷處。 在本發明之一實施例中，上述這些導電柱的材質例如 是選自於銅、鋁、金、鉑、鈦、該等之組合及該等之合金 所組成族群中的一種材質。 上述這些第一導電體可為導 上述這些第一導電體的外型 此外，這些第一導電體的材 鉑、鈦、該等之組合及該等 在本發明之一實施例中 電凸塊。 在本發明之一實施例中 可與這些導電柱的外型相同 質例如是選自於銅、鋁、金一 之合金所組成族群中的一種材質。 電凸i本發明之一實施例中，上述這些第二導電體可為導 可盘之一實施例中，上述這些第二導電體的外裂 電柱的外型相同。此外，這些第二導電_ 二^疋廷自於銅、紹、金、翻、鈦、該等之組合及該筹 a孟所組成族群中的一種材質。 Μ、Another object of the present invention is to provide a wafer stack having a higher density of contacts in the wafer. For the above or other purposes, the present invention relates to a wafer stacking structure including a substrate, a first wafer, a plurality of conductive bodies, a second wafer and a plurality of guides (_du Coffee e -). The substrate has a first surface, and the first wafer is disposed on the first surface and forms a first orthographic projection (第rth〇g〇nai projection) on the first surface. The electrical conductors are disposed and electrically connected between the first cymbal and the second surface. The second wafer is disposed on the first surface and forms a second orthographic projection on the surface: wherein at least a portion of the first wafer is between the second, the sheet and the substrate, and the first-right projection and the second orthographic projection At least part of the ovedap. In addition, the impurity is disposed between and electrically connected between the two wafers and the first surface. In an embodiment of the invention, the substrate may further have a cavity on the first surface, wherein the first wafer is located at the recess. e. In one embodiment of the present invention, the material of the conductive pillars is, for example, one selected from the group consisting of copper, indium, gold, #, titanium, combinations thereof, and alloys of the alloys. In an embodiment of the invention, the electrical conductors may be conductive bumps. In one embodiment of the invention, the electrical conductors described above may have the same appearance as the 'some' electric posts. Further, the material of these conductors is, for example, one selected from the group consisting of copper, aluminum, gold, platinum, titanium, combinations thereof, and alloys thereof. In an embodiment of the invention, the wafer stack package structure further includes an adhesive layer disposed between the first wafers and the second wafers. 89. In an embodiment of the invention, the wafer stack package includes an underfill layer covering at least the conductive pillars. In one embodiment of the present invention, the wafer stack package (including a plurality of solder balls) disposed on a second surface of the substrate opposite to the surface. For other purposes, the present invention provides a wafer package structure including a substrate, a first wafer, a plurality of electrical conductors, a first right, a first conductive pillar, a third wafer, and a plurality of second conductive pillars. a surface-, and a first wafer is disposed on the first surface and projected on the first surface. The electrical conductors are disposed between and electrically connected to the surface of the younger and the latter. The second wafer is disposed at the first Forming a second orthographic projection on the ί surface, wherein at least a portion of the second cymbal cymbal is interposed between the second wafer and the substrate, and the two orthographic projections at least partially overlap, and wherein the two dies are (four) and the first Forming a third orthographic projection on the first surface of the first surface, wherein at least a portion of the first of the first wafers is at least partially overlapped with the third orthographic projection of the third wafer; On the third wafer and the first surface ^ brother - ¥ electric column is configured and electrically in the hair In the embodiment of the present invention, the substrate may have a recess 8 200830520 UMCD-2006-0167 21623 twf.doc/e P is located on the first surface, wherein the first wafer is located in the recess. The materials of the above-mentioned first conductive pillars are: copper, inscriptions, gold, inscriptions, titanium, combinations of the above, and one of the materials of the group. In the case of mi, the above second conductive pillars Material = 疋 selected from the group consisting of copper, inscription, gold, uranium, titanium, combinations of these, and the alloys of the alloys. Ρ In one of the embodiments of the present invention, the above-mentioned conductors may be It is a conductive bump. 丄f本1本之, „ 'The shape of these conductors can be the same as the shape of some of the first-conducting pillars or & some of the second conductive pillars. In one embodiment of the group consisting of copper, sau, gold, shanghai, shanghai, the combination of the alloys, and the alloy of the special alloy, in the embodiment of the invention, the wafer package includes a -adhesive layer , which is configured in the first wafer and the second one forest invention - implementation of the above, the above crystal riding overlay = package a second adhesive layer disposed on the second wafer and the third embodiment. In the embodiment of the present invention, the wafer stack t includes a primer layer covering at least the conductors, which is more In one embodiment of the present invention, the S includes a plurality of solder balls disposed on a surface of the substrate opposite to the first surface mounting structure. Or for other purposes, the present invention provides a cymbal stack, 9 200830520 UMCD-2006-0167 21623 twf.doc/ef structure, which includes a substrate, a _th wafer, a second wafer, a plurality of first factory conductors and more The first - conductive column. The substrate has a first surface, and f is placed on the first surface and forms a first positive surface on the first surface. = the wafer is disposed on the first surface and forms a 3 ϋ on the first surface [its t portion ϊ a wafer is interposed between the second wafer and the substrate, and the projection and the second orthographic projection at least partially overlap . These first are connected between the first wafer and the second wafer. The surface = the first conductive pillar is disposed and electrically connected to the second wafer, and the substrate is further provided with a recessed surface, wherein the first wafer is located at the recess. For example, in the examples, the material of the first conductive pillars, for example, is selected from the group consisting of copper, aluminum, gold, platinum, and alloys. The first electric conductor of the present invention may be a guide (in the embodiment, the outer shape (four) of the above-mentioned first electric conductors is, for example, selected from copper,绍,金,翻"=The material of the group of towels composed of these alloys....,' and the mouth includes the above-mentioned wafer stacking and sealing structure more sticky layer, which is disposed on the first wafer and Between the substrates, including the ^ (four) chip-stacked package structure, at least the first conductors and the first lead 200830520 UMCD-2006-0167 21623 twf.doc / e electric column. In the embodiment of the present invention, The above includes a plurality of solder balls 'which are disposed on the substrate relative to the first; the surface is formed on the surface. A second surface of the music surface. In one embodiment of the present invention, the above-mentioned crystal-third wafer, multiple The second conductor and the plurality of second conductors are formed on the surface and formed on the first surface: the first projection and the third orthographic projection at least partially overlap, and the The body conductive pillars electrically connected to the first wafer and the third wafer are disposed and electrically connected to Two of the second brothers and one outside the 'the second conductive right two::=: between the surfaces. This structure, including the base s 堆叠 堆叠 堆叠 ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( Forming a first conductive projection on the first surface. The first surface is formed on the surface of the first wafer and is connected between the first wafer and the first surface and is electrically conductively suspended and electrically formed. 'And these second shadows, of which the -1 piece: the first day formed on the first surface - the third positive; the sub-Asian and the second Orthodox projections respectively and the - Orthographic projection and ^ and the substrate only ~ and the second Orthographic projections to 200830520 UMCD-2006-0167 21623twf.doc/e are partially overlapped, and these conductive pillars are disposed and electrically connected between the third crucible and the first surface. In the embodiment of the invention, the above The substrate may further have two recesses on the first surface, wherein the first wafer and the second day are divided into the recesses. In an embodiment of the invention, the materials of the conductive pillars are selected, for example. In copper, aluminum, gold, platinum, titanium, combinations of these, and alloys of such alloys A material of the first conductors may be an outer shape of the first conductors, and a combination of the first conductors, platinum, titanium, and the like, and the like in an embodiment of the invention. The electric bump may be one of the materials selected from the group consisting of copper, aluminum, and gold alloy in one embodiment of the present invention. In an embodiment, the second conductive body may be an embodiment of the conductive disk, and the outer splitting posts of the second conductive bodies have the same outer shape. Further, the second conductive materials are from the copper. , Shao, Jin, Fu, Titanium, the combination of these and one of the materials of the group. Oh,
包括實關中，上叙Μ堆料裝結構吏 三晶二晶=於第三晶片與第-晶W 在本發明之—實施射，上述之晶片堆疊封I結構竟 12 200830520 UMCD-2006-0167 21623twf.doc/e 包括-底膠層，其至少包覆這些第 a 電體與這些導電柱。 冷电體、這些第二導 在本發明之-實施例中，上述 β 包括多轉球，其配置於基板之相對於封裝結構更 表面上。 表面的~第二In the actual customs, the upper Μ Μ Μ 装 吏 = = = = = = = = = = = = = = = 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 2008 2008 2008 2008 .doc/e includes a primer layer that coats at least these a-th electrical bodies with the conductive posts. The cold conductor, these second guides In the embodiment of the invention, the above β comprises a multi-turn ball which is disposed on a surface of the substrate opposite to the package structure. Surface ~ second
基於上述，由於本發明之晶片 這些晶片的至少其t之-是藉由這些導斤具有的 基板’且各個導電柱所佔據的空間較小至 =:疊封裝結構相較’本發明之晶片^^ 為讓本發明之上述和其他目的、特徵 2下了文特舉較佳實施例，並配合所附圖^ ί詳= 【實施方式】 _弟一貫施例 圖1Α繪示本發明第一實施例之一種晶片堆疊封裝处 構的剖面示意圖，圖1Β繪示圖1Α之晶片於基板上形成^ 投影的示意圖。請參考圖1Α與圖1Β，第一實施例之晶片 堆豐封裝結構100包括一基板110、一第一晶片12〇、多個 導電體130、一第二晶片140與多個導電柱15〇。基板11〇 具有一第一表面112,而第一晶片120配置於第一表面112 上且於第一表面112上形成一第一正投影ρΐ2()。 這些導電體130配置於且電性連接於第一晶片120與 第一表面112之間。第二晶片140配置於第一表面112上 13 200830520 UMCD-2006-0167 21623twf.doc/e 且於第一表面112上形成一第二正投影pi4〇，其中至少部 分第一晶片120是介於第二晶片ho與基板11〇之間，且 第一正投影P120與第二正投影P14〇至少部分重& (overlap)。此外，這些導電柱15〇配置於且電性連接= 第二晶片140與基板11〇之第一表面η]之間。 由於第二晶片140是藉由這些導電柱15〇而電性連接 至基板110，且各個導電柱150所佔據的空間較小，所以 ) 第二晶片140的各個接墊（bonding pad) 142對應與各個 導電柱150相接觸的面積可較小，且相鄰這些接墊的 間距（pitch)可較小。因此，與習知技術之晶片堆疊封裝 結構相較，本實施例之晶片堆疊封裝結構1〇〇的第二晶片X 140在這些接墊142的數量固定的情形下，第二晶片a9M〇 的體積可較小，進而使得晶片堆疊封裝結構1〇〇的體積可 較小。 請參考圖1C，其繪示本發明第一實施例之另一種晶 片堆疊封裝結構的剖面示意圖。在此必須說明的县， ί 使晶片堆疊封裝結構100,的體積更小，基板11〇，更可具有 一位於第一表面112,上的凹陷114，，且第一晶片12〇，ς於 凹陷114’處。這樣的特徵可間接地縮短這些導電柱15〇 長度。 請再參考圖1Α與圖1Β，第一實施例中，這些導電柱 150的材質例如是選自於銅、麵、金、銘、鈦、該等之組 合及該等之合金所組成族群中的一種材質。另外，第一實 施例之這些導電體13〇可為導電凸塊，其材質可為含錯材 14 200830520 UMCD-2006-0167 21623twf.doc/e 料（例如錯或錫錯合金）或無錯材料，其包括金、銅、錫 或錄，而亦可包括含有金、銅、錫或鎳之合金或化合物。 在此必須說明的是，為了使得第一晶片12〇的體積可較 小，第一貝施例之這些導電體13〇的外型亦可與這些導電 柱150的外型相同（但是並未以圖面繪示），同時&些導 電體130的材質可與這些導電柱15〇的材質相同。 在第一實施例中，晶片堆疊封裝結構1〇〇更包括一黏 著層160、一底膠層170與多個焊球180。黏著層16〇配置 於第一晶片120與第二晶片14〇之間，黏著層16〇的功能 在於讓第二晶片140穩固地黏著於第一晶片12〇上。此外， 底膠層170至少包覆這些導電體13〇與這些導電柱15〇， 在第一實施例中，底膠層170更可包覆第一晶片12〇。底 膠層170用以保護這些導電體13〇與這些導電柱15〇，並 且當晶片堆疊封裝結構100運作而產生熱時，底膠層17〇 可缓衝受熱的基板110與受熱的第一晶片丨2〇之間以及受 熱的基板110與受熱的第二晶片14〇之間所產生的熱應變 ( (thermal strain)之不匹配（mismatch)的現象。 這些焊球180配置於基板no之相對於第一表面U2 的弟^一表面116上’用以電性連接其他的電子裝置（未 繪示）。第一實施例之這些焊球180可以陣列的方式排列， 以提供球格陣列（ball grid array，BGA)類型之訊號輸出入 介面。值得說明的是，這些焊球180亦可由多個導電針腳 (conductive pin)或多個導電柱腳（conductive c〇lumn) 所取代’以分別提供針格陣列（pin grid array，PGA)類型 15 200830520 UMCD-2006-0167 21623twf.doc/e 或柱格陣列（column grid array，CGA)類型之訊號輪出入 ’丨面’但疋後面兩者並未以圖面表不。 第二實施例 圖2A繪示本發明第二實施例之一種晶片堆疊封裝結 構的剖面示意圖，圖2B繪示圖2A之晶片於基板上形成正 投影的示意圖。請參考圖1A、圖2A與圖2B，第二實施 例之晶片堆疊封裝結構200與第一實施例之晶片堆疊封裝 結構100的主要不同之處在於，第二實施例之晶片堆疊封 裝結構200包括第一晶片220、第二晶片24〇與第三晶片 260。 、—曰曰 進吕之，至少部分第一晶片220是介於第二晶片24〇 與基板210之間，並且第一晶片220於基板21〇之第一表 面212上所形成的第一正投影P22〇是與第二晶片24〇於 第一表面212上所形成的第二正投影p24〇至少部分重 疊。此外，至少部分第二晶片24〇是介於第三晶片26〇與 基板210之間，並且第三晶片於第一表面212上所形 成的第三正投影P260是與第二正投影p24〇至少部分重 疊。在第二實施例中，第一正投影P220例如是位於第二 正投影P240内部，且第二正投影咖例如是位於第三正 投影P26G内部。然而，料者可依其設計需求而改變第 一晶片、第二晶片240與第三晶片·的相對位置， 只要第-正投影P220是與第二正投影p細至少部分重 $，以及第三正投影P260是與第二正投影p24〇至 重疊即可。Based on the above, since at least the t of the wafers of the present invention is the substrate which is provided by the guides and the space occupied by the respective conductive pillars is small to =: the stacked package structure is compared with the wafer of the present invention^ The above and other objects and features of the present invention have been described in detail with reference to the accompanying drawings in which: FIG. A schematic cross-sectional view of a wafer stack package structure, and FIG. 1 is a schematic view showing the projection of the wafer of FIG. Referring to FIG. 1 and FIG. 1 , the wafer stack package structure 100 of the first embodiment includes a substrate 110 , a first wafer 12 , a plurality of electrical conductors 130 , a second wafer 140 , and a plurality of conductive pillars 15 . The substrate 11 has a first surface 112, and the first wafer 120 is disposed on the first surface 112 and forms a first orthographic projection ΐ2() on the first surface 112. The electrical conductors 130 are disposed and electrically connected between the first wafer 120 and the first surface 112. The second wafer 140 is disposed on the first surface 112 13 200830520 UMCD-2006-0167 21623twf.doc / e and forms a second orthographic projection pi4 于 on the first surface 112 , wherein at least part of the first wafer 120 is between The second wafer ho is between the substrate 11 and the first orthographic projection P120 and the second orthographic projection P14 are at least partially overlapped. In addition, the conductive pillars 15 are disposed between and electrically connected between the second wafer 140 and the first surface η of the substrate 11A. Since the second wafer 140 is electrically connected to the substrate 110 by the conductive pillars 15 and the space occupied by the respective conductive pillars 150 is small, each bonding pad 142 of the second wafer 140 corresponds to The area in which the respective conductive pillars 150 are in contact may be small, and the pitch of adjacent pads may be small. Therefore, compared with the wafer stack package structure of the prior art, the second wafer X 140 of the wafer stack package structure 1 of the present embodiment has a second wafer a9M〇 in the case where the number of the pads 142 is fixed. It can be small, and the volume of the wafer stack package structure can be made smaller. Referring to FIG. 1C, a cross-sectional view of another wafer stacked package structure according to a first embodiment of the present invention is shown. In the county that must be described here, the wafer stacking package structure 100 is smaller in size, and the substrate 11 is further provided with a recess 114 on the first surface 112, and the first wafer 12 is folded. 114'. Such features can indirectly shorten the length of these conductive posts 15〇. Referring to FIG. 1 and FIG. 1 again, in the first embodiment, the material of the conductive pillars 150 is selected, for example, from the group consisting of copper, face, gold, metal, titanium, and the like, and the alloys of the alloys. A material. In addition, the conductive bodies 13A of the first embodiment may be conductive bumps, and the material thereof may be a material containing a faulty material: 200830520 UMCD-2006-0167 21623 twf.doc/e material (for example, wrong or tin-alloy) or error-free material. It includes gold, copper, tin or recorded, and may also include alloys or compounds containing gold, copper, tin or nickel. It should be noted that, in order to make the volume of the first wafer 12 可 small, the shape of the first conductors 13 亦可 can also be the same as those of the conductive pillars 150 (but not The surface of the conductor 130 can be the same as the material of the conductive pillars 15〇. In the first embodiment, the wafer stack package structure 1 further includes an adhesive layer 160, a primer layer 170 and a plurality of solder balls 180. The adhesive layer 16 is disposed between the first wafer 120 and the second wafer 14A. The adhesive layer 16 is configured to firmly adhere the second wafer 140 to the first wafer 12A. In addition, the primer layer 170 covers at least the conductive bodies 13 and the conductive pillars 15A. In the first embodiment, the primer layer 170 may further coat the first wafers 12A. The primer layer 170 is used to protect the conductors 13 and the conductive pillars 15A, and when the wafer stack package structure 100 operates to generate heat, the primer layer 17 buffers the heated substrate 110 and the heated first wafer. A phenomenon of thermal strain mismatch between 丨2〇 and between the heated substrate 110 and the heated second wafer 14〇. These solder balls 180 are disposed on the substrate no relative to The first surface U2 of the first surface U2 is electrically connected to other electronic devices (not shown). The solder balls 180 of the first embodiment may be arranged in an array to provide a ball grid. Array, BGA type signal input and output interface. It is worth noting that these solder balls 180 can also be replaced by a plurality of conductive pins or conductive c〇lumn to provide separate pin grids. Pin grid array (PGA) type 15 200830520 UMCD-2006-0167 21623twf.doc/e or column grid array (CGA) type of signal wheel in and out of '丨面' but the latter two are not shown No. No. Second 2A is a schematic cross-sectional view showing a wafer stack package structure according to a second embodiment of the present invention, and FIG. 2B is a schematic view showing the positive projection of the wafer of FIG. 2A on the substrate. Please refer to FIG. 1A, FIG. 2A and FIG. The main difference between the wafer stack package structure 200 of the second embodiment and the wafer stack package structure 100 of the first embodiment is that the wafer stack package structure 200 of the second embodiment includes the first wafer 220 and the second wafer 24 and The third wafer 260, at least a portion of the first wafer 220 is interposed between the second wafer 24 and the substrate 210, and the first wafer 220 is formed on the first surface 212 of the substrate 21 The first orthographic projection P22 is at least partially overlapped with the second orthographic projection p24 formed by the second wafer 24 on the first surface 212. Further, at least a portion of the second wafer 24 is interposed between the third wafer 26〇. The third orthographic projection P260 formed between the substrate 210 and the third wafer on the first surface 212 is at least partially overlapped with the second orthographic projection p24. In the second embodiment, the first orthographic projection P220 is, for example, Located in the second positive The inside of the P240 is projected, and the second orthographic projection coffee is located inside the third orthographic projection P26G. However, the relative position of the first wafer, the second wafer 240, and the third wafer may be changed according to the design requirements, as long as - The orthographic projection P220 is at least partially weighted by the second orthographic projection p, and the third orthographic projection P260 is overlapped with the second orthographic projection p24.
200830520 UMCD-2006-0167 2l623twf.doc/e 弟一實施例中，這此裳—m , _ a u 二弟 ¥笔柱250配置於且電性連 接於弟一晶片240與基板21〇的第— 運 些第二導她27()配 =面12之間’而這 拓210 66筮^ 罝於且电陸連接於第三晶片260與基 、—表面212之間，並且這必導 且電性連接於第-晶片22Gi配置於 這些第-導電柱25〇i 弟:;面212之間。此外， $ 興绝些弟二導電柱270的外型、材皙 一實施例對於導電柱15。(見圖⑷： ί,同於i::贅述。這些導電體230的外型、材質與功 从同；弟—貝施例對於導電體130 (見圖1A)的描述， 故於此亦不再贅述。 第三實施例 圖3A!會示本發明第三實施例之一種晶片堆疊封裝姓 構的剖面示意圖，圖3B繪示圖3A之晶片於基板上形成^ 才又〜的示思圖。請麥考圖2a、圖3A與圖3B，第三實施 例之晶片堆疊封裝結構3〇〇與第二實施例之晶牌疊封裝 結構200的主要不同之處在於，第三實施例之晶片堆疊封 裝結構獅的第—晶片320、第二晶片340與第三晶片36〇 的堆疊方式有所不同。 進言之’至少部分第一晶片320是介於第二晶片34〇 與基板310之間，並且第一晶片32〇於基板31〇之第一表 面312上所形成的第一正投影P320是與第二晶片340於 第一表面312上所形成的第二正投影p34〇至少部分重 疊。此外，至少部分第一晶片320是介於第三晶片360與 基板310之間，並且第一正投影P320是與第三晶片360 17 200830520 UMCD-2006-0167 21623twf.doc/e 於基板310之第一 至少部分重疊。 表面312上所形成的第三正投影 P360 f) i 電體330配置於且 署!^日in 間’且另—部分這些導電體330配 置於且讀連接於第一晶片320與第三晶片細之間。此 外’运些第-導妹350配置於且電料接於第二晶片補 與基板的第-表面312之間，以及這些第 配置於且電性連接於第三⑼⑽與第—表面312之間。 另!!，这些弟—導電柱350與這些第二導電柱370的外型、 材質與功能類同於第—實施例對於導電柱15G (見圖 的描述’故於此不再贅述。這些導電體现的外型 與功能類同於第-實關對於導電體13G (見圖 述，故於此亦不再贅述。 田 圖3C繪示本發明第三實施例之另一種晶片堆疊封裝 結構的剖面示意圖，圖3D繪示圖3C之晶片於基板上 正投影的示意圖。請參考圖3C與圖3D，晶片堆疊封裝結 構300’與晶片堆疊縣結構的主要*同之處在於，^ 片堆疊封裝結構300,不具有第三晶片遍（見圖3A) 須強調岐，第二晶片34〇,於基板31G，之第—表面312, 上所形成的第二正投影P340,的面積可小於第一晶片32〇, 於基板31G，之第-表面312，上所形成的第—正 的面積。 差力實施例 圖4A繪示本發明第四實施例之一種晶片堆疊封裴結 18 200830520 UMCD-2006-0167 21623twf.d〇c/e 構的剖面示意圖，圖4B繪示圖4A之晶片於基板上形成正 投影的示意圖。請參考圖2A、圖4A與圖4B，第四實施 例之晶片堆疊封裝結構400與第二實施例之晶片堆疊封裴 結構200的主要不同之處在於，第四實施例之晶片堆疊封 裝結構400的第一晶片420、第二晶片440與第三晶片460 的堆疊方式有所不同。 進言之，第一晶片420與第二晶片440是介於第三晶 ζ) 片460與基板41〇之間，並且第三晶片460於基板410之 第一表面412上所形成的第三正投影ρ46()是分別與第一 晶片420於第一表面412上所形成的第一正投影p42QR 及第二晶片440於第一表面412上所形成的第二正投影 P420至少部分重疊。在第四實施例中，第一正投影p42〇 與第二正投影P440例如是分別位於第三正投影p46〇内 部。然而，設計者可依其設計需求而改變第一晶片42〇、 第二晶片440與第三晶片460的相對位置，只要第一正投 影P420是與第三正投影P460至少部分重疊，以及第二= I 投影p440是與第三正投影P460至少部分重疊即可。 第四實施例中，這些第一導電體43〇配置於且電性連 接於第一晶片420與基板410之第一表面412之間，而這 些第二導電體450配置於且電性連接於第二晶片44〇與第 一表面412之間，並且這些導電柱47〇配置於且電性連接 於第三晶片460與第一表面412之間。此外，這些第一導 電體430與這些第二導電體450的外M、材質與 於第-實施例對於導電體13〇 (見圖1A)的描述，故於此 19 200830520 UMCD-2006-0167 21623twf.doc/e 不ϋ述射這i導電柱470的外型、材質與功能類同於第 導電柱150 (見圖1A)的描述，故於此亦不 的優=所述’本發明之晶片堆疊封裝結構至少具有以下 -、由於本發明之晶牌疊縣 是藉由這些導電柱而電性連 o i 斜雇彻ϊ餘所佔制㈣較小，所以此w的各個接塾 二= 導電柱相接觸的面積可較小，並且相鄰這些接 明之晶片堆疊封:結較小’進而使得本發 少-：置=發明之晶片堆疊封農結構的基板可具有至 體積的凹陷’所以本發明之晶片堆疊封裝結構的 雖然本發明已以較佳實施例揭露如上，然其並非用以 發明’任何所屬技術領域中具有通常知識者，在不 ==之精神和範圍内，當可作些許之更動與潤:不 =本發明之保魏圍當視後附之申請專鄕圍所界定者 【圖式簡單說明】 構的本發明第一實施例之一種晶片堆叠崎结 20 200830520 UMCD-2006-0167 21623twf.doc/e 圖 圖。 IB繪示圖1A之晶片於基板上形成正投 影的示意 圖1C繪示本發明第一實施例之另_種晶片 結構的剖面示意圖。 ％ 圖 :封裝 2A繪示本發明第二實施例之_種晶片堆聂 構的剖面示意圖。 &封I結 2B繪示圖2A之晶片於基板上形成正投影的示 圖 c 圖 意 圖3A繪示本發明第三實施例之一種晶片堆疊 構的剖面示意圖。 & 圖3B繪示圖3A之晶片於基板上形成正投影的 圖 示意 圖3C繪示本發明第三實施例之另—種晶片堆疊封壯 結構的剖面示意圖。 I ^ 圖3D繪示圖3C之晶片於基板上形成正投影的示音 圖。 、思 •圖4A繪示本發明第四實施例之一種晶片堆疊封裝結 構的剖面不意圖。 圖4B緣示圖4A之晶片於基板上形成正投影的示咅 圖。 ^ 【主要元件符號說明】 100、100’、200、300、300’、400 :晶片堆疊封裝結 構 110、110’、210、310、310’、410 :基板 21 200830520 UMCD-2006-0167 21623twf.doc/e 112、112’、116、212、312、312’、412 :表面 114’ ：凹陷 120、120,、140、220、240、260、320、320,、340、 340’、360、420、440、460 :晶片 130、230、330、430、450 :導電體 142 :接墊 150、250、270、350、370、470 :導電柱 160 :黏著層 170 :底膠層 180 :焊球 P120、P140、P220、P260、P260、P320、P320,、P340、 P340’、P360、P420、P440、P460 :正投影 22200830520 UMCD-2006-0167 2l623twf.doc/e In an embodiment, the sputum-m, _ au two-person pen pen 250 is disposed and electrically connected to the first of the wafer 240 and the substrate 21 The second guides her 27() with the face 12' and the extension is electrically connected to the third wafer 260 and the base, the surface 212, and this must be electrically connected The first wafer 22Gi is disposed between the first conductive pillars 25; In addition, the appearance of the second conductive pillar 270 is reduced by an embodiment of the conductive pillar 15. (See Figure (4): ί, the same as i:: narration. The appearance, material and work of these conductors 230 are the same; the description of the conductor 130 (see Figure 1A) is not described here. 3A is a schematic cross-sectional view of a wafer stack package of the third embodiment of the present invention, and FIG. 3B is a schematic diagram of the wafer of FIG. 3A formed on the substrate. The main difference between the wafer stack package structure 3 of the third embodiment and the cell stack package structure 200 of the second embodiment is that the wafer stack of the third embodiment is the same as that of the third embodiment, FIG. 3A and FIG. 3B. The stacking manner of the first wafer 320, the second wafer 340, and the third wafer 36A of the package structure lion is different. In other words, at least a portion of the first wafer 320 is interposed between the second wafer 34 and the substrate 310, and The first orthographic projection P320 formed by the first wafer 32 on the first surface 312 of the substrate 31 is at least partially overlapped with the second orthographic projection p34 formed on the first surface 312 of the second wafer 340. At least a portion of the first wafer 320 is interposed between the third wafer 360 and the substrate 310. And the first orthographic projection P320 is at least partially overlapped with the third wafer 360 17 200830520 UMCD-2006-0167 21623 twf.doc/e on the substrate 310. The third orthographic projection P360 formed on the surface 312 f) 330 is disposed between the first and second wafers 320 and the third wafer is disposed between the first and second wafers. In addition, the first guides 350 are disposed between the second wafer and the first surface 312 of the substrate, and the first portion is electrically connected between the third (9) (10) and the first surface 312. . In addition, the appearance, material and function of the conductive pillars 350 and the second conductive pillars 370 are similar to those of the first embodiment for the conductive pillars 15G (see the description of the drawings), and thus will not be described herein. The appearance and function of the embodiment are the same as those of the first embodiment for the electrical conductor 13G (see the description, and therefore will not be further described herein. FIG. 3C illustrates another wafer stacking package structure according to the third embodiment of the present invention. 3D is a schematic view showing the positive projection of the wafer of FIG. 3C on the substrate. Referring to FIG. 3C and FIG. 3D, the main difference of the wafer stack package structure 300' and the wafer stack county structure is that the chip stack package The structure 300 does not have a third wafer pass (see FIG. 3A). It should be emphasized that the second wafer 34, the second orthographic projection P340 formed on the first surface 312 of the substrate 31G, may have a smaller area than the first The wafer 32A, the first positive area formed on the first surface 312 of the substrate 31G. Differential embodiment FIG. 4A illustrates a wafer stacking and sealing junction of the fourth embodiment of the present invention. 200830520 UMCD-2006 -0167 21623twf.d〇c/e structure schematic view, Figure 4B shows Figure 4 A schematic diagram of a positive projection of a wafer on A. Referring to FIG. 2A, FIG. 4A and FIG. 4B, the main difference between the wafer stack package structure 400 of the fourth embodiment and the wafer stack package structure 200 of the second embodiment. The first wafer 420, the second wafer 440, and the third wafer 460 of the wafer stack package structure 400 of the fourth embodiment are stacked differently. In other words, the first wafer 420 and the second wafer 440 are interposed. A third orthographic projection ρ46() formed by the third wafer 460 on the first surface 412 of the substrate 410 is on the first surface 412 of the first wafer 420, respectively. The formed first orthographic projection p42QR and the second orthographic projection 420 formed by the second wafer 440 on the first surface 412 at least partially overlap. In the fourth embodiment, the first orthographic projection p42 〇 and the second orthographic projection P 440 For example, they are respectively located inside the third orthographic projection p46. However, the designer can change the relative positions of the first wafer 42〇, the second wafer 440 and the third wafer 460 according to the design requirements, as long as the first orthographic projection P420 is The third orthographic projection P460 is at least The first and second projections 440 are at least partially overlapped with the third orthographic projection P460. In the fourth embodiment, the first electrical conductors 43 are disposed and electrically connected to the first wafer 420 and the substrate 410. The second conductive body 450 is disposed between the first surface 412 and electrically connected between the second wafer 44 and the first surface 412, and the conductive pillars 47 are disposed and electrically connected to the third surface. The first conductive body 430 and the outer surface M of the second conductive body 450 are made of the first embodiment for the conductor 13 (see FIG. 1A). 19 200830520 UMCD-2006-0167 21623twf.doc/e It is to be noted that the shape, material and function of the i-conductive pillar 470 are similar to those of the first conductive pillar 150 (see Fig. 1A), so Preferably, the 'wafer stack package structure of the present invention has at least the following--because the crystal card of the present invention is electrically connected to the oi by the conductive pillars, and the occupation is small (4). Each of the junctions of the w = the area where the conductive pillars are in contact can be small, and adjacent to these The wafer stacking of the wafer: the junction is smaller, and thus the present invention is less - the substrate of the wafer stacking and sealing structure of the invention can have a recess to the volume. Therefore, although the present invention has been preferred in the wafer stacking package structure of the present invention. The embodiments are disclosed above, but they are not intended to be used in the art of any of the ordinary skill in the art, and in the spirit and scope of the non-==, when a little change and run can be made: not = the Wei Weiwei of the present invention A wafer stacking of a first embodiment of the present invention is set forth in the following description of the application specification [2008]. IB is a schematic view showing the wafer of FIG. 1A forming a positive projection on a substrate. FIG. 1C is a schematic cross-sectional view showing another wafer structure according to the first embodiment of the present invention. % Figure: Package 2A shows a schematic cross-sectional view of a wafer stack structure of a second embodiment of the present invention. & I-B 2B shows a diagram of the wafer of FIG. 2A forming an orthographic projection on a substrate. FIG. 3A is a cross-sectional view showing a wafer stack structure according to a third embodiment of the present invention. 3B is a schematic view showing the positive projection of the wafer of FIG. 3A on the substrate. FIG. 3C is a schematic cross-sectional view showing another wafer stack structure of the third embodiment of the present invention. I ^ Figure 3D is a pictorial diagram of the wafer of Figure 3C forming an orthographic projection on a substrate. Fig. 4A is a cross-sectional view showing a structure of a wafer stack package of a fourth embodiment of the present invention. Figure 4B is a perspective view showing the wafer of Figure 4A forming an orthographic projection on a substrate. ^ [Main component symbol description] 100, 100', 200, 300, 300', 400: wafer stack package structure 110, 110', 210, 310, 310', 410: substrate 21 200830520 UMCD-2006-0167 21623twf.doc /e 112, 112', 116, 212, 312, 312', 412: surface 114': recesses 120, 120, 140, 220, 240, 260, 320, 320, 340, 340', 360, 420, 440, 460: wafer 130, 230, 330, 430, 450: conductor 142: pads 150, 250, 270, 350, 370, 470: conductive pillar 160: adhesive layer 170: primer layer 180: solder ball P120, P140, P220, P260, P260, P320, P320, P340, P340', P360, P420, P440, P460: Orthographic projection 22