200830508 20767twf.doc/n 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種電鍍(electroplating)的方法，且特 別是有關於一種無需額外增加電鍍導線及其配置空間的電 鍍方法。 【先前技術】 、 在目别較為業界所常用的晶片封裝技術中，其主要步 驟可大致分為晶圓切割(Die Saw)、黏晶(Die Bond)、打線 接合(Wire Bond)、封膠(Mold)以及切割(Trim)等。 其中在進行上述打線接合的步驟時，一般是利用一金 (Au)線連接封裝基板上與晶片上的鲜塾(b〇n(jing pa(j)，使 晶片與封裝基板電性連接(electriCaUy c〇nnected)。其中封 裝基板上銲墊的材質以銅(CU)較為常見，但是銅金屬很容 易文到外界的水氣或氧氣的影響，在銅表面產生氧化銅， 進而造成導電性不佳以及電阻值增加等現象。因此，習知 在進行打線接合的步驟前，會將封裝基板進行一電鍍製 程，以於銲塾表面鑛上其他種類的金屬或合金，例如是鎳 金合金，以減少銅金屬表面氧化銅的生成。 、請參照目1A至圖1D，所示為習知之封裝基板電鐘方 法的流程示意圖。請參照圖1A，習知之封裝基板包括一基 板100、一電鍍導線(platingbar)11〇、多個銲墊12〇以及多 線130。其中電鐘導線11〇、多個銲墊12〇與多條導線 130皆位於基板100上，且電鍵導線u〇經由導線13〇與 200830508 20767twf.doc/n 銲墊120電性連接。 請繼續參照圖1B’將縣基板浸泡於—具有電鍍液 (plating liqUid)15〇的電鍍槽14〇中，並施予電鍍導線ιι〇 -外加偏壓’使多個銲藝12G的表面進行—電鍵反應。 請繼續參_ 1C ’進行上述之紐反應之後，會在各 個銲塾12G的表面上形成_層紐金屬122，成為具 鍍金屬122的銲墊12〇。 請繼續參照圖1D，沿著圖1C中所示的切割線16〇， 將封裝基板上具有電鍍導線11〇部份的基板1〇〇切除，使 各具有電鍍金屬122的銲墊120之間彼此斷路。即完成 知封裝基板的電鍍方法。 由上述習知的封裝基板電鍍方法中可知，習知的封裝 基板需要額外增加電鍍導線以及電鍍導線的配置空間，且 電鍍反應完成之後又需將具有電鍍導線部份的基板移除， 不僅增加製程的成本與複雜度，且亦使得封裝基板上線路 的積集度受到限制。 ' 【發明内容】 本發明之目的是提供一種電艘方法，不需額外增加電 錢導線及其配置空間，即可進行電鍍的方法。 為達上述或是其他目的，本發明提出一種電链方法， 包括提供一埋入式線路基板，此基板具有至少一第一金屬 層以及多個銲墊層，其中第一金屬層位於埋入式線路基板 的外側，且鮮墊層位於第一金屬層的内側。接著移除部份 的第一金屬層，以於第一金屬層中形成多個待鍍區，且各 200830508 20767twf.doc/n $待鐘區内暴露出各銲墊層。再於各個待舰巾的各 層上，電鍍一層第二金屬層。 在本發明之一實施例中，上述之形成接 =於第：金屬層上形成-抗電_。接著進^圖案化^ 形成圖案化之抗電鍍膜。爾後再進行製程， 私除未被圖案化之抗電鍍膜覆蓋的第一金屬層。 芦上tir狀—實施财，上述之於各待鍍“之鋅墊 ㈢B鍍弟—金屬層後’更包括移除_化之抗電鑛膜。 臈後在ίί明之—實施财’上述之移除®案化之抗電鍵 、，更匕括移除圖案化之抗電鍍膜下之第一金屬層。 第-ΐίΓ之—實施例中，上述之埋入式線路基板^括一 上至屬層、一第一下金屬層、一介電層、多個上鲜塾 固下銲塾層。其中介電層位於第-上金屬層與第 而下銲墊㈣位时電層岐位於第一下金 上金tr之—貫施例巾，上述之電鍍方法可同時於第一 里屬層表面以及第一下金屬層表面進行。 層，例中，上述之待舰對應於各銲墊 待鍍區之見度略小於對應之各銲墊層的寬度。 材質相實關巾，上述H朗與銲墊層的 貝相同，其材質包括銅。 錦金2明之—實施射’上述之第二金屬層的材質包括 7 200830508 20767twf.doc/n 、本發明之-實施财，上述之電鍍方法，更包括於 入式線路基板内形成至少—導電孔，且上述之導電孔 相對應之一上銲墊層與一下鮮墊層。 、 -為讓本發明之上述和其他目的、特徵和優點能更明顯 易懂，下文特舉較佳實施例，並配合所附圖式，作 明如下。 ^ 本發明因採用埋入式線路基板、抗電鐘膜以及第 屬層的電财法，因此可以在電鐘方法中選擇性的於待鍵 區的表面進行電鍍，與習知需增加電料線的方法^ 同，故可簡化電鍍方法以及節省電鍍方法的成本。 【實施方式】 圖2Α至圖2F為本發明一實施例之電鍍方法流程示意 圖。凊芩照圖2Α，首先提供一埋入式線路基板2〇〇，此埋 入式線路基板200包括一第一上金屬層21〇、一第一下金 屬層220、一介電層230、多個上銲墊層212以及多個下銲 。 塾層2U。其中介電層230位於第一上金屬層21〇與第一 下金屬層220之間，而上銲墊層212位於介電層23〇'内且 位於第一上金屬層212的内側，下銲墊層222則位於介電 ^ 230内且位於第一下金屬層220的内側。在本實施例中， 第一上金屬層210、第一下金屬層22〇、多個上銲墊層212 以及多個下銲墊層222的材質皆為相同，例如是銅。9 在本實施例中，上述之第一上金屬層21〇以及第一下 金屬層220，與習知的電鍍導線具有類似的功用，可做為 200830508 20767twf.doc/n 進行電鍍反應時的導線之用。然而第一上金屬層21〇以及 第一下金屬層220是直接形成於埋入式線路基板2〇〇之介 電層23G的兩側表面上，不同於習知中電料線的配置方 法，故不會增加基板的配置空間。 ^請繼續參照圖2B，接下來是於第一上金屬層210與 第一下金屬層220的表面各形成一抗電鍍膜24〇，再接著 進行一圖案化製程，以形成圖案化之抗電鍍膜24〇。在本 、 實施例中，形成抗電鍍膜的方法例如是利用旋轉塗佈(spin gating)法’將抗電鍍材料分別塗佈於第一上金屬層2ι〇與 第下金屬層220上，再進行烘烤(baking)的步驟，使得抗 笔鑛材料硬化成為抗電鑛膜240。之後再將先置μ晉於p 電鍍膜240的上方，並利用一光源例如是紫外光，照射抗 屯鍵膜240，使得反應光源照射到的抗電鍍膜24〇可經由 後續的製私移除，而形成一圖案化之抗電鑛膜24〇。此抗 電鍍膜240不僅本身不會進行電鑛反應，且可以使抗電鍵 膜240所覆蓋住的第一上金屬層210與第一下金屬層22〇 U 亦不會在後續的步驟中進行電鍍反應。 請繼續參照ffl 2C及圖2D，進行一钕刻製程，將未被 圖案化之抗電鍍膜240所覆蓋的第一上金屬層21〇以及第 一下金屬層220移除，並暴露出對應的上銲墊層以及 下銲塾層222。此外，在本實施例中所採用的侧製程例 如是濕式蝕刻(wet etching)製程，採用的蝕刻劑例如是過氧 化氫（hydrogen peroxide，H2〇2)與氫氧化銨（amm〇nium hydroxide，NEU0H)的混合液，以移除銅金屬。 9 200830508 20767twf.doc/n 請繼續參關2D，經由上述之細】製程後 金屬層210與第一下金屬層22〇中 上 謂。此外，各待魅25G具有—了多個待鍵區 塾層m或下銲墊層222具有—寬見/j1 :而對應的上輝 ^ 見度D2，在本實施例中， D1<D2，但不限定於此，只要經圖案化之第一上金 與上鲜，212 (或其線路）電性連接，且經圖“之第 -下金屬層220和下鮮塾層222 (或其線路）電性連 可0 請繼續參照圖2E，進行—電鍍製程，於待鍵區25〇 中之上銲塾層2丨2與下銲墊層如上電鍍第二金屬層 260。由前述可知，在本實施例中因D1<D2，故第一上金 屬層210與上銲墊層212間以及第一下金屬㉟do與下鲜 墊層222 Μ皆為通路。因此，當外加—偏壓於第一上金屬 層210或第一下金屬層22〇上時，即可進行電鍍製程。 更詳細的說，上述之電鍍製程包括，將圖2D中的埋 入式線路基板200置於一電鍍液(未繪示）中，並施予一外 。 加偏壓於上第一上金屬層210與第一下金屬層220上，即 可於未被圖案化之抗電鍍膜240所覆蓋的上銲墊層212與 下銲墊層222的表面進行電鍍，以形成第二金屬層26〇， 並於第二金屬層260形成之後，移除圖案化之抗電鍍膜 240。此外，在本實施例中，第二金屬層26〇所採用的材質 例如是鎳金合金(Ni-Au alloy)。 凊繼續參照圖2F，將圖案化之抗電鑛膜240所覆蓋的 第上金屬層210以及第一下金屬層220移除。在本實施 200830508 20767twf.doc/n 例中採用濕式蝕刻法，例如是一具有選擇性的蝕刻劑，可 以選擇性的移除銅金屬，而保留鎳金合金的部份。 在其他實施例中，更可視製程所需，於基板中形成數 個導電孔（未緣示），用以導通相對應之一上銲墊層212 與一下銲墊層222，作為後續晶片封裝之用。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electroplating method, and in particular to an electroplating method which does not require an additional plating wire and a space for arrangement thereof. [Prior Art] In the chip packaging technology commonly used in the industry, the main steps can be roughly divided into Die Saw, Die Bond, Wire Bond, and Sealant ( Mold) and cutting (Trim) and so on. In the step of performing the above-mentioned wire bonding, a gold (Au) wire is generally used to connect the fresh enamel on the package substrate (b〇n (jing pa(j), and the wafer and the package substrate are electrically connected (electriCaUy). C〇nnected). The material of the pad on the package substrate is more common with copper (CU), but the copper metal is easy to affect the external water vapor or oxygen, causing copper oxide on the copper surface, resulting in poor conductivity. And the phenomenon that the resistance value increases, etc. Therefore, it is conventional to perform an electroplating process on the package substrate before the step of bonding the wire to weld other kinds of metals or alloys on the surface of the soldering surface, such as nickel gold alloy, to reduce The formation of copper oxide on the surface of the copper metal. Please refer to FIG. 1A to FIG. 1D, which is a schematic flow chart of a conventional method for packaging a substrate electric clock. Referring to FIG. 1A, a conventional package substrate includes a substrate 100 and a plating bar (platingbar). 11〇, a plurality of pads 12〇 and a plurality of wires 130. The electric clock wires 11〇, the plurality of pads 12〇 and the plurality of wires 130 are all located on the substrate 100, and the key wires u〇 are connected via wires 13 and 2008. 30508 20767twf.doc/n The soldering pad 120 is electrically connected. Please continue to refer to FIG. 1B' to soak the county substrate in the plating bath 14〇 with plating liquid (plating liqUid) 15 ,, and apply the plating wire ιι〇-plus The bias voltage enables the surface of a plurality of soldering art 12G to be subjected to a key reaction. Please continue to participate in the above-mentioned reaction, and then a layer of gold metal 122 is formed on the surface of each solder fillet 12G to become a plated metal 122. The solder pad 12 is continued. Referring to FIG. 1D, along the cutting line 16A shown in FIG. 1C, the substrate 1 having the plated wire 11 portion on the package substrate is cut away so that each has a plating metal 122. The solder pads 120 are disconnected from each other. That is, the plating method of the package substrate is completed. It is known from the above-mentioned conventional package substrate plating method that the conventional package substrate needs to additionally increase the arrangement space of the plating wires and the plating wires, and the plating reaction is completed. After that, the substrate having the plated wire portion needs to be removed, which not only increases the cost and complexity of the process, but also limits the integration of the lines on the package substrate. The object is to provide an electric boat method, which can be electroplated without additional wires and their arrangement space. To achieve the above or other purposes, the present invention provides an electric chain method, including providing a buried line. a substrate having at least a first metal layer and a plurality of pad layers, wherein the first metal layer is located outside the buried circuit substrate, and the fresh pad layer is located inside the first metal layer. The first metal layer is formed in the first metal layer to form a plurality of regions to be plated, and each of the pads is exposed in each of the 200830508 20767 twf.doc/n$ areas. A layer of a second metal layer is electroplated on each layer of each of the tows. In an embodiment of the invention, the forming is performed on the metal layer to form an anti-electricity. Then, patterning is performed to form a patterned anti-plating film. The process is then carried out to remove the first metal layer that is not covered by the patterned anti-plating film. The tir-like shape of the reed - the implementation of the above, after the "Zinc pad (3) B plating of the metal-metal layer to be plated", including the removal of the anti-electrical film of the _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ In addition to the chemical resistance of the case, the first metal layer under the patterned anti-plating film is removed. In the embodiment, the buried circuit substrate includes an upper layer. a first lower metal layer, a dielectric layer, and a plurality of upper ruthenium lower soldering layer, wherein the dielectric layer is located at the first upper metal layer and the lower and lower pads (four) The above-mentioned plating method can be simultaneously performed on the surface of the first inner layer and the surface of the first lower metal layer. In the layer, for example, the above-mentioned waiting ship corresponds to each pad to be plated. The visibility is slightly smaller than the width of the corresponding pad layer. The material is solidly closed, and the above-mentioned H-lang is the same as that of the pad layer, and the material thereof includes copper. Jinjin 2 Mingzhi- implements the above-mentioned second metal layer The material includes 7 200830508 20767twf.doc/n, the invention-implementation, the above electroplating method, and further includes At least one conductive hole is formed in the circuit substrate, and the conductive hole corresponds to one of the pad layer and the fresh pad layer. The above and other objects, features and advantages of the present invention are more apparent and easy to understand. The preferred embodiment is described with reference to the accompanying drawings, as follows: ^ The present invention can be selected in the electric clock method by using the embedded circuit substrate, the anti-electric clock film, and the electrical layer method of the first layer. Electroplating on the surface of the keypad to be used is the same as the conventional method of adding an electric wire, so that the electroplating method and the cost of the electroplating method can be simplified. [Embodiment] FIG. 2A to FIG. 2F are an embodiment of the present invention. The schematic diagram of the electroplating method is as follows. Referring to FIG. 2, a buried circuit substrate 2 is first provided. The buried circuit substrate 200 includes a first upper metal layer 21 and a first lower metal layer 220. a dielectric layer 230, a plurality of upper pad layers 212, and a plurality of underlying pads. The dielectric layer 230 is located between the first upper metal layer 21 and the first lower metal layer 220, and the upper pad The layer 212 is located in the dielectric layer 23〇' and is located on the first layer The lower pad layer 222 is located inside the dielectric layer 230 and is located inside the first lower metal layer 220. In this embodiment, the first upper metal layer 210 and the first lower metal layer 22, The materials of the plurality of upper pad layers 212 and the plurality of lower pad layers 222 are the same, for example, copper. 9 In this embodiment, the first upper metal layer 21〇 and the first lower metal layer 220 are The conventional electroplated wire has a similar function and can be used as a wire for electroplating reaction in 200830508 20767 twf.doc/n. However, the first upper metal layer 21 and the first lower metal layer 220 are directly formed in the buried type. On both side surfaces of the dielectric layer 23G of the circuit substrate 2, unlike the conventional method of arranging the electric material lines, the arrangement space of the substrate is not increased. Continuing to refer to FIG. 2B, an anti-plating film 24 is formed on the surfaces of the first upper metal layer 210 and the first lower metal layer 220, and then a patterning process is performed to form a patterned anti-electricity. The coating is 24 inches. In the present embodiment, the method of forming the anti-plating film is, for example, applying a plating resist material to the first upper metal layer 2 ι and the lower metal layer 220 by a spin coating method, and then performing the method. The step of baking causes the anti-pen mineral material to harden into the anti-mine film 240. Then, the first layer is applied to the upper portion of the p plating film 240, and the anti-electrode film 240 is irradiated with a light source such as ultraviolet light, so that the anti-plating film 24 照射 irradiated by the reaction light source can be removed through subsequent etching. And forming a patterned anti-mineral film 24 〇. The anti-plating film 240 not only does not perform the electrominening reaction itself, but also prevents the first upper metal layer 210 and the first lower metal layer 22 〇U covered by the anti-electrode film 240 from being plated in a subsequent step. reaction. Referring to FIG. 2C and FIG. 2D, an engraving process is performed to remove the first upper metal layer 21 and the first lower metal layer 220 covered by the patterned anti-plating film 240, and expose corresponding ones. The upper pad layer and the lower pad layer 222. In addition, the side process used in the embodiment is, for example, a wet etching process, and the etchant used is, for example, hydrogen peroxide (H 2 〇 2) and ammonium hydroxide (amm 〇 nium hydroxide, A mixture of NEU0H) to remove copper metal. 9 200830508 20767twf.doc/n Please continue to participate in 2D, after the above process, the metal layer 210 and the first lower metal layer 22 are said to be in the middle. In addition, each of the charms 25G has a plurality of to-be-keyed layer layers m or a lower pad layer 222 having a width of /j1: and a corresponding upper luminance D2, in this embodiment, D1 < D2, However, the present invention is not limited thereto, as long as the patterned first gold and the upper fresh, 212 (or its line) are electrically connected, and the figure "the first-lower metal layer 220 and the lower fresh layer 222 (or its line) The electrical connection can be continued. Referring to FIG. 2E, the electroplating process is performed, and the second metal layer 260 is plated on the solder layer 2丨2 and the lower pad layer in the keypad 25〇. As can be seen from the foregoing, In this embodiment, because D1 < D2, the first upper metal layer 210 and the upper pad layer 212 and the first lower metal 35do and the lower fresh pad layer 222 are both paths. Therefore, when the external bias is applied to the first When the upper metal layer 210 or the first lower metal layer 22 is on the upper surface, the electroplating process can be performed. In more detail, the electroplating process described above includes placing the buried circuit substrate 200 of FIG. 2D in a plating solution (not In the drawing, and applying an external force. The biasing is applied to the upper first upper metal layer 210 and the first lower metal layer 220, so as to be unpatterned. The upper pad layer 212 and the surface of the lower pad layer 222 covered by the coating 240 are plated to form a second metal layer 26, and after the second metal layer 260 is formed, the patterned plating resist 240 is removed. In addition, in the present embodiment, the material used for the second metal layer 26 is, for example, a Ni-Au alloy. 凊Continuing to refer to FIG. 2F, the patterned upper surface of the anti-mine film 240 is covered. The metal layer 210 and the first lower metal layer 220 are removed. In the embodiment of 200830508 20767 twf.doc/n, a wet etching method, such as a selective etchant, is used to selectively remove copper metal. Retaining a portion of the nickel-gold alloy. In other embodiments, a plurality of conductive holes (not shown) are formed in the substrate to turn on the corresponding one of the pad layer 212 and the lower pad. Layer 222 is used as a subsequent wafer package.
值付庄思的是’本實施例中是採取第一上金屬層21〇 與第一下金屬層220同時進行的電鍍方法，而在其他實施 例中，亦可以採取先將其中一面進行上述之電鏡方法，之 後再對另一面進行上述之電鍵方法。 此外，在本實施例中，所採用的埋入式線路基板為具 有第一上金屬層210以及第一下金屬層22〇之雙面式的埋 入式線路基板200，而在其他實施例中，本電鐘方法亦適 用於僅具有第-上金屬層21G之單面式的埋入式線路基 板0 綜上所述，本發明由於採用抗電鑛膜、第一上金屬 層、第-下金屬層以及搭配埋人式線路基板的電鍵方法， 可以於待舰内電麟定金屬如鎳金合金等，以減少基板 上銅銲墊層發生氧化的機會。由於本發明與習知中採用電 鍍導線的方法不同，可免技前基板空間給電鑛導線， =及在進行電鍍後移除電鑛導線的步驟。對於電鑛方法的 間化以及成本的節省皆能有所助益。 =本發㈣哺佳實關縣如上，然其並非用以 二明丄任何熟習此技藝者，在不脫離本發明之精神 和靶圍内’虽可作些許之更動與潤飾，因此本發明之保護 11 200830508 20767twf.doc/n 範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1A至圖1D為習知之封裝基板電鍍方法的流程示意 圖0 圖2A至圖2F為本發明一實施例之電鍍方法流程示意 圖0The value of the value of Zhuangsi is 'in this embodiment is to take the first upper metal layer 21 〇 and the first lower metal layer 220 simultaneously, the plating method, and in other embodiments, may also take one of the above to carry out the above The electron microscopy method is followed by the above-described electric key method on the other side. In addition, in the embodiment, the buried circuit substrate used is a double-sided buried circuit substrate 200 having a first upper metal layer 210 and a first lower metal layer 22, but in other embodiments, The present electric clock method is also applicable to a single-sided buried circuit substrate having only the first-upper metal layer 21G. In summary, the present invention adopts an anti-mineral film, a first upper metal layer, and a first-lower The metal layer and the electric key method with the embedded circuit substrate can be used to replace the metal such as nickel-gold alloy in the ship to reduce the chance of oxidation of the copper pad on the substrate. Since the present invention differs from the conventional method of using an electroplated wire, the front substrate space can be omitted to give the electric ore wire, and the step of removing the electric ore wire after electroplating. It can be helpful for the inter-mineralization of electric ore methods and cost savings. =本发(四), according to the above, but it is not intended to be used by anyone skilled in the art, without departing from the spirit and scope of the present invention, although some modifications and retouchings may be made, the present invention Protection 11 200830508 20767twf.doc/n Scope is subject to the definition of the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A to FIG. 1D are flow diagrams of a conventional method for electroplating a package substrate. FIG. 2 is a schematic diagram showing a flow of a plating method according to an embodiment of the present invention.
【主要元件符號說明】 100 基板 120 銲墊 130 導線 150 電鍍液 200 埋入式線路基板 212 上銲墊層 222 下銲墊層 240 抗電鍍膜 260 第二金屬層[Main component symbol description] 100 substrate 120 solder pad 130 wire 150 plating solution 200 buried circuit substrate 212 upper pad layer 222 lower pad layer 240 anti-plating film 260 second metal layer
110 :電鍍導線 122 :電鍍金屬 140 :電鍍槽 160 :切割線 210 :第一上金屬層 22〇 :第一下金屬層 230 ·介電層 250 :待鍍區 Μ :光罩 12110 : Electroplated wire 122 : Electroplated metal 140 : Electroplating bath 160 : Cutting line 210 : First upper metal layer 22 〇 : First lower metal layer 230 · Dielectric layer 250 : Area to be plated Μ : Photomask 12