TW200830470A - Charge trapping memory cell and method of manufacturing the same - Google Patents

Abstract

A charge trapping memory cell and a method of manufacturing the same. First, a substrate is provided, and a first insulating layer is formed on the substrate. Then, a trapping layer is deposited on the first insulating layer via a first gas and a second gas. The flow ratio of the first gas to the second gas is 2:1. Next, a second insulating layer is formed on the trapping layer. Then, a bit-line region is formed at the substrate. Further, a gate electrode is formed on the second insulating layer. The first insulating layer, the trapping layer, the second insulating layer and the gate electrode compose a stack structure of the cell. Moreover, a spacer is formed on the side-wall of the stack structure.

Description

200830470,

- Migration: ι / child, aW3296PA IX. Description of the invention: [Technical field of the invention] The present invention relates to a memory cell of a memory and a method of manufacturing the same, and in particular to a memory cell of a stacked structure memory And its manufacturing method. [Prior Art] A memory device that can store non-volatile information, such as read-only memory (ROM), programmable read-only memory (PROM), can be eliminated. Erasable Programmable ROM (EPROM) and other advanced memory devices are widely used in electronic computers, communication devices and consumer electronics. Among them, the high-level memory device includes a current-erasable programmable read-only memory (EEPROM), a flash EEPROM, and a charge trapping memory. Since the memory cell of the stacked structure memory can store two bits of data, it has a high memory density and is compatible with the original complementary metal oxide semiconductor (CMOS). The process makes the stacked structure memory one of the main applications and development directions of the current memory device. In general, the components of the stacked structure memory can be divided into an array area and a peripheral area. The array area includes multiple insulation/storage/insulating and 6 200830470,

The second gate _ muscle. iW3296PA " gate structure, as a memory cell unit of stacked structure memory, each insulation / storage / insulation structure is separated from each other by a barrier buffer layer. In addition, the stacked structure memory system is used for the edge of the array region to perform a diffusion barrier and a silver mark of a spacer to form a contact hole to electrically connect the corresponding plurality of memory cells. However, as the memory system progresses, the size of memory components has gradually shrunk, such as 〇·〇75 nm, or even 〇〇45 nm. As a result, there is a problem that an offset occurs in the remaining time, causing an error in the position of the C contact hole. The current practice is to change the traditional insulation spacer to a nitride spacer for self-contained

I align with the process of Self-Align Contact etching (SAC etching). However, the above-described method of using a nitride material spacer causes an increase in the threshold voltage of the memory cell. The higher threshold voltage relatively increases the operating voltage of the memory device, thereby not only aggravating the damage of the bottom insulating layer, increasing the power consumption of the memory device, but also reducing the operation of the memory device. Time stability. SUMMARY OF THE INVENTION The present invention is directed to a memory cell of a stacked structure memory and a method of fabricating the same. The deposition of the storage layer in the insulating/storage/insulating structure is performed by means of different gas flow ratios, so that the memory cells of the stacked structure memory have the advantage of lowering the threshold voltage. According to a first aspect of the present invention, a stacked structure memory is proposed.

A method for manufacturing m-aWj296PA B memory cells. This method first provides a substrate. Next, a first insulating layer is formed on the substrate. Then, deposition is performed by a first gas and a second gas to form a storage layer on the first insulating layer, and the flow ratio of the first gas and the second gas is 2 to 1. Then, a second insulating layer is formed on the storage layer. Then, a single line region is formed on the substrate. Next, a gate is formed on the second insulating layer. The first insulating layer, the storage layer, the second insulating layer and the gate are stacked structures of memory cells. Then, a spacer is formed on the sidewall of the stacked structure. According to a second aspect of the present invention, a memory cell of a stacked structure memory is provided, comprising a substrate, a stacked structure, a gate, and a spacer. The substrate has a one-dimensional line area. The stack structure is disposed on the substrate, and the bit line regions are located on both sides of the stacked structure. The stacked structure includes at least a plurality of insulating layers and a storage layer. The storage layer is disposed between the insulating layers and is formed by depositing a first gas and a second gas at a flow rate of 2 to 1. The gate is at the top of the stack structure. The spacers are located on the side walls of the stacked structure. BRIEF DESCRIPTION OF THE DRAWINGS In order to make the above description of the present invention more comprehensible, the preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings. . However, the invention is not limited thereto, and this embodiment does not limit the scope of the invention to be protected. Furthermore, the illustrations in the embodiments also omit unnecessary elements to clearly show the technical features of the present invention. 8

W3296PA 200830470 " Please also refer to Figures 1 and 2A-21. 1 is a flow chart showing a method for manufacturing a memory cell of a stacked structure memory according to the present invention; FIGS. 2a to 2G are respectively a schematic diagram showing steps 11 to 17 of FIG. 1; FIG. 2H is a second G diagram; A cross-sectional view taken along the A-A' direction of the middle section; and 21 is a schematic view of the step 18 of Fig. 1. According to the manufacturing method of the embodiment, a substrate 21 is provided first as shown in steps 11 and 2A. Next, in step 12, as shown in Fig. 2B, a first insulating layer 22 is formed on the substrate 21. In this embodiment, the first insulating layer 22 is exemplified by a C-oxide layer. The first insulating layer 22 is deposited on the substrate 21 in a wet oxidation manner. In one embodiment, the thickness of the first insulating layer 22 is, for example, about 48 angstroms. Further, as shown in step 13, the step of depositing by a first gas and a second gas is performed and the flow ratio of the first gas and the second gas is 2 to 1. As shown in Fig. 2C, a storage layer 23 is deposited on the first insulating layer 22. In this embodiment, the storage layer 23 is exemplified by a nitride layer. In a preferred embodiment of the present invention, the storage layer 23 utilizes 200 (Standard Cubic Centimeter per Minute (SCCM) first gas and 100 standard flow of second gas at a temperature of 680 ° C and 0.3 Torr. Under pressure conditions, low pressure chemical vapor deposition is performed, wherein the first gas is preferably dichlorosilane (DCS), the second gas is preferably ammonia, and the thickness of the storage layer 23 is about 70 Å. As shown in Fig. 2D, the manufacturing method according to the present invention is followed by step 14 to form a second insulating layer 24 on the storage layer 23. In this embodiment, 9 200830470

Sanda number: TW3296PA The second insulating layer 24 is described by taking another oxide layer as an example. The second insulating layer 24 is formed on the storage layer 23 by chemical vapor deposition at a high temperature of about 800 °C. And the second insulating layer 24 is deposited to a thickness of about 90 angstroms. The first insulating layer 22, the storage layer 23, and the second insulating layer 24 constitute an insuiating/trapping/insuiating structure. In the present embodiment, a first insulating layer 22 such as an oxide layer, a storage layer 23 such as a germanium layer, and a second insulating layer 24 such as another oxide layer constitute a germanium structure. C then 'in step 15, as shown in FIG. 2, preferably using an ion implantation method to form a bit-lme region 25 on the substrate 21 as The source and drain regions of the memory cell 0 Next, as shown in steps 16 and 2F, a gate 26 is formed over the first insulating layer 24. At this time, the first insulating layer 22, the storage layer 23, the first, the barrier layer 24, and the gate 26 constitute a stack structure, 27. The bit line regions 25' are located on either side of the stack structure 27. I Next, as shown in steps 17 and 2G to 2H, a diffusion barrier layer 28 is formed on the substrate 21. The diffusion barrier layer 28 is located on the sidewall of the stacked structure 27. Further, the diffusion barrier layer 28 is not formed on both sides of the gate 26 corresponding to a direction γ, and the direction Y is a bit line direction. Furthermore, step 18 is performed to form a spacer on the sidewalls 26a and 26b of the gate 26 corresponding to the direction Y. In this embodiment, the material of the spacer 较佳 is preferably nitrite (siiiC0I1 nitri(ie), and forms 200830470

—· TW3296PA The method of this spacer 29 includes, for example, the following steps. First, a tantalum nitride layer (not shown) is formed on the stacked structure 27 by chemical vapor deposition. Next, the nitride layer is defined by photolithography and anisotropic etching to form spacers 29 on the sidewalls 26a, 26b of the gate 26 corresponding to the direction Y. Figure 21 is a diagram showing the memory cell structure of a stacked structure memory in accordance with a preferred embodiment of the present invention. The memory cell structure 20 manufactured according to the above steps 11 to 18 includes: a substrate 21, a first insulating layer 22, a storage layer 23, a second insulating layer 24, a gate 26, and a diffusion barrier layer 28 (shown in 2G in the figure) and spacer 29. Please refer to FIG. 3A, which is a graph showing the threshold voltage characteristics of the memory cells deposited in the storage layer under different flow conditions. Curve 31 is a threshold voltage characteristic curve of the memory cell in which the storage layer 23 is deposited using a ratio of the first gas to the second gas flow rate of 1 to 6. Curve 32 is to deposit a storage layer 23 by using a ratio of the first gas and the second gas flow of 2 to 1 to form (a silicon-rich nitride of the first insulating layer 22 and the second insulation). The threshold voltage characteristic of the memory cell between layers 24 (as shown in Figure 2H). When the drain current (ID) is 5 microamperes, the gate voltage value (VG) corresponding to curve 31 is about 1.54 volts. The gate voltage value corresponding to the curve 32 is about 0.89 volts. It can be seen that the deposition of the storage layer 23 by using the ratio of the first gas and the second gas flow rate of 2 to 1 can lower the threshold voltage of the memory cell 20. Please refer to Figure 3B, which shows the spacers of different materials and 11 200830470...

I. iWj296PA • The threshold voltage characteristic of the memory cell of the storage layer. The curve 33 and the curve 34 are the threshold voltage characteristics of the memory cell 20 which is insulated and stored as the material of the spacer 29, respectively. At a pole current of 5 microamperes, curve 33 corresponds to a gate voltage of approximately 0.71 volts and curve 34 corresponds to a gate voltage value of approximately 1.12 volts. Curve 35 is a material having a storage voltage as a spacer 29 and a threshold voltage characteristic of the memory cell 20 in which the storage layer 23 is deposited at a flow ratio of 2 to 1. Under the condition that the drain current is also 5 microamperes, the gate voltage corresponding to curve 35 is about 0.79 volts. As is apparent from the curve 33, the curve 34, and the curve 35, the memory cell 20 which is stored as the spacer 29 material and the storage layer 23 deposited at a flow ratio of 2 to 1 has a memory cell 20 which is made of insulating material as the spacer 29. The threshold voltage value. From the data measured by the above experiment, it is known that the deposition of the storage layer 23 by using the ratio of the first gas and the second gas flow rate of 2 to 1 can effectively lower the threshold voltage value of the memory cell 20. The memory, cell and manufacturing method thereof for the memory of the memory layer according to the preferred embodiment of the present invention are formed by chemical vapor deposition at a high temperature to form a second insulating layer on the storage layer. And using a ratio of the first gas to the second gas flow rate of 2 to 1, deposition of the storage layer is performed to lower the critical voltage value of the memory cell. The advantage is that under the memory cell structure of the existing storage layer memory (for example, without adding or changing any structure in the memory cell), the threshold voltage value of the memory cell can be lowered, so that the production cost is not increased. In addition, the manufacturing method disclosed in the preferred embodiment of the present invention is compatible with the original production process, so that the original production process can be changed without changing the original production process.

TW3296PA 200830470 Create memory cells for storage layer memory. Moreover, since the memory cells of the memory layer memory fabricated in accordance with the preferred embodiment of the present invention have a lower threshold voltage value, the memory cells can maintain operational stability. In the above, the present invention has been disclosed in a preferred embodiment, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims. 13 200830470

2D Illustrated Airflow/W3296PA' [Simplified Schematic Description] FIG. 1 is a flow chart showing a method for manufacturing a memory cell of a stacked structure memory according to the present invention; FIG. 2A is a schematic view showing a step 11 of FIG. 2B is a schematic diagram of step 12 of FIG. 1; FIG. 2C is a schematic diagram of step 13 of FIG. 1; FIG. 2D is a schematic diagram of step 14 of FIG. 1; FIG. 2F is a schematic view showing the step 16 of FIG. 1; FIG. 2G is a schematic view showing the step 17 of FIG. 1; and FIG. 2H is a view along the A-A' direction of the 2G drawing. FIG. 21 is a schematic diagram showing the step 18 of FIG. 1; FIG. 3A is a graph showing the threshold voltage characteristics of the memory cells deposited under different flow conditions; and FIG. 3B is a diagram showing the spacing of different materials. A graph of the critical voltage characteristics of the memory cells of the object and the storage layer. 14 200830470

Erda Griffin · 1.W3296PA ' [Main component symbol description] 20 : Memory cell 21 : Substrate 22 : First insulating layer 23 : Storage layer 24 : Second insulating layer 25 : Bit line region 26 : Gate ( 26a 26b: sidewall of the gate 27: stack structure 28: diffusion barrier layer 29: spacers 31, 32, 33, 34, 35 · · curve Y: direction of the bit line 15

Claims (1)

200830470 三达编号·· TW3296PA X. Patent application scope: 1 . A method for manufacturing a memory cell of a charge trapping memory, comprising: providing a substrate to form a first insulating layer on the substrate Depositing a first gas and a second gas to form a storage layer on the first insulating layer, and the flow ratio of the first gas and the second gas is 2 to 1; f forming a a second insulating layer on the storage layer; forming a bit-line region on the substrate; forming a gate on the second insulating layer, the first insulating layer, the storage layer, the first The two insulating layers and the gate are the stacked structure of the memory cell, and a spacer is formed on the sidewall of the stacked structure. 2. The manufacturing method according to claim 1, wherein in the step of forming the storage layer, the first gas of 200 standard flow (SCCM) and the standard flow of 1 (8) are used. The second gas is subjected to low pressure chemical vapor deposition to form the storage layer. 3. The manufacturing method according to claim 2, wherein the first gas system is dichlorosilane (DCS), and the second gas system is a gas. 4. The manufacturing method of claim 2, before the step of forming the spacer, further comprising: 16 rW3296PA 200830470 forming a diffusion barrier layer on the substrate, the diffusion barrier layer being located on a side of the stack structure wall. 5. The method of claim 4, wherein the forming the spacer further comprises: forming a tantalum nitride layer on the stacked structure; and defining by lithography and anisotropic etching The tantalum nitride layer is formed to form the spacer. 6. The manufacturing method according to claim 5, wherein the niobium nitride layer is formed by chemical vapor deposition. 7. The manufacturing method according to claim 5, wherein the spacer is located on both sides of the gate corresponding to the direction of the bit line of the memory cell. 8. The manufacturing method according to claim 1, wherein the first insulating layer is formed on the substrate by wet oxidation. 9. The manufacturing method of claim 8, wherein the first insulating layer has a thickness of about 48 angstroms. 10. The method of manufacture of claim 1, wherein the storage layer has a thickness of about 70 angstroms. 11. The method of manufacturing of claim 1, wherein the second oxide layer is formed on the reservoir layer by high temperature chemical vapor deposition. 12. The method of manufacturing of claim 1, wherein the second insulating layer has a thickness of about 90 angstroms. The method of manufacturing the invention of claim 1, wherein the bit line region is formed on the substrate by ion implantation, and the bit line region is Located on either side of the stack. The manufacturing method according to claim 1, wherein the first insulating layer is an oxide layer. 15. The method of manufacturing of claim 1, wherein the storage layer is a nitride layer. 16. The manufacturing method according to claim 1, wherein the second insulating layer is an oxide layer. 17. The memory cell of the stacked structure memory, comprising: a substrate having a one-dimensional line The stacking structure is disposed on the substrate, the bit line region is located on two sides of the stack structure, the stack structure includes at least: a plurality of insulating layers; a storage layer disposed between the insulating layers The storage layer is formed by depositing a first gas and a second gas at a flow rate of 2 to 1; and a gate is disposed at a topmost layer of the stacked structure; and a spacer is disposed on the stack The side wall of the structure. 18. The memory cell of claim 17, wherein the flow rate of the first gas is 200 standard flow rate, and the flow rate of the second gas is 100 standard flow rate. The memory cell according to the item 18, wherein the first gas system is dioxane, and the second gas system is ammonia gas. 18: W3296PA 200830470 - 20 · The memory cell according to claim 17 of the patent application scope, Which should The insulating layer is a first insulating layer and a second insulating layer. The first insulating layer is disposed on the substrate, the storage layer is disposed on the first insulating layer, and the second insulating layer is disposed on the storage layer. The gate is disposed on the second insulating layer. The memory cell is as described in claim 20, wherein the first insulating layer is formed on the substrate by wet oxidation, the second insulating layer. The memory cell is formed by high temperature chemical vapor deposition. f 22. The memory cell of claim 17, further comprising: a diffusion barrier layer located on a sidewall of the stacked structure. The memory cell according to claim 22, wherein the spacer is located on both sides of the gate corresponding to the direction of the bit line of the memory cell. 24. The memory cell according to claim 17 The material of the spacer is a gasification stone. The memory cell according to claim 17, wherein the thickness of the first insulating layer is about 48 angstroms. The memory cell described in the item, wherein the storage The thickness of the layer is about 70 angstroms. The memory cell of claim 17, wherein the thickness of the second insulating layer is about 90 angstroms. 28. The method of manufacturing according to claim 17 The first insulating layer is an oxide layer. The manufacturing method according to claim 17, wherein the storage layer is a nitride layer. 19 'xW3296PA 200830470 30 · as claimed in claim 17 The manufacturing method according to the item, wherein the second insulating layer is an oxide layer.