TW200830313A - Magnetic memory - Google Patents

Abstract

Provided is a magnetic memory. After data is written into a memory cell, a step for determining whether the written data from outside and the logic of the read-out data of the memory cell is consistent or not (step S3) is performed. When this written data is not consistent with the logic value of the memorized data of the memory cell, a step for once more writing the data to the memory cell which is the writing target (step S4) is performed. After this, the memorized data of the memory cell which is the writing target is read out, and the consistence between the written data and the read-out data is determined. This operation is repeated till the written data and the read-out data is consistent. Thereby, reliability of data writing of magnetic random access memory can be assured.

Description

200830313 w9, invention description: [Technical Field] The present invention relates to a magnetic memory, and more particularly to an MTJ (Magnetic Tunneling Junction) component (magnetic tunneling interface component) or The MJT (Magnetic Junction T leg ngmg; magnetic junction tunneling) component (spin tunnel junction element; Spin Tunnel Junction) is used as a memory element for memory. More specifically, the present invention relates to a configuration for ensuring reliability of writing data to an MTJ element _ (MJT element). [Prior Art] As a semiconductor memory device that non-volatilely memorizes data, a flash memory has been known in the past. The memory unit of the flash memory is composed of a laminated positive electrode and a transistor having a control gate and a floating gate (fi〇ating _). According to the amount of accumulated charge of the floating gate, the threshold voltage (threshold v〇ltage) of the memory is changed. The threshold voltage of the memory cell of the body is corresponding to the memory data. When the data is read, a nominal voltage is supplied to the control terminal. Memory unit: 曰 The system will vary in the amount of current flowing depending on its threshold voltage. The data is read out by detecting the current amount of the memory cell of the memory cell. Machine k In the flash memory, the data is written in the following way. According to the data, the charge is moved between the floating gate and the substrate region (the channel region n between the ocean gate and the source/(four) region, and according to the amount of accumulated charge of the coarse or fixed floating gate. Therefore, in the flash The memory and the shaking are set to 'because the charge moves through the insulating film, so the number of writings is 1 (3), the horse is insulated 5 319644 200830313, and the characteristics of the film are limited. In addition, the data is moved by the electric charge. Write, so there is a problem of long data write time and long access time. In order to solve this problem of flash memory, MRAM (Magneto) with short access time and unlimited number of rewrites has been developed. -Resistive Random-Access Memory. This MRAM uses a variable magnetic resistance element as a memory cell element. In the variable magnetic resistance element, it is called a free layer and fixed. The laminated structure of the magnetic bodies of the layers. The resistance values of the magnetization directions of the magnetic bodies are different, and the data is memorized according to the resistance values. As the MRAM, in the conventional current magnetic field writing mode MRAM When the data is written, the current flows to the mutually orthogonal digit line and the bit line. The pig is set by the combined magnetic field of the magnetic field induced by the current flowing through the digit line and the bit line. The magnetization direction of the free layer of the variable magnetic resistance element (MTJ element (magnetic tunneling junction element). The magnetization direction of the fixed layer is fixed in a certain direction regardless of the applied magnetic field. 0 In this conventional MRAM, In order to generate the magnetic field required for rewriting, a certain amount of current is required. Therefore, as the memory unit is characterized, the width of the power supply line is also reduced, and thus the current required to generate the magnetic field is also increased. When P is miniaturized, the distance between the variable magnetic resistance elements of the memory unit is also small. Due to the leakage magnetic field applied to the magnetic field of the selected memory unit, the memory data of the non-selected memory unit is changed. In addition, in the memory unit of the current magnetic field writing method, the easy axis of magnetization is arranged in parallel with the bit line or the digit 6 319644 200830313 w line. To this. 愔勒·^ μ ^ ^, first down 'in the + select state (select the state of the digit line or bit line) but the + touch a + + especially k, body early tl, due to the circulation of the digit line Or the bit-line error induced by the current of the bit-line is a problem of the one-axis interference (distuTb) that reverses its memory data. As a mram that has to overcome this one-axis interference problem, Developed a dual L-toggle MRAM and a spin-injection magnetization inversion write mode MRAM (Spin-Torque Tmnsfer RAM; hereinafter referred to as spin injection type ΑΜ). r The easy magnetization axis and the hard magnetization axis of the memory element of the memory cell in the two-state thixotropic MRAM are arranged to be 45 with the digit line and the bit line. angle. In addition, a free layer is formed by a SAF (synthetic antiferromagnetic) structure. In the SAF structure, two ferromagnetic layers are disposed with an antiferromagnetic light layer interposed therebetween. When the data is written, the timing of the current flowing through the digit line and the bit line is shifted, and the magnetization of the free layer is rotated. Since the magnetization direction of the free layer is rotated by using both the digit line and the bit line, even if a leakage magnetic field from one axis (digit line or bit line) is applied, the magnetization direction of the free layer does not rotate. Can eliminate the problem of one-axis interference. In the spin injection type magnetization inversion writing type MRAM (spin injection type MRAM), the spin polarization direction of electrons passing through the pinned layer is set by the magnetization direction of the pinned layer. The electric current that has determined the direction of the spin polarization is introduced into or extracted from the free layer, thereby adjusting the self-polarization direction of the electrons of the free layer to set the magnetization direction of the free layer.自In the spin called spin-torque transfer random access memory, the main type 7 319644 7 200830313 MRAM 'when writing' current will be freely magnetic via the memory unit and 70 pieces (MT J TG pieces) and circulate. Therefore, since the magnetic field is not generated by the use of the electron spin, the problem of the one-axis interference can be eliminated. The memory device has a plurality of memory cells. For example, in a memory device having a memory capacity of one megabit, a memory cell of about 1 〇〇 = memory is provided. There is a subtle bias between these multiple memory cells. Therefore, in the case where all of the memory cells are rewritten with the same conditions, it is necessary to set a region in which the rewritable ranges of the plurality of memory cells overlap each other as a rewriting condition. Therefore, the writing conditions for writing will become narrower, and the probability of writing bad people will be used to write whether the data has been correctly written when the bedding is written =: verification one action, always flashing In the memory, in the ίli literature 1 (曰本特开平平- 10-302487) ^...Into the verification action, when writing the data and writing the object of the memory, the memory is stopped, after the stop people. The verification operation is performed every time the nest is performed, and the writing and verification actions are performed in advance; 'until the memory data of the memory unit of the writing object and the writing material _f are written. Change the write pulse width and write each time you write. When the verification is performed for a predetermined number of times and the data is not correctly written: The memory unit of the object is regarded as defective. It is known that the invention of Patent Document 1 performs write and write verification interactively. 319644 8 200830313 , This stops for the memory unit that does not need to be written, 隹/一亚对母位元«丁记忆单位的In the case of the memory, in the memory, in the memory, after writing, the person is authenticated to determine whether the memory cell: the critical value of the crystal (threshGld) is In the reservation, around. When the person writes again after the test, the user will change the write wave and/or the pulse wave and perform the writing. , Zeng Zhuan, the invention of Document 2 maintains the critical electric castle distribution width of the written memory unit within a predetermined range, and widens the difference between the threshold voltage after writing and the eliminated threshold voltage to seek The characteristic deterioration of the memory device is suppressed. Patent Document 3 (Japanese Laid-Open Patent Publication No. 2004-22112) discloses a flash memory for the purpose of performing page pr graming at high speed. In the configuration shown in Patent Document 3, the writing and verification in units of pages are performed for one page of data, and the writing after the writing is stopped for each unit that has finished writing. . The invention of Patent Document 3 is repeatedly written and verified in a plurality of address units. Compared with the case of writing and verifying readout at each address, it is necessary to shorten the time required for programming and realize high-speed page programming. Further, Patent Document 4 (Japanese Patent Laid-Open Publication No. 2003-346484) discloses a charge trapping type f® body for performing an insulation test. In the configuration shown in the special document 4, after writing the certificate, the pin 9 319644 200830313 t adjusts the write voltage level to the memory unit having a bad write and performs rewriting. The write = verification number is set to t maximum value, and when the target unit is still defective even if the maximum value is reached, it is judged that the memory unit is defective. 1 (4) by writing and verifying, the number of writes to the pulse wave is reduced (4) to prevent the application of excessive write pulse waves to the insulating film of the etched transistor (NROM cell transistor). Maintain reliability. - In addition, in the special contribution 4, 'there is a step in the process of re-introduction: the incursion does not prevent the application of excessive (four) to the memory element (NROM transistor). 5 (Japan Special Kaiping 〗 〖. Milk is a bulletin) is a view of revealing one: the maximum time required for the purpose of the flash memory, the lack of composition, in the test mode neck, two pre-, fixed The maximum number of verifications is performed in the memory of the nest and the second is completed. When the maximum number of writes/verifications is completed, the busy stone is sent to the external bus BUSY. By observing the busy letter in the outside, the second is fine. Programming time as a specification value is not intended to simplify the design of the system. Bao Ye and 2 Document 6 (曰本特开平(10)面) - a flash memory with long beak material writing time. Special contribution (4) Finding intrusion From the π 士 an ^ f ~ x 献 6, it is judged whether the write current value of the entrant flow is smaller than the λ λ from the soil value. , the mouth is judged 舄 ' '" 丨 L edge is smaller than the judgment value, stop Jingjin = after the data is written, from the write object Memory 2: 1 row verification operation is necessary, and shortening the writing time is required to continue the Beccoli document 7 (Japanese Patent Laid-Open No. 2) 319644 10 200830313 'A type is performed in phase change memory The configuration of the write and write verification. The invention of Patent Document 7 writes a memory cell in a reset state in a high resistance state, that is, writes to the phase change memory. In the cell, the memory value of the phase change memory cell of the write target is read and compared with the written data. When the comparison result is inconsistent, the write current is supplied. The write current amount is repeated each time the write is repeated. The invention of Patent Document 7 is in the phase change memory unit, that is, the contact area between the lower electrode and the phase change element is deviated, and the resistance value is deviated due to incomplete non-crystallization. In order to prevent erroneous reading of data, that is, repeating the writing and writing verification, the phase change of the reset state is set to a predetermined value or more regardless of the phase value of the reset unit. The size of the contact area between the variator and the lower electrode is reduced, and the variation in the resistance value is reduced. Patent Document 8 (JP-A-2004-362761) discloses a configuration for performing writing and verification in a phase change memory unit. Patent Document 8 According to the invention, when the writing is performed in the set state of the phase change memory cell toward the low resistance, the resistance value of the memory cell in the set state depends on the resistance value in the reset state, thereby preventing the occurrence of the resistance. In the case of writing in the set state, the bit line voltage is monitored, and when the bit line voltage reaches a predetermined reference voltage, writing to the set state is stopped. When the bit line voltage is changed from the reference voltage, it indicates that the memory cell to be written has become a low resistance setting state. Thereby, the deviation of the resistance value of 11 319644 200830313 * in the set state after writing to the memory unit is suppressed. The above-mentioned Patent Documents 丨 to 8 show a configuration in which (4) is written to stabilize the writing of the memory of the phase change memory. That is to say, in the special: 1, the write verification of the memory unit is first performed, and then the result of the fresh verification is pure (4). When the stock certificate (4) line == time ^ writes the time width of the pulse wave, and controls the amount of injected charge U of the floating gate, the composition shown in the special offer will be the object, when the writer is written, Note that there is a floating charge (the electronic boundary is the same as the voltage. Therefore, when t is rewritten, the state of the cell is different from that of the case of the Lie, so in order to reduce the deviation of the threshold voltage after writing, it is required to skillfully Adjust the write pulse width to write. The other side: In the case of MR^AM, 'When the write is bad, the memory cell after writing is the same as before the write, and the start state is the same. Therefore, as shown in the patent document, when the write pulse width is slightly adjusted and the writing is repeated, the number of write/write verifications is increased instead, so that the writing time may become long. Therefore, the configuration of Patent Document i cannot be directly applied to the MARM. In the configuration of Patent Document 2, in a rewritable memory cell (NROM cell), charges are trapped in the insulating film, and the memory cell transistor is adjusted. Threshold voltage. Therefore, accumulation at the insulating film during writing Since the charge voltage is changed, the threshold voltage of the memory cell changes every time it is written. Therefore, Patent Document 2 cannot be directly applied to, for example, MRAM, and when the write failure occurs, the memory unit is restored to the pre-write state. Memory device of the state. 12 319644 200830313 ' ^ Patent Document 3, although page programming is shown, the charge voltage of the (four) pole is changed to cause the threshold voltage of the memory cell transistor to change and eat-remember data. In the same manner as the patent documents 丨 and 2, it is not possible to directly apply the data writing of the two 'MRAM'. The patent document 4 shows the write verification in the flash memory. However, in Patent Document 4, each write is performed. The critical electric enthalpy of the human-time memory cell transistor also changes. Therefore, the constitutional method of Patent Document 4 is applied to the write configuration of the MRAM. The patent document 5 is written only during the maximum programming time in the test mode. And the verification and the maximum programming time at the time of writing can be observed externally in the test mode. Therefore, in the configuration shown in Patent Document 5, it is recorded as a flash memory unit, each time When a person, a single memory ⑽ = voltage will change. Accordingly, also designed to be objective for offering 5_ not suitable for direct 〃 iv written into memory cell will not restored to the original state like) constituting the MRAM. C Original In the configuration shown in Patent Document 6, the write completion is monitored at the time of data writing. Therefore, Patent Document 6 (4) Μ Μ 始 始 始 始 始 始 始 始 始 始 始 始 始 始 始 始 始 始 始 始 始 始 始 始 始 始 始 始 始 始 始 始 始 始 始 始 始 始 始 始This memory =: Inverted write mode of the spin torque transfer random deposit -, 'in the type of MRAM, according to the logic of the written data, 7 series shows the phase change memory unit write and test 319644 13 200830313, card. In the phase change memory unit, the resistance value of the high resistance reset state depends on the resistance value in the set state of the low resistance state, and the resistance value of the set-state memory cell depends on the reset state. The resistance value of the memory is 1 yuan. In the MRAM, there is no dependence on the directness of the resistance value of the memory cell before data writing and the resistance value of the memory cell after data writing. Therefore, in the MRAM, in the case where the size of the write current is changed every time the write verification is performed, the write current is supplied after the completion of the write, and the unnecessary write is generated. Therefore, the writing sequence of Patent Document 7 cannot be directly applied to the MRAM. In the configuration shown in Patent Document 8, the bit line voltage of the phase change memory unit is changed to a predetermined reference voltage. Therefore, as in the case of the two-state thixotropic MRAM, the configuration shown in Patent Document 8 cannot be applied in the case where a constant current is flown regardless of whether or not it is in the write state. Similarly, in the spin injection type MRAM, the direction of the electric current flowing through the bit line is different each time the data is written, so that the phase change memory of the bit line current flows in one direction as shown in Patent Document 8 The write order cannot be applied to MRAM. SUMMARY OF THE INVENTION An object of the present invention is to provide an MRAM capable of correctly writing data. Another object of the present invention is to provide a two-state thixotropic MRAM or a spin injection MRAM capable of stably writing data. MRAM without any axis interference In short, the magnetic and memory (non-volatile magnetic memory 14 319644 200830313 -) of the present invention is a data write and verifier when the feed is written. When the poor material write failure is detected at the time of verification, the memory cell becomes the same complaint as before the write, and is rewritten from the same state as before the write. That is, in one embodiment of the present invention, the magnetic memory system 2 includes a plurality of memory cells, and the write system circuit writes the written data into the plurality of memory cells to be written. The memory unit; the horse enters the control circuit, compares the memory data of the written object with the written material. Each of the plurality of memory cells includes a variable magnetic resistance element and the data is memorized by the resistance value of the variable magnetic resistance element. The write circuit is a memory unit that writes the data to the person to be written, and stores the data and data of the memory unit of the object. According to the rut and the fruit, the write circuit selectively performs writing for the memory unit to be inserted. When the memory cell to be written is rewritten, rewriting is performed from the same initial state as before writing. In the present invention, it is checked whether or not the writing has been correctly performed. Port = This suppression results in poor data writing and can achieve high reliability. In addition, a badly written memory unit is re-injected from the same state as the previous write. Therefore, in the consistent mode, the write condition of 2% at the time of each write enables the rewrite to be performed according to the characteristics of the memory cell, and accurate rewriting can be realized. 319644 15 200830313 • [Embodiment] The following is a schematic view of a preferred embodiment of the present invention. • "Construction principle", the configuration of the variable magnetic resistance element of the memory unit. Fig. 1 schematically shows the two-state thixotropic unit used as the variable magnetic land resistance element VR included in the memory unit. The structure of J Yuan. In Fig. 1, the variable magnetic resistance element is further comprised of a free layer 1, a pinning layer (])] [11116 (11 lamps > 2, and a setting 10 in the free layer 1 and pinning) a tunneling barrier layer (layer) between the layers 2. The free layer 1 includes a ferromagnetic film fmi, fm2 having substantially the same magnetic moment, and a non-magnetic film af. It is placed between the ferromagnetic film: FM1 and FM2. The free layer 1 is an anti-parallel coupling element (SAF) with two ferromagnetic films FM1 and FM2 sandwiching the non-magnetic layer AF in the middle of the three-layer structure. In the middle, the non-magnetic layer AF acts as an antiferromagnetic bonding layer. In the state where no magnetic field is applied, the magnetization steep films FM1 and FM2 are opposite in direction (anti-parallel state) due to the exchange of filial piety. The pinning layer 2 is composed of, for example, a ferromagnetic film and an antiferromagnetic film, and the magnetization direction is fixed irrespective of the direction in which the magnetic field is applied due to the antiferromagnetic exchange coupling. According to the magnetization direction of the ferromagnetic film FM2 and the pinning layer 2 The variable magnetic resistance element V is in the same direction (parallel state) or anti-parallel state The resistance value of R (MJT component: SaVChENKO MJT component) will be different. The resistance value corresponds to the binary value information. In the state where no magnetic field is applied, the magnetization of the free layer 1 and the pinning layer 2 is 16 319644 200830313. The direction does not change. In addition, the information is memorized only in accordance with the magnetization direction. Therefore, the data can be stored non-volatilely without affecting the leakage current, etc. - Fig. 2 schematically shows the array of the variable magnetic resistance element VR The bit line is pulled and the digit line DL is set for the variable magnetic resistance element VR. The bit line and the digit line DL are arranged to be orthogonal to each other. The easy magnetic (four) system of the variable magnetic resistance element VR is substantially The vertical line BL and the digit line DL are 45. The variable magnetic resistance element VR is supplied in an angular manner. In a state where no magnetic field is applied, the magnetization direction of the variable magnetic electric resistance element VR is along the direction of the easy magnetization axis. A hard magnetic axis is present in a direction orthogonal to the easy axis of magnetization. Fig. 3 is a view showing the magnetization rotation order of the MJT element when the data of the two-state thixotropic MRAM cell is written. Hereinafter, the data writing operation of the έ 忆 体 unit will be described with reference to Fig. 3 . First, in the period # ,, the digit line DL and the bit line BL do not flow current. Therefore, in the variable magnetic resistance element VR, the magnetization direction of the free layer is set and maintained in accordance with the easy magnetization axis XE. In the period #1, only the digit line DL flows current. Thereby, the magnetic field H1 is generated along the extending direction of the bit line. By the magnetic field H1, the exchange coupling in the free layer collapses (spin fl〇p state), and the combined magnetic fields of the two ferromagnetic films (FM1, FM2) of the free layer become the induced magnetic field H1. For the same direction. In the period #2, in the state where the digit line DL flows current, the line BL flows a current. In this case, due to the current of the bit line bl, the magnetic field H2 is generated in a direction parallel to the direction in which the digit line extends. The magnetization of the 17 319644 200830313 y solid magnetic film of the free layer rotates, so that the combined magnetic field of the magnetic fields m and H2 and the resultant magnetic field of the free layer become the same direction. ώIn the period #3, the current of the digit line DL is turned off, and only the bit line BL 2 is turned on. In this case, only the magnetic field H2 is generated in the direction of the digit line DL. Therefore, the resultant magnetic field of the free layer becomes the same direction as the induced magnetic field H2 of the bit line electric & the magnetization of the free layer re-rotates. In the period #4, the current supply of the bit line BL is cut off. At this time, the number and line DL are not supplied with current. In this case, in the free layer, the magnetization of the free layer is dominated by the replacement of the light. The magnetization of the free layer is aligned with the easy magnetization and reversed. In the period # 〇 and period # 4, the magnetization direction of the free layer is reversed. The resistance of the variable magnetic resistance element vr (Savchenk 元件 element) will be based on the free layer! The ferromagnetic film web 2 and the magnetization direction of the pinned layer 2 are set. Therefore, in the period #〇 and period #4, the resistance value of the variable magnetic resistance element VR changes, and the binary data can be memorized. As described above, in the two-state thixotropic MRAM>, it is possible to write a person's data by using a unipolar current. In the order of writing, the initial state of the variable magnetic resistance element is free in the writing order, layer = magnetization = 18 向 to the suspect. . Therefore, when the data is written to the memory unit, the magnetization direction of the variable magnetic resistance element of the memory unit is reversed only when the memory data and the data are written. Further, in the variable magnetic resistance element, the easy magnetization axis has 45 for the bit line and the digit line through which the write current flows. Angle. Therefore, bit inversion cannot be performed with only one power supply line, so the problem of -axis interference 319644 18 200830313 • does not occur. However, when the external magnetic magnetic film is aligned with the external magnetic corpse and is reported to be strong, the two of the free layers will not be aligned to the second. When the magnetic field strength is reduced, this is appropriately written into the magnetic field system. There is a Bu, Beike into the day, more powerful than the strength of the magnetic field of Jiang Baiwei' and the strength of the two magnetisms of the free layer is less. The magnetization of the membrane is stronger toward the magnetic field in the same direction. When the data is written, the hopper bin + uses the current pulse of the early polarity, and the part of the sputum input and the electric current can be simplified. The structure of the variable magnetic resistance element 2 ·· The figure of the 4 shows the tile纟I,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, The structure of the material is changed from ^^. The variable magnetic resistance element VR is composed of bribe elements, 匕δ has free layer 11, pinning sound 12, ["Fen you recognize 丄ρ The glazing layer 12 and the tunneling insulating film 丨3 between the free layer 11 and the pinning layer 12. The free layer 11 and the pinned layer 12 are composed of a ferromagnetic body. In the variable magnetic resistance element VR, when electrons flow from the needle layer 12 into the insulating film 13, the spin directions of the electrons are made uniform. By the spin torque action of the electrons in the spin direction at this time, the spin directions of the electrons of the free layer 11 are made uniform to set the magnetization direction. In the mjt θ element, the resistance value of the magnetization direction of the free layer 11 and the pinning layer 12 is also different, and the data is memorized based on the resistance value. In the following description, the magnetic field-resistive element of the current magnetic field inversion type is referred to as an MTJ element, and the magnetic resistance element of the spin-injected magnetic field inversion type is referred to as 319644 19 200830313 as an MJT element. Figs. 5(A) and 5(B) are diagrams schematically showing the flow of current when the data of the MJT element shown in Fig. 4 is written. In the figure (8) • the medium write current IW flows from the pinning layer 12 toward the free layer u. In this case, when the electrons e flow from the free layer 1 of the age-bearing layer 12, the direction of the spin-bias of the spin-direction layer 12 is different, and the spin of the electron of the free layer u is reflected by the J-edge film 13 The direction changes to the opposite direction of the pinned layer 12. It has the same spin as the spin biasing direction of her layer 12, and the electron e of the pole passes through the pinning layer 12. Therefore, in the free layer 11, the magnetization direction is set to a direction opposite to the magnetization direction of the pinned layer 12 by the transmission of the spin torque. " In the nuclear state, the magnetization directions of the free layer and the pinned layer 12 are in an anti-parallel direction, which is a high resistance state. This state corresponds, for example, to a state in which the memory information is "H" (logic high level). In Fig. 5(B), the write current Iw flows from the free layer jj to the pinion=layer 12. In this case, the electrons flow from the pinning layer toward the free layer n. The spin polarization direction of the electron e is aligned to the spin biasing direction of the pinning layer 12. Therefore, the electrons e injected into the free layer u via the tunneling insulating film 13 have the same spin biasing direction as the spin biasing direction of the pinning layer 12, and the 'free layer 11 is magnetized and bonded to the pinning layer. The magnetization direction of 12 is the same direction. This state is a low resistance state, and corresponds to, for example, a state in which the memory material is "L" (logic low level). When the main lean material is read, the read current flows from the free layer 11 toward the pinned layer 12. In this case, the read current is set to be much smaller than the write current so that the magnetization direction of the free layer 11 is not reversed due to the read current. 20 319644 200830313. In the case of the variable magnetic one shown in Fig. 4, it is preferable to enter a few pieces of VR, and the Beca write % does not use the current induced magnetic field. That is, Mram 疋 T injected into the magnetization inversion writing mode <堇 Supply current to early selection. Therefore, in the memory unit of the semi-selected state, the write = stream does not flow 'and the scene is not present, so the problem of a cypress is fully controlled. These section components and bribe components can constitute a memory that does not cause a single axis interference. In the present invention, the data writing in the MRAM without the axis interference is stabilized by the Eucalyptus and the 碟. The figure of the figure shows the overall principle of the magnetic memory of the present invention. In Fig. 6, the magnetic memory system includes memory cells [memory cell arrays arranged in a matrix] 2c> the memory cells may contain the MTJ components shown in Figs. 1 and 4 And any of the MJT components are constructed as § recall elements. The present invention can be applied to the two-state thixotropic MRAM cell shown in Fig. 4 and the spin injection MRAM cell shown in Fig. 4. The second magnetic memory has also included: a write system circuit 22 for writing data to the memory unit 70 MC; a read system circuit 23 for performing a material on the memory unit; and a write control circuit 24 controls the writing operation of the write system circuit 22. The write system circuit 22 supplies a write current for writing data to the memory unit to be written in accordance with the write data WD. Therefore, the write-in system 22 is different in accordance with the memory unit MC being a two-state thixotropy 21 319644 200830313 MRAM and a spin injection type MRAM. Here, the write second (four) way 22 supplies a write current to the memory early MC of the write target, and the resistance value of the variable magnetic resistance element 2 of the set memory unit Mc is set. The specific configuration of the write system circuit 22 will be described later. The details of the embodiments will be described in detail. The circuit 23 supplies a read current to the selected body when the data is read. The readout of the memory cell based on the current value is different. The current is generated in the readout system circuit 23 to generate the I purchase data RD. The intrusion control circuit 24 reads the memory data RD from the write memory unit MC via the readout system circuit 23, and determines that the logical level of the read secondary ancestor RD and the written data WD are identical or different; the determination result indicates In the case of poor write, the write is performed according to the written data: the two memory cells are written. The configuration of the writer control circuit 亦 will also be described in detail in the respective embodiments described. And /s Fig. 7 is a flow chart showing the writing operation when the magnetic recording 雔a MRAM shown in Fig. 6 is displayed. Figure 8 shows the magnetic memory of the first::: The spin injection MRAM should not be a flow chart. Hereinafter, the order of writing operations of the magnetic memory of Fig. 7. and Fig. δ is referred to, respectively. First, referring to Fig. 7, the data writing sequence in the state of the thixotropic MRAM shown in Fig. 6 will be described. The body is double. The write control circuit 24 monitors an external command from a not shown, and 22 319644 200830313 - determines whether the command has been designated and waits for receive write = two). Write control circuit • So far. ‘·’, 曰 until the specified data is written to " when the designated data is appropriate.士 ^ eDonkey? 3. The input control circuit 24 prepares the circuit 23 to read out the memory unit "the RD RD of the sector read system unit (step S2). The data RD virtual socket a - = whether the alignment is the same (step S3). When writing the pair of = fat milk memory data ribs and writing data toe logic: f memory unit to the memory of the intrusion The unit writes. When the same, do not believe the other side 'When the write data WD and the read data P value are different, the logic for writing the data to the written object is entered. The write control circuit 24 is based on: (step S4). The input circuit 24. _,,, and 吉果 drive the write and write by the write system 22 to write the data to the write target, and then write The control circuit takes two memory data of the memory unit of the body unit MC image (step S5), and the write pair performs the pre-reading with step S2 (pre_r in step S5) and returns to step S3 again to determine the read data. RD and one. After the value is - or not - repeat the steps ϋ the data WD side until the data WD is written The operation of the data RD is performed in the light step %. Referring to Fig. 8, the value of Fig. 6 is shown as the soil. The data is written in the spin injection type MRAM. No Ck rhyme intrusion control circuit 24 monitoring From the neighbor Q 1 to know, and determine whether '· 319644 23 200830313. Received an instruction to indicate the write (step s1 。). When the indicated data is written, the write system 22 will control the circuit 24兮 悔 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ According to the write control circuit 24, the memory data of the memory unit of the person object is called (step material, the write control circuit 24 performs a judgment read (10) whether the logic values of the bedding material WD match (step S13). When the result of the determination is said to be the same, the writing of the data to the writing unit is ended. On the other hand, if the logical values of the materials do not match, the process returns to step su again, and the data of the input memory unit is written. Repeat the steps to = • verify the action until the write The memory value of the object's memory is the same as the logical value of the material RD and the written data.). As shown in Figure 7 and Figure 8, the memory of the memory unit of the object is entered when the data is written. After the data and write: = out:, the reliability of writing to the memory unit of the write target is reliably stopped for the memory unit of the write target. And this guarantee is $9. Figures (A) to (C) show the map of the Gentleman's Gentleman and the probability of bad occurrence. In Figure 9 (A) to, ", 4 inch [), the upper side of the 319644 24 200830313 graphic system Less than the write characteristics of the memory of the early memory, the lower side of the system does not produce a probability. In the graphs showing the write characteristics and the probability of occurrence of defects, the magnitudes of the write magnetic fields are displayed in accordance with each other. Further, in Fig. 9 (a) and (C), the rewriting conditions of the unit for the probability of occurrence of 1 FIT failure are shown. ratio! The writing conditions for the probability of occurrence of a large defect are slanted: 1 FIT indicates that a defect occurred at 1 〇 5 hours (100,000 hours). _ The MRAM cell will be in the same state as the previous write (the magnetization direction is parallel or anti-parallel). The cell basically uses the magnetic polarization of the magnetic body to become the source of the magnetic polarization. In the spin-polarization of electrons, the direction of the spin-feeding precession changes probabilistically due to the influence of heat. Therefore, as shown in Fig. (a) to (C), even if written under the same conditions In, because the mouth is increased by the number of times, the possibility of writing a bad person is reduced. D... and the writing condition is changed every time the writing is performed, thereby making the same in each of the fine elements and the smoothing elements. When the writing is performed, the condition of the human memory unit is written correctly, so that the anti-parallel state and the parallel direction of the variable magnetic resistance of the memory unit can be surely entered when the component is changed. The middle row of the state = two in' but the parallel state or the anti-parallel state before the write is entered: therefore, the initial state at the time of rewriting is the same, - and the problem of excessive intrusion is considered. Will not pass the sound Into, so there is no need to make the threshold voltage 曰 . 行 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 And the correct writing can be performed in a short time. As described above, according to the present invention, when the data is written, the verification operation of whether or not the writing material has been correctly written is performed. Therefore, even the memory list is included. In the case where the characteristics of the element are changed, the correct writing can be ensured. [Embodiment 1] Fig. 1 is a view schematically showing the overall configuration of the two-state thixotropic MRAM according to the first embodiment of the present invention. The memory cells MC are arranged in a matrix in the memory cell array 20. The row lines corresponding to the memory cells are provided with bit lines BL, and the row corresponding to the memory cells MC is provided with The digit line DL and the word line WL. The memory unit MC includes a variable magnetic resistance element VR (ΜΊ7 element) and an access transistor TRS connected in series with the variable magnetic resistance element VR. Crystal TRS is tied to the corresponding word When WL is selected, it is turned on, and the variable magnetic resistance element VR is coupled to the source line (represented by the ground node). When the data is written, the word line WL is in a non-selected state, and the 10 access transistor TRS is in a non-conducting state. The variable magnetic resistance element VR is arranged so as to correspond to the intersection of the digit line DL and the bit line BL. The digit line DL is connected to the power supply node at one end, and one end of the |yuan line BL is also coupled to the power supply node. The input control circuit 24 includes an instruction decoder 62 that decodes an instruction received via the connection pad PAD to generate a write instruction signal Write and a read instruction signal Read, and a timing generator 64. Generating a write bit line drive signal W_BL and a timing control signal for writing a bit line to drive 26 319644 200830313 'motion signal w_DL, etc. according to an operation mode indication signal from the instruction decoder 62; and a comparator (4) from the memory unit Array 2 〇 选 扪 择 择 择 择 择 择 择 择 择 择 择 择 择 择 择 择 择 择 择 择 择 择 择 择 择 择 择 择 择 择 择 择 择 择 择 择 择 择 择 择 择Line comparison. ^ TO 65: The sequence generation 64 system is composed of, for example, a sequence controller (_ _tr〇ller), and controls the writing of the data to the decibel-out operation according to a predetermined order. In Fig. 1G, a control signal associated with writing is generated in the sequence generator 64. The #write system circuit 2 includes an X decoder 50 set for the digits and the word line machine, and an IO drive crying/WT trace WL and a bit 绫 state 52' set for the bit line BL·. And a pin-shaped bit line driver 56 and a Y decoder 54. The X decoder 50 decodes the internal address mark ADD (X address signal) from the address latch 69 to generate a signal for specifying the memory cell row of the ^ address. The DL driver/WL driver 52 drives the digit line and word line fox based on the memory cell row designation signal from the acknowledgment and the write enable indication signal from the timing generator. In the case of data writing, the driver and the /WL driver 52 form a discharge path corresponding to the selected memory cell, the digit line DL. Thereby, in selecting the memory bank: the digit line DL, the current flows from the power source node to the ground node via the DL driver. The driver is configured to be in the selected state when the data is read out corresponding to the row of the memory cells that have been designated. Thus, in the selected memory cell, the access transistor TRS is turned on, and the current path is formed between the bit line BL and the source line (ground node) = 319644 27 200830313 Y decoder 54 receives the latch from the address The internal address number ADD (Y address signal) of the device 69 generates a signal for selecting the memory cell column of the memory cell array 20 that has been designated. The bit line driver 56 discharges the selected bit line when the data is written. When the bit field machine is in the non-selected state, the bit line driver (6) maintains the non-selected bit line BL at the (four) (four) level. At the time of data reading, the bit line driver 56 becomes an output high impedance (_-dan state. The sense amplifier 58 is connected to the selected bit line when reading the data, and compared with the reference value (electrical comparison) And an internal signal for indicating the memory data of the memory early MC. For example, the ★selling amplifier compares the voltage of the current flowing through the selected bit line to the voltage. The reference voltage in the amplifier 58, the reference voltage for specifying the amount of discharge current of the bit driver 56, and the reference voltage for specifying the amount of discharge current of the digit line DL of the DL driver are generated by the heart rate generating circuit 60. Further, the input data latch 65 reads the input data DJ supplied to the connection pad pAD to generate internal write data. The output data latch reads the material read from the sense amplifier 58, And the external read data D0 is rotated through the corresponding connection pad. The address latch 69 is latched from the external address signal AD provided by the connection pad, and generates an internal address signal AD (X And gamma address signals. The latch timing of these flash locks is set by the timing generator 64. When the instruction specifies the access mode 319644 28 200830313 * (data write or read mode), the timing generator Under the control of 64, these latches 65, 67, 69 will become latched. - Fig. 11 is a view showing more specifically the configuration of the main portion of the two-state thixotropic-MRAM shown in Fig. 10. In the figure, the configuration of the portion associated with the bit line BL and the bit line DL provided in the memory cell array 20 is representatively displayed. In Fig. 11, the X decoder 50 includes digital bit line decoding. The circuit 70 is corresponding to the digit line DL rain setting. The digit line decoding circuit 70 includes _ contains: AND gate G1, which generates an activation signal when writing; AND gate G2, which is an X address signal XADD Decoding; and NAND (reverse) gate NG1, according to the output signals of these AND gates G1 and G2, generate signals for selecting corresponding digit lines. AND gate G1 receives and writes digit line drive signals W_DL, The output signal P/F of the comparator 66 and the write indication signal Write.AND G2 receives the X address signal XADD and generates an active state signal when the X address signal XADD_ specifies the corresponding digit line address. The output signals of the NAND gate NG1 to these AND gates G1 and G2 are active. In the state (Ή level), a signal of an active state (L level) is generated. The DL driver included in the DL driver/WL driver 52 includes a bit line driving circuit 72 provided for each digit line DL. The drive circuit 72 discharges the teaching bit line DL when the output signal of the corresponding X decoding circuit 70 is at the L level. That is, the digit line driver circuit 72 includes: inverter circuits IVK1 and IVK2, 29 319644 200830313 - respectively receiving the output signal of the NAND gate NG1; p-channel m〇s transistor (insulated gate type) Field effect transistor) PQ1, according to the output of the inverter circuit IVK1 • "is number' to the corresponding digit line DL to the power supply node; and, N channel MOS turtle crystal NQ1, according to the output of the inverter circuit The signal combines the digit line DL to the ground node. ^ Inverted TM Freeway 1VK1 receives the voltage on the power supply node (ground node) on the south (high) side power supply node as the operating power (four) voltage. The inverter circuit IVK2 receives the reference voltage Vref as a gate side source. Therefore, the output signal amplitude of the inverter circuit IVK2 is the reference (four) Vref. The reference voltage Vref is supplied as the operating power supply voltage to the inverter circuit IVK2, thereby adjusting the gate voltage level of the MOS transistor NQ1. Thereby, the current driving force of the M〇s transistor NQi is adjusted, and the amount of current flowing through the digit line DL· is adjusted. In the digit line drive circuit 72, when the d signal of the X decoding circuit 7 is L level, the output signals of the inverter circuit IVK1 and the inverter circuit μ become the Η level. In this state, Μ 〇 will become non-conducting, and the surface transistor NQ1 will become conductive. The M 〇S transistor NQ1 is connected to the gate receiving reference Μ 立 立 (4) and is specified by the reference voltage Vref. The current driving force is the number (four) to discharge (the end line of the digit line DL is coupled to the power supply node). # From & pass the current of the digit line to induce a magnetic field. : When the turn-out signal of the X decoding circuit 7 is clamped, the output signals of the inverters M〇S+ and 1 become the L-bit rate. In this state, the electro-crystal ❹ 'Q1 will become the conduction state, and the M 〇 晶晶晶 will total 319644 30 200830313 • become non-conducting state. Therefore, both ends of the digit line DL are coupled to the power supply node while remaining at the power supply voltage (VDD) level. In this state, since the digital line DL does not have a current flowing, the magnetic field is not induced. The Y decoder 54 includes a decoding control circuit 73 that is commonly provided in the bit line of the memory cell array 20, and a Y decoding circuit 74 that is provided corresponding to the bit line BL. The decoding control circuit 73 includes an OR gate OG1, a reception verification read activation signal VFREN and a read instruction signal Read, and an AND gate G3, a reception bit bit line drive signal W_BL, and a comparator. The output signal P/F of 66 and the write indication signal Write. The verification read activation signal VFREN is activated at the time of pre-read and write verification after writing. When the normal data reading has been designated, the read instruction signal Read is activated (driving to the Η level), and when the verifying operation (including the pre-reading) is performed, the verification read activation signal VFREN is verified. Activation (driving to Η level). Therefore, the OR win gate OG1 generates a signal that becomes an active state when the data of the memory cell MC is read. The AND gate G3 generates a signal of an active state (Η level) when all of the received signals are in an activated state (Η position). Therefore, the AND gate G3 generates a signal for specifying a period during which the write current flows through the bit line when the data is inserted. The Y decoding circuit 74 includes an AND gate G4 that receives the Y address signal YADD and a NAND gate NG2 that receives the output signals of the AND gates G3 and G4. Therefore, the Y decoding circuit 74 is a signal in which the wheel becomes active during the period in which the write current flows through the corresponding bit line when the /Y address signal 31 319644 200830313 ‘YADD has designated the corresponding bit line BL. The bit line driver 56 includes a bit line driving circuit 76 provided with each of the corresponding bit lines BL. The bit line driving circuit 76 includes an inverter IV3 that inverts an output signal of the OR gate OG1 of the decoding control circuit 73, and a NAND circuit NK1 that receives an output signal of the inverter IV3 and the NAND gate NG2. The output signal; and the NOR (reverse OR) circuit NRK1 receives the output signal of the OR gate OG1 and the _ output signal of the NAND gate NG2. The NAND circuit NK1 receives the power supply voltage and the ground voltage as the high side power supply voltage and the low side power supply voltage, respectively. The NOR circuit NRK1 receives the reference voltage Vref as a high side power supply voltage. Therefore, the amplitude of the round-out signal of the NAND circuit NK1 is the power supply voltage VDD level, and the amplitude of the output signal of the NOR circuit NRK1 is the reference voltage Vref level. The bit line driving circuit 76 further includes: a P channel MOS transistor 10PQ2, which combines the bit line BL to the power supply node according to the output signal of the NAND circuit NK1; and an N channel MOS transistor NQ2 according to the NOR circuit NRK1. The output signal combines the bit line BL to the ground node. When the data is written, the output signal of the OR gate OG1 is the L level, so the output signal of the inverter IV3 is the Η level. When the write bit current is selected by the bit line BL, the output signal of the NAND gate NG2 is at the L level. In this state, the output signal of the NAND circuit NK1 becomes the power supply voltage level. < Η level, the output signal of the NOR circuit NRK1 will become the reference voltage Vref 32 319644 200830313 • Level Η level. Therefore, the MOS transistor PQ2 becomes non-conductive, and the MOS transistor NQ2 becomes conductive. Therefore, the bit line BL • is discharged via the MOS transistor NQ2 (one end of the bit line BL is combined to the power supply node). The amount of current flowing from the power supply node to the ground node via the bit line BL is set by the voltage supplied to the gate of the MOS transistor NQ2, that is, by the voltage level of the reference voltage Vref. Moreover, when the data is written, the bit line BL of the non-selected column becomes the Η level due to the output signal of the inverter IV3, and the output signal _ of the NAND gate G2 also becomes the Η level, so the MOS transistor PQ2 It will be turned on, and both ends of the bit line BL are coupled to the power supply node. In the configuration shown in Fig. 11, the sense amplifier 58 includes a sense amplifier (Sense Amplifier) circuit 78 provided for each of the bit lines BL. The sense amplifier circuit 78 includes a comparison circuit CMP for comparing the voltage of the bit line BL with the read reference voltage VRFER, and an AND gate G5 for receiving an output signal of the OR circuit OG1 0 included in the decode control circuit 73 and The output signal of the AND gate G4 included in the Y address decoding circuit 74 generates an output signal of the NAND gate G2 of the decoding circuit 74 when the sensing activation signal EN for activating the comparison circuit CMP is generated. It is a standard. Therefore, in the bit line driving circuit 76, the output signal of the NOR circuit NRK1 becomes the L level, and the MOS transistor NQ2 becomes non-conductive. In addition, when the data is read, the output of the OR gate OG1 will become the Η level, and the output signal of the inverter IV3 will become the L level. Therefore, the output signal of the NAND circuit ΝΚ1 becomes a Η level, and 33 319644 200830313 M 〇 S electric 曰 _ JQ2 will become non-conductive. - Pay, one end of the bit line rainbow is coupled to the power supply node, and the bit το line drive circuit 76 is provided on the iron &, (3) Ai Cheng output high impedance state. The current flowing through the bit line BL is controlled by the variable lightning resistance of the Ida 5 body early to MC and the access of the unillustrated Thunder Touch 2 ^ package to pick up the B body The amount of current discharged is determined. In the salt ampere amplifier circuit 78, 趑 A A — Ά Τ compares the voltage of the bit line BL with the read base car + voltage VREFR - lL 士士,

仃 轶 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , > Also, when the comparison circuit CMP is in an inactive state, the sense amplifier circuit 78 is in a high-impedance state, and does not affect the data readout of the bit line of the selected column. The comparator 66 includes an EX〇R (mutually exclusive OR) gate eg, which receives an output signal of the output data flash lock 67 of the output signal of the lock sense amplifier circuit 78, and the input data latch 65. The input of the flash lock is poor. The EXOR gate EG is inconsistently detecting the gate, and when the output data asks that the locker 67 and the input data locker 65 have different logic values of the flash lock data, the wheel signal ρ/F is set to the clamp level. The output data latch 67 is used to output the data read from the sense amplifier circuit 78 as the external = read data D when the read mode for reading the data to the outside is output. Although the internal readout and the external read path switching of the output data latch 67 are not explicitly shown, they are executed by the timer 64. The output signal P/F of the comparator 66 is supplied to the timing to generate a cries. The timing generator 64 sets the write order based on the operation mode # 314644 34 200830313 'signal and verification result indication signal Ρ/F from the instruction decoder 62. Further, since the command decoder 62 and the address latch 69 correspond to the configuration shown in Fig. 10, detailed description thereof will not be repeated. * Fig. 12 is a timing chart showing the operation of the data of the two-state thixotropic MRAM shown in Fig. 11. Hereinafter, the data writing operation of the two-state thixotropic MRAM shown in Fig. 11 will be described with reference to Fig. 12. At the time of data writing, the write data is supplied to the input data latch 65, and the write instruction (write command) is supplied to the command decoder 62. The address latch _ 69 receives the write address. Based on the write instruction, the command decoder 62 sets the write instruction signal Write to the active state. The read instruction signal Read is in an inactive state (L level). The memory device is a two-state thixotropic MRAM. In order to prevent data inversion and prevent the writing of erroneous data, the memory data of the memory unit to be written is read before the first writing according to the write address. Out. At the time of the pre-reading, the timing generator 64 activates the verification read activation signal VFREN. Therefore, in the decoding control circuit 73, the output signal of the OR gate OG1 becomes a Η level. In this state, the bit line driving circuit 72 outputs a south impedance. The word line driving circuit is not driven, and the word line is driven to the selected state based on the X address signal XADD supplied from the address latch 69. Next, according to the Υ address signal YADD, the output signal of the AND gate 04 of the Υ decoding circuit 74 becomes 11 levels. Therefore, the sense activation signal EN is activated, and the sense amplifier circuit 78 compares the voltage corresponding to the current flowing through the bit line BL with the read reference voltage VREFR and generates it based on the comparison result. Read data internally. 35 319644 200830313 .# The memory data of the memory of the write object read from the sense amplifier circuit 78 is inconsistent with the logical value of the write data from the outside: when the output signal of the comparator 66 is jvu H Level. Therefore, in the decoding circuits 70 and 74, the NAND gates (1) and (7) are enabled ((10)(4). In addition, the B-order generator, 64 will indicate the account number IVF according to the verification result of the H-level, and the number of digits will be written. The driving signal w_DL and the writing bit line driving signal W_BL are sequentially activated. During the writing of the digit line driving signal W_DL·, by the decoding circuit 70 and the digit line driving circuit 72. The current flows from the power supply node to the ground node on the corresponding θ digit line DL. Further, for the bit line, the signal is driven by the Υ decoding circuit 74 and the bit line driving circuit 76 according to the write bit line. A BL is discharged. When the writing is completed, the timing generator 64 again activates the verification readout 彳 旒 旒 VFREN. In this case, when a write failure to the body unit MC is generated, When the written data does not match the logical value of the memory cell, the verification result indication signal p/F is also the Η level. Therefore, the timing generator 64 will again drive the signal w_dl and the sequence. Activation. After the second writing is completed, it is used again. Whether the broken data has been correctly written into the verifying action. When the writing is normally performed to the recording unit, the read data from the output data latch 67 and the data from the output door latch 65 The logical value of the input data will be the same, and the verification result indicating signal P/F of the comparator $6 will become the L level. In this case, the timing generator 64 ends the writing. Then, the indication signal is written. 36 319644 200830313 'Write is driven to inactive state. On the other hand, in the write verification operation, when it is judged that the write is defective, • Write is performed again. Repeat the write and write verification until the data is positive. The normal write or the predetermined write test condition is satisfied. The write test condition will be described later in detail. Further, in the comparator 66, the verification result instruction signal P /F may be used in the initial state (standby state). The configuration of the output data latch 67 and the input data latch 65 can be set to a value different from the initial logical value. Medium display The order in which the bit data is written. For example, like a burst write, when a write instruction instructs data to be sequentially written to a plurality of addresses, the address latch 69 can also be read into the original address. The received address ADD (refer to Fig. 10), and the write address is sequentially updated from the previous address to perform data writing. In this case, pre-read and write verification are performed on each address. The figure shows an example of the configuration of a portion associated with one word line WL. The X decoder 50 includes an X address decoding circuit 80 provided for each of the word lines WL. The X address decoding circuit 80 includes: The AND gate G6 receives the X address signal XADD and the NAND gate NG3 receives the output signal of the OR gate OG1 included in the word line control circuit shown in FIG. 11 and the output signal of the AND gate G6. The AND gate G6 is an AND type decoding circuit that outputs a level signal when a corresponding word line is designated by the X address signal XADD. Therefore, the NAND gate NG3 outputs a signal of the L level at the time of data reading and selection. When the corresponding word 37 319644 200830313 • the line WL is in the non-selected state, the output signal of the X decoding circuit 80 becomes the H level. • In the DL driver/WL driver 52, the word line driver circuit 82 of each of the corresponding word lines • WL is provided. The word line driving circuit 82 includes a P channel MOS transistor PQ3 and an N channel MOS transistor NQ3, and the gate receives the output signal of the NAND gate NG3. The word line WL is connected to the gate of the access transistor TRS of the memory cell MC of the corresponding row. In Fig. 13, a memory cell of one bit is representatively displayed. In the word line driving circuit 82, when the output signal of the X address decoding circuit 80 is L level, the P channel MOS transistor PQ3 is turned on, and the word line WL is driven to the power supply voltage level. Therefore, in the memory cell MC, the access transistor TRS is turned on, and a path is formed in which a current flows from the bit line BL through the variable resistance element VR to the source line (ground node). In the non-selected state, the output signal of the X address decoding circuit 80 is at the Η level, and the word line WL is maintained at the ground A voltage level by the MOS transistor NQ3. In this state, in the memory cell MC, the access transistor TRS is in a non-conduction state, and a path through which a current flows through the variable magnetic resistance element (MT J element) is cut. As shown in Fig. 13, the word line drive circuit and the X address decoding circuit are used to allow a current corresponding to the resistance value of the variable resistance value VR to flow through the memory cell MC during data reading. [First Modification] Fig. 14 is a view schematically showing the configuration of a writing/reading unit of a two-state thixotropic MRAM according to a modification of the first embodiment of the present invention. At 38 319644 200830313

In the Fig. 14, the read gates RGO to RGn are set for each of the bit lines BL0 to BLn, and the write column selection gates WG0 to WGn are set. Read column selection • Select gates RG0 to 11〇11 are turned on when the read column selection signals 5^81^ to RCSLn are activated. The write column selection gates WG0 to WGn are turned on when the write column selection signals WCSL0 to WCSLn are activated. The read column select gates RG0 to RGn are commonly coupled to the internal read data line ROL. The write column select gates WGO to WGn are commonly connected to the internal write data line WIL. The read column selection signals RCSL0 to RCSLn are generated based on the Y address signal YADD when data is read. The write column selection signal WCSL0 is generated based on the Y address signal YADD when data is written. The sense amplifier 90 is provided for the internal read data line ROL, and the write driver 92 is provided for the internal write data line WIL. The sense amplifier 90 is provided with the same configuration as the sense amplifier 10 circuit 78 shown in Fig. 11. The write driver 92 is also provided with the same configuration as the bit line drive circuit shown in Fig. 11. The operation of these sense amplifiers 90 and write drivers 92 is performed in accordance with the output signal of the decode control circuit 73 shown in Fig. 11 (as long as the output signal of the gate G4 receiving the Y address signal YADD is set to a constant time selection The status can be). In the configuration shown in Fig. 14, it is not necessary to provide the sense amplifier circuit and the bit line drive circuit for each of the bit lines BL0 to BLn, so that the layout area is reduced. The data writing and reading operations are the same as the two-state thixotropic changes shown in Fig. 11 319644 200830313 • MRAM. The read column selection gate RCSLi and the write column selection gate WCSLi corresponding to the selected column are driven to the selected state in accordance with the Y address signal at the time of reading and writing. Further, in the configuration shown in Fig. 14, the sense amplifiers 90 may be commonly provided in the bit lines BL0 to 3111, and the write driver 92 may be provided one-to-one for each of the bit lines BL0 to BLn. It can avoid the wiring resistance of the internal write data line WIL affecting the bit line write current, and the rain can correctly generate the bit line write current. In addition, as with the word line driver circuit, the digit line driver circuit is separately provided for the digit line. [Variation 2] FIG. 15 is a view schematically showing an overall configuration of a spin injection type MRAM according to a second modification of the first embodiment of the present invention. In the spin injection type MRAM shown in Fig. 15, in the memory cell array 22, the memory cells MC are arranged in a matrix, and each of the memory cell rows is provided with a word line WL and a digit line DL. Further, bit lines BL and source lines SL are provided for each column of the corresponding memory cell MC. In the spin injection type MRAM, since the magnetization direction of the text early element is set in accordance with the spin injection, it is not necessary to particularly set the digit line DL. However, the magnetic field is applied to the hard magnetization axis direction of the variable magnetic resistance element (MJT element) VR by the current of the digit line DL, thereby assisting the magnetic field inversion. In the spin injection type MRAM, the easy magnetization axis and the hard magnetization axis of the variable magnetic resistance element VR are arranged in parallel with the bit line and the word line, respectively. In this MRAM, the source current decoder 100 and the source line driver 102 are provided in the write system circuit 2A between the bit line BL and the source line SL by 40 319644 200830313. The source line driver 102 and the bit line driver 56 determine the direction of the current flowing between the bit line bl and the source line SL based on the logic value of the input data. In the write control circuit 24, the instruction decoder Π2, the timing generator 114, and the comparator 116 are provided similarly to the toggle flop MRAM. In the spin injection type MRAM, pre-reading before writing is not required. The command decode state U2 is written in order to invalidate the judgment result of the comparator 116 at the time of the first write, so that the comparison invalidation signal \StyWnte is further generated. According to the comparison invalidation signal 1st_Write, the comparison result of the comparator 116 is invalidated during the first write-down period, and there is no information about the data input and the memory unit of the object to be written. The logical value will be written. However, in the spin injection type MRAM, it is not necessary to generate the comparison invalidation signal lst_Wdte when performing the pre-reading, and the same writing order as the two-state thixotropic MRAM. The write control circuit can be constructed in the same way as the two-state tactile change and the self-lighting type.

The ancestor generation system 114 generates the write clock signal W ΡΤτγ 1 -1 port 跣W_PULSE only based on the write bit line drive signal w BL . The error is written by the pulse nightmare W-PULSE to set the write time. The MRAM two-state thixotropic MRAM shown in Fig. 15 constitutes the same reference numerals and the detailed description thereof will be omitted. The other configuration is the same as that shown in the first drawing. The same reference numeral 16 is used to more specifically display a bit line BL of the spin injection MRAM of the 盥u ” _ 4 Under | Known bit line DL, and a source 319644 41 200830313 • Structure of the connected part of line SL. In the spin injection type MRAM, according to the logic value of the written data, it flows through the bit line BL and the source line. The direction of the current between the SLs will be different. When the first data is written, in order to stop the pre-reading, the comparator Π6 is reset to receive the output signal of the EXOR gate EG and the comparison invalidation signal lst_Write. OR gate OG2. The verification result indication signal P/F is output from the OR gate OG2. In the decoding control circuit 73, in order to change the direction of the bit line current corresponding to the logical value of the written data, the reset setting is useful to receive the input from the input. The input data of the material latch 65 and the AND gate G7 of the verification result indication signal P/F from the comparator 116. The output signal of the AND gate G7 is applied to the AND gate G3. The AND gate 03 receives the replacement write bit. Yuan line drive signal W—write pulse signal W_PU The configuration of the bit line driving circuit 76 provided in the bit line driver 56 and the Y address decoding circuit 74 provided in the Y decoder 54 is the same as that of the two-state thixotropic MRAM shown in FIG. The same reference numerals are attached to the corresponding parts and the detailed description thereof is omitted. Further, the digit line driver circuit 72 included in the digit line driver for driving the digit line DL and the digit line decoding circuit 70 included in the X decoder 50 are provided. The configuration is the same as the configuration shown in Fig. 10. The same reference numerals will be given to the corresponding parts, and the detailed description will be omitted. The source line decoder 100 includes a source line decoding circuit 122 corresponding to the source. Each of the lines SL is provided; and the source line decoding control circuit 120 is commonly disposed on the source line SL. The source line decoding control circuit 120 includes an inverter IV4, which is an inverted input data latch. 65~ latch 42 319644 200830313 'data; and AND gate G8, receive output signal of write verification result indication signal P /F and inverter IV4. When writing data is L level and write and verify result The indication signal P/F is Η When it is indicated as a write failure, the AND gate G8 generates a signal of the level. The source line decoding control circuit 120 includes: an AND gate G9, which receives the output of the write pulse signal WJPULSE and the AND gate G8. The signal and the write indication signal Write; the OR gate OG3 receives the read instruction signal Read and the verification read activation signal VFREN; and the OR gate OG4, 10 receives the output of the OR gate OG3 and the AND gate G9. At the time of writing, during the activation of the write pulse signal W_PLUSE, the AND gate G9 outputs a signal of the level. The OR gate OG3 has the same function as the OR gate OG1 included in the bit line decoding control circuit 73, and the signal of the level is rotated when the data is read. By using the OR gate OG3, the source line SL is coupled to the ground node at the time of data reading, and a path through which the current flows from the bit line BL to the source line SL is formed. The source line decoding circuit 122 includes: an AND gate G10, which receives the Y address signal YADD; and a NAND gate NG4 that receives the output signal of the OR gate OG4 and the output signal of the AND gate G10. The AND gate G10 has a function as an AND type decoding circuit, and outputs a 11-level signal when the Y address signal YADD specifies a corresponding column. The source line driver 102 includes a source line driver circuit 124, which is provided corresponding to each of the source lines SL.

The source line driving circuit 124 includes: inverter circuits IVK3 and IVK4, which respectively receive output signals of the NAND gate NG; P channel MOS 43 319644 200830313, transistor PQ4, which is outputted by the inverter circuit IVK3. When the signal is L-level, the corresponding source line SL is coupled to the power supply node; and the N-channel MOS • transistor NQ4 is connected to the output signal of the inverter circuit IVK4, and the corresponding source line SL is combined. To the ground node. _ The reverse tank circuit IVK3 receives the power supply voltage as a high-side power supply voltage. The inverter circuit IVK4 receives the reference voltage Vref as a high side power supply voltage. Therefore, when the N-channel MOS transistor NQ4 is turned on, the amount of current flowing to the ground node via the source line SL is controlled by the reference voltage Vref. In the source line decoder 100 and the source line driver 102, the following operations are performed at the time of data writing. First, when the verification result indicating signal P/F is L level and indicates normal writing, the output signal of the AND gate G8 becomes L level, and thus the output signal of the AND gate G9 also becomes the L level. When the data is written, the read instruction signal Read and the verification read activation signal VFREN are also at the L level. In this state, the output signal of the OR gate OG4 will become the L level, and the output signal of the NAND gate NG4 will become Η.

W level. Thus, in the source line driving circuit 124, the MOS transistor PQ4 becomes conductive, and the MOS transistor NQ4 becomes non-conductive. As such, the source line SL is coupled to the power supply node. At this time, in the bit line decoder, the output signal of the AND gate G7 is also the L level, and therefore, the output signal of the NAND gate NG2 becomes the Η level. The output signal of the OR gate OG1 is the L level. Therefore, the output signal of the NAND circuit NK1 becomes the L level, and the output signal of the NOR circuit NRK1 becomes the L level. Thus, the bit line BL will remain at the supply voltage level 44 319644 200830313, which is accurate. In the standby state or the non-selected state, the Y address signal YADD does not - specify the corresponding bit line BL and source line 81^. Therefore, in the bit line decoding, in the circuit 74, the output signal of the NAND gate NG2 becomes 11 level, and the minus 08 transistor NQ2· becomes non-conductive. Also, the output signal of the OR gate OG1 is the L level, and therefore, the output signal of the inverter circuit IV3 is the Η level. Therefore, the output signal of the NAND circuit ΝΚ1 becomes the L level, the MOS transistor PQ2 is turned on, and the bit line BL is maintained at the power supply voltage level. The source line is also the same, the output signal of the NAND gate NG4 will become the Ή level, the MOS transistor PQ4 will become conductive, and the MOS transistor NQ4 will become the non-conductive state. Thus, the source line SL is also maintained at the power supply voltage level. The configuration of the decoding circuit and the word line driving circuit for word line selection is the same as the configuration shown in Fig. 13 except that the word line decoding circuit 80 performs the X address decoding operation at the time of writing and reading. That is, in the configuration of ▲ shown in Fig. 13, the OR gate OG1 is not used. When the data is written, the verification result indicates that the signal P/F is the Η level. At this time, the potentials of the bit line BL and the source line SL differ depending on the logical value of the write data from the input data latch 65. (1) Writing of H data: In this case, first, for the bit line, the output signal of the AND gate G7 becomes the Η level. At the time of writing, according to the write pulse signal WJPULSE, the output signal of the AND gate G3 becomes a Η level, and thus, the output signal of the NAND gate NG2 becomes a binary level. here? Assume that the corresponding 45 319644 200830313 • bit line is selected. In this case, the output signal of the NAND circuit NK1 becomes a Η level, and the MOS transistor PQ2 becomes a non-conductive state. QR gate • The output signal of OG1 is L level when data is written, and the output signal of NOR circuit NRK1 ' becomes Η level. Thus, the MOS transistor NQ2 is turned on, and the bit line BL is coupled to the ground node via the MOS transistor NQ2. On the other hand, for the source line SL, the output signal of the inverter IV4 becomes the L level, and the output signal of the AND gate G8 becomes the L level. Thus, the state of the 10 is the same as the non-selected state or the standby state, and the source line SL is coupled to the power supply node by the source line driving circuit 124. For the digit line, the output signal of the digit line driver circuit 72 becomes the L level. On the digit line DL, current flows from the power node to the ground node. Further, by the word line drive circuit (not shown), the corresponding word line is driven to the selected state, and the access transistor TRS is turned on. Thus, in this case, current flows from the source line SL to the bit line BL. The write current for this memory 10 cell MC is controlled by the gate voltage (i.e., the reference voltage Vref) of the MOS transistor NQ2 included in the bit line drive circuit 76. (2) Writing of L data: In this case, for the bit line, the output signal of the AND gate G7 will change to the L level. Thus, the output signal of the NAND gate NG1 will become the Η level. Thus, in the same manner as in the standby state, in the bit line driving circuit 76, the MOS transistor PQ2 is turned on, and the bit line BL is coupled to the power supply node.乂 · ... In the case where the L data is written to, the word \ line WL is also driven to the Η level, 46 319644 200830313 • The digit line DL is driven to the selected state and the digit line current is passed. On the other hand, for the source line, the output signal of the inverter IV4 will change to a Η level, and thus, the output signal of the AND gate G8 will become a Η level. • When the write pulse indication signal WJ>ULSE becomes clamped, the NAND gate NG4 becomes a Η level. Thus, in the source line driving circuit 124, the MOS transistor NQ4 becomes conductive, and the MOS transistor PQ4 becomes non-conductive. Thus, in this state, current flows from the bit line BL to the source line SL. At this time, the electric current flowing through the memory cell MC is controlled by the high side power supply voltage (i.e., the reference voltage Vref) of the inverter IVK4 of the source line driving circuit 124. When reading data, for the bit line, the output signal of the OR gate OG1 will become the Η level, so that the output signal of the NOR circuit NRK1 will become the L level. The output signal of the inverter IV3 will become the L level, and thus, the output signal of the NAND circuit NK1 will become the Η level. Thus, the MOS transistor PQ2 becomes non-conductive. That is, at the time of data reading, the bit line driving circuit 7 6 becomes the output south impedance state. On the other hand, for the source line, in the source line decoding control circuit 120, the output signal of the OR gate OG3 becomes a Η level. Thus, in the source line decoding circuit 122, the output signal of the OR gate OG4 becomes a Η level, and the output signal of the NAND gate NG4 becomes an L level. Thus, in the source line driving circuit 124, the MOS transistor NQ4 becomes conductive, and the MOS transistor PQ4 becomes non-conductive. Thus, the source line SL is coupled to the ground node. When reading data, use the connection gate (not shown) to connect the line of the selected column 47 319644 200830313 to the power supply node, so that the current will flow from the bit line to the source line SL, and the remaining current will be It is supplied to the sense amplifier circuit for comparison. In this case, the sense amplifier circuit may be configured to have a current source, and the current of the current source is supplied to the selected bit line in accordance with activation of the read activation signal. Therefore, in the spin injection type MRAM shown in Fig. 16, it is also possible to confirm whether or not the write operation has been normally performed after the data is written by using the comparator 116. _ and 'In the memory cell in which the column is selected and is not selected, the access = TRS is in a non-conducting state, and the current flow path between the bit line BL and the source line is cut off. In the memory cell in which the row is selected and is not selected, the bit line BL and the source line SL are maintained at the same power supply voltage level and the current does not flow. Fig. 17 is a timing chart showing the operation of the spin note, the smram, and the write operation shown in Fig. 16. Hereinafter, the operation at the time of data writing of the spin injection type MRAM shown in Fig. 16 will be briefly described with reference to Fig. 17. The instruction decoder 112 drives the write instruction signal Write to an active state in accordance with a write = indication command received via the connection pad PAD. In this case, the deduction decoder 112 drives the comparison invalidation signal lst-Wdte to the active state. The sequenced generation 114 is driven to the active state by writing the digit line drive signal W-DL& write pulse apostrophe W-PULSE at a predetermined timing based on the write instruction from the instruction decoder 112. Based on the activation of the comparison |effect signal lst_Write from the instruction decoder ,2, the verification result indicating signal P/F from the comparator 48 319644 200830313 116 is fixed to the H level. =' By the digit line decoding circuit 7G and the digit line driver ^ = = current flows through the digit line, and a supplementary magnetic field is generated. In addition, 2^=' is controlled by the bit line decoding circuit 74 and the bit line decoding control unit, and the bit line BL corresponding to the selected column is input from the data block lock 65_ source (4) or the ground node. . The bit line bl of the non-selected column is maintained at the power supply voltage level by the corresponding bit line driving circuit 76. The post-solution St selects the source control line for the source line SL', and combines it with the logic value of the written data to the ground node or the power point. The non-selective source line SL is coupled to the power supply node by the source line driver circuit 124.

In this state, between the bit line and the source line SL, the current will flow in the direction corresponding to the value of the written material, and the data of the executing unit is written. U When the predetermined period elapses, the write digit line activation signal w_dl and the write pulse signal W_PULSE are driven to the inactive state (L level). This writes the digit line activation signal WJ>L_ The change in the magnetization direction of the variable magnetic resistance source member VR of the memory το MC can be driven to the inactive state at a timing earlier than the write pulse (4) w_puLSE. In Fig. 17, the inactivation timing of the write bit line activating signal W-DL may also have a temporal width, and the reset period is displayed in a two-way arrow. / 319644 49 200830313, When this writing ends (when the write pulse signal WJPULSE is deactivated), the comparison invalidation signal lst_Write is driven to the L level. After this write, the timing generator 114 will drive the verification activation 'signal VFREN to an active state for a predetermined period of time. When the verification activation signal VFREN is activated, in the bit line drive circuit 76, both the P channel MOS transistor and the N channel MOS transistor NQ2 become non-conductive and become output south impedance states. In the source line driver circuit 124, the source line SL of the selected column is also coupled to the ground 10 node via the N-channel MOS transistor NQ4. Further, the word line WL is driven to the selected state by the word line driving circuit (not shown), and the access transistor TRS is turned on. Thus, a path of current flow is formed between the bit line BL and the source line SL. The supply current (not shown) from the sense amplifier circuit 78 also flows to the bit line via the gate circuit that connects the bit line BL to the power supply node when read. This bit line current varies depending on the memory material of the memory cell MC. The sense amplifier circuit 78 senses the power of the bit line BL

A pressure change or current change. Here, the sense amplifier circuit 78 is activated by sensing the activation of the W activation signal EN (only for the selected column). In the case of poor writing, the verification result from the comparator 116 indicates that the signal P/F is at the Η level. Therefore, when the verification result signal VRFEN is deactivated, the timing generator 114 drives the write digit line activation signal W_DL and the write pulse signal W_PULSE to the active state again in a predetermined order, and Rewriting to the memory cell MC is performed again. Next, the verification operation after writing is performed again. When the verifying action is performed by verifying the activation signal VRFEN, the verification result indicating signal p/F from the comparator m becomes the l level after the writing 50 319644 200830313 has been normally performed. In this way, the timing generator 丨j 4 will supply the signal that the intrusion indication signal 'Wme is deactivated to the instruction decoder ι2 with M and end the writing of the data. In this case, in the standby state, the bit line machine and the source line are repeatedly leveled by the bit line driving circuit 76 and the source line driving circuit 124. Therefore, the digital line sinking system is maintained at the power supply voltage level by the digital line driving circuit 72. ...in this standby state, the verification result indication signal P/F from the comparator 116 is only required to be set to the initial state. The timing generator 114 is configured, for example, by a sequence controller (se), and generates a write pulse in a predetermined order based on a write instruction signal or a read instruction signal from the instruction decoder ι2. The ^W_PULSE, the write digit line activation signal w_dl, and the verification activation signal VFREN (considering the logic level of the verification result indication signal p/F), the instruction decoder 112 generates pulses according to instructions from the outside. The wave signal is used to define the inactivation of the pulse signal by the timing generator 114, whereby the write indication signal WHte and the read indication signal - can be generated. As described above, according to the embodiment of the present invention, in the magnetic memory (MRAM), the verification operation of whether or not the writing has been normally performed is performed after the data is written. Therefore, high reliability data writing can be realized. In addition, in the case of poor write, the MRAM will revert to the initial state before writing. Therefore, even if rewriting is performed under the same writing condition, the probability of writing failure is caused by the reduction of the 219644 51 200830313 repetition of the rewriting due to the influence of heat on the spin state of the electron. Can guarantee the actual data to be written. At this time, as described in the embodiment described later, the writing condition can be changed at the time of Cao writing. [Embodiment 2] Fig. 18 is a timing chart showing the spin injection MRAM of the second embodiment of the present invention. Hereinafter, an embodiment of the present invention will be described with reference to Fig. 18: #MRAM(四) Person order. Here, the same operation is performed for both the mRAM, the m! thixotropic MRAM, and the self-mutilation type (the two-state thixotropic mram is described later). The MRAM system takes in the external T CMD and the address signal AD from the outside in synchronization with the clock signal CLK. Moreover, the internal operation cycle is also specified by the clock signal CLK. 8. In the loop starting from time T0, the write command is received as the finger τ CMD, and the address signal AD is received as the address signal AD from the external port. According to the write command, it is internally triggered by one shot. The mode of the pulse wave (〇ne sh plus pulse) generates a write mode indication signal Φ W . According to the write mode indication signal (DW, the write command letter Write becomes active during a predetermined period. According to the write instruction signal Write, the digital line drive signal W_DL and the write pulse signal W-PULSE are written. Will be activated. In the first write, the comparison invalidation signal lst_Write will be activated. When writing, send busy / ready signal B / RZ to the outside, indicating write中^ 319644 52 200830313 ^ Next, in the loop starting from time το, when the writing ends, the write instruction signal Write is deactivated, and the comparison invalidation signal 1 st_Write is deactivated. When the indication signal Write is not 'activated, the write verification activation signal VFREN is activated, and the read data and the write data from the memory unit to be written are compared with the internal read data. When the input is bad, the verification result indication signal P/F is the Η level. In the cycle starting from the time Τ1, the verification result _ indication signal P/F according to the Η level is again supplied as a one-shot pulse wave type. Write mode indication No. Φ W. In this way, the write operation is performed again for the same address and the write verify operation is performed. In the loop starting from time Τ1, the busy/ready signal B/RZ is external, in this loop. The access from the outside is prohibited. According to the verification result, when the display has been normally written, the verification result indication signal P / F will become the L level. Thus, the busy green / ready signal / / RZ will be set To the L level, it is set to allow access. Therefore, in the loop from time Τ2, the processor (or controller) can access the MRAM (write or read data)- -------------10.--------------- - As shown in Figure 18, in the case of synchronization with the clock signal CLK Next, the busy/ready signal B /RZ is transmitted to the outside during the internal writing period, whereby the external processor (or controller) can know the internal state of the MRAM. When the writing is bad, the writing is internally generated. Incoming mode indication signal Φ" 53 319644 200830313 W 'and equivalently send internal sequence for write verification after rewriting =, borrow The writing can be performed even with the same touch time. / 19 The figure schematically shows the instruction decoder 112 and the timing generator u of the spin type = type 祖 of the second embodiment of the present invention. The decoder 112 corresponds to the spin decoder = MRAM instruction decoder 112 shown in Fig. 15. In the figure, the 'instruction decoder 112 includes: the write command detection/circuit 202 is synchronized with the 8 pulse signal CLK. If the finger 7 C^D is taken in from the outside, then the write command is received; the circuit outline receives the output signal of the write command detection circuit 2〇2 and the rewriter indication from the timing generator 1H. The signal φψΙ; and the write activation circuit are applied, and the write indication signal Write is generated according to the write mode indication signal output from the OR private channel 204. The t write command detecting circuit 2 〇 2 detects whether the CMD is a write command when the clock signal CLK rises. The command CMD can be supplied by combining the logical levels of a plurality of letters, or as a decoded signal. The write command detection circuit 20.2 generates a one-shot pulse wave signal when a write command is detected. Thus, when the OR circuit 2〇4 receives a write command from the external or receives the rewrite instruction signal from the timing generator 21〇, Φ WI 8 ’ will activate the 指instruction signal φ^. The rewrite instruction signal Φ has the same pulse width as the pulse signal generated by the write command detecting circuit 202, and the rewrite instruction signal 〇W1 is used as an internal write command. Intrusion, the sexualization circuit 2 0 6 is responsive to the write mode indication signal φ $ 319644 54 200830313 activation, which is generated by a pulse signal Write having a predetermined time width. The number is used as a write instructing letter. • The I command solution includes a pre-reading inhibiting circuit 2〇8, and the 私-type private signal φ w is input to generate a comparison ▲', according to 1 st-WHte. The pre-reading inhibiting circuit 2〇8 generates a pulse wave signal having a one-shot with the heart of the write indication signal according to the activation of the write mode, the second signal, and the W, and enters the first time of the write time. The data reading and comparison operation of the memory cell of the object, (4) 彳 = timing generator 114 is equivalent to the day ± T ° ° 114 shown in Fig. 15. The timing generator 114 includes a write current to drive the activating power: =, the "G human mode indication signal φ % from the instruction decoder 2 (8) to generate the horse-in control signal W_DL and w-PULS] E. The mram is a spin injection type MRAM, and the write current drive activation circuit 2 is based on the input mode indication signal (DW generates a write bit line drive number W-DL and a write pulse wave signal w_pijls at a predetermined timing; e The 10s s order generation state 114 includes: a verification activation circuit 212 that generates a verification read activation signal VFREN in response to inactivation of the write indication signal Write from the instruction decoder 112; and a busy signal generation The circuit 213 generates a current/ready signal B/RZ according to the verification result indication signal p/F. The verification activation circuit 212 is composed of, for example, a circuit for generating a one-shot pulse wave signal, and responds to the write indication. The signal Write moves toward inactivation, and it is difficult to verify that the read activation signal vfren is active in a predetermined period. _ 55 319644 200830313 When the busy signal generation circuit 213 is in the write mode, it does not signal according to the verification result. P/F to generate the busy/ready signal B/RZ. When the busy//ready signal B/RZ is set to the H level when the busy state is configured, the busy signal generating circuit 213 is On the other hand, when the busy/ready signal B/RZ g β is again set to the l-level when the busy state is formed, the busy green signal generating circuit 2 is constructed by an inverter circuit. The verification result indication signal!VF is set to the l I level when it is in the standby state. The order generation is 114 and includes: the flash locker 214, which passes through the activation of the verification read f activation signal VFREN ( The result of the test also means that the signal p/F is not passed; and the pulse wave generating circuit generates a re-intrusion indication signal 1WI according to the output signal of the lock 214 and the clock signal CM. In the test, the 发 矣 、 、, gong & ϋ 出 活性 活性 活性 活性 活性 活性 活性 活性 活性 活性 活性 活性 活性 活性 活性 活性 活性 活性 活性 活性 活性 活性 活性 活性 活性 活性 活性 活性 活性 活性 活性 活性 活性 活性 活性 活性 活性 活性 活性 活性 。 。 。 The W-skin generation circuit 215 is synchronized with the rise of the clock φ 丄〇 丄〇 clock CLK CLK, to generate the waveform of the pulse wave early to generate a re--partial 冉舄 private 私 private signal Φ The WI is written as the internal I5. At the time of verification, the action control is also performed to execute the writer. This U-grain is applied with the same flaw, and in the two-state thixotropic MRAM, the ο 贝 动作 action in the Ma Da loop of the D-U is stopped. After the write, the • ancestor action will be read corresponding to the re-write. Into the cycle time.

When the line is written normally, 'Because the verification result indication signal p/F 319644 56 200830313 will be moxibusted to the L· level, the pulse wave generating circuit a can be prevented in the next cycle after the normal writing. :produce::. The 'this' signal Φ wi is used as an internal write command. Intrusion refers to - as described above, when writing internally, the verification operation is performed, and when::==, 'will generate a corresponding write command internally=two, and the data can be written reliably. people. And, ς or controller. Thereby, in _, the processor can reliably prevent access from the outside. (Revision) The second diagram is a view schematically showing the configuration of the instruction decoder 62 and the timing generator 64 of the two-state toggle-through AM according to the modification of the second embodiment of the present invention. In FIG. 20, the instruction decoder 62 includes: a write command detection circuit 22 that takes a person from the external CMD and generates an intrusion indication detection signal 1 in synchronization with the clock signal CLK; The write activation circuit 224 generates the write instruction signal Write based on the internal write detection signal (rewrite human indication signal) Φ Μ and the clock signal CLK from the timing generator 64. When the instruction signal is rewritten (D WI is activated, the write activation circuit 224 generates a write instruction signal Write of a predetermined time width in synchronization with the fall of the clock signal CLK. The write current drive activation circuit 231 generates the write digit line drive signal W_DL and the write bit line drive signal 319644 57 200830313 W-BL in a predetermined order according to the activation of the write instruction signal Write; The verification activation circuit 232 generates a verification activation signal VFREN based on the write detection signal cdwf and the write activation signal from the command Crypoke 62. The verification activation circuit 232 responds to the write mode detection signal 1 The activation or writing of WF indicates the inactivation of the signal Wdte, and the verification of the read-activated k-number VFREN is generated by the type of the single-shot pulse having a predetermined time width. This verification reads the activation signal VFREN. The pulse width is the time width required to read the data internally and perform the consistent judgment of the logical read of the internal read data and the written data. The timing generator 64 includes: a busy signal The circuit 233 generates a busy/ready signal RZ according to the verification result indication signal P/F, and latches the benefit 234, and responds to the verification. The inactivation of the read activation signal Vfren is used to request the lock verification result indication signal p/F. And the pulse wave generating circuit 235' generates an internal write command signal (rewrite indication signal) according to the turn-off signal of the latch 234 and the verification read activation signal VFREN. φ Φ WI 忙 busy signal generation circuit When the 233 is in the write mode, the busy/preparation signal B/Rz is generated according to the verification result instruction signal P/F. When the verification result indication signal P/F is 1 level in the standby state, the busy green signal generation circuit 233 is The busy/preparation signal B/RZ is always generated based on the verification result indicating signal ρ/ρ. When the read-activating active signal VFREN is verified as the Η level, and the internal data reading is performed, the latch 234 becomes a pass (through State, and when verifying that the activation signal is read. VFREN will become L, the position is respected, and when the internal reading 319644 58 200830313 is output, the latch 234 will become latched. § Verify that the read activation signal VFREN drops When the value of the latch 234 is Η, the pulse wave generating circuit 235 generates an internal write indication signal (rewrite the indication signal) in the form of a one-shot (D WI. w Figure 21 shows The timing of the operation of the instruction decoder 62 and the timing generator 64 shown in Fig. 20 is not shown. Hereinafter, the operation of the instruction decoder 62 and the timing generator 64 shown in Fig. 2 will be described with reference to the 21st W. In the cycle starting from the start, the write command is received as the command (10) and the received address signal is fined as the address signal AD in synchronization with the clock signal. According to this write command, the write command detection circuit adds a write indication detection signal 1 in the form of a one-shot pulse. Based on this writing, the activation of the detection signal 〇WF is verified, and verification of the activation circuit = 2 will verify that the read activation signal vfre is activated. At this time, the write instruction signal Wdte is in an inactive state. Pre-processing internally: It is judged whether the memory data of the memory unit to be written and the data of the written data are - or not. When the result of this determination is inconsistent, the indication signal 1>/!? is the H level. Thus, the result is that the output signal of the latched state 234 is the Η level, and the pulse wave generating circuit 235 generates the singularity of the readout activation signal VFREN in the form of a one-shot pulse signal. Then u write the indication signal Φ WI. At this time, according to the verification result, the money "F, busy/preparation B/RZ is displayed as the level of the busy state (via the busy green signal ς 233). The electric code Φ WI, the write activity 319644 is based on the re-write indication signal of the f-trigger pulse wave. The control circuit 224 f is driven in synchronization with the falling of the clock signal CLK to drive the write instruction signal Wdte to the active state. In Fig. 21, the write indication apostrophe is set during the period in which the clock signal CLK is at the L level. However, the activation period of the U write indication signal may also be shorter than the clock signal clk quasi-period. When the write instructing signal Write is activated, the write current drive activating circuit 231 is activated, and the write digit line drive signal w sink and the write bit line drive signal W_BL are sequentially activated in a predetermined order. In the circadian ring from the time ni, in response to the inactivation of the write instruction signal w, the verification read activation signal /FREN of the self-verification activation circuit 232 is activated. In this way, verification for written data is performed internally. When the verification result indicates that the write is defective, the rewrite instruction signal is internally activated again, and then the write activation circuit (10) ^ activates the write instruction signal Wdte. Write the number of bit line drive letters lu W: DL and the write bit line drive signal W-BL will be activated again, and | In the loop from the time mi, when the writer instructs the signal w gamma = listen, the verification read activation signal VFREN is activated to determine the b/f action. At this time, when the right/who is positively entering, the verification result indication signal is lowered to verify that the readout activation signal vf is clear to the second level and the output signal of the locker 234 is the L level and In a second sorrow. Therefore, the pulse wave generating circuit 235 does not generate a pulse wave and writes again.

= = will not be generated. The response verification result indication signal iVF π is activated, and is busy/prepared in synchronization with the rise of the clock signal CLK 319644 60 200830313 'No. Β / RZ is driven to the l level. 'Busy' preparation signal B/Rz can also be based on the verification result - M 'not synchronized with the clock signal CLK and set to 1 bit ^ day - as shown in Figure 21, although missing, Yin I w A card « / Though the T-Ding is from the time of the verification period and the time from the time T12 to the opening of the π / - 丄 1 to open the preparation signal β / RZ, it can be surely stopped. (4) Access. Therefore, external access is licensed in the second half of the cycle. As described above, according to the second embodiment of the present invention, the external verification processing (4) (4) H can surely know that the internal is in the (4) verification (4), so that the external access and the external access are performed. Internal verification action conflicts. [Embodiment 3] Fig. 22 is a view schematically showing a configuration of a command decoder 62 and a timing generator 64 of a dual-disengagement MRAM according to a third embodiment of the present invention. In the configuration shown in Fig. 22, a timing generator The material system is different from the configuration of the timing generator 64 shown in Fig. 2 . That is, set in the timing generator 64

The switching turtle path 240 switches the transmission path of the pulse wave signal (rewriting signal) from the pulse wave generating circuit 235 every time the verification activation signal VFREN is activated, and the communication path of the WI; The re-write request transmission circuit 242' transmits a re-write request WREQ according to the pulse wave signal from the switching circuit 240. The switching circuit 240 responds to the verification activation of the activation signal VFREn for the first time, and generates the pulse wave. The pulse breaking signal of the circuit 235 (further 61 319644 200830313 'dot indication signal 0 gt; WI) is supplied to the write activating circuit 224. In response to the second activation of the activation activation signal VFREN, the switching power supplies the pulse wave signal from the pulse wave generating circuit 235 (rewriting the indication signal CDWI to the rewriting request transmission circuit %. Requirement 2; = 242 will respond to the rise of the pulse signal from the switching circuit 24A: the WREQ is rewritten to be activated (transmitted). The instruction decoder 62 and the timing generator shown in Fig. 22 The other configuration is the same as the timing generator 64 and the command decoder aj shown in FIG. 2G. The same reference numerals will be given to the corresponding portions, and detailed descriptions thereof will be omitted. /, Fig. 23 shows the figure 22 The illustrated instruction decoder | and the timing chart of the operation of the timing generation W. Hereinafter, the operation of the instruction decoder 62 and the timing generator 64 which are not shown in the U diagram will be described with reference to Fig. 23. In the clock cycle starting at 20, the write finger stop signal AD0 is simultaneously received. According to the write-in command, the write command detection circuit 222 calls for the insertion of the private detection finger number Φ WF. Thus, the verification activation circuit 232 will Will verify the readout activation signal WREN According to the verification, the VF surface of the activation signal is output, and the memory cell of the object to be written is read = °# The data of the memory cell read from the inside and the data of the write data are not accurate. At the same time as the configuration shown in Fig. 2G, the pulse wave generating circuit 235 generates the rewrite instruction signal Φ WI in the form of a one-shot pulse wave signal. The one-knife change packet 240 is activated in response to the verification readout. The signal VFREN is ... the biochemical '~ pulse signal from the pulse wave generating circuit 235 < DWr 62 319644 200830313 • is supplied to the write activation circuit 224. Thus, the write instruction signal Write is activated, and then, The activation current circuit 231 is driven by the write current, and the drive signals W_DL and W_BL are sequentially activated. In the clock cycle from time T21, when the writing is completed, the verification activation circuit 232 will verify again. The read activation signal VFREN is activated. The switching circuit 240 reads the activation signal VFREN in response to the second verification, the rain switches its connection path, and supplies the rewrite indication signal OWI output by the pulse generation circuit 235. To again The input request transmission circuit 242. In the write verification at the time of writing, when the write failure is detected, the verification result indication signal P/F is at the Η level. Therefore, the pulse wave generation circuit 235 will again be a single trigger pulse. The waveform form generates a rewrite instruction signal φ WI. At this time, the switching circuit 240 supplies the rewrite instruction signal OWI outputted by the pulse wave generation circuit 235 to the rewrite request transmission circuit 242. Circuit 242 will send a rewrite request WREQ based on the received rewrite indication signal φ xin WI. According to this rewrite request WREQ, the external processor or controller will again supply the write command with the same address AD0. Therefore, in the loop from the time Τ22, the same operation as the loop from the time T20 is executed again. When a write failure occurs internally, a write request is sent to the external processor or controller, whereby the external processor or controller can reliably detect the write status. In this way, it is possible to monitor the number of occurrences of write failures and the like, and take necessary measures. • Also, the re-write request WREQ can also be sent synchronously with the period of the last 63 319644 200830313 of the clock signal CLK. Further, the time T20 to the time T22 may be a clock cycle period of the external clock signal. [Modification]

Fig. 24 is a view schematically showing the configuration of a command decoder 112 and a timing generator of a spin injection MRAM according to a modification of the third embodiment of the present invention. The instruction decoder 112 and the timing generation crying 1U shown in Fig. 24 are different from the instruction decoder 112 shown in Fig. 19 in the lower point: the configuration of the generator 114 is different. That is, in the command decoder ι2, the output signal of the write command detecting circuit 2〇2 is directly supplied to the write activating circuit 2〇6 as the write mode command signal Φ w .设置The re-write request transmitting circuit is provided in the timing generator m' based on the pulse wave signal from the pulse wave generating circuit 215 (rewriting the pointing signal) (DWI is used to transmit the rewriting request WREQ. The n 114 and the instruction decoder 112 are configured to be identical to the configuration of the instruction decoder, 112, and the timing generator ι 4 shown in the first step, and the same reference numerals are attached to the corresponding portions, and detailed description thereof will be omitted. Fig. 25 is a timing chart showing the operation of writing the data of the command decoder m shown in Fig. 24. Hereinafter, the command decoder 112 and the timing generator shown in Fig. 24 are shown in FIG. _ T3G P wire loop, in synchronization with the clock signal €lk will supply the write command as the command CMD, and will be used for the acknowledgement = number as the address signal AD. According to this write command ^ / The %% road 206 t activates the write instruction letter f Tiger Write. Root 319644 64 200830313 - According to the activation of the write indication signal Write, the write current drive activation circuit 211 writes the digit line drive signal WJ) L and write pulse signal W_PULSE to live Of. At this time, the comparison for prohibiting the pre-reading is invalidated. 1 1st-Write is activated. At the end of the intrusion operation, the verification activation signal VFREN is activated by the verification activation circuit 212 to perform write verification. When the write is defective, as described above in the timing chart shown in FIG. 18, the rewrite instruction signal (internal write instruction signal) from the pulse wave generation circuit 215 (DWI is activated. According to the rewrite) The activation of the indication signal 'rewrites the request to the transmitting circuit 25G to send the writer to request the micro-call. According to the write request WREQ 'the external processor or controller will send the write command 苳 the same address signal AD〇 again. In this way, the same write/write verification as that from the time T3〇 is executed in the loop from the start of the call. # ' In the loop of the rewrite person from the time T3i, #normally executes the jump. , the verification result, the money p / F will become (four) traits away, Table 1 is normally written. In this case, because the pulse wave generating circuit does not generate a pulse wave signal, then the writer asks the sending circuit to say no longer write Into the request micro EQ. Therefore, the next access can be performed from the time τ ^. In the clothing, Ya, in the timing chart shown in Figure 25, rewrite

It can also be transmitted in synchronization with the rise of the clock signal CLK ... REQ ^ _. In this case, the loop started by the JT31 will become a waiting loop. (As stated above, according to the third embodiment of the present invention, when the write is bad, 65, 319644 200830313 'send rewrite request俾The external command is sent to the write command indicating the write. Therefore, the external processor or controller can grasp the state of the data write, and can perform the necessary processing when the write is bad. In the same manner as in the second embodiment, the busy/preparation signal can be used. [Embodiment 4] Fig. 26 is a view schematically showing an overall configuration of an MRAM according to the fourth embodiment of the present invention. The MRAM shown in Fig. 26 can be Any of the two-state thixotropic 10MRAM and the spin injection type MR AM. In Fig. 26, the memory array 20 of the ^[footer]\4 is divided into a plurality of memory blocks ΜΒ0 to MBn. In each of the body blocks ΜΒ0 to MBn, the memory cells are arranged in a matrix. The structure of the MRAM, the word line, the digit line, the bit line, and the source line are arranged corresponding to each memory cell row/column. Corresponding memory block ΜΒ0 Each of the MBn sets the sub-writing system electric circuits SBW0 to SBWn. Each of the sub-writing system circuits SBW0 to SBWn includes a digit line driver and a bit line driver. When it is a spin injection type MRAM The source line driver and the source line decoder are repeatedly provided. The sub-write system circuits SB W0 to SB Wn operate in parallel and write multi-bit data. However, as described in detail later, these sub-write systems are The operation of the circuit re-writing can be separately controlled. The memory blocks ΜΒ0 to MBn correspond to the external input data DI0 to Din and the sub-output data DOO to DOn, respectively, and are respectively output between the corresponding data output eight connection pads. Data transmission and reception are performed. 66 319644 200830313 ^ Each of the memory blocks MB0 to MBn is provided with readout column selection circuits RSKO to RSKn. As shown in Fig. 14, the readout column selection circuit 'RSKO to RSKn The system includes a read/exit selection gate and a read column selection decoder set for each bit of the corresponding memory block. The data is activated (including the verification action) and is activated according to the figure. Address letter A bit line corresponding to the column of the specified address is selected in the corresponding memory block. Corresponding to each of the read column selection circuits RSKO to RSKn, 10 sense amplifier circuits SAKO to SAKn are provided. These sense amplifiers The circuits SAKO to SAKn are activated in response to activation of the sensing activation signals EEO to ENn from the corresponding sensing control circuits SCKO to SCKn, and verify the reference voltage VREFR from the corresponding readout column selection circuit RSKO to The data read by RSKn is compared. The output signals of these sense amplifier circuits SAK0 to 8 are input to the correspondingly arranged wheel data latches QDL0 to QDLn.

• For each of the output data latches QDL0 to QDLn, comparators COM0 to COMn are set. When the general data is read, the output data latches QDL0 to QDLn generate the external read data DOO to Don via the connection pad. During the verify operation (internal readout), the output data latches QDL0 to QDLn will The latch data is supplied to the corresponding comparator COMO to 0: 〇]\111. The comparator (:〇)^0 to (:〇]^11 compares the latch data of the input data request locks DDL0 to 001^ set by the other 4 with the data from the output data latches QDL0 to QDLn. And generate a signal indicating the comparison result P/F0 to P/flat η. These comparators COMO 67 319644 200830313. The COMn system is the same as the one shown in Embodiments 1 to 3, corresponding to the two-state thixotropic MRAM and The spin-injection type is used to set the configuration. The verification result indication signals P/F0 to P/Fn from the comparisons COMO to COMn are supplied from the respective sensing control circuits to SCKn, and supplied to The sub-write system circuits SBW〇 to SBWn. Thus, in each memory block, re-writing is selectively performed separately according to the verification result. The turn-out signals of the comparators COM0 to COMn are re-supplied to the R-electricity The shoe 304. The circuit 101 generates a main verification result indication signal Mp/F and sends it to the timing generator 302. The timing generator 302 generates a digital line driver based on the write phase indication from the instruction decoder 3A. Signal W_DL, verify readout activation signal

^BL ON ": As a configuration of the timing generator 302, the configuration shown in the embodiment or the second can be used. The decoder 300 will be in the same command CMD as the clock signal CLK, and when receiving the input j匕-士本目 w.f~ 舄W, when the person indicating the letter 2 is received, the read instruction is received. The instruction to dissipate 3 〇〇 will produce read = two ead. From the instruction decoder and timing generator 3, the tiger will supply the sensing control circuit S(10) to SCKn and the sub-writing system SBW0 to SBWn 〇j 曰 了 收 收 ' ' 斟 亚 亚 亚 亚 亚 亚 亚 亚 亚 亚 亚 亚 亚Let's live out the 'out of the selection circuit RSK. To the coffee, the verification read-activated 仏5 tiger VFREN and the read instruction signal Read. In addition, although not shown in Fig. 26, there is an address_er, 319644 68 200830313 - an internal address signal (ADD) for specifying an address is generated in each of the memory blocks. • The sense amplifier circuits S ΑΚ0 to S ΑΚ η are respectively provided corresponding to the memory regions 'blocks ΜΒ0 to ΜΒη, to specify that the address signals of the selected columns are not supplied to the sensing control for activating the sense amplifiers. Circuits SCK0 to SCKn. That is, the sense amplifier circuits SAK0 to SAKn are commonly set for the corresponding memory block. The sensing control circuits SCK0 to SCKn respectively detect the corresponding sense amplifier circuit S ΑΚ0 according to the verification readout activation signal VFREN when the results of the corresponding verification result indication signals P/F0 to P/ • Fn are expressed as inconsistent S ΑΚη is activated. In the configuration of the MRAM shown in Fig. 26, when data is written, input data DI0 to 0111 from the outside are written in parallel to the selected memory cells of the memory blocks ΜΒ0 to 〇11. At the time of the verification operation, by the sensing control circuits SCK0 to 8 (:1^11, the sense amplifier circuit 8 is activated to SAKn, and the comparison operation is performed in parallel by the comparators COM0 to COMn. At the time of rewriting, according to the verification result instruction signals P/F0 to P/Fn, only the memory block in which the write failure is generated is rewritten, although the remaining memory cell regions that have been normally written are written. The block supply write refers to the 7 Tiger Write 'but the corresponding sub-input circuit will be hunted by the verification result indication signal and become the disable state, so the data will not be rewritten. ·- • Figure 27 The data of the MRAM data shown in Fig. 26 is displayed. 69 319644 200830313 • Flow chart of the operation. Hereinafter, the writing sequence of the MRAM shown in Fig. 26 will be described with reference to Fig. 27. 'First, instruction decoding The device 300 judges that the write has been designated by the external command CMD (step S21). Until the write command is received, the external command is monitored and the write command is received. When the write command is received and When being written by the cursor, first of all, by The instruction decoder 300 and the timing generator 302 perform pre-reading (step S22). In each of the memory blocks ΜΒ0 to 1〇11, the memory data θ of the memory unit of the write target 10 is read in parallel. In the comparators COM0 to COMn, it is judged that the logical values of the write data DI0 to Din received from the input data latches DDL0 to DDLn and the corresponding internal read data are identical or inconsistent (step S23). The main verification result indication signal from the OR circuit 304]\0>/丨 is the Η level or the L level, and it is determined whether all the bits of the written data are consistent with the written data. When the main verification result indicates the signal If the memory unit and the write data are inconsistent for at least one bit of the memory unit, the data is again generated based on the control signals from the timing generator 302 and the instruction decoder 300. Writing (step S24). At this time, based on the verification result instruction signals P/F0 to P/Fn from the comparators COM0 to COMn, the writing of the nurturing is performed only for the memory block to be written. Memory area The block will remain in the standby state (step S24). Next, the verification readout is performed (step S25). The sense amplifier circuits ... SAK0. to SAKn will be in accordance with the verification result indication signal P/F0. to P/Fn 70 319644 200830313 - Selectively activated, the sensing operation is performed only for the memory block that has been written and written, and the verification is read out. 'For the memory block in the standby state, the corresponding output data is flashed. The QDL0 to QDLn are in a latched state, and the logic level of the verification result indicating signal P/Fi output by the corresponding comparator COMi does not change. Next, it is judged whether or not all of the bits have been written based on whether or not the main verification result indicating signal MP/F from the OR circuit 304 is the level (step S26). When all the bit writes have been written, the data is written to _. On the other hand, when there is a write failure in at least one bit of the memory cell, the action from step S24 is repeated again. Thus, in the memory blocks ΜΒ0 to ΜΒη, until the writing ends normally, the rewriting is repeated, and the memory block whose writing has ended is maintained in the standby state. Further, in the spin injection type MR AM, step S22 and step S23 for performing the pre-reading may be omitted. In this case, the operations of steps S24 to S26 are performed at the time of writing. Fig. 28 is a view schematically showing the configuration of a bit line decoding control circuit and a bit line decoding circuit included in the sub-writing system circuits SB W0 to SB Wn shown in Fig. 26. In Fig. 28, the bit line decoding control circuit 376i and the digit line decoding circuit 3701 of the sub writing system circuit SBWi are representatively shown. In Fig. 28, the bit line decoding control circuit 376i includes: AND The gate G3i receives the write bit line drive signal WJ3L, the write finger display signal Write, and the verification result indication signal Ρ/Fi; and the sense control 71 319644 200830313 • the circuit SCKi, which reads the activation signal according to the verification The VFREN, the readout instruction signal Read, and the verification result indication signal P/Fi are generated to generate the sensing/activation signal ENi. * AND gate G3i corresponds to the AND gate G3 shown in Fig. 16 and Fig. 11 〇 The sensing control circuit SCKi includes: AND gate 380, which receives the verification result indication signal P/Fi and verifies the read activation signal VFREN And the OR gate OGli receives the output signal of the AND gate 380 and the read_indication signal Read to generate the sensing activation signal ENi. The OR gate OGli corresponds to the OR gate OG1 shown in Figs. 11 and 16. The digit line decoding circuit 370i receives the write digit line drive signal -W_DL, the write indication signal Write, and the address signal 00, and supplies the output signal to the digit line drive circuit 72 of the next stage. The configuration of the digit line decoding circuit 370i is the same as that of the digit line decoding circuit shown in Figs. 11 and 16, and the detailed configuration thereof is not shown. φ As shown in Fig. 28, the verification result instruction signal P/Fi is supplied to the corresponding bit line decoding control circuit 376i and the digit line decoding circuit 370i, whereby sub-writing can be set for each memory block according to the verification result. The activation/deactivation of the writing of the circuit SB Wi. Further, in the case of the spin injection type MRAM, the write pulse signal WJPULSE is supplied instead of the write bit line drive signal W_BL. The configuration of the bit line decoding circuit 72 and the digit line driving circuit 72 in the next stage is the same as that shown in Fig. 11 or Fig. 16. When at least the verification result indicating signal P/Fi is at the L level, it is indicated that ♦ no need to be 72 319644 200830313 - writing, the output signals of the AND gates G3i and 380 will become the L level. The read instruction signal Read is at the L level when the data is written. Therefore, the bit line decoding circuit 74 of the next segment is maintained in an inactive state (disengaged state) without bit line selection. Further, the sensing activation signal ENi is also in an inactive state, so no sensing action is performed. Fig. 29 is a view showing the configuration of the source line decoding control circuit 380 when the MRAM of the fourth embodiment is a spin injection type MRAM. The source line decoding control circuit 380 shown in Fig. 29 corresponds to the configuration of the source line_decoding control circuit 120 shown in Fig. 16. In the configuration of Fig. 29, the circuit in the SB circuit SB Wi is also representatively displayed. In Fig. 29, the source line decoding control circuit 380 includes: an inverse phase comparator IV4i for inverting input data; and an AND gate G8i for receiving an output signal of the inverter IV4i and a verification result indicating signal. P/Fi. These inverters IV4i and AND gates G8i correspond to the inverter IV4 and the AND gate G8 of the decoding control circuit 120 shown in Fig. 16. The φ source line decoding control circuit 380 includes: an AND gate 382 for receiving the verification result indication signal P/Fi and the verification read activation signal VFREN; and an OR gate OG3i for receiving the input and output of the AND gate 382 Indicates the signal Read. The OR gate OG3i corresponds to the OR gate OG3 included in the source line decoding control circuit 120 shown in Fig. 16. By the AND gate 382, the verification read activation signal VFREN is selectively set to the active/inactive state based on the verification result instruction signal P/Fi. The source line decoding control circuit 380 includes: an AND gate G9i, which receives the write pulse signal W_PULSE, an output gate number of the AND gate Gh, ~ 73 319644 200830313 ^, and a write activation signal Write; and an OR gate OG4i The output signal of the OR gate G9i and the output signal of the OR gate OG3 i are received, and the output signal is supplied to the source line decoder of the next segment. The AND gate G9i corresponds to the AND gate G9 included in the source line decoding control circuit 120 shown in Fig. 16. The OR gate OG4i corresponds to the OR gate OG4 included in the source line decoding control circuit 120 shown in Fig. 16. The configuration of the source line decoder is the same as that of the source line decoder 122 shown in Fig. 16. In the configuration of the source line decoding control circuit 380 shown in Fig. 29, when the verification result indicating signal P/Fi is at the L level, the output signals of the AND gates G8i and 382 become the L level. In the write mode, the L level in which the instruction signal Read is in an inactive state is read. Therefore, the L level signal is supplied from the OR gate OGi to the source line decoder (122) of the next stage, so the source line decoder is maintained in the disabled state. The verification result indication signals P/F0 to 1>/^11 from the comparators COM0 to COMn provided by the respective memory blocks are supplied to the respective sub-write system circuits SBW0 to SBWn and the sensing control The circuits SCK0 to SCKn can be individually controlled to be rewritten to the memory blocks ΜΒ0 to MBn. When rewriting, all of the circuits can be rewritten under the same conditions, or the writing can be changed as described later. Into the conditions. When writing multi-bit data, only the memory cells to be written are written, and for the cells (memory cells) that have been normally written, the memory cells that are not required to be written can be stopped. Write, so it can reduce the current consumption. As described above, according to the fourth embodiment of the present invention, it is configured to perform rewriting in units of the memory block of 74 319644 200830313, which is preferable. In addition, since it can be operated and maintained in the standby state after the memory of the writer has been completed, the power consumption is not reduced. The horse to be exemplified [Embodiment 5] Fig. 30 is a view schematically showing the configuration of the MRAM's private decoder of the MRAM of the MRA1U. In the human decoder 400, there is included a write-in person, and the fingerprint 检测 有 舄 令 令 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 Receive = 2: and _ way 404, according to the write command from the write command check packet 402 detection, you can set the initial value and internal clock with the wiper 1 ̄#uCI)WF The signal CLKi synchronously performs a 1-dip number operation on the common person a. When the count value of the counting circuit 4〇4 is set to the initial value according to the write buffer McDWF, the counting circuit 404 will operate in synchronization with the upper and lower sides of the internal clock signal CLKi: the predetermined amount of material, the counting circuit 4 〇4 will stop counting. The instruction decoder 400 further includes: a pulse wave generating circuit 4〇6, which generates a one-shot pulse wave signal in synchronization with the internal clock signal CLKi when the count increment indicating signal from the counting circuit is in an inactive state; and R The circuit 408' generates the write instructing signal φw based on the intrusion command detection signal 1WF and the pulse wave signal from the pulse wave generating circuit 406. When the count value of the counting circuit 404 reaches a predetermined value and the count up signal Φ is tongue-shaped, the pulse wave generating circuit stops the pulse wave generating operation. Therefore, the pulse wave generating circuit 406 generates a pulse according to the number of times the predetermined counting value is set by the counting circuit 4〇4 in advance. The writing instruction signal (4) according to the instruction decoder circuit weight is supplied to the downstream circuit. Or supplied to the timing generator. Therefore, the activity is applied to the tenderness shown in Fig. 22 for taking and g gamma. Further, the configuration of the request to the outside is shown in Fig. 31 as a flowchart showing the instruction decoder shown in Fig. 30. In the following, the third action of the reference, the action of the decoder _, and the instruction shown in the figure 3 of the brothers make the detection circuit system and the clock signal CL come from the external command CMD, and wait for the orphan. The instruction CMD from the outside is not (step please). The path 402 activates the write detection as 舄...intrusion command detection power w...a number 0WR. Next, the number of circuits 404 is initialized and the number of turns is 踗4M to the h action. At this time, the pulse wave generates a signal. On the other hand, (10) the circuit will be ^ Γ 4 〇 ^ ). According to the deaf person indication signal (4), the verification action will be in and after the writing, and according to the verification result, the test::= P/F (or P/Fi) backup point 皲-and, 、, σ fruit deduction k 准 ((4) _. In the case of the logical position of the (4) verification result, the read-in is not performed when the gh is *the binary haptic MRAM is written by the younger one (see Figure 19). Further, the count value of the number Hr counter circuit 404 does not reach the predetermined value, so the tip incremental cut (10) P is inactivated state (step is as follows). Therefore, the 319644 76 200830313 will generate the pulse signal CLU = The wave signal 'and re-sends the write indication signal value to the pre-+/s' in (4) S43. 'When the count circuit can count the history, the number Φυρ will become active, and the pulse generation circuit 406 will stop. You generate an action from the pulse wave after the singularity. The g-heart uses the command decoder 400 shown in Figure 30, even if it is normal in the interior. Shou, will also send a write finger

',, 'Intrusion order. In this case, when the inquiring gentleman strikes 匕 俨 俨 / / F or p / Fi is displayed as normal writing, :=: Guo 曰, P body early 兀 贤 写入 。 。 。 。 。 — 1 In the case of the figure, the instruction shown in the figure =, in the case of the intrusion of the person, the "received from the outside", the execution of the write and write verification of the predetermined number of times. The predetermined value table (4) the writing of the predetermined Luli material. In addition, the "processor or controller is written to the person who guarantees the end of writing, so the system design == the time is set to within the predetermined period. For the predetermined value, Shihe Yi (this can be written and accessed as described above. 'According to the real power + command according to the present invention, it can be carried out and verified in the predetermined cautious ancestor-number of people. Correct, ~in' and can set the write access time to a predetermined value. The internal clock signal CLKi can be the same as 盥氺A from * CLK 啼 啼 了 了 了 了 了 、 、 、 、 、 、 、 Internal clock signal generated by dividing the material (1) C to the cutting frequency. Only the internal data is written and verified. ^ Guarantee the specified scoop, the internal clock signal of the period of the month 319644 77 200830313 • Yes. [Embodiment 6] Fig. 32 is a view schematically showing the sixth embodiment of the present invention MRam

A diagram of the main part of the timing generator 3G2. In the configuration shown in Fig. 32, a busy signal generating circuit 4 is set in the timing generator 3A2. The busy signal generating circuit 4 is based on the verification result indicating signal from the 〇r circuit 3 Mp/F comes to the production line. The preparation signal V is in the configuration shown in Figure 32. Until the end of the end of the multi-bit data, the busy/preparation signal B/rz will be $ Busy. Therefore, the external processor or controller can detect the period of all bits of the multi-bit data. Write here According to the busy n preparation money B / RZ, the external device will become a special state. The configuration of the timing generator shown in the <2> diagram is the same as the configuration of the timing generator including the diagram 产生: generation circuit 233. The result indicates the signal p/F. In place of the verification of one — - as described above, according to the fifth embodiment of the present invention, during the internal execution of the intrusion, the outside sends a busy anvil, t 彔 / preparation nickname. Therefore, it is possible to confirm the end of the data writing time and to avoid the conflict of access and only the correct data is written. [Embodiment 7] Fig. 1 is a view schematically showing the configuration of a main part of the timepiece production of the seventh embodiment of the present invention, 319644 78 200830313. In the 33rd picture, the device 3〇2 towel, according to the main verification result indicating signal Mp/ CLK, will send the re-writing person to request the job EQ to the outside. Therefore, == will resend the write WREQ repeatedly during the period when there is a bit that is badly written. In the internal, the verification result indication signal P/Fi for the end of the write 'will be stopped according to the configuration shown in the corresponding stop 2, until the end of the data write is the external line, the write command is sent repeatedly. Therefore, it is possible to achieve the correct information. In addition, the processor or controller may also be configured to re-enter Q to monitor the "condition, and in the pure number of times: write =; WREQ, determine that the corresponding bit is bad and perform the necessary error and 'rewrite The incoming request transmission circuit 412 generates a rewrite request wreq in synchronization with the clock signal (10) (which may also be an internal clock signal). However, as shown in FIG. 22, the read activation signal vf surface is read according to the verification. The main verification result indicating signal MP/F transmits the rewriting request WREQ in a manner not synchronized with the clock signal CM. As described above, according to the seventh embodiment of the present invention, even when the multi-bit data = writing person' Until all the bits are written in person, and then the person asks 'to be able to write the multi-bit data reliably. The processor or controller of the external device can rewrite the request by this. Since the write status is monitored, the write control becomes easy. [Embodiment 8] Fig. 34 shows the reference voltage generation according to the eighth embodiment of the present invention. 319644 79 200830313

An example of the configuration of the circuit (Vref generating circuit) 42A. The reference voltage generating circuit 42 shown in Fig. 100 corresponds to the W generating private path shown in Fig. 2 or Fig. 15 or the Vref generating circuit 所示 shown in Fig. 26. In Fig. 34, the reference voltage generating circuit 42 includes a resistor element f1 to Z4' connected in series between the power supply node and the node NDa; = 疋 current source CIS is connected to the node Νϋ & Between nodes. ^ Da produces a reference voltage heart. In the case of the two-state thixotropy]^1^]^, the reticle drive voltage W is supplied to the bit-field drive circuit and the digits are respectively set to the reference voltage generation circuit, and the reference electric house Vref to the bit line drive circuit and the digits The line drive circuit can be. In the case of the in-type mram, 'also for the source line driver circuit. In this case, the base line for the source line driver circuit can be set as long as the base n "f number L material (4) is additionally used to generate the reference voltage generated by the circuit. The fixed ν'# system is designed according to the characteristics of the supplied circuit, and the 2 ° _ pair digit line _ circuit, the bit line drive circuit Μ and the source line drive circuit respectively produce the same + pressure level. However, the electrical circuit 420 includes: the switching component is added to be connected in parallel according to the write == the parts Ζ2 to Ζ4; the selector 422 is the idle CH0 fork ^ (4) to generate the selection signal; The wheel center t wire of 11.422 will be cut to 319644 80 200830313 'the components TX1 and TX2 are driven to the on state respectively. The output signal of the selector 422 is also supplied to the gate of the switching element TX3. These switching elements TX1 to TX3 are respectively The case where the N-channel MOS electric current is formed is shown as an example. However, it is only necessary to selectively set the switching element to the on/off state based on the signal supplied to the control electrode. These switching elements TX1 to TX3 Corresponding resistive elements Z2 to Z4 are respectively short-circuited during turn-on. The selector 422 is configured, for example, by a shift register, and internally sets the power supply voltage level according to the write mode indication signal. The signal (the level-aligned signal) is shifted. Therefore, each time the write mode indication signal Φ W is generated, the number of signals that become the Η level increases in the output signal of the selector 422. In this case, As an example, the following order is considered. When the write mode instruction signal (DW is generated for the first time, the selector 422 is set to the initial state, and all the switching elements ΤΧί to ΤΧ3 are set to the non-conduction state. Then, each The secondary transmission write mode indication • When the signal Φ W, the switching elements ΤΧ3, ΤΧ2, and ΤΧ1 are sequentially turned on. In this case, when the current flowing through the constant current source CIS is set to I, the reference voltage Vref will be The following voltage levels change sequentially: Initial value: VDD—lx (Z1 + Z2 + Z3 + Z4) Maximum value: VDD—IxZl When the resistance values of the resistance elements Z1 to Z4 are equal to each other, the reference voltage V The voltage level of ref is adjusted by step IxR. Fig. 35 shows an example of the order of change of the reference voltage Vref. The reference voltage Vref is increased by the minimum value Vref (min) to the maximum - 81 319644 200830313 The value Vref (max). Take the voltages V1 and V2 at the intermediate value. Between this maximum value and the minimum value, the reference voltage of the intermediate state is generated by the step IxR. In the MRAM, when the writing is bad, Revert to the state before writing. Therefore, when the writing is defective, a large amount of writing current flows in order to increase the induced magnetic field or the writing current, and the magnetization state of the memory cell is surely changed. For example, in the case of flash memory or the like, in a case where the state thereof changes after writing, there is a possibility of occurrence of an excessive write or the like. However, the problem of such overwriting does not occur in the MRAM, and it can be confirmed. Write is performed locally. However, in the case of the two-state thixotropic MRAM, since the magnetic field is applied, the exchange coupling of the free layer is destroyed at a large time, so the maximum value is limited. Therefore, the reference voltage Vref at the time of writing must be set to a value below the allowable maximum value ^[(max). As shown in the previous embodiment, the reference voltage Vref is supplied to the gate of the transistor for driving in the bit line driving circuit, the bit line driving circuit, and/or the (qua) line driving circuit. Therefore, by sequentially increasing the voltage level of the reference voltage # repeatedly V, the amount of driving current of the driving transistor can be increased, and the writing current can be increased. Further, in the configuration shown in Fig. 34, the write mode indication number is supplied to the selector 422, and the selector 422 sequentially shifts the elements TX1 to τχ3 (4) to the on state. The write mode indication signal (4) supplied to the selector 422 may be a signal for writing a person generated internally. You can also use the re-write f signal. According to the composition of the corresponding MRAM, the signal for displaying the number of times of the horse is only required to be shifted by the selector (4) signal; 319644 82 200830313. Further, the selector 422 adjusts the level of the generated reference voltage Vref in three stages. However, the amount of voltage change at the time of rewriting of the reference voltage Vref generated by the reference voltage generating circuit 420 can be divided into a plurality of stages. Between the minimum reference voltage Vref (min) and the maximum reference voltage Vref (max), the voltage level of the reference voltage Vref may be adjusted in order of a smaller step. In addition, depending on the number of rewrites, this step can also be changed. [Modification] Fig. 3 is a view schematically showing the configuration of a drive circuit 430 according to a modification 1 of the seventh embodiment of the present invention. In Fig. 36, the drive circuit 430 is a bit line drive circuit or a source line drive circuit of a spin injection type MRAM. The signal line SGL is a bit line BL or a source line SL in a spin injection type MRAM. The driving circuit 430 includes front-end circuits 432 and 10434 in the internal signal; and a driving section 436 for driving the signal line SGL based on the output signals of the preceding-stage circuits 432 and 434. The front-end circuits 432 and 434 receive the power supply voltage as their high-side operating power supply voltage. When the drive circuit 430 is a bit line drive circuit, the front stage circuits 432 and 434 are the NAND circuit and the NOR circuit shown in Fig. 16, respectively. When the drive circuit 430 is a source line drive circuit, the front stage circuits 432 and 434 are the inverter circuits shown in Fig. 16. The driving section 436 includes a P-channel MOS transistor PQ10, which drives the signal line SGL to the reference power 83 319644 200830313 according to the input signal of the front-end circuit 432. • The voltage Vref level; and the N-channel MOS transistor NQ10. The signal line SGL is coupled to the ground node in accordance with the output signal of the front stage circuit 430. ^ By the driving circuit 430, the signal line SGL is driven to the reference voltage • Vref, and the other end is coupled to the ground node. The write current flowing through the signal line SGL can be adjusted by the voltage level of the reference voltage Vref (the wiring resistance is the same, and the current amount is supplied by the ratio of the reference voltage Vref to the wiring resistance). Moreover, the digit line driving circuit generally combines the digit line DL to the ground node to circulate the digit line current. When the digit line system is configured such that one end is coupled to the ground node, and the digit line of the selected row is a current flowing according to the output voltage of the digit line driving circuit, the driving circuit 430 shown in FIG. 36 can be driven as a digit line. The circuit is used. The digital line current can be adjusted by the reference voltage Vref. [Modification 2] Fig. 37 is a view schematically showing a configuration of a modification of the eighth embodiment of the present invention. In Fig. 37, a voltage follower 439 is provided for the bit line BL in the two-state thixotropic MRAM. The voltage follower 439 is connected to the positive input terminal to receive the reference voltage Vref, and the negative input terminal is coupled to the corresponding bit line BL. A bit line drive circuit 43 7 is provided at one end of the bit line BL. The high side power supply voltage of the bit line driving circuit 437 is the power supply voltage. The bit line driving circuit 437 has the same configuration as that shown in Fig. 11 (the power supply voltage VDD is supplied instead of the reference voltage Vref). In the configuration shown in Fig. 37, the reference voltage Vref is adjusted in accordance with the number of times of rewriting 84 319644 200830313. The bit line drive circuit 437 combines the corresponding bit line BL to the power supply node at the time of selection. Therefore, by adjusting the voltage level of the reference voltage Vref, the voltage difference across the bit line bl is different, and the amount of current flowing through the bit line BL can be adjusted. In this case, as the number of rewrites is increased, the voltage level of the reference voltage Vref is lowered. Thus, as the number of rewrites is increased, the amount of current in the bit line can be increased, so that the bit line current induced magnetic field can be increased. Thus, in this case, in the reference voltage generating circuit, the selector 422 shown in Fig. 34 sequentially increases the number of switching elements τ χ to TX3 that are turned on. [Modification 3] FIG. 38 is a view schematically showing the configuration of the write current drive activation circuit 211 having the configuration of the third modification of the eighth embodiment of the present invention. In the spin injection type MRAM, the write current drive activating circuit 21 generates a write pulse signal W-PULSE (refer to Fig. 24). In the third drawing, the write current drive activation circuit 2 includes: a timing adjustment circuit 442 that delays the write instruction detection signal 1...^ for a fixed time; and a count circuit 444 that is based on the write instruction. The detection signal OWF is set to an initial value, and in the write mode, the counting operation is performed every time the activation of the read activation signal VFREN is verified. The timing adjustment circuit 442 writes the instruction detection signal (DWF is delayed by a fixed time to adjust the activation timing of the internal write pulse signal WJpULSE. The horse-in current drive activation circuit 21 includes the variable delay circuit 446. Delaying the timing adjustment circuit .442; and setting (a) to 85 319644 200830313 - resetting the flip-flop 448 according to the output 仏唬 of the timing adjustment circuit 442, and according to the variable delay circuit The 446 rounds out the reset number and generates a write pulse = WJPULSE from its output Q. The delay amount of the delay circuit 446 is adjusted by the count value of the counting circuit 444. In this case, the variable delay circuit can also include a plurality of cascade connected delay segments, and is further used to output a delay segment of k according to the output of the counting circuit 444. The variable delay circuit 446 can also be configured as a delay section of the complex number & and based on the count value of the counter circuit 444 = setting the drive operation current of each delay section to change the delay of each delay section 1 using any of the above configurations Can be. Fig. 39 is a signal waveform diagram showing the operation of the write current drive activating circuit 211 shown in Fig. 38. Hereinafter, the operation of the inrush current drive activation circuit 211 shown in Fig. 38 will be described with reference to the % diagram. At the time of data writing, the write instruction detection signal 〇WF is activated in accordance with a write command from the outside (by the write command detection circuit in the instruction decoder). The count value of the counting circuit 444 is set to an initial value. = The delay amount of this variable delay circuit 446 is set to an initial value. When the person writes once, the bit line is written according to the initial value to write the human wave wave mark W-PULSE. The counting circuit 444 is responsive to verifying that the read activation signal VFREN is moving toward the biochemical transition of _f to update the meter. Value. Thus, the variable delay circuit 446 updates the delay amount of its initial value and delays the output signal of the timing adjustment circuit to a predetermined value. According to the timing adjustment circuit, the output of the circuit is set to 319644 86 200830313. The signal is set to set/reset the flip-flop 448, and the write pulse signal W_PULSE is activated. Then, after the delay time required by the variable delay circuit 446, the flip-flop 448 is reset, and the write pulse signal -W_PULSE is deactivated. Therefore, after the second write, the pulse width of the write pulse signal WJPULSE is sequentially updated. As described above, in the MRAM, when a write failure occurs, the memory cell of the write target returns to the state before the write. Therefore, in this case, by sequentially increasing the write time, the rain can surely write the write data to the memory unit that is poorly written. Unlike the flash memory cells, the initial state of writing is often the same, so the problem of overwriting does not occur even if the writing time is long. As described above, according to the ninth embodiment of the present invention, the writing condition is changed in accordance with the number of rewriting times, and the data can be surely written to the memory element of the writing target. [Embodiment 9] Fig. 40 is a view schematically showing the configuration of a write current driving live Xenon circuit 450 of a two-state toggle MRAM according to Embodiment 9 of the present invention. The digit line write current activation signal WJDL and the bit line write current activation signal WJBL are generated from the write current drive activation circuit 450. The write circuit 450 corresponds to the circuit 211 or 231 shown in Figs. 19 and 23. The write current drive activating circuit 450 includes delay elements DLY1 to DLY6 connected in series, and selection circuits SLT1 to SLT5 for selecting output signals of the delay elements DLY2 to DLY6, respectively. The outputs of the selection circuits SLT1 to SLT5 are commonly combined, and a write bit line drive is generated. - _, . - >. 87 319644 200830313 The dynamic signal WJBL. The selector 々Μ is set for the intrusion turbulence drive activation circuit 45. The selector = 452 is, for example, provided to the timing generator, and drives the selection circuits SLT1 to SLT5 to the selected state in order according to the write mode constraint ^(4). Therefore, the selector 452 can also be configured by shifting the temporary storage crying according to the write mode indication signal (4): two initial values, sub-sequence activation according to the clock signal or verification readout (4) (4) (four) (four) material 452 It is also possible that the count/decoding circuit will decode the count value by writing the human mode indication signal (4). The selection circuits SLT1 to _ can be selectively driven to the selected state. • The k-select circuits SLT1 to SLT5 are used to pass the output signal of the corresponding delay element when selected, and become the output high-impedance state when not selected. Since =' is from the delay element DLγ2 to the redundant output signal to the d, a ## is selected as the write bit line drive signal. The delay time of the two DLY1 to DLY6 is fixed. The input % pulse signal CLKw can be generated by generating a wave signal in the write mode. In addition, the write clock signal 2: can be the internal clock signal CLKi generated by the crane %. In this case, the write 溆 bit line drive signal W_DL changes depending on the internal clock signal, so there is no problem. Fig. 41 is a timing chart showing the operation of the write current drive active path shown in Fig. 4. Hereinafter, the operation of the write current drive activation circuit 450 shown in Fig. 319644 88 200830313 * will be described with reference to the third section. V. At the time of data writing, the write clock signal CLKw is generated as a pulse wave signal having a predetermined 'time width' (or is constantly supplied as the internal clock signal CLKi). The delay elements DLY1 to DLY6 have delay times At, respectively, and sequentially delay the received signals and output them. First, the output signal D1 from the delay element DLY1 of the first stage is generated as the write digit line drive signal W_DL. The selector 452 is set to the initial state at the time of the initial writing. As a result, the wheeling signals of any of the delay elements DLY2 to DLY6 are selected. As shown in Fig. 41, when the input signal D2 of the delay element DLY2 is selected, the write bit line drive signal W_BL becomes a Η level at time ta to time tc. On the other hand, when the output signal DL6 of the delay element DLY6 of the last stage is selected, the write bit line drive signal W_BL becomes a Η level between the time and the time td. During this period, the write bit line drive signal WJBL is sequentially delayed according to the number of rewrites. The writing to the memory cell is performed during the period in which the write digit line current activation W_DL coincides with the write bit line drive signal W_BL (rotation of the magnetic field). Therefore, by lengthening the period in which the combined magnetic field is generated, the magnetization direction of the variable magnetic resistance element (MTJ element) of the memory cell can be surely set to the combined magnetic field of the magnetic field induced by the digit line current and the bit line current. Direction, and can perform writes reliably. By adjusting the timing relationship of the relative relationship between W_DL and WJ3L each time writing, the writing of the data can be surely performed. When the cause of the write failure is a poor separation of the magnetic field (a spin flop is not generated in the state of 89 319644 200830313 sorrow), the time for flowing the digit line current is lengthened. When the reason for writing is not good, the magnetic field is poorly rotated, and the time for flowing the bit line current and the digital line current is lengthened. When the cause of the write failure is caused by the poor rotation of the easy magnetization axis due to the bit line current, the transition of the current of the flow bit line is lengthened. The order of changing the delay time is set based on the cause of these write failures. In the test, the cause of the defect is high, and the delay change order is set to 0. [Modification] Fig. 42 is a view schematically showing a configuration of a modification of the embodiment (4) activation circuit 45A of the present invention. In the inrush current drive activation circuit 450 of the 42th=, selection circuits SLT10 to SLT12 are respectively provided, and the selection circuits SLT1() to SLT corresponding to the delay elements DLY1 to DLY3 are respectively based on the delivery from the selector 452. It is selectively turned into a conducting state and becomes an impedance state when it is not selected. The y 7 selection 452 is the same as the configuration shown in the 40th, and the initial value is set based on the write/f type name signal 1 并 and the counting operation is performed. Option 2: The write operation can be performed by replacing the write/secondary and no k Φ W according to the verification read activation signal (VFREN). The signal for displaying the number of people driving inside is selected as the shift control signal, and the second is configured to count the number of rewrites according to the shift control signal and generate a pair, and the selection signal of the count value can be . The connected current-driven activation circuit includes: two-stage cascade connection, DLY10 and Dlyu, which are output signals of the selection circuit slti[319644 90 200830313 'to SLT12; and OR circuit 454, receiving selection The output signal of any of the circuits SLT10 to SLT12 and the output signal D1 of the delay element DLY1'. The write bit line drive 'signal W-BL is generated from the delay element DLY11, and the write bit line drive signal W_DL is generated from the OR circuit 454. Fig. 43 is a timing chart showing the operation of the write current drive activating circuit 450 shown in Fig. 42. Hereinafter, the operation of the write current drive activation circuit 450 shown in Fig. 42 will be described with reference to Fig. 43. > First, consider the state in which the selector 452 has selected the selection circuit SLT12. In this case, the write digit line drive signal W_DL rises in synchronization with the rise of the output signal D1 of the delay element DLY1, and then falls in response to the fall of the output signal D3 of the delay element DLY3. On the other hand, the write digit line drive signal W_BL is delayed with respect to the output signal D3 of the delay element DLY3 by the delay time of the delay elements DLY10 and DLY11. > Therefore, when the write digit line drive signal W_DL is at the Η level and the write bit line drive signal WJBL is in an inactive state, in the variable magnetic resistance element (MTJ element), the spin flip state is established. . Then, when both the write digit line drive signal W_DL and the write bit line drive signal W_BL become clamped, the magnetization direction of the variable magnetic resistance element of the unit cell generated by the combined magnetic field is rotated. Further, after the digit line current is stopped, while the write bit line drive signal W_BL is in the active state, the magnetization direction of the variable magnetic resistance element of the memory unit is further rotated, and the magnetization direction is set. 91 319644 200830313 • The direction of the easy magnetization axis is 45 degrees with the bit line current induced magnetic field. Therefore, in this case as well, the selection "circuits SLT10 to SLT12 can be selectively set to the selected state by the selector 42, whereby the writing time can be adjusted, and the writing of the data can be surely performed. When the write failure is a failure condition in which the spin flip state is not formed, the write time is sequentially increased for each write count in such a manner that the write time is lengthened. On the other hand, when the combined magnetic field is weak, the selection order of the selection circuits SLT10 to SLT12 is set in such a manner as to lengthen the writing time. Therefore, the write bit line current activation signal W_BL can shift the waveform within the range indicated by the arrow in Fig. 43. Further, in the write current drive activating circuit 410 shown in Fig. 41, the delay elements DLY4 to DLY6 are not used. The output signals 04 to 06 of the delay elements DLY4 to DLY6 can also be used in order to generate file signals associated with other writes. For example, when the activation of the verification read activation signal VFREN is set, the output signals D5 and D6 of the delay elements DL Y5 and DLY6 can also be used. As described above, according to the ninth embodiment of the present invention, in the two-state thixotropic or MRAM, the period in which the digit line current and the bit line current are passed can be adjusted during internal rewriting to accurately perform writing. Further, in the ninth embodiment, the configuration of the two-state thixotropic MRAM shown in the other first to seventh embodiments can be used in combination. The present invention is applicable to a magnetic memory (MRAM) which is used as a memory element by using a variable magnetic resistance element such as an MTJ element or an MJT element. As the MRAM, it can be a single memory, or as 92 319644 200830313

It is not intended to limit the scope of the invention, and the scope of the present invention can be clearly understood as a β microcomputer. [Simple description of the diagram] Sectional structure of the early element Fig. 1 schematically shows the diagram of the two-state thixotropic mram. A diagram of the configuration within a 10-element array. Fig. 2 is a view schematically showing the writing order of the memory cells of the two-state thixotropic]^& Fig. 3 is a view schematically showing a two-state thixotropic display shown in Fig. 2. Fig. 4 is a view schematically showing a cross-sectional structure of a spin injection type MRAM cell. Fig. 5 (A) and (B) are views showing the direction of magnetization and the direction of writing current when data is written by the spin injection type MRAM cell. Fig. 6 is a view schematically showing the overall configuration of the mram of the present invention. Fig. 7 is a flow chart showing the writing sequence of the mram of the present invention. Fig. 8 is a flow chart showing another writing sequence of the MRAM of the present invention. Figs. 9(A) to (C) schematically show the relationship between the writing conditions at the time of writing data and the probability of occurrence of defects. Fig. 10 is a view schematically showing the overall configuration of a two-state thixotropic MRAM according to the first embodiment of the present invention. , 319644 93 200830313 The πth diagram more specifically shows the composition of the main part of the two-state thixotropic MRAM shown in Fig. Fig. 12 is a signal waveform diagram showing the writing operation of the two-state thixotropic MRAM shown in the figure. Fig. 13 is a view showing an example of the configuration of a word line driver circuit included in the wl driver shown in Fig. 1. Fig. 14 is a view showing the configuration of a column selection unit according to a modification of the first embodiment of the present invention.

Fig. 15 is a view schematically showing the overall configuration of a spin injection type MRAM according to a modification of the first embodiment of the present invention. Fig. 16 is a view showing more specifically the configuration of the main portion of the spin injection type MRAM shown in Fig. 15. The figure shows the signal waveform of the first signal. The data writing sequence of MrAm shown in the figure is a timing chart showing the writing sequence of the MRAM according to the second embodiment of the present invention. =19 ® is a diagram showing the configuration of the second embodiment of the schematic shafting invention and the configuration of the timing generator. The diagram of the MRAM of the second embodiment of the present invention and a modification of the timing generator are schematically shown in the drawings. The second diagram of the device shows the timing chart of the operation of the instruction decoder and the timing sequence shown in Fig. 2 . Figure 22 shows this diagram roughly

The composition of the main part of the diagram. (4) MRAM 319644 94 200830313 is a diagram showing the movement of the structure shown in Fig. 22, and the modification of the third embodiment of the present invention is schematically shown. A diagram showing the composition of the depletion device and the timing generator. „. 二二图 shows the timing diagram of the operation of the instruction decoder and the timing-inducing-before-injection shown in Figure 24. Figure 26 is a diagram showing the overall structure of the _. The pattern of the 4th brother of the Besch form 4 shows the mram shown in Fig. 26.

Flow chart. The figure of the main portion of the sub-writing system shown in Fig. 26 is schematically shown in the figure of only the T-Ter. The diagram showing the configuration of the main portion of the fifth embodiment of the fifth embodiment of the present invention is schematically shown in Fig. 30. . Fig. 31 is a flow chart showing the operation at the time of writing the data of the instruction decoder. The figure 32 is a view schematically showing the configuration of the main part of mRam according to the sixth embodiment of the present invention.

Fig. 33 is a view schematically showing the configuration of the main part of the seventh embodiment of the present invention. AM ^ Figure 34 is a diagram showing an example of the configuration of a reference voltage generating circuit of an MRAM according to an eighth embodiment of the present invention. · 319644 95 200830313 准恭压# The diagram of the steps of the reference voltage generating circuit shown in the figure. The main diagram of the present invention is a view schematically showing the configuration of a modification of the main part of the inscription 8.5 according to the eighth embodiment of the present invention. A diagram showing a configuration of a second modification of the main portion of the MR 人 of the human body of the embodiment of the present invention. The main diagram and the diagram schematically show the overnight ninth embodiment of the present invention. A diagram showing the configuration of a third modification of the main diagram. Fig. 39 shows the signal waveform of the operation of the circuit shown in Fig. 38. The figure 40 shows the write power of the ninth embodiment of the present invention. A diagram showing the configuration of the drive activation circuit. The Lr diagram of the circuit displays a timing chart of the operation of the write current drive activation circuit shown in FIG. Fig. 42 shows a modification of the write current drive wide tongue-forming circuit according to the ninth embodiment of the present invention. Fig. 43 shows the timing of the circuit operation shown in Fig. 42 [Major component symbol description] disorder 1, 11 free layer 2 - 12 pinning layer 3 tunneling barrier layer 13 tunneling insulating film 20 memory cell array 22 ... write system circuit 319644 96 200830313 23 read system circuit 24 write control circuit 50 X decoder 52 DL driver / 1 [driver 54 Y decoder 56, 76 bit line driver 58, 90 sense amplifier 60, 306 Vref generation circuit 62, 112, 300, 400 instruction decoder 64, 114, 210, 302 job generator 65. Input data latch 66, 116 comparator 67 output data latch 69 address latch 70 digital Line decoding circuit (X decoding circuit) 72 Digital line driving circuit 73 Decoding control circuit 74 Y decoding circuit 78 Sense amplifier 80 X address decoding circuit 82 Word line drive circuit 92 Write driver 100 Source line decoder 102 Source line Drive 97 319644 200830313 • 120, 380 122 — 202, 222 ' 204, 304, 206 ^ 224 208 211 , 231 212 ^ 232 • 213 , 233 214 , 234 215 , 235 240 242 , 250 3 70i 376i A 382 402 404, 444 412 420 422, 452 430 432 ^ 434 Source line decoding control circuit source line decoding circuit write command detection circuit 408, 454 OR circuit write activation circuit pre-read disable circuit write current Driving activation circuit verification activation circuit, 410 busy signal generation circuit latch, 406 pulse wave generation circuit switching circuit, rewriting, request transmission circuit, bit line decoding circuit, bit line decoding control circuit, AND gate, write command detection circuit, counting circuit Re-write request transmission circuit reference voltage generation circuit, 453 selector drive circuit front-end circuit drive section ^ 98 319644 436 200830313 ^ 437 bit line drive circuit 439 voltage with 1 * * 442 timing adjustment circuit 446 variable delay circuit 448 setting /reset flip-flop 450 write current drive activation circuit AD address signal ADD internal address signal • AF non-magnetic film BL, BLOiBLn bit line B/RZ busy/ready signal CMP comparison circuit CLK clock signal CLKi internal Clock signal CIS constant current source • COMOjCOMn comparator DDLO to DDLn input Data latch DL digit line DO External readout data DOO to DOn Sub output data DI, DIO to Din Input data DLY1 to DLY6, DLY10, DLY11 Delay element E Electronic ΕΝ, ENO to ENn, ENi Sensing activation signal 99 319644 200830313 ^ EG EXOR gate FM1, FM2 ferromagnetic film G1 to G10, G3i, G8i, G9i AND gate T OG1 to OG4, OGli, OG3i, OG4i OR gate HI > H2 magnetic field IVK1JIVK4 inverter circuit IV3, IV4, IV4i Phase Iw Write current 10MC Memory unit ΜΒ0 to MBn Memory block MP/F Main verification result refers to signal NG1 to NG4 NAND gate NK1 NAND circuit NRK1 NOR circuit NQ1 to NQ4, NQ10 N channel MOS transistor • NDa node PAD connection pad P/F comparator output signal (verification result indication signal) P/Fi verification result indication signal PQ1 to PQ4, PQ10 P channel MOS transistor QDL0 ^ QDLn Output data latch RD Read data Read RGO to RGn Buy out the signal signal read gate, read column select gate RGO to RGn 100 319644 200830313 ^ RCSLi read column select gate RCSL0 to RCSLn readout column Select signal RSK0 to RSKn Readout column selection circuit | ROL Internal sense data line SΑΚ0 to SΑΚn Sense amplifier circuits SCK0 to SCKn, SCKi sense control circuit SL source lines SLT1 to SLT5, SLT10 to SLT12 Select circuit to SGL signal line SBW0 to SBWn, SBWi Sub-write system circuit TRS Access transistor TX1 to TX3 Switching element VDD Power supply voltage VR Variable magnetic resistance element, variable resistance element VREFR Read reference voltage ^ Vref Reference voltage VJFREN Verify read-activated signal WD write data WL word line Write write instruction signal lst_Write compare invalidation signal W_BL write bit line drive signal W_DL write digit line drive signals WG0 to WGn, WCSLL · write column select gate 101 319644 200830313 - WCSL0 to WCSLn Write column select signal W__PUSLE Write clock signal -WIL Internal write data line • WREQ Rewrite request XADD X address signal XE Easy magnetization axis YADD Υ Address signal Z1 to Z4 Resistive element • ΦΨ Write mode indication Signal Φ WI Rewrite indication signal Φ WF Write indication detection signal Φ WR Write Detection signal Φυρ count increment signal .102 319644

Claims (1)

200830313 ^, the scope of application for patents · · A magnetic memory system having: a plurality of memory cells arranged in a matrix, and each having a variable Wei resistance element, by the variable resistance element The resistance value is used to memorize the data; the write=system is based on the written data, and the written data is written into the plurality of memory cells as a writing unit; and the G writing control circuit is written in the foregoing data. After writing, the memory data of the memory unit to be written is compared with the write data, and the write system circuit selectively performs writing on the memory unit of the write target according to the comparison result. ; basin ψ J ”, , 八 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 a magnetic memory device in which a plurality of bit lines are provided, and a memory cell is disposed corresponding to each memory cell row and connected to a corresponding column; The logical value of the incoming data is, and when the data is written, V__仳仳^筏 is returned to the memory of the object, and the current line flows through the same direction. The front control circuit is repeated in the same direction. Before the written data is written to the memory unit of the object for the first time, the memory value of the written pairing unit and the logical value of the written data are determined to be 319644 103 200830313 3· In the case of the above-mentioned write system, the memory of the object to be input is stopped and written. = The magnetic body of the second item of the application garden (4), in which a bit line is duplicated, corresponding to each The memory cell is arranged in a row, and the gamma-input tool adds a magnetic field corresponding to the first write circuit from the write system circuit to the memory cell of the corresponding column, and, a plurality of bit lines Corresponding to each memory cell row, the write %·knife is applied to the memory cell from the first "field" of the write circuit to the corresponding row; .', and the write system is described above. The judgment of writing to the control circuit 4. ^致# The way that the first - and second opposing relationship written into the current supplied to the timing when the timing relationship is different from the writing. The magnetic memory according to the first aspect of the invention, wherein at least one of the number of judgments and the writing time of the write control circuit has a predetermined value set in advance; In the judgment of the control circuit, the result of writing the object to be written is: the body is 70, and the writing sequence is repeated until the predetermined value is reached as described in the fourth aspect of the patent application. The plurality of memory units are divided into a plurality of memory blocks, and in each memory block, the written pair unit is used as a writer for not writing the data bits, respectively. Pair = 319644 104 5· 200830313 is selected; 刖逑 Write control circuit is determined according to the consistency of each memory; Τ The write system circuit is equipped with: Write circuit, which is set for each memory block And writing the corresponding write data bit to the corresponding write target memory unit, and, -, the road is determined according to the consistent determination of the write control circuit = the corresponding The memory of the memory block written to the object is written earlier. 6· 7· The magnetic memory of the first item of the scope has the function of -, when the control circuit detects that it is not, send the request to the magnetic memory = the scope of the patent scope Zhao Ji is second and borrows a lifetime = the non-detection of the write-in control circuit, and the internal to ί (2): instead of the write instruction from the outside, and supplies the i-intrusion system. The magnetic memory of claim 7, wherein the intrusion control circuit performs the foregoing writing on the outside of the intrusion-incorporated I"1 magnetic memory from the part. Whether the result of the determination of whether or not the memory unit of the object is identical to the written data is such that the write system circuit execution port is instructed to internally generate the memory data and the write of the two-body unit. Input data: Si::: 319644 105 200830313 9· Directly write the write system circuit. For example, in the magnetic memory of the first, ..., , and the magnetic memory of the item, the memory unit is in the middle, and the data is written by the current flowing through the variable resistance element. The write control circuit forcibly sets the signal for displaying the previous comparison result to the state in which the display 4 is inferior when the first data is written. 106 319644