200839262 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種封裝構造，特別係有關於一種 用以檢測一半導體測試機台之迴路阻抗之封裝構造。 【先前技術】 在半導體製程中，通常會利用一半導體測試機台對 一半導體封裝構造進行測試，以確保產品之品質。目前 既有半導體封裝構造之型態，概可區分為側面具有引腳BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a package structure, and more particularly to a package structure for detecting a loop impedance of a semiconductor test machine. [Prior Art] In a semiconductor process, a semiconductor package structure is usually tested using a semiconductor test machine to ensure the quality of the product. At present, there are existing types of semiconductor package structures, which can be divided into pins on the side.
和底面具有外接端子等兩大類型，前述中具引腳之半導 體封裝構造包含S0P(smaU outline package，小尺寸封 裝）、TSOP(thin small outline package，薄型小尺寸封裝） 及 TSSOP(thin shrink small 〇utW 邸山队薄型收縮 小尺寸封裝）等多種形式。此外，依據引腳數量之不同 可進一步區分為 TS〇p 54-pin、TS〇p “ pin 及 丁_ 86-pin 等等。 、在測試過程中’ $測的半導體封裝構造會被裝載在 半導體'則忒機台之測試槽座内，槽座内之複數個探針 係-對-對應接觸該半導體封裝構造之該些引腳，以進 行電性測試。缺二 . 然而，在重複的使用下，該半導體測試機 台之該些探針合古你 可曰有銹化、歪斜、磨損或接觸不良等現 象，導致連續的、日^ ^ 的測试錯誤。在測試進行中無法預測那一There are two types of external terminals, such as external terminals. The semiconductor package structure of the above-mentioned pins includes SOP (smaU outline package), TSOP (thin small outline package), and TSSOP (thin shrink small 〇). utW Lushan team thin shrink small package) and other forms. In addition, depending on the number of pins, it can be further divided into TS〇p 54-pin, TS〇p “pin and D-86-pin, etc. The semiconductor package structure measured during the test will be loaded on the semiconductor. 'In the test socket of the machine, the plurality of probes in the housing - pair-corresponds to the pins of the semiconductor package structure for electrical testing. No. 2. However, in repeated use Under the test, the probes of the semiconductor test machine can be rusted, skewed, worn or poorly contacted, resulting in continuous, daily test errors. It is impossible to predict which one is in progress during the test.
根或那一些撞扯a A 、十《先行損傷而影響測試正確性，通常是 在連續且固定> ^ 、 的不良產生，才更換新的測試槽座（或測 試板）並重新測4 A 1 J忒先别誤測之半導體封裝構造，造成測 200839262 試時間的浪費。以往為了避免測試時間的浪費，會 = 則地更換所有的測試槽座以避免連續的測試錯 =、所有被更換下來的測試槽座仍有部份良好的探針存 在，導致耗費的測試成本提高。 【發明内容】 ▲、本發明之主要目的係在於提供一種檢測半導體測 式機口之封裝構造，用以檢測該半導體測試機台之 阻於 、略The root or the some hit a A, ten "first damage affects the correctness of the test, usually in the continuous and fixed > ^, the bad production, replace the new test socket (or test board) and retest 4 A 1 J忒 Don't misjudge the semiconductor package structure, causing a waste of test time for 200839262. In the past, in order to avoid the waste of test time, it will replace all the test sockets to avoid continuous test errors. = All the test sockets that have been replaced still have some good probes, resulting in higher test cost. . SUMMARY OF THE INVENTION ▲ The main purpose of the present invention is to provide a package structure for detecting a semiconductor test machine port for detecting the resistance of the semiconductor test machine.
几，可依據檢測結果並分析比對以釐清或判 凡疋否有微斷裂、開路或短路之問題，以在預定排程 中獲知探針之變化資訊並判斷是否堪用。 /本發明的目的及解決其技術問題是採用以下技術方 案來實現的。依據本發明揭示一種檢測半導體測試機台 、封裝構造用於測試該半導體測試機台之迴路阻抗，該 封裝構造主要包含一導線架之複數個引腳、一擬晶美 :、複數個被動元件以及一封膠體。其中每一引腳：： 内引腳與一外引腳。該擬晶基板係具有一上表面、 一下表面以及複數個設置於該上表面之第一銲墊與第 銲墊。該些被動元件係表面黏著於該擬晶基板之該下 表面’每一被動元件係具有一第一電極與一第二電：， 母第一電極係電性連接至至少兩個之該些第_銲 墊，母一第二電極係電性連接至至少兩個之該些第二銲 I該封膠體㈣封該擬晶基板、該些被動元件與㈣ 内引腳，且顯露該些外引腳。 本發明的目的及解決其技術問題還可採用以下技術 6 200839262 措施進一资實現。 在前述的封裝構造中，該擬晶基板係可共用型，該 些第一銲墊與該些第二銲墊係區分為複數組晶片模擬 銲墊。 在前述的封裝構造中，該些第一銲塾與該些第二銲 墊係可為中央銲墊。 在前述的封裝構造中，該些第一銲墊與該些第二銲 墊係可為周邊銲墊。 馨 在前述的封裝構造中，該擬晶基板可另包含有複數 個導通孔，以供雙面電性連接。 在前述的封裝構造中，可另包含有複數個銲線，其 係電性連接該擬晶基板與該導線架。 在前述的封裝構造中，可另包含一非導電膠材，其 係黏設該擬晶基板之該上表面於該導線架。 在前述的封裝構造中，該擬晶基板之厚度係可不大 於 〇 · 2 6 m m 〇 • 一 在刖述的封裝構造中，該些被動元件之高度係可不 大於 0.27mm。 在前述的封裝構造中，該導線架係可另包含有一晶 片承座，該些被動元件係黏貼於該晶片承座。 在則述的封裝構造中，可另包含一非導電膠材，其 係黏設該些被動元件於該晶片承座。 、 在刖述的封裝構造中，該些外引腳係可沿該封膠體 之周緣而下彎形成鷗型接腳。 7 200839262 在岫述的封襞構造中，該些被動元件係可選自〇 2 〇 ! 晶片型被動元件。 【實施方式】 依據本發明之第一具體實施例，揭示一種檢測半導 體測試機台之封裝構造。請參閱第1圖所示，該封裝構 造100主要包含一導線架之複數個引腳110與120、一 擬晶基板130、複數個被動元件140以及一封膠體15〇。 該封裝構造1 〇〇係用於測試一半導體測試機台中包含 φ 探針之迴路阻抗。在本實施例中，該導線架並未有晶片 承座’而是LOC(Lead_〇n-Chip，引腳在晶片上）型態， 以該些引腳110與12〇黏接該擬晶基板130。該些引腳 係包含位於兩側之複數個第一引腳丨丨〇與複數個第二 引腳120。依該封膠體15〇之内外作區分，每一第一引 腳11 0係具有一第一内引腳111與一第一外引腳11 2 ; 每一第二引腳120係具有一第二内引腳121與一第二外 引腳122。 _ 該擬晶基板130係具有一上表面131、一下表面132 以及複數個設置於該上表面131之第一銲墊133與第二 銲墊134。該擬晶基板130不具有傳統晶片之積體電路 或其它主動元件，該擬晶基板1 30之尺寸係模擬一晶片 之尺寸’該擬晶基板130之第一銲墊133與第二銲墊 1 3 4之數量與位置係可模擬至少一種以上晶片之銲墊配 置。在本實施例中，該些第一銲墊133與該些第二銲墊 134係可為中央銲墊。其中該擬晶基板130之具有銲墊 8 200839262 之表面尺寸係為7 ·0 mm X 3.8mm。 較佳地’該擬晶基板13 0係可共用型，該此第一鲜 塾133與該些第二銲墊134係區分為複數組晶片模擬辉 塾，以供製成不同之封裝構造。例如，該些第一鲜塾 1 3 3或該些第二銲墊1 3 4在相同功能的部分係為串連， 由内而外分為三排，該些第一銲墊133與該些第二焊塾 134之總數量可分別為86、66與54，以模擬Ts〇p 86-pin(thin small outline package 86 pins，具有 86 根引 •腳之薄型小尺寸封裝）、TS〇P 66-Pin(thin small 〇utHne package 66 pins，具有66根引腳之薄型小尺寸封裝）與 TSOP 54-pin(thin small outline package 54 pins，具有 54根引腳之薄型小尺寸封裝）。故該封裝構造i〇〇可直 接配合 TSOP 54_pin、TSOP 66-pin 或 TSOP 86-pin 之半 導體測試機台之測試槽座作適當打線變化之封裝，不需 要因該擬晶基板1 3 0之銲墊數量變更與線路設計重新 _ 設另一種基板，故能對不同產品測試槽内探針作迴路阻 抗檢測。請參閱第2圖所示，該擬晶基板i 3 〇可另包含 有複數個導通孔1 3 5，以達到雙面電性連接。 請再參閱第1圖所示，該封裝構造1〇〇可另包含有 一非導電膠材1 7 0，其係黏設該擬晶基板丨3 〇之該上表 面131於該導線架之該些第一引腳110與該些第二引腳 !2〇’且不遮蓋所預定打線之部分之該些第一銲墊I” 與該些第二銲墊134。另可利用打線形成之複數個第一 鲜線1 6 1係電性連接該擬晶基板〗3 〇之該些第一銲墊 9 200839262 n3至該些第一引腳110之該些第一内引腳111。複數 個第一鲜線1 62係電性連接該擬晶基板1 3 〇之該些第二 鲜塾134至該些第二引腳120之該些第二内引腳121。 在不同實施例中，亦可以熱壓合或是點焊方式使該擬晶 基板13 0與該導線架之該些第一引腳11 0與該些第二引 腳120之間達成内部電性互連。 请再參閱第1及3圖所示，該些被動元件140係表 面黏著於該擬晶基板130之該下表面132，每一被動元 • 件140係具有一第一電極141與一第二電極142。在本 實施例中’該些被動元件140係為低成本且大量取得之 規格品，例如可選自〇2〇 1晶片型電阻被動元件或更小 的規格。該些被動元件140之尺寸係為l.lmm χ 0.5mm ’其中該些被動元件140之間之間距係約為 0 ·5 mm。睛參閱第4圖所示，該擬晶基板1 3 〇之厚度係 可不大於0.26mm。該些被動元件140之高度係可不大 於0.2 7mm，使焊設該些被動元件14〇之高度可控制在 • 小於0.3mm，而能封裝在該封膠體150内部。 該封膠體150係密封該擬晶基板130、該些被動元 件140、該些第一内引腳111與該些第二内引腳121， 且顯露該些第一外引腳112與該些第二外引腳122，以 供該半導體測試機台之測試槽座之複數個探針之電性 測觸。通常該些第一外引腳11 2與該些第二外引腳i 22 係可沿該封膠體1 50之周緣而下彎形成鷗型接腳。 此外，請參閱第5圖所示，該些被動元件〗4〇之每 10 200839262 第一電極1 4 ί係電性連接至至少兩個之該些第一銲 墊133，每一第二電極ι42係電性連接至至少兩個之該 些第二銲墊1 3 4。因此，上述檢測半導體測試機台之封 裝構造1 00能在預定排程中，如保養或停機時間，獲得 探針之迴路阻抗變化資訊並判斷是否堪用 以TSOP 54-pin說明檢測該半導體測試機台之迴路 阻抗之方法，請再參閱第5圖所示，其中一之該些被動 元件1 4 0係編號為r i，其第一電極1 4〗係連接編號為工 _ 與4之該些第一銲墊133，其第二電極142係連接及編 號為51與54之該些第二銲墊134。 對照到該些第一銲墊133與該些第二銲墊134由内 而外起算第三排銲墊，當連接編號為R1之被動元件 兩端為編號1之第一銲墊133與編號54之第二銲墊134 之間所測得之迴路阻抗係為異常時，則表示連接對應於 編號為1之第一銲墊133之TSOP 54第1號探針與連接 _ 編就為54之該些第二銲墊134之TSOP 54第54號探針 之任一或兩者可能為異常。接著，進一步檢測，當連接 編號為R1之被動元件140兩端為編號1之第一銲墊in 與編號5 1之第二銲墊丨34之間所測得之迴路阻係為正 常時，則表示連接對應於編號1之第一銲墊133之TSOP S4第1號探針與連接編號51之第二銲墊134之TSOP 54 51號探針係為正常。故可推論上述連接編號54之第 —辉塾134之TSOP 54第54號探針係為異常。如此， 進行交叉比對與分析。 11 200839262 、因此，該封裝構造1 00係可檢測該半導體測試機台 之料阻抗是否正常，由迴路阻抗辨識測試迴路中，該 些探針與該些第一引腳110及該些第二引腳120接觸比 率及該半導體測試機台之測試迴路校正。也就是說，利 用封閉迴路檢測電性特性，藉由電性特性以釐清或判斷 封閉迴路是否有微斷裂、開路或短路。此外，該封裝構 造"0亦可檢測出是否有異常之探針，故僅需替換具異 常探針之測試槽座即可繼續使用，以降低測試時間與成 _ 本。 在第二具體實施例中，揭示另一種檢測半導體測試 機台之封裝構造用於測試一半導體測試機台之迴路阻 抗。句參閱第6圖所示，該封裝構造2〇〇主要包含一導 線架之複數個引腳210與220、一擬晶基板23〇、複數 個被動元件240以及一封膠體250。在本實施例中，該 導線架係可另包含有一晶片承座28〇，以供設置該些被 動兀件240。該些引腳係包含位於兩侧之複數個第一引 _ 腳210與複數個第二引腳220。每一第一引腳21〇係具 有一第一内引腳211與一第一外引腳212 ;每一第二引 腳220係具有一第二内引腳221與一第二外引腳222。 該擬晶基板230係具有一上表面231、一下表面2^ 以及複數個設置於該上表面23 1之第一銲塾233與第一 銲塾2 3 4。可利用複數個第一銲線2 6 1係電性連接該擬 晶基板23 0之該些第一銲墊23 3至該些第一引腳21〇之 該些第一内引腳211。複數個第二銲線262係電性連接 12 200839262 該擬晶基板230之該些第二銲墊234至該些第二引腳 2 2 0之該些第二内引腳2 2 1。 請參閱第7圖所示，該擬晶基板230係可共用型， 該些第一銲墊233與該些第二銲墊234係區分為複數組 晶片模擬銲墊。在本實施例中，該些第一銲墊2 3 3與該 些第二銲墊2 34係可為周邊銲墊。其中該擬晶基板230 另包含有複數個導通孔235，以供雙面電性連接。 請參閱第6及8圖所示，該些被動元件240係表面 Φ 黏著於該擬晶基板23 0之該下表面23 2，每一被動元件 240係具有一第一電極241與一第二電極242，每一第 一電極241係電性連接至至少兩個之該些第一銲墊 233’每一第二電極242係電性連接至至少兩個之該些 第二銲塾234。請再參閱第6圖所示，該些被動元件240 可利用一非導電膠材27〇之黏貼，使該些被動元件24〇 黏貼於該晶片承座28〇。藉由該非導電膠材27〇之非導 馨 電避免該些被動元件240之第一電極241與第二電極 242產生電性短路，進而影響測試結果。 該封膠體250係密封該擬晶基板23〇、該些被動元 件240、該些第一内引腳211與該些第二内引腳221， 且顯露該些第一外引腳212與該些第二外引腳222，以 供該半導體測試機台之複數個探針進行電性探測。故該 封裝構造200係可用以檢測該半導體測試機台之迴路 阻抗是否正常。 以上所述’僅是本發明的較佳實施例而已，並非對 13 200839262 本發明作任何形式上的 例福♦ ‘ w 制，雖然本發明已以較佳 例揭路如上，然而並非 定本發明，任何熟悉 :, 人員，在不脫離本發明技術方案範圍内， 利用上述揭示的技術内容作出些許更動或修飾為 ，化的等效實施例，但凡是未脫離本發明技術方案 容’依據本發明的技術實質對以上實施例所作的任 單修改、等同變化與修飾，均仍屬於本發明技術方 範圍内。 【圖式簡單說明】 第1圖：依據本發明之第一具體實施例，一種檢谋 體測試機台之封裝構造之截面示意圖。 第2圖：依據本發明之第—具體實施例，該封裝福 一擬晶基板之上表面示意圖。 第3圖··依據本發明之第一具體實施例，該封裝構 該擬晶基板之下表面示意圖。 第4圖··依據本發明之第一具體實施例，該封裝構 複數個被動元件設置於該擬晶基板之側 意圖。 第5圖··依據本發明之第一具體實施例，繪示該封 造中該些被動元件連接該擬晶基板之複 銲墊之線路示意圖。 第6圖··依據本發明之第二具體實施例，另—種檢 導禮測試機台之封裝構造之截面示意圖。 第7圖：依據本發明之第二具體實施例，該封裝福 蠓 實施 本專 當可 等同 的内 何簡 案的According to the test results and analysis of the comparison to clarify or determine whether there is a problem of micro-fracture, open circuit or short circuit, to know the change information of the probe in the predetermined schedule and judge whether it is applicable. The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. According to the present invention, a semiconductor test machine and a package structure for testing a circuit impedance of the semiconductor test machine are disclosed. The package structure mainly includes a plurality of pins of a lead frame, a pseudo-crystal: a plurality of passive components, and a Sealing body. Each of these pins:: an internal pin and an external pin. The pseudomorphic substrate has an upper surface, a lower surface, and a plurality of first pads and first pads disposed on the upper surface. The passive components are adhered to the lower surface of the pseudocrystalline substrate. Each passive component has a first electrode and a second electrical: the female first electrode is electrically connected to the at least two of the first _ solder pad, the mother-second electrode is electrically connected to at least two of the second solders. The sealant (4) seals the crystal substrate, the passive components and (4) inner leads, and exposes the external leads foot. The object of the present invention and solving the technical problems thereof can also be implemented by the following technology 6 200839262. In the above package structure, the pseudomorphic substrate is of a common type, and the first pads and the second pads are divided into a plurality of array dummy pads. In the foregoing package structure, the first solder pads and the second solder pads may be central solder pads. In the foregoing package structure, the first pads and the second pads may be peripheral pads. In the foregoing package structure, the crystal substrate may further comprise a plurality of via holes for electrical connection on both sides. In the foregoing package structure, a plurality of bonding wires may be further included, which electrically connect the crystal substrate to the lead frame. In the foregoing package structure, a non-conductive adhesive material may be further disposed to adhere the upper surface of the crystal substrate to the lead frame. In the foregoing package construction, the thickness of the pseudomorphic substrate may be no more than 〇 · 2 6 m m 一 • In the package construction described above, the height of the passive components may be no more than 0.27 mm. In the foregoing package construction, the lead frame may further include a wafer holder to which the passive components are attached. In the package construction described above, a non-conductive adhesive material may be further included to adhere the passive components to the wafer holder. In the package structure described above, the outer leads may be bent down along the circumference of the sealant to form a gull-type pin. 7 200839262 In the enclosed construction described above, the passive components may be selected from the group consisting of 〇 2 〇 ! wafer type passive components. [Embodiment] According to a first embodiment of the present invention, a package structure for detecting a semiconductor test machine is disclosed. Referring to FIG. 1, the package structure 100 mainly includes a plurality of pins 110 and 120 of a lead frame, a crystal substrate 130, a plurality of passive components 140, and a gel 15 〇. The package structure 1 is used to test the loop impedance of a φ probe in a semiconductor test machine. In this embodiment, the lead frame does not have a wafer holder' but a LOC (Lead_〇n-Chip) type, and the pins 110 and 12A are bonded to the crystal. Substrate 130. The pins include a plurality of first pins 两侧 and a plurality of second pins 120 on both sides. Each first pin 110 has a first inner pin 111 and a first outer pin 11 2 according to the inside and outside of the sealing body 15; each second pin 120 has a second The inner pin 121 and the second outer pin 122. The crystal substrate 130 has an upper surface 131, a lower surface 132, and a plurality of first pads 133 and second pads 134 disposed on the upper surface 131. The crystal substrate 130 does not have an integrated circuit or other active component of a conventional wafer. The size of the crystal substrate 130 is a size of a wafer. The first pad 133 and the second pad 1 of the crystal substrate 130. The number and location of 3 4 can simulate a pad configuration of at least one wafer. In this embodiment, the first pads 133 and the second pads 134 may be central pads. The surface size of the crystal substrate 130 having the bonding pad 8 200839262 is 7·0 mm X 3.8 mm. Preferably, the crystal substrate 130 is of a common type, and the first fresh 133 and the second pads 134 are divided into a plurality of arrays of dummy dies for making different package configurations. For example, the first fresh slabs 133 or the second solder pads 134 are connected in series in the same function, and are divided into three rows from the inside to the outside, and the first pads 133 and the The total number of second soldering 134s can be 86, 66, and 54, respectively, to simulate Ts〇p 86-pin (thin small outline package 86 pins, with a small footprint of 86 pins), TS〇P 66- Pin (thin small 〇utHne package 66 pins, thin and small package with 66 pins) and TSOP 54-pin (thin small outline package 54 pins, small package with 54 pins). Therefore, the package structure can be directly matched with the test socket of the TSOP 54_pin, TSOP 66-pin or TSOP 86-pin semiconductor test machine for proper wire change packaging, and the soldering of the crystal substrate is not required. The number of pads changed and the circuit design was re-set to another substrate, so the loop impedance detection can be performed on the probes in different product test slots. Referring to FIG. 2, the crystal substrate i 3 〇 may further include a plurality of via holes 135 to achieve a double-sided electrical connection. Referring to FIG. 1 again, the package structure 1 further includes a non-conductive adhesive material 170 that adheres the upper surface 131 of the crystal substrate 于3 于 to the lead frame. The first pin 110 and the second pins !2〇' do not cover the first pads I" and the second pads 134 of the portion of the predetermined wire. The plurality of wires may be formed by using a plurality of wires. The first fresh line 161 is electrically connected to the first solder pads 9 200839262 n3 of the pseudo-crystal substrate to the first inner leads 111 of the first pins 110. The fresh wire 1 62 is electrically connected to the second fresh 塾 134 of the susceptor substrate 13 to the second inner leads 121 of the second pins 120. In different embodiments, it may also be hot Pressing or spot welding causes internal interconnection between the crystal substrate 130 and the first pins 110 of the lead frame and the second pins 120. Please refer to the first and As shown in FIG. 3, the passive components 140 are adhered to the lower surface 132 of the crystal substrate 130. Each of the passive components 140 has a first electrode 141 and a second electrode 142. In the present embodiment, the passive components 140 are low-cost and widely obtained specifications, for example, may be selected from the 〇2〇1 chip-type resistive passive components or smaller specifications. The passive components 140 are sized l .lmm χ 0.5mm 'where the distance between the passive components 140 is about 0. 5 mm. As shown in Fig. 4, the thickness of the crystal substrate 1 3 〇 may be no more than 0.26 mm. The height of the component 140 can be no more than 0.27 mm, so that the height of the passive components 14 can be controlled to be less than 0.3 mm, and can be packaged inside the encapsulant 150. The encapsulant 150 seals the crystal substrate 130. The passive component 140, the first inner leads 111 and the second inner leads 121, and the first outer leads 112 and the second outer leads 122 are exposed for the semiconductor test Electrical probes of a plurality of probes of the test socket of the machine. Generally, the first outer pins 11 2 and the second outer pins i 22 can be bent down along the circumference of the seal body 150 Form a gull-type pin. In addition, please refer to Figure 5, the passive components are 4 per 10 20083926 2 The first electrode 1 4 电 is electrically connected to at least two of the first pads 133 , and each of the second electrodes ι 42 is electrically connected to at least two of the second pads 1 3 4 . The above-mentioned inspection semiconductor test machine package structure 100 can obtain the loop impedance change information of the probe in a predetermined schedule, such as maintenance or downtime, and determine whether the TSOP 54-pin description can be used to detect the semiconductor test machine. For the method of circuit impedance, please refer to FIG. 5 again. One of the passive components is numbered ri, and the first electrode is connected to the first number of workers _ and 4. The pad 133 has a second electrode 142 connected to the second pads 134 numbered 51 and 54. Referring to the first pad 133 and the second pads 134, the third row of pads is calculated from the inside to the outside. When the passive component of the connection number R1 is connected to the first pad 133 of the number 1 and the number 54 When the measured loop impedance between the second pads 134 is abnormal, it means that the TSOP 54 No. 1 probe corresponding to the first pad 133 numbered 1 and the connection _ is 54 Either or both of the TSOP 54 No. 54 probes of the second pads 134 may be abnormal. Then, it is further detected that when the loop resistance measured between the first pad in the number 1 of the passive component 140 with the connection number R1 and the second pad 编号 34 of the number 51 is normal, then It is indicated that the TSOP S4 No. 1 probe corresponding to the first pad 133 of No. 1 and the TSOP 54 No. 51 probe of the second pad 134 of Connection No. 51 are normal. Therefore, it can be inferred that the probe No. 54 of the TSOP 54 of the above-mentioned connection number 54 is an abnormality. In this way, cross comparison and analysis are performed. 11 200839262, therefore, the package structure 100 can detect whether the material impedance of the semiconductor test machine is normal, and the probes and the first pins 110 and the second leads are identified by the circuit impedance identification test circuit. Foot 120 contact ratio and test loop correction of the semiconductor test machine. That is to say, the closed loop is used to detect the electrical characteristics, and the electrical characteristics are used to clarify or judge whether the closed loop is slightly broken, open or shorted. In addition, the package structure "0 can also detect the presence of an abnormal probe, so it is only necessary to replace the test socket with the abnormal probe to continue to use, in order to reduce the test time and the cost. In a second embodiment, another package inspection configuration for testing a semiconductor test machine is disclosed for testing the loop impedance of a semiconductor test machine. As shown in Fig. 6, the package structure 2 includes a plurality of pins 210 and 220 of a wire frame, a crystal substrate 23, a plurality of passive components 240, and a colloid 250. In this embodiment, the lead frame may further include a wafer holder 28A for providing the movable member 240. The pins include a plurality of first pin 210 and a plurality of second pins 220 on both sides. Each of the first pins 21 has a first inner pin 211 and a first outer pin 212; each second pin 220 has a second inner pin 221 and a second outer pin 222. . The crystal substrate 230 has an upper surface 231, a lower surface 2^, and a plurality of first solder pads 233 and first solder pads 234 disposed on the upper surface 23 1 . The plurality of first bonding wires 216 are electrically connected to the first pads 23 3 of the dummy substrate 23 0 to the first inner leads 211 of the first pins 21 . The plurality of second bonding wires 262 are electrically connected to the second pads 234 of the second substrate 230 to the second inner pins 2 2 1 of the second pins 220. Referring to FIG. 7, the crystal substrate 230 is of a common type, and the first pads 233 and the second pads 234 are divided into a plurality of wafer dummy pads. In this embodiment, the first pads 2 3 3 and the second pads 2 34 may be peripheral pads. The microcrystal substrate 230 further includes a plurality of via holes 235 for electrical connection on both sides. Referring to FIGS. 6 and 8, the passive component 240 has a surface Φ adhered to the lower surface 23 of the crystal substrate 230, and each passive component 240 has a first electrode 241 and a second electrode. 242, each of the first electrodes 241 is electrically connected to the at least two of the first pads 233 ′ each of the second electrodes 242 is electrically connected to the at least two of the second pads 234 . Referring to FIG. 6 again, the passive components 240 can be adhered to the wafer holder 28 by a non-conductive adhesive 27 黏. The non-conductive rubber 27 is used to prevent the first electrode 241 and the second electrode 242 of the passive component 240 from being electrically short-circuited, thereby affecting the test result. The encapsulant 250 seals the crystal substrate 23 , the passive components 240 , the first inner leads 211 and the second inner leads 221 , and exposes the first outer leads 212 and the The second outer lead 222 is electrically probed by a plurality of probes of the semiconductor testing machine. Therefore, the package structure 200 can be used to detect whether the loop impedance of the semiconductor test machine is normal. The above description is only a preferred embodiment of the present invention, and is not intended to be a simplification of the present invention in the form of a preferred embodiment of the present invention. Any person skilled in the art, without departing from the technical scope of the present invention, may make some modifications or modifications to the equivalent embodiments, but without departing from the technical scope of the present invention. Technical singular modifications, equivalent changes and modifications to the above embodiments are still within the scope of the technical scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view showing a package structure of a test body testing machine in accordance with a first embodiment of the present invention. Fig. 2 is a schematic view showing the upper surface of the package of a crystal substrate according to the first embodiment of the present invention. Fig. 3 is a schematic view showing the lower surface of the crystal substrate according to the first embodiment of the present invention. Figure 4: According to a first embodiment of the present invention, the package is constructed with a plurality of passive components disposed on the side of the crystal substrate. Fig. 5 is a schematic view showing the circuit of the passive bonding pads of the dummy substrate in the package according to the first embodiment of the present invention. Fig. 6 is a cross-sectional view showing the package structure of another type of inspection test machine in accordance with a second embodiment of the present invention. Figure 7: In accordance with a second embodiment of the present invention, the package is implemented in accordance with this internal equivalent
半導 造中 造中 造中 面示 裝構 數個 測半 造中 200839262 一擬晶基板之上表面示意圖。 第8圖：依據本發明之第二具體實施例，該封裝構造中 該擬晶基板之下表面示意圖。 【主要元件符號說明】 100 封裝構造 110 第， 一引腳 120 第， —引腳 130 擬 晶基板 133 第 一銲整 140 被動元件 150 封膠體 170 非 導電膠材 200 封裝構造 210 第 一引腳 220 第 二引腳 230 擬 晶基板 233 第 一銲塾 240 被動元件 250 封 膠體 270 非 導電膠材 ill第一内引腳 121第二内引腳 131上表面 134第二銲墊 141第一電極 161第一銲線 211第一内引腳 221第二内引腳 231上表面 234第二銲墊 241第一電極 261第一鍀線 280晶片承座 112第一外引腳 122第二外引腳 132下表面 導通孔 142第二電極 162第二銲線 212第一外引腳 222第二外引腳 232下表面 235導通孔 242第二電極 262第二銲線 15In the middle of the semi-conductor, the mid-surface, the fabrication, the surface, the fabrication, the fabrication, the fabrication, the fabrication, the fabrication, the fabrication, the fabrication, the fabrication, the fabrication, the fabrication, the fabrication, the construction Figure 8 is a schematic view showing the lower surface of the crystal substrate in the package structure in accordance with a second embodiment of the present invention. [Main component symbol description] 100 package structure 110 first, one pin 120 first, - pin 130 crystal substrate 133 first soldering 140 passive component 150 encapsulant 170 non-conductive adhesive material 200 package structure 210 first pin 220 Second pin 230 crystal substrate 233 first pad 240 passive component 250 encapsulant 270 non-conductive rubber ill first inner pin 121 second inner pin 131 upper surface 134 second pad 141 first electrode 161 a bonding wire 211 first inner pin 221 second inner pin 231 upper surface 234 second pad 241 first electrode 261 first twist line 280 wafer holder 112 first outer pin 122 second outer pin 132 Surface via 142 second electrode 162 second bond wire 212 first outer pin 222 second outer pin 232 lower surface 235 via hole 242 second electrode 262 second bond wire 15