TW200837930A - Semiconductor memory device with ferroelectric device and refresh method thereof - Google Patents

Abstract

A semiconductor memory device with a ferroelectric device comprises a channel region, a drain region and a source region formed in a substrate, a ferroelectric layer formed over the channel region, and a word line formed over the ferroelectric layer. A different channel resistance is induced to the channel region depending on a polarity state of the ferroelectric layer, a data read operation is performed by a cell sensing current value differentiated depending on the polarity state of the ferroelectric layer while a read voltage is applied to the word line and a sensing bias voltage is applied to one of the drain region and the source region, and a data write operation is performed by a polarity of the ferroelectric layer changed depending on a voltage applied to the word line, the drain region and the source region.

Description

200837930 IX. INSTRUCTIONS: This application claims Korean patent applications No. 10-2006-00135179, 00135181, 00135182, 10-2007-0065033, 0065034, which were applied for on December 27, 2006 and June 29, 2007. Priority protection of 0065008, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD Embodiments of the present invention relate to a semiconductor memory device having a ferroelectric element and a method for updating the same, and more particularly to a single transistor-field effect transistor (1T) having non-volatile characteristics The -FET) type ferroelectric memory element is applied to a technique of dynamic random access memory (DRAM). [Prior Art] In general, power must be continuously supplied to store data in DRAM as a volatile memory. Since the memory cell design DRAM according to a small amount of charging electrons to store the charged power, when the power is instantaneously cut off, the RAM data is destroyed. If these charged electrons are not continuously recharged, the previously charged power will be destroyed. The update operation is a process of recharging the cells of the memory chip. The memory cells of the column can be charged during each update cycle. Although the update operation is performed by the memory control of the system, several wafers are designed to perform a self-updating operation. For example, the DRAM has a self-updating control circuit, so that a self-updating operation can be performed without requiring a central processing unit or an external updating circuit. Self-renewal methods to reduce power consumption have been applied to portable computers. Because DRAM is volatile and has a short update cycle, -5- 200837930 traditional DRAMs often perform update operations. As a result, frequent update operations increase power consumption and reduce performance. In general, ferroelectric random access memory (FeR AM) is highly regarded as a memory component of the next generation because it has a fast data processing speed as DRAM and can retain data even when the power is turned off. . A FeRAM having a structure similar to a DRAM may include a capacitor made of a ferroelectric substance such that it employs a highly residual polarity characteristic of the ferroelectric substance, and the data is not deleted even if the electric field has been removed. ® Single-Crystal 1 - Capacitor (1T1C) type cell of conventional FeRAM includes a switching element configured to perform switching operations according to the state of the word line and to connect the bit line to the non-volatile ferroelectric capacitor and A non-volatile ferroelectric capacitor connected between the flat wire and one of the switching elements. The switching element is an NMOS transistor whose switching operation is controlled by a gate control signal. SUMMARY OF THE INVENTION According to the present invention, there is provided a semiconductor memory device having a ferroelectric element, the memory element comprising: a 1-TFET type memory cell; and a complex even-numbered bit line in a manner perpendicular to the complex digital line Arranging, and odd bit lines arranged in a manner perpendicular to the complex digital line and interleaved with the even bit lines, wherein the memory cell is coupled to the plurality of even bit lines and the plurality One of the odd bit lines is between adjacent even/odd bit lines and is configured to sense the data current of the memory cell by the polarity of the ferroelectric layer, wherein the polarity of the ferroelectric layer depends on The word line changes with the voltage of the pair of even/odd bit lines and is changed by the -6 depending on the complex write voltage applied to the word line and the pair of even/odd bit lines - 200837930 The polarity of the ferroelectric layer, storing 2 η bit data (η is a natural number). According to the present invention, there is provided a method of updating a semiconductor memory device having a ferroelectric element, the memory element comprising: a complex digital element line arranged in a column direction; and the plurality of bit lines 'configured perpendicular to the complex digital line And a single transistor (1-T) field effect transistor (FET) type memory cell, comprising a channel region, a drain region and a source region formed in the substrate, wherein the ferroelectric layer is formed over the channel region, And a word line formed over the ferroelectric layer, wherein a polarity state of the ferroelectric layer is changed depending on a pair of bit lines applied to the word line and connected to the memory cell, the method comprising : sensing different channel resistances of the channel region of the 1T-FET type memory cell to read and/or write data; and updating the data of the memory cell with a specific update period to improve the memory cell The retention characteristics of the stored data. According to the present invention, there is also provided a semiconductor memory device having a ferroelectric element, the memory device comprising: a single transistor (1-T) field effect transistor (FET) type memory cell, comprising a channel region formed in the substrate, a drain region and a source region; a ferroelectric layer formed above the channel region; and a word line formed above the ferroelectric layer, wherein the complex digital line arranged in the column direction depends on a polarity state of the ferroelectric layer And arranging the plurality of bit lines and the frames perpendicular to the complex digital element lines to form an update control unit that performs an update operation with a specific update period to improve the retention characteristics of the data stored in the memory cells, and induces different channel resistances to the channel regions.値, and the memory cells thereof are connected between one of the plurality of bit lines and the adjacent bit lines and the frame is formed by changing the polarity of the ferroelectric layer according to the voltage applied to the word line and the pair of bit lines. Read/write data. According to the present invention, there is also provided a semiconductor memory element 200837930 having a ferroelectric element, wherein the memory element comprises: a single transistor (1-turn) field effect transistor (FET) type memory cell, which is formed on a substrate a channel region, a drain region and a source region; a ferroelectric layer formed above the channel region; and a word line formed above the ferroelectric layer, wherein the channel region is induced different depending on the polarity state of the ferroelectric layer The channel resistance 値, and the ferroelectric element thereof include: a complex digital element line arranged in a column direction, a complex bit line arranged perpendicular to the complex digital element line, and a memory cell connected to one of the complex bit lines The adjacent bit lines and the frame structure read/write data by changing the polarity of the ferroelectric layer according to the voltage applied to the word line and the pair of bit lines. According to the present invention, there is also provided a semiconductor memory device having a ferroelectric element, the memory element comprising: a channel region, a drain region and a source region formed in the substrate; a ferroelectric layer formed over the channel region; and a word a line formed above the ferroelectric layer, wherein a different channel resistance of the channel region is caused, a read voltage is applied to the word line, and a sensing bias is applied to the drain region depending on a polarity state of the ferroelectric layer In one of the source regions, the data reading operation is performed by the cell sensing current 取决于 depending on the polarity state difference of the ferroelectric layer, and the data writing operation is performed by applying a voltage to the word line, The drain region and the source region are implemented to change the polarity of the ferroelectric layer. [Embodiment] Fig. 1 is a cross-sectional view showing a semiconductor memory device. A single transistor (1--) field effect transistor (FET) type ferroelectric device includes a P-type channel region, an N-type drain region 2, and an N-type source region 3 formed in a P-type substrate 1. A ferroelectric layer 4 is formed on the channel region, and a word line 5 is formed on the ferroelectric layer 4. -8- 200837930 A buffer insulating layer 6 may be formed between the channel region and the ferroelectric layer 4 for stabilizing the process. In other words, the buffer insulating layer 6 is formed to eliminate the process and material differences between the channel region and the ferroelectric layer 4. The semiconductor memory element reads and writes data in response to the channel resistance of the memory cell which is distinguished by the polarity state of the ferroelectric layer 4. When the polarity of the ferroelectric layer 4 induces a positive charge to the channel, the memory element becomes in a state of a local resistance channel and becomes an off state. On the other hand, when the polarity of the ferroelectric layer 4 induces a negative charge to the channel, the memory cell changes to a low resistance state and becomes conductive. The ferroelectric memory cell can select the polarity of the ferroelectric layer 4, and the data is written into the cell so that the memory cell can be non-volatile. Figures 2a and 2b are graphs showing the bit line currents of the read mode of the semiconductor memory device. As shown in Fig. 2a, when the P-type channel region is οη/off, the voltage 値 is set to the word line read voltage Vrd. By reading the voltage Vrd by the word line, when the channel region is turned on, the maximum amount of bit line BL current can flow, and when the channel region is turned off, the minimum amount of bit line BL, current can flow. As shown in FIGS. 2 and b, when the same word line read voltage Vrd is applied while changing the voltage of the bit line BL, the memory cell has a different current 位 of the bit line BL, which depends on the memory stored in the memory. The cell data in the cell is 値. In other words, when the data "0" is stored in the memory cell, a large amount of bit line BL current flows as the bit line BL voltage increases. When the data " 储存 is stored in the memory cell, the bit line BL current does not change, and although the bit line BL voltage increases, it can flow in a small amount. -9-200837930 FIG. 3 is an embodiment of the present invention Timing diagram of the write cycle operation of the semiconductor memory device. In period 10, the cell data is 'read and amplified' in all cells of the selected column address and stored in the scratchpad. During the period tl In the 'data' 0 is written to all memory cells, it is not clear which data is stored in the existing memory cells. As a result, in order to know which data is stored in the existing memory cells, in the data Before “〇” is written to the cell, the data “0” will be stored in the scratchpad. ® In the period t1, the data “0” will be written to all the selected column addresses. In the cell, during the period t2, the data stored in the register is rewritten and re-stored in the memory cell, and new external data is written into the cell. During the period t2, because In the period t1, the data "0" is pre-written and the capital is saved. "〇", or write a new data "1" to the cell. Figure 4 is a timing diagram of the update cycle operation of the semiconductor memory device of the present invention. During the period to, the cell data will be selected. All cells of the column address are read and amplified, and stored in the scratchpad. In the period t1, an update "0" operation is performed to respond to the data of the selected column address. In the period t2, an update "丨" operation is performed to reply to the data "Γ" in response to the cell of the selected column address. Fig. 5 is a view showing a semiconductor memory device of the present invention. The semiconductor memory device includes a pad array 100, an update control unit 110, a column address register 120, a column timing logic 13A, a column decoder 140, 40-'200837930 cell array 150, read/write control The unit 1 60, the row decoder 1 7 0, the row address register 1 800, the row timing logic 1 90, the update status information register 200, the sense amplifier, the register, the read driver 210, Input/output logic 2 20, I/O register 230, I/O buffer 240, and I/O pin 250. The update control unit 110 includes an update controller 111 and an update counter 112. The cell array 150 may include a plurality of 1T-FET type cell elements of Fig. 1. The pad array 1A can include a plurality of pads PAD, each of which becomes a ® receive column address and a row address, thereby outputting the address over time. The update controller 11 1 outputs an update signal REF and an update enable signal REF — EN for controlling the update operation in response to the ras signal /RAS, the cas signal/CAS, the read/write command R, /W, and the update control signal. . The update counter 1 1 2 counts the update period to output the count address CA in response to the update signal REF applied by the update controller 1 1 1 and the update control signal applied by the update status information register 200. The update controller 111 and the update counter 1 1 2 output update operation information and update count information to the new state information register 200. The column address register 1 20 receives the column address from the pad array unit 100 and temporarily stores the address. The column address register 1 20 is an output signal of the column timing logic 1 30 and a read/write control signal RWCON applied by the read/write control unit 160 to output a column address RADD to column decoding. The device 140. Column timing logic 130 controls the store operation and address output timing of column address register 120 in response to ras signal /RAS'. Column decoder 140 decodes the column address RADD applied by column address register 1 20 from -11-200837930 to output the address to cell array 150. The read/write control unit 160 outputs a read/write control signal for controlling a read/write operation in response to the ras signal /RAS, the cas signal /CAS, and the read/write command R, /W. The RWCON is in the column address register 120 to control the row decoder 170 and the sense amplifier, the register and the read driver 210. Row decoder 170 decodes the row address applied by row address register 180 to determine the output address to input/output logic 220, depending on the control of read/write control unit 160. The row address register 180 temporarily stores the row address from the pad array 100 to output the address to the row decoder 170 depending on the control of the row timing logic 1 90. The line timing logic 190 controls the row operation of the row address register 180 and the address output timing in response to the cas signal/CAS. When the update signal REF is enabled, the register 2 1 0 outputs the update data to the memory element depending on the control of the line timing logic 1 90. The update information register 200 is a non-volatile scratchpad that is configured to store relevant parameters of the update operation. The update information register 200 stores update count information, power cutoff timing information of the system or internal memory, and other parameter information. The update status information register 200 outputs an update control signal based on the parameter information in the update operation. In the power cutoff sequence, the information of the update control unit 111 and the update counter 112 is transmitted to the update status information register 200, and the associated -12-200837930 information of the external command received by the I/O buffer 240 is stored. The information stored in the update status information register 200 through the I/O buffer 240 and the I/O pin 250 is output to the system controller 300. The sense amplifier S/A senses and amplifies the cell data to identify the data "Γ and data "〇". When the data is written into the memory cell, the read driver W/D is responsive to the write data to generate Driving voltage to supply driving voltage to the bit line. The register REG temporarily stores the data sensed in the sense amplifier S/A and re-stores the data in the memory cell during the write operation. Logic 220 relies on the output signals from row decoder 170 and read/write commands R, /W to read the data stored in cell array 150 and store the data in cell array 150. The input/output logic 2 20 includes a row select signal C/S and outputs a data stored in the cell array 150 to the data I/O register 230 in response to the output enable signal /OE. The I/O buffer 240 is The read data stored in the I/O register 230 is buffered, and the buffered data is output to the I/O pin 250. The I/O buffer 240 is buffered and received through the I/O pin 250. The data is written, and the buffered data is output to the I/O register 230. The I/O buffer 240 is transmitted through the I/O. The O pin 25 0 outputs the information stored in the update status information register 200 to the system controller 300. The I/O pin 250 outputs the data received from the I/O buffer 240 to the system through the data bus. Within the controller 300, or through the data bus, to output data from the system controller 300 to the I/O buffer 240. The read/write operation of the semiconductor memory device will be described below. A plurality of pads PAD are used to receive the column address and the row-13-200837930 address, and the output address is to the column address register 1 20 and the row address register 180. The column address register 120 and the row The address register 180 outputs the column address and the row address in a predetermined time difference according to the control of the column timing logic 130 and the row timing logic 190 in a timing multiplexing mode. The column address register 120 can be temporarily synchronized with the ras signal. /RAS to store the column address, and can output the column address RADD to column decoder 140. When the column address is output, the row address register 1 80 temporarily stores the row address. The device 120 selects the column address from the pad array 100 in a normal operation to output the address to Within the column decoder 140. When the update enable signal REF_EN is enabled in the update mode, the column address register 120 selects the count address CA accepted from the update counter 112 to output the address to the column decoder 140. The row address register 180 can temporarily synchronize the cas signal/CAS to store the row address and can output the row address to the row decoder 170. When the row address is output, the column address register 1 20 The column address is temporarily stored. In the read mode, when the output enable signal /OE is started and the read command is started, the data stored in the cell array 150 is output to the output I according to the input/output logic 220. /O register 230. On the other hand, in the write mode, when the output enable signal /OE is not activated and the write command /W is started, the data is stored in the cell array 150 in accordance with the input/output logic 22. How to update the memory component. When an update operation command is applied, the update controller 111 outputs a signal for performing an update operation in response to the ras -14-200837930 signal/Ras, cas signal/CAS, read/write command R, /W, and update control signal. The update signal REF is updated into the counter 1 1 2 and the update enable signal REF__EN is output to the column address register 120. The update counter 1 1 2 counts the update cycle to update the update cycle to output the count address CA to the column address register 120 in response to the update signal REF and the update control signal applied by the update controller 1 1 1 . The count address CA output from the update counter 1 1 2 is stored in the column address • register 120. The line timing logic 190 outputs the data stored in the row address register 180 to the row decoder 170 in response to the cas signal/CAS. When the sense amplifier S/A is activated, the updated data stored in the register REG through the input/output logic 220 is written into the cell array 150. The update signal REF may be a control signal using the ras signal /RAS and the cas signal /CAS. In other words, when the update signal REF is a control signal using the ras signal /RAS and the cas signal /CAS, the update operation is first performed in /CAS before the /RAS method (/01311). In the general mode for performing read and write operations, the ras signal /RAS is initiated faster than the cas signal /CAS, such that the general operation is performed in accordance with the column timing logic 130 and the row timing logic 190. When the ras signal /Ras is started earlier, the external column address is enabled, causing the sense amplifier S/A to be activated. When the cas signal/CAS is started, the external row address is started. In the update mode, the update control unit U丨 senses that the cas signal /cAS of the start update signal rEF is converted earlier than the ras signal /RAS. In other words, when the update control unit 101 detects a cas signal/CAS that is earlier than the ras signal /RAS -15·200837930, the update control unit 1 1 1 determines the update mode to start the update enable signal REF_EN. . When the update enable signal REF_EN is enabled, the column address register 120 performs an update operation in response to the count address CA generated in accordance with the update counter 1 1 2, while the line of the normal mode is cut off. The column address register 1 20 senses the simultaneous transition of the cas signal /CAS and the ras signal /RAS to initiate the update signal REF. Although in the embodiment of the present invention, the update method using the /CBR method is taken as an example, the update operation can be performed by various methods of self-updating, automatic updating, or clock. In the update mode, the word line WL of the cell array 150 can be selected in accordance with the count address CA belonging to the output signal of the update counter 112. As a result, the data of the corresponding cell having the 1T-FET architecture in the cell array 150 is sensed and amplified and stored in the sense amplifier register REG. The new data will be written to the cell array 150, or the data stored in the register REG will be re-stored in the cell array 150. The following will describe the updating method of the semiconductor memory device depending on the power supply ΟΝ/OFF. When the power is turned on and the system power of the DRAM belonging to the volatile memory is turned off, the data of the memory is uploaded, and a new update operation is started. In other words, when the system power is activated, the data of the memory needs to be uploaded. However, in the non-volatile ferroelectric memory element of the embodiment of the present invention, when the power is turned on and the system power is turned off, the update state can determine whether the update time is exceeded. When the update time is exceeded, the data of the memory is uploaded, so a new update operation is started. On the other hand, when the update time is not exceeded, the update time will take effect so that the previous update operation can continue. The update status information register 200 stores parameters related to the update operation in the non-volatile register. The update status information register 200 stores updated count information, power cutoff timing information of the system or internal memory, and other parameter information to become non-volatile. In the Update Status Information Register ® 200, an additional power sensing unit (not shown) senses the οη/off status of the system or internal memory. When the power is turned off, the data stored in the update status information register 200 can be read to calculate the update transition time. The update transition time can be stored in the mode register group MRS or controlled at the system level. The update transition time calculated in response to the update control signal is transmitted to the update control unit 1 1 1 and controls the update operation. As a result, in this embodiment, it is not necessary to upload update related information even if the power is turned on. ® update methods include distribution update methods and burst update methods. In the distribution update method, the update operation is performed with the same time distribution so that all cells can be updated within the update time in response to the count address CA counted in the update counter 112. In other words, when the 8k column is updated, each distribution update operation period is represented by (total update time) / 8k. As a result, the cell becomes initialized only when data is written to all of the word lines WL. In the burst update method, during the burst update cycle, the -17-200837930 line is continuously executed for 8k update cycles. Each pulse wave means each update cycle, and a general operation is performed during a read/write operation cycle in which the pulse wave is not started. In the updating method of the non-volatile ferroelectric memory element, the timer control operation will be described below. The update status information register 200 identifies if the system power is off and stores the result. When the power is turned off, the system timer in the system is used, and the internal memory timer is off, thus controlling the update operation. The system timer can store the date and time with the battery when the power supply needs to be sustained. ® On the other hand, when the power supply is not turned off, the internal memory timer of the individual operation is used, thus controlling the internal update operation. Select one of the external system timer or internal memory timer according to the power ο η / 〇 f f status via the input/output data pin 2 5 0. In other words, the update status information register 200 of the memory element including the internal memory timer can exchange data in the data bus through the I/O buffer 240 and the I/O pin 250. The system CPU, including the system timer, can exchange data with memory elements through the data bus. W When the power is turned off by data exchange between the memory element and the system controller 300, the update operation is performed with an external system timer that is not interrupted by the power supply. When the power is on, the internal memory timer is used to perform the update operation. As a result, the update period and the memory data can be effectively maintained regardless of whether the power state of the memory chip is on or off. Between the update periods, the memory chip power is cut off to reduce power consumption, and only the wafer power is supplied during the update. -18- 200837930 Fig. 6 is a graph showing the data retention characteristics of the semiconductor memory device of the embodiment of the present invention. Over time, the cell data of traditional semiconductor memory components will be degraded, resulting in a limitation on the lifetime of data storage. As a result, as time passes, the bit line BL current corresponding to the cell data "Γ" and "0" is reduced. However, when the power supply is turned off, the timing of the current reduction by the predetermined bit line BL is set to a predetermined period. To perform an update operation to restore the deteriorated cell data to improve the data retention characteristics. When the data storage feature of the memory cell is reduced to more than a preset target, the update circuit is driven to restore the cell data to The initial state. The deterioration of the cell target time will become the update time, so that all cells can operate in the update time. The semiconductor memory device of the present invention is a DRAM having non-volatile characteristics. 〇n/0ff which will be added to the power supply. The time is set to the entire data retention time, so that the update operation is not performed frequently, thereby reducing power consumption and improving performance. Fig. 7 is a plan view of a cell array of a semiconductor memory device according to an embodiment of the present invention. A plurality of word lines WL arranged in the column direction are included. The plurality of bit lines BL may be arranged to be perpendicular to the plurality of word lines WL (in the row direction) A plurality of unit cells C may be arranged in a region where a plurality of word lines WL intersect with a plurality of bit lines BL. Odd bit lines BL<1>, BL<3>, BL<5>, BL<;7>,BL<9> are alternately arranged with the even bit lines BL<0>, BL<2>, BL<4>, BL<6>, BL<8> in the same layer not -19-200837930 When one cell cell c is connected to two bit lines BL, the area of the bit line BL can be prevented from increasing. In other words, the even bit lines BL<0>, BL<2>, BL<4>, BL<6>,BL<8> is formed on the upper or lower layer of the odd bit line BL<1>, BL<3>, BL<5>, BL<7>, BL<9>. Odd bit line BL<1>;,BL<3>,BL<5>,BL<7>,BL<9> are formed in even bit lines BL<0>, BL<2>, BL<4>, BL<6>, :6 The upper or lower layer of B <8> The cell C includes a word line WL and two ® bit lines BL arranged in a different layer. For example, the cell C is connected by a bit line contact point BLC. Character WL < 0 >, even-numbered bit line BL < 2 > and the odd bit lines BL < 3 >. Fig. 8 according to the present invention the cell cell array structure of a semiconductor memory device according to the embodiment, and read showing the operation of FIG. A plurality of word lines WL are arranged in the column direction at predetermined intervals. The plurality of bit lines BL are arranged to be perpendicular to the plurality of word lines WL, in other words, in the row direction. A plurality of unit cells C are located in a region where a plurality of word lines WL intersect a plurality of bit lines BL. The cell C having the 1-TFET structure is connected to the word line WL<0> and the bit line BL<0>, BL<1> formed in a different layer. Although in the embodiment of the present invention, the word line WL<0> and the bit line BL<0>, BL<1> are taken as an example, the present invention is applicable to other word lines WL<1>, WL<lt;;2>,... and other bit line pairs BL<2>, BL<3>, .... The cell C has a drain and a source connected between the pair of bit lines BL<0>, BL<1>, and a gate connected to the word line WL<0>. Arrangement -20- 200837930 The paired bit lines BL<0>, BL<1> in different layers are connected to the sense amplifier S/A, the read driver W/D, and the register REG. The sense amplifier S/A senses and amplifies the cell data to identify the data "1" and the data "〇" such that the sense amplifier S/A is connected to the pair of bit lines BL<0>, BL<1> . The sense amplifier S/A transmits a reference voltage through a reference voltage terminal ref for generating a reference current. When data is written to the memory element, the read driver W/D is configured to generate a driving voltage in accordance with the write data, thereby supplying the driving voltage to the bit line BL. The read driver W/D is connected to the pair of bit lines ^<0>, BL<l> as a temporary memory element for temporarily storing the data of the sense amplifier S/A. Connected to the pair of bit lines BL<0>, BL<1> ° In the read mode of the cell array, the read voltage Vrd is applied to the selected word line WL<0>, and the ground voltage GND It is applied to the unselected word lines WL<1>, WL<2>. The sense bias voltage V s en for sensing the sense current of the cell C is applied to the bit in the pair of bit lines BL<0>, BL<1> connected to the cell C Line BL<0>. The ground voltage is applied to the bit line BL<1>. The cell sensing current Isen flows according to the cell data storage state. As a result, the current flowing in the pair of bit lines BL<0>, BL<1> becomes different due to the polarity of the ferroelectric layer 4, thereby reading the cell data stored in the cell C. . In other words, when the read voltage Vrd is applied to the word WL<0>, the sense bias voltage Vse? is applied to the bit line BL < 0 >, and the ground voltage is applied - 21 - 200837930 in place When the line 6丄<1>, the sense amplifier S/Α senses the cell sensing current lsen flowing in the bit line BL<0>. When the channel region of the memory element is turned off, the cell sensing current lsen is sensed, so that the data stored in the memory element can be read. 另一方面 On the other hand, when the channel region is turned on, the cell is sensed. The element senses the 电流 of the current Is en and thus can read the data “0” stored in the memory element. FIG. 9 is a cell array structure and data '0' write operation of the semiconductor memory element of the embodiment of the present invention. In the case of writing data "0", the power supply voltage VDD exceeding the threshold voltage Vc and changing the ferroelectric property is applied to the selected word line WL<0>, and the ground voltage GND is applied to The unselected word line WL<1>, WL<2>. The ground voltage is applied to the pair of bit lines BL<0>, BL<1> connected to the cell C. Read voltage Vrd is smaller than the threshold voltage Vc, and the power supply voltage VDD is greater than the threshold voltage Vc. The sense bias voltage Vsen is smaller than the read voltage Vrd. When the channel region of the memory element is turned on, the ferroelectric material is polarized. , the data '〇' is written to the memory In other words, when the power supply voltage VDD is applied to the word line WL<0>, and the ground voltage is applied to the pair of bit lines BL<0>, BL<1>, according to the ferroelectric layer 4 Polarization to turn on the channel region, so the data '〇' can be written into the memory device. Figure 10 is a cell array structure of the semiconductor memory device of the embodiment of the present invention and a representation of the data '1' write operation When the data "写入" is written, the negative read voltage -Vrd is applied to the selected word line WL<0>, and the ground voltage GND is applied to the uncharacterized line WL<1>;,WL<2>. The read voltage Vrd is applied to the element line BL<0>, BL<1> connected to the cell C. The positive read voltage Vrd is applied to the drain of the cell C and the negative read voltage -Vrd is applied to the gate of the cell C. By the channel area of the voltage memory element commencing the threshold voltage Vc (the polarization of the ferroelectric layer 4 is changed), the material '1' can be written to the record. When the negative read voltage _Vrd is applied to the word line WL<〇>a voltage Vrd is applied to the pair of bit lines BL<0>, BL<1>, the polarization of the ferroelectric layer 4 is illuminated By the end, the data '1' can be written to the component. A voltage lower than the threshold voltage Vc is applied to the cell of the selected data '0', thus maintaining the data '0'. Fig. 1 is a timing chart showing the operation of the semiconductor memory cell of the embodiment of the present invention. In the period t1, the selected word line WL<0>M is grounded to the read voltage Vrd level, and the bit line BL is converted from the ground level to the sense bias voltage Vsen level. The sense amplifier S/A amplifies the cell sensing voltage Isen flowing through the bit line BL and stores the 値 in the register REG. Fig. 12 is a timing chart showing the operation of the semiconductor memory element of the embodiment of the present invention. In the period t1, the selected word line WL<0> selects the bit source of the pair from the ground, and as a result, the read-write channel region of the memory device is read to the GND bit of the memory pair. The sense is turned on, and the write GND bit -23·200837930 is quasi-transformed into the read voltage Vrd level' and the bit line BL is converted from the ground GND level to the sense bias voltage Vsen level. The sense amplifier S/A senses and amplifies 値' of the cell sensing voltage Isen flowing through the bit line BL and stores the 値 in the register REG. In the period t2, the selected word line WL<0> is converted from the read voltage Vrd level to the power supply voltage VDD level, and the bit line is converted from the sense bias voltage Vsen level to the read voltage Vrd or Ground voltage GND level. As a result, the material '〇' can be written to all cells selected.

® In the period t3, the selected word line WL<0> is converted from the power supply voltage VDD level to the negative read voltage -Vrd level, and the bit line BL is maintained at the read voltage Vrd or the ground voltage GND level. . The data stored in the scratchpad REG is rewritten or replied to in the memory element, or new externally applied data can be written. Since the material '〇' is pre-written in the period U, the data '0' can be maintained, or the data '1' can be written in the period t3. Figure 13 is a view showing a cell array of a semiconductor memory device of an embodiment of the present invention. The cell array includes a plurality of word lines WL arranged in the column direction. The plurality of bit lines BL may be arranged to be perpendicular to the plurality of word lines WL (in the row direction). A plurality of unit cells C may be arranged in an area where a plurality of word lines WL intersect with a plurality of bit lines B L . Bit lines BLO(W), BL1(W), BL2(W), BL3(W) for write operations and bit lines BLO(R), BL1(R), BL2 for read operations ( R) and BL3(R) are staggered in different layers. When one cell C is connected from -24 to 200837930 to two bit lines BL, the area of the bit line BL can be prevented from increasing. In other words, the bit lines BLO(R), BL1(R), BL2(R), and BL3(R) are formed on the bit lines BLO(W), BL1(W), BL2(W), BL3(W). Upper or lower. The bit lines BLO(W), BL1(W), BL2(W), and BL3(W) in the odd row direction are formed in the bit lines BLO(R), BL1(R), and BL2(R) in the even row direction. , the upper or lower layer of BL3 (R). The cell C includes a word line WL and two bit lines BL arranged in a different layer. For example, the cell C includes a word line WL<0> and a bit line BLO(W), BLO(R) connected through the bit line contact point BLC^. Fig. 14 is a view showing a cell array structure, a write driving unit W/D, a sense amplifier S/A, and a register REG of the semiconductor memory device of the present invention. The sense amplifier S/A senses and amplifies the cell data to identify the data "Γ and data "0" such that the sense amplifier S/A is connected to each read bit line BL(R). Register REG The data of the sense amplifier S/A is temporarily stored and connected to the read bit line BL(R). The sense amplifier S/A and the register ^ REG are connected to the input/output line IO belonging to the data bus, / When the data is written into the memory element, the write driver W/D is configured to generate a driving voltage in accordance with the write data, thereby supplying the driving voltage to the write bit line BL (W). The read driver W/ D will be connected to the write bit line BL(W). Fig. 15 is a circuit diagram showing the column decoder 140 of the semiconductor memory device of the embodiment of the present invention. The column decoder 1 40 is input according to the column address. Controls the voltage level supplied in word line -25 - 200837930 WL. Column decoder 丨 40 includes column address decoder unit 400, voltage supply unit 410, and word line drive unit 43. Column address decoder unit 400 includes a NAND gate ND1 configured to perform a NAND operation on an input of a column address, thereby outputting an enable message The voltage supply unit 410 includes a plurality of NMOS transistors N 1 to N 3 belonging to the switching elements. The NMOS transistor N1 connected between the first voltage v 1 terminal and the word line driving unit 430 has a gate. The NMOS transistor N2 connected between the second voltage V2 terminal and the word line driving unit 430 has a gate for receiving the voltage control signal V2 - C. The third voltage V3 is connected. The NMOS transistor N3 between the word line driving unit 430 has a gate for receiving the voltage control signal V3_C. The first voltage VI, the second voltage V2, and the third voltage V3 supplied to the word line WL are read. Voltage Vrd, power supply voltage VDD, and negative read voltage -Vrd 〇® As shown in FIG. 8, the read voltage Vrd as the first voltage VI can be supplied to the selected word line WL<0> in the read mode. As shown in Fig. 9, when the data '0' is written, the power supply voltage VDD as the second voltage V2 can be selected as the word line WL<0> as shown in Fig. 10, when the data is written' At 1', the negative read voltage -Vrd as the third voltage V3 can be selected as the word line The WL<0>° word line driving unit 43 0 includes a word line driving element, a pull-down element, and an inverter connected between the voltage supply element 410 and the word line WL. 26-200837930 IV1. Word line WL connection The NMOS body N4 belonging to the word line driving element and the NMOS transistor N5 belonging to the pull-down element. N Μ 0 S The transistor N 5 has a gate for receiving the enable signal 输出 output from the column address decimation unit 400. Inverter IV1 inverts the enable signal to output an enable signal ΕΝ. The NM0S transistor Ν4 has a gate for receiving the enable signal ΕΝ. Fig. 16 is a view showing the operation of the decoder 140 of Fig. 15. ® During the period t0, when the column address is input, the enable signal ΕΝΒ will move to the low level. As a result, the NMOS transistor N5 is kept turned off. The NMOS transistor N4 is turned on. When the voltage control signal V1_C is activated, the NM0S transistor N1 is turned on to supply the first voltage VI to the word WL. During the period t1, the enable signal ENB is maintained at a low level. As a result, the NM0S transistor N5 is kept turned off, and the NM0S transistor 1 is turned on. When the voltage control signal V2_C is activated, the NM0S ^^2 is turned on to supply the second voltage V2 to the word line WL. During the period t2, the enable signal ENB is maintained at a low level. If the N Μ〇 S transistor N 5 is kept off, the N Μ〇 S transistor is turned on. When the voltage control signal V3_C is activated, the NM0S power N3 is turned on to supply the third voltage V3 to the word line WL. After the period t2, when the column address is not input, the enable signal ENB is erased at a high level. As a result, the NM0S transistor N5 is turned on and the ground voltage is applied to the word line WL. The crystal encoder ENB pole, the waveform is turned on, and the force, the line is the junction 1 N4 crystal, the junction N4 crystal is deactivated. • 27- 200837930 Figure 17 is the write drive unit W of Figure 14 of the present invention /D and the circuit diagram of the sense amplifier S/A. The sense amplifier S/A includes a row selection unit 500, an equalization unit 510, a register unit 520, a pull-up unit 530, an amplification unit 540, an amplification start control unit 550, load units 560, 562, and a bias control unit 570. The 572 ° row selection unit 500 includes NMOS transistors N6, N7. An NMOS transistor connected between the input/output line 10, /10 and the output terminal 〇UT, /OUT • Μ6, Ν7 has a common gate for receiving the row selection signal YS. The equalization unit 510 includes a PMOS transistor Ρ1. ~Ρ3. The PMOS transistor Ρ1 is connected between the power supply voltage VDD terminal and the output terminal OUT. The PMOS transistor P3 is connected between the power supply voltage VDD terminal and the output terminal /OUT. The PMOS transistor P2 is connected between the output terminals s〇UT, /〇UT. The PM0S transistors P 1 to P3 have a common gate for receiving the sense amplifier equalization signal SEQ. The register unit 520 includes PMOS transistors P4, P5 and NMOS transistors N8, N9 having a pair of inverter latching architectures. The PMOS transistors P4 and P5 are cross-coupled to the NMOS transistors N8 and N9. In this embodiment, the register unit 520 is used as the register REG. The pull-up unit 530 includes a PMOS transistor P6. The PMOS transistor P6 connected between the two nodes of the sense amplifier has a gate 'for receiving a sense amplifier equalization signal SEQ. The amplification unit 540 includes NMOS transistors N10, Nil. The NMOS transistor N10 connected between the NMOS transistor N8 and the 'N12 has a gate, -28-200837930 to receive the cell voltage Vcell. The NMOS transistor N11 connected between the NMOS transistors N6, N9 has a gate to receive the reference voltage Vref. The amplification start control unit 505 connected between the amplifying unit 540 and the ground voltage terminal has a drain for receiving the sense amplifier enable signal SEN. The load unit 560 includes a PMOS transistor P7. The PMOS transistor P7 connected between the power supply voltage terminal and the bit line BL (R) has a gate for receiving the load voltage Vload. The load unit 562 includes a PMOS transistor P8. The PMOS transistor P8 connected between the power supply voltage terminal and the reference voltage Vref terminal has a gate for receiving the load voltage Vload. The bias control unit 570 includes an NMOS transistor N13. The NMOS transistor N13 connected between the cell voltage Vcell terminal and the bit line BL(R)· has a gate for receiving the clamp voltage VCLMP. The bias control unit 572 includes an NMOS transistor N14. The NMOS transistor N14 0 connected between the reference voltage Vref terminal and the reference current lref terminal has a gate for receiving the clamp voltage VCLMP. The word line drive unit W/D is connected between the output terminal OUT and the write control unit 580. The write control unit 580 includes an NMOS transistor N15. The NMOS transistor N 1 5 connected between the write driving unit W/D and the bit line BL (W) has a gate for receiving the write control signal W C S. Fig. 18 is a waveform diagram of the write drive unit and the sense amplifier S/A of Fig. 17 of the present invention.

If the clamp voltage VCLMP increases, the NMOS transistor N13 turns on to transmit the bit line current Icell of the main cell. If the clamp voltage VCLMP -29-200837930 increases, the NMOS transistor N14 turns on to transmit the reference current Iref. The load cells 560, 562 include PMOS transistors P7, P8 controlled by a load voltage Vload. The load PM of the PM0S transistors P7, P8 converts the current Icell of the bit line BL and the reference current Iref into a cell voltage Vcell and a reference voltage V r e f . The amplification start control unit 550 is controlled by the sense amplifier enable signal SEN. The amplifying unit 5 40 is activated in accordance with the state of the amplification start control unit 505. The amplifying unit 540 amplifies the cell voltage Vcell and the reference voltage Vref with the gain of the NM0S transistors N10, N11. In accordance with the operation of the pull-up unit 530, during pre-charging, the two nodes of the sense amplifier are precharged to a high level to improve the first amplification characteristic of the sense amplifier S/A. The amplified voltage in the amplifying unit 540 is transmitted and stored in the register unit 520. When the sense amplifier enable signal SEN is activated, the register unit 520 stores the write data of the sense amplifier. The register unit 520 exchanges data in response to the row selection signal YS and through the input/output lines 10, /10. The register unit 5 20 amplifies the gain of the amplifying unit 540 to improve the compensation characteristics of the sense amplifier S/A. During pre-charging, equalization unit 510 pre-charges the output signal of register unit 520 to achieve a high level. When the row select signal YS is activated, the NM0S transistors N6, N7 of the row select unit 500 are turned on, thereby selectively connecting the input/output lines 1〇, /1〇 to the output terminal UT, /〇UT. When the write control signal WCS is activated, the write drive unit W/D transfers the input/output line 10, /10 data to the bit line BL (W), or transfers the data stored in the register unit 5 20 To the -30- 200837930 bit line BL (W). Fig. 19 is an explanatory view of a semiconductor memory device of an embodiment of the present invention. In an embodiment, the 1-TFET type ferroelectric memory device includes a left bit memory cell 10 for storing 1 bit and a right bit memory cell 20 for storing 1 bit for cell cells. Store double bits. Hereinafter, the left bit is referred to as 'L-bit' and the right bit is referred to as 'R-bit'. The L-bit storage unit 10 includes a channel area and a ferroelectric layer 4 disposed on the left side portion of the channel region of the unit cell, thereby storing the data 'Γ or '. The R-bit storage unit 20 includes a channel area and a ferroelectric layer 4 disposed on the right side portion of the channel area of the unit cell, thereby storing the material '1' or '0'. When the data stored in the L-bit storage unit 10 is read, the N-type region 2 serves as the source region and the N-type region 3 serves as the drain region. When the data stored in the R-bit storage unit 20 is read, the N-type region 3 serves as the source region and the N-type region 2 serves as the drain region. One of the N-type regions 2, 3 is a drain region and a source region. In the write mode of the memory element, data can be simultaneously written to the L-bit ® storage unit 10 and the R-bit storage unit 20. In the read mode, the data stored in the L-bit storage unit 10 and the R-bit storage unit 20 can be simultaneously read. The L-bit storage unit 1 is configured to set an area in which the polarity of the ferroelectric layer 4 is changed by a voltage applied between the gate region (channel region) and the N-type region 2 as the source region. Become a valid data storage area. The R-bit storage unit 20 sets a region 'in this region' by the voltage applied between the gate region (channel region) and the N-type region 3 as the source region, the ferroelectric layer 4 -31-200837930 The polarity will change to a valid data storage area. The expected data will not be read or written, but invalid data will not be stored that does not affect the read/write operation of the data because the weak channel bias voltage is applied to the L-bit memory unit 10 and R-bit. The area of the storage unit 20. The width of the storage area corresponding to the L-bit storage unit 1 and the R-bit storage unit 20 varies depending on the bias voltage applied to the drain/source regions. Figure 20 is a diagram showing the write operation of the material '00' of the semiconductor memory device according to the embodiment consistent with the present invention. The power supply voltage VDD is applied to the word line 5 to store the data '' in the L-bit storage unit 1'' and the R-bit storage unit 20. Ground voltage is applied to the N-type drain/source regions 2, 3. The negative charge is induced into the channel region depending on the polarity of the ferroelectric layer 4 to write the data '〇〇. Fig. 2 is a diagram showing the writing operation of the material ' 0 1 ' in accordance with the semiconductor memory device of the embodiment consistent with the present invention. A negative read voltage - Vrd to word line 5 is applied to store the data, 〇, in the 1-bit memory cell 10 and the stored data '1' in the R bit memory cell 2 。. The ground voltage GND is applied to the N-type drain/source region 2, and the positive read voltage Vrd is applied to the N-type drain/source region 3. The negative charge is induced in the channel region of the L-bit storage unit 10 depending on the polarity of the ferroelectric layer 4 to write the data '〇. The positive charge is induced in the channel region of the R bit storage unit 20 depending on the polarity of the ferroelectric layer 4 to write the material '1'. Figure 22 is a diagram showing the data read operation of the semiconductor memory element in accordance with an embodiment consistent with the present invention. -32- 200837930 Apply a negative read voltage -Vrd to word line 5 to store data in the L-bit storage unit 10 and store the data in the R-bit storage unit 20. A positive read voltage Vrd is applied to the N-type drain/source region 2, and a ground voltage GND is applied to the N-type drain/source region 3. The positive charge is induced in the channel region of the L-bit storage unit 10 depending on the polarity of the ferroelectric layer 4 to write the data, 1, . The negative charge is induced in the channel region of the R-bit memory cell 20 depending on the polarity of the ferroelectric layer 4 to write the data '〇'. Figure 23 is a diagram showing the write operation of the material '1 1' of the semiconductor memory device in accordance with an embodiment consistent with the present invention. A negative read voltage - Vird to word line 5 is applied to store the data 'in the L bit storage unit 10 and store the data' in the R bit storage unit 20. A positive read voltage Vrd is applied to the N-type drain/source regions 2, 3. The positive charge is induced in the channel region depending on the polarity of the ferroelectric layer 4 to write the data, 11'. Figure 24 is a diagram showing the read operation of the L-bit data of the semiconductor memory device in accordance with an embodiment consistent with the present invention. The read voltage Vrd is applied to the word line 5 to read the data stored in the L-bit memory unit 1 . A ground voltage GND is applied to the N-type drain/source region 2, and a sensing bias voltage Vsen is applied to the N-type drain/source region 3. The cell sensing current flowing in the channel region is sensed to read the data stored in the L-bit storage unit 10. Figure 25 is a diagram showing the read operation of the R bit data of the semiconductor memory device in accordance with an embodiment consistent with the present invention. -33- 200837930 The read voltage Vrd is applied to the word line 5 to read the data stored in the R bit storage unit 20. A sense bias voltage Vsen is applied to the N-type drain/source region 2, and a ground voltage GND is applied to the N-type drain/source region 3. The cell sensing current flowing in the channel region is sensed to read the data stored in the R bit storage unit 20. Figure 26 is a timing diagram of a write cycle of a semiconductor memory device in accordance with an embodiment consistent with the present invention. During t0, the R bit data of ® in all cells of the selected column address is read and amplified and stored in the scratchpad. During tl, the L-bit data in all cells of the selected column address is read and expanded and stored in the scratchpad. During t2, since the data '0' is written in all the cells, it is not clear that the data is stored in the existing memory cells. Therefore, in order to understand the data stored in the existing memory cells, the data '0' is stored in the scratchpad before the data is written into the memory cell. During t2, data '0' is written to all cells I of the selected column address. During 13th, the data stored in the register of the update mode is again written and re-stored in the memory cell, or a new external data is written in the cell. During the period of 12, since the material '05 is written in advance during the 11th period, or the material '1' is written, the material '〇' is retained. Figure 27 is a timing diagram of an update cycle of a semiconductor memory device in accordance with an embodiment consistent with the present invention. During t0, the R bit data in all cells of the selected column address is read and amplified and stored in the scratchpad. During the 11th period, the L-bit data in all the cells of the selected column address of the 34-200837930 is read and placed, and stored in the scratchpad. During t2, an update '0' operation is performed to store L bits or R bit data 'in all cells of the selected column address' (Γ. During t3, an update '1' operation is performed to re Storing L-bit or R-bit data 51' in all cells of the selected column address. Figure 28 is a plan view of a cell array of a semiconductor memory device in accordance with an embodiment consistent with the present invention. The complex digital element line WL is arranged in the column direction. The complex bit line BL is arranged in a manner perpendicular to the complex digital element line WL (in the row direction). Each of the plurality of unit cells C is arranged in The area of the complex digital element line WL where the complex bit line BL intersects. The odd bit line BL<1>, BL<3>, BL.<5>, BL<7>, BL<9> R bits. Even bit lines BL<0>, BL<2>, BL<4>, BL<6>, BL<8> are architectures for storing L bits. Odd bit lines BL<1>, BL<;3>,BL<5>,BL<7>,BL<94 and even bit line BL<0>, BL<2>, BL<4>, BL<6>, BL& Each bit line of lt;8> is alternately arranged in different layers. When one unit cell C is connected to two bit lines BL, the area of the bit line BL can be prevented from increasing. Also, in the odd bit line An even bit line BL<0>, BL<2>, BL<4>, BL<2> is formed in the upper or lower layer of BL<1>, BL<3>, BL<5>, BL<7>, BL<9>;6>,BL<8>. An odd bit line BL<<>> is formed on the upper or lower layer of the even bit line BL<0>, BL<2>, BL<4>, BL<6>, BL<8>1>,BL<3>,BL<5>,BL<7>,BL<9> -35- 200837930 The unit cell C includes a configuration word line WL and two bit lines BL in a different layer. The cell cell V includes a word line WL<0>, an even bit line L-BL<2> connected through the bit line contact portion BLC, and an odd bit line R-BL<3> An illustration of a cell array structure and R bit data read operation of a semiconductor memory device in accordance with an embodiment consistent with the present invention. The complex digital element line WL is arranged at a given interval in the column direction. The complex even/odd bit lines L-BL and R-BL are arranged perpendicular to the complex digital element lines WL (also in the row direction). Each cell of the complex cell C is located in a region in which the complex digital line WL intersects the complex even/odd bit lines L-BL, R-BL. A cell C having a 1-T FET structure is connected to a word line WL < 0 > and an even/odd bit line L - BL < 0 >, R - BL < 1 >. However, the word line WL<0> and the even/odd bit line L-BL<0>, R-BL<1> are merely exemplary in the embodiment consistent with the present invention, and the present invention is still applicable to other bits. Lines WL<1>, WL<2>, and other bit line pairs l_BL<2>, ® R-BL<3>, . The cell C has a drain and a source connected between the pair of bit lines 1-BL<0>, R-BL<1>, and a gate connected to the word line WL<〇>. The pair of bit lines L - B L < 〇 >, r - b l < 1 > disposed in different layers are connected to the sense amplifier S/A, the write driver W/D, and the register reG. That is, each bit line B L is connected one-to-one to the sense amplifier s / A, the write driver W/D, and the register REG. The sense amplifier S/A senses and amplifies the cell data to discriminate the data, 丨, and -36-200837930 data '0', so that the sense amplifier S/A is connected to the pair of bit lines L-BL<>,R-BL<1>. The sense amplifier S/A transmits a reference voltage through a reference voltage terminal ref to generate a reference current. When data is written into the memory cell, the driver W/D architecture is written to generate a driving voltage depending on the write data to supply the driving voltage to the bit line BL. The write driver is connected to the pair of bit lines L-BL<0>, R-BL<1>. The register REG serves as a temporary memory element for storing data of the sense amplifier S/A, wherein the sense amplifier S/A is temporarily connected to the pair of bit lines L-BL<0>, R- BL<1>. In the read mode of the R bit data of the cell array, the read voltage Vrd is applied to the selected word line WL<0>, and the ground voltage GND is applied to the unselected word line WL<1>WL<2>. A sensing bias voltage Vs en for sensing the sensing current of the cell C is applied to a bit line L-BL <0> connected to the cell C. The ground voltage GND is applied to the bit line R-BL<1> connected to the cell C. The cell sensing current Isen flows according to the storage state of the cell data. Therefore, the current flowing in the pair of fe-yuan lines L-BL <0>, R-BL<1> differs depending on the polarity of the ferroelectric layer 4, so that the cells stored in the unit cell C are read. Metadata. That is, when the read voltage Vrd is applied to the word line WL<0>, the sense bias voltage Vsen is applied to the bit line L-BL<0>, and the ground voltage is applied to the bit line--^<1> When the sense amplifier S/A senses the bit line 1 :^<1>, the cell sense current Is en is read to read the R bit data. When the channel region of the memory cell is cut off, the cell sensing current Isen -37 - • 200837930 is sensed so that the material '1 ' stored in the R bit storage unit 20 can be read. On the other hand, when the channel region is turned on, the cell sensing current Isen is sensed, so that the data '〇' stored in the R bit storage unit 20 can be read. FIG. 3 is consistent with the present invention. Illustration of the left bit data read operation of the semiconductor memory device of the embodiment. In the read mode of the L bit data, the read voltage vrd is applied to the selected word line WL<0>, and ground is applied. Voltage GND to the unselected ® word line WL<1>, WL<2>. The ground voltage GND is applied to the line L-BL<0> connected to the cell C. A sensing bias voltage Vsen for sensing the sensing current of the unit cell C is applied to the bit line R-BL<1> connected to the cell cell C. The cell sensing current Isen flows according to the storage state of the cell data. Therefore, the current flowing in the pair of bit lines L-BL<0>, R-BL<1> differs depending on the polarity of the ferroelectric layer 4 in order to read the data stored in the cell C. That is, when the read voltage Vrd is applied to the word line WL<0>, the ground voltage is applied to the bit line L-BL<0>, and the sense bias voltage Vsen is applied to the bit line R-BL<1> When the sense amplifier S/A senses the cell sense current Isen in the bit line L-BL<0>, to read the L bit data. When the channel region of the memory cell is cut off, the sensing cell senses the current Isen, so that the data 5 stored in the L-bit storage unit 10 can be read. On the other hand, when the channel region is turned on, the sensing cell senses the current Isen, so that the data '0' stored in the L-bit storage unit 10 can be read 0-38-.200837930 Figure 31 An illustration of the write operation of the '0000..'' data for a semiconductor memory device in accordance with an embodiment consistent with the present invention. When the data '写入 is written, a power supply voltage VDD greater than the threshold voltage Vc is applied to the selected word line WL<0>, wherein the threshold voltage Vc changes the ferroelectric property' and the ground voltage GND is applied to The selected word line WL<1>, WL<2>. A ground voltage is applied to all of the pair of bit lines L-BL, R-BL connected to cell C. The read voltage Vrd is less than the threshold voltage Vc, and the power supply voltage VDD• is greater than the threshold voltage Vc. The sense bias voltage Vsen is smaller than the read voltage vrd. The ferroelectric material is polarized when the channel region of the memory cell is turned on. Therefore, the data '0 0 0 0...' is written in the memory cell. That is, when the power supply voltage VDD is applied to the word line WL<0>& applying a ground voltage to the pair of bit lines L-BL, R-BL, the channel region is turned on according to the polarization of the ferroelectric layer 4, Make the data '0000..·' can be written into the memory cell. Fig. 3 is a view showing the writing operation of the data "〇1〇1..." of the semiconductor device according to the embodiment consistent with the present invention. When the data '0101' is written, the negative read voltage -Vrd is applied to the selected word line WL<0>, and the ground voltage GND is applied to the unselected word lines WL<1>, WL<2>; A ground voltage is applied to the bit line L-BL connected to the cell cell c. A positive read voltage Vrd is applied to the bit line R-BL connected to the cell. Applying the positive read voltage V rd to the N-type drain/source region 3 of the bit line R-BL, and applying a negative read voltage -Vrd greater than the threshold voltage Vc to the gate, wherein the threshold voltage changes the ferroelectric The polarity of layer 4. Therefore, when the channel area of the -39- ‘200837930 memory cell is cut off, the ferroelectric material is polarized. A voltage less than the threshold voltage V C is applied to the bit line L-BL of the selected column, so that the data in the L-bit storage unit 1 is retained, and the data 'Γ is written into the R-bit storage unit 20. A negative read voltage -Vrd is applied to the word line W L < 0 >, and a ground voltage and a positive read voltage v r d are applied to the pair L - B L, R-BL. According to the polarity of the ferroelectric layer 4, the cut-off channel region allows the material '0101...' to be written into the memory cell. Figure 3 3 is a diagram of a write operation of a semiconductor memory ® component according to an embodiment consistent with the present invention, 1 0 1 0.... When the material '1010' is written, the negative read voltage -Vrd is applied to the selected word line WL<0>, and the ground voltage GND is applied to the unselected word lines WL<1>, WL<2> . A positive read voltage Vrd is applied to the bit line L-BL connected to the cell C, and a ground voltage is applied to the bit line R-BL connected to the cell. Applying the positive read voltage Vrd to the N-type drain/source region 2 of the bit line L-BL, and applying a negative read voltage -Vrd greater than the threshold voltage Vc to the gate, wherein the threshold voltage Vc changes the iron The polarity of the electrical layer 4. Therefore, the ferroelectric material is polarized when the channel region of the memory cell is cut off. A voltage less than the threshold voltage Vc is applied to the bit line R-BL of the selected column such that the data in the R bit storage unit 20 is retained, 0', and the data 'Γ is written into the L bit storage unit 10. A negative read voltage -Vrd is applied to the word line WL<0>, and a positive read voltage Vrd and a ground voltage are applied to the paired L-BL, R-BL. According to the polarity of the ferroelectric layer 4, the cut-off channel region allows the material '1 0 1 0...' to be written into the memory cell. -40 200837930 Figure 34 is a diagram showing the write operation of the material '1111...' of the semiconductor memory device in accordance with an embodiment consistent with the present invention. When the material '1111' is written, a negative read voltage -Vrd is applied to the selected word line WL<0>, and the ground voltage GND is applied to the unselected word lines WL<1>, WL<2> . A ground voltage is applied to all of the pair of bit lines L-BL, R-BL connected to the cell C. Therefore, the ferroelectric material is polarized when the channel region of the memory cell is cut off. A negative read voltage -Vrd is applied to the word line WL<0>, and a positive read voltage Vrd is applied to the pair of L-BL, R-BL. The polarity of the ferroelectric layer 4 is turned off the channel region so that the material '1 1 1 1 ' can be written into the memory cell. Figure 35 is a timing diagram of the read operation of the semiconductor memory device in accordance with an embodiment consistent with the present invention. During t1, the selected word line WL<0> conversion ground level GND is the read voltage level Vrd, and the bit line L-BL converts the ground level GND to the sensing bias voltage Vsen level. Measure R bit data. The sense amplifier S/A senses and amplifies the cell sensing current ^ Isen flowing through the bit line L-BL, and reads and stores the cell data of the bit line R-BL in the register REG. . During t2, the selected word line WL<0> conversion ground level GND is the read voltage level Vrd, and the bit line R-BL converts the ground level GND to the sensing bias voltage Vsen level. Measure L bit data. The sense amplifier S / A senses and amplifies the cell sensing current Isen flowing through the bit line R - B L and reads and stores the cell data of the bit line L-BL in the register REG. 41-200837930 Figure 36 is a timing diagram of a read/update operation of a semiconductor memory device in accordance with an embodiment consistent with the present invention. During t1, the selected word line WL<1> converts the ground level GND to the read voltage level Vrd, and the bit line L-BL converts the ground level GND to the sense bias Vsen level. The sense amplifier S/A senses and amplifies the cell sensing current lsen flowing through the bit line L-BL, and reads and stores the cell data of the bit line R-BL in the register REG. During t2, the selected word line WL<0> conversion ground level GND® is the read voltage level Vrd, and the bit line R-BL conversion ground level GND is the sensing bias voltage Vs en level. The sense amplifier S/A senses and amplifies the cell sensing current I sen flowing through the bit line R-BL of all cells of the selected column, and reads and stores the bit in the register REG Cell data of line L-BL. During t3, the selected word line WL<0> conversion read voltage level Vird is the power supply voltage level VDD, and the pair of bit lines L-BL, R-BL conversion sensing bias level Vsen is Read voltage level Vrd or ground voltage level ® GND. Therefore, the material '〇' can be written to all cells of the selected column. During t4, the selected word line WL<0> conversion power supply voltage level VDD is a negative read voltage level -Vrd, and the pair of bit lines L-BL, R-BL are maintained at a read voltage level. Bit Vrd or ground voltage GND level. The data stored in the REG is rewritten and stored in the memory cell, or the newly applied external data is written. Since the material '0' is written in advance during t1 or t2, the data '0' and the data '1' are maintained during t3. -42- 200837930 Figure 37 is a diagram of a cell array of a semiconductor memory device in accordance with an embodiment consistent with the present invention. ^ The cell array contains complex digital element lines WL arranged in column direction. The complex bit line BL is arranged in a manner perpendicular to the complex digital element line WL (in the row direction). Each cell of the complex cell C is disposed in a region in which the complex digital line WL intersects the complex bit line BL. The odd bit lines BL<1>, BL<3>, BL<5>, BL<7>, BL<9> are architectures for storing R bits. The even bit lines BL<〇>, BL<2>, BL<4>, BL<6>, BL<8> are architectures for storing L bits. The odd-numbered bit lines BL < 1 >, BL < 3 >, BL < 5 > 'BL < 7 >, BL < 9 > and even bit lines BL < 〇 >, BL < 2 > 'BL < 4 >;·,BL<6>,3B<8> are alternately placed in different layers. When one unit cell C is connected to the two bit lines BL, the area of the bit line BL can be prevented from increasing. That is, the even bit lines BL < 0 >, BL < 2 >, BL < 4 >, BL < 6 >, BL < 8 > are based on odd bit lines BL < 1 >BL<3>,BL<5>,BL<7>,BL<9> are formed above or below. Bit lines BL<1>, BL<3>, BL<5>, BL<7>, ^8[<9> are based on even bit lines BL<0>, BL<2>, BL<4> , BL<6>, BL<8> is formed above or below. The cell C is included in a word line WL and two bit lines BL of a different layer configuration. For example, the cell C includes a word line WL<0>, an even bit line L-BL<2> and a odd bit line R-BL<3> connected through the bit 'yuan line contact BLC. Figure 38 is a diagram of a semiconductor memory device in accordance with an embodiment consistent with the present invention. -43- 200837930 Single transistor (1--) field effect transistor (FET) type ferroelectric memory cell includes left n-bit memory cell 10 for storing n-bit, and right n-bit memory cell 20 For storing n bits to store 2η bits in the unit cell (η is a natural number). Thereafter, the left η bit is referred to as 'L - η bit' and the right ^ bit is referred to as 'R - η bit'. The L-n bit memory cell 10 includes a channel region and a cell-based channel region disposed on the left portion of the ferroelectric layer 4 for storing n-bit data. The R-n bit storage unit 20 includes a channel region and a cell region based on the cell to be arranged in the right portion of the ferroelectric layer 4 to store the n-bit data. When reading the data stored in the L - η bit storage unit 1 Ν, the Ν type area 2 serves as the source area, and the Ν type area 3 serves as the drain area. When reading the data stored in the R-n bit storage unit 20, the Ν-type region 3. serves as the source region, and the N-type region 2 serves as the drain region. One of the N-type regions 2, 3 may be a drain region or a source region. In the write mode of the memory cell, data may be simultaneously written into the L_n bit storage unit 10 and the R-n bit storage unit 20. In the read mode, the data stored in the L-n bit storage unit 10 and the R-n bit storage unit 20 cannot be simultaneously read. By applying a voltage between the gate region (channel region) and the N-type region 2 as the source region, the L-n bit memory cell 10 sets an area in which the polarity of the ferroelectric layer 4 is changed as an effective data storage region. The R-n bit storage unit 20 sets an area for changing the polarity of the ferroelectric layer 4 as an effective data storage area by applying a voltage between the gate region (channel region) and the germanium region 3 as the source region. Since a weak channel bias is applied to the area between the Ln bit memory cell 1〇|gf Rn bit cell storage unit 20, the data of the expected -44-200837930 cannot be read and written, and invalid data is generated, which cannot be It affects the read/write operations of the stored data. The width of the storage area corresponding to the L-n bit memory cell 1〇 and the R-n bit memory cell 20 can be varied depending on the bias applied to the drain/source region. Figure 39 is a graphical representation of the write level of the n-bit memory cells of a semiconductor device in accordance with an embodiment consistent with the present invention. A 2n write voltage level is required to store the n-bit data. That is, the write voltage VW0 ' VW1 ,...' VWn is used to store the resource "00..00", "0 0·.01",...,"11.. 0 0","11· . 11". Figure 40 is a graphical representation of the sense current levels of the n-bit memory cells of a semiconductor memory device in accordance with an embodiment consistent with the present invention. The reference reference current Iref(0)~lref(m) is required to sense the n-bit data "00··00", "〇〇··〇1",...,"1 1..00","1 1..1 1". For example, when the data '3' is stored in the memory cell, 8 different sensing voltages are applied to the bit line (or sub-bit line) determined according to the level of the cell data stored in the memory cell. ). ^ The voltage sensed through the bit line is divided into 2n data levels in the main bit line, such as: "111", "110", ..., "001", ,, 000,,. Compare the 2η level with the 2η-1 level and amplify the 2η-1 level. Figure 41 is a graphical representation of the operation of the low profile data of a semiconductor memory device in accordance with an embodiment consistent with the present invention. The power supply voltage VDD is applied to the word line 5 to store data in the L-n bit storage unit 丨〇 and the R-n bit storage unit 20. Apply a ground voltage GND to the N-type drain/source regions 2, 3. A negative charge is applied to the channel region depending on the polarity of the -45-200837930 of the ferroelectric layer 4 to write the data, 0,. Figure 42 is a diagram of a 2n-bit write operation of a semiconductor memory device in accordance with an embodiment consistent with the present invention. A negative read voltage -Vrd to word line 5 is applied to store the n-bit data in the L-n bit cell storage unit 10 and the R-n bit memory unit 20. One of the n write voltages VW1, ..., VWm applies VWn to the Ν-type drain/source regions 2, 3. Figure 43 is a timing diagram of the write cycle operation of a semiconductor memory device in accordance with an embodiment consistent with the present invention. During to, the R-n bit data of all cells of the selected column address is read and amplified and stored in the scratchpad. During tl, the L-n bit data of all cells of the selected column address is read and expanded and stored in the scratchpad. During t2, since the data '〇' is written in all the memory, it is not clear that the data is stored in the existing memory cells. Therefore, in order to understand the data stored in the existing memory cells, the data '〇' is stored in the temporary memory before the data '〇' 0 is written into the memory cells. During 12, the data '〇' is written to all cells of the selected column address. During t3, the data stored in the scratchpad in the update mode is then written and re-stored in the memory cell' and new external data is written into the cell. During t2, since the material '〇' is written in advance during t1 and a new 2n-bit material is written, the material '〇' is retained. Figure 44 is a plan view of a cell array of a semiconductor memory device in accordance with an embodiment consistent with the present invention. -46- 200837930 The cell array contains complex digital element lines WL arranged in column direction. The complex bit line BL is arranged in a manner of vertically complexing digital element lines WL (in the row direction). Each cell of the complex cell η-bit cell C is disposed in a region in which the complex digital element line WL intersects the complex bit line BL. The odd bit lines BL<1>, BL<3>, BL<5>, BL<7>, BL<9> are architectures to store R-n bits. The even bit lines BL<0>, BL<2>, BL<4>, BL<6>, BL<8> are architectures for storing L-n bits. The odd bit lines BL<1>, BL<3>, BL<5>, BL<7>, BL<9> and even bit lines BL<0>, BL<2>, BL<4>, BL <6>, BL <8> are alternately arranged in different layers. When one unit cell C is connected to two bit lines]8L, the area of the bit line BL can be prevented from increasing. That is, the even bit lines BL<0>, BL<2>, BL<4>, BL<6>, BL<8> to odd bit lines BL<1>, BL<3>, BL<5> , BL<7>, BL<9> is formed above or below. The odd bit lines BL < 1 >, BL < 3 >, BL < 5 >, BL < 7 >, BL < 9 > are in even bit lines BL <0>, BL < 2 > Formed above or below the BL<4>, BL<6>, BL<8>. The unit 兀n-bit cell C includes a word line WL and two bit lines BL arranged in different layers. For example, the cell C includes a word line WL<0>, an even bit line L-BL<2> connected through the bit line contact BLC, and an odd bit line R-BL<3>. Figure 45 is a diagram showing the cell array structure and R-n bit data reading operation of the semiconductor memory device in accordance with an embodiment consistent with the present invention.

The complex digital element line W L is arranged in a column direction by a given interval. The complex bit line even/odd bit line L - B L, R - B L are arranged in the manner of the vertical complex digital element line W L -47 - 200837930 (in the row direction). Each cell of the complex cell η-bit cell c is disposed in a region in which the complex digital element line WL intersects the complex even/odd bit line L-BL, R-BL. A single cell C having a 1-T FET structure is formed in a different layer to be connected to the word line WL<0> and the even/odd bit line L-BL<0>, R-BL<1>. Although the word line WL<0> and the even/odd bit line b-BLcO>, R-BLcl> are merely examples of embodiments consistent with the present invention, the present invention can apply other word lines WL<1>, WL<lt;;2>,... and other bit line pairs L-BL<2>, R-BL<3>, . The cell η-bit cell C has a drain and a source connected between the pair of bit lines L-BL<0>, R-BL<1S, and a gate connected to the word line WL<0>; Each row select switch C/S is connected to a pair of bit lines L-BL<0>, R-BL<1> configured in a different layer. That is, each bit line BL is one-to-one configured to the row selection switch C/S' which is connected to the data bus D B . The signal is transmitted between the bit line B L determined by the start of the row selection switch C / S and the data bus DB. When the Rn bit data is read, 'the read voltage Vrd is applied to the selected word line WL<0>, and the ground voltage GND is applied to the unselected word line WL < 1 >, WL < 2 >. A sensing bias voltage v sen for sensing the sense current of the cell n cell C is applied to a bit line L - B L < 0 > connected to the cell n cell cell c. Applying the ground voltage G N D to the bit line R - B L < 1 > ° The cell sensing current Is en flows according to the storage state of the cell data. Therefore, the current flowing in the pair of bit lines L-BL <0>, R-BL<1> differs depending on the polarity of the ferroelectric layer 4, so that the cells 48- stored in the unit cell - are read. 200837930 Information. That is, when the read voltage Vrd is applied to the word line WL<0>, the bit line L-BL<0> is applied, and the ground voltage is applied to the bit line-6 丄<1>, the sense amplifier The S/A system senses the 感 of the cell sensing current flowing in the bit line R-BL<1> to read the Rn bit data. Figure 46 is a diagram showing the cell array structure and L-n bit data reading operation of the semiconductor memory device in accordance with an embodiment consistent with the present invention. When the L-n bit material is read, the read voltage Vrd is applied to the selected word line WL<0>, and the ground voltage GND is applied to the unselected word line WL<1>'WL<2>. The ground voltage GND is applied to the bit line L - B L < 〇 > connected to the n-bit cell C. A sensing bias voltage Vsen for sensing the sensing current of the cell n cell C is applied to the bit line R-BL <1>. The cell sensing current Isen flows according to the storage state of the cell data. Therefore, the current flowing in the pair of bit lines L-BL<0>, R-BL<1> differs depending on the polarity of the ferroelectric layer 4 in order to read the cell data stored in the cell cell c. That is, when the read voltage Vrd is applied to the word line WL<0>, the ground voltage is applied to the bit line L-BL<0>, and the sense bias voltage Vsen is applied to the bit line R-BL<1W#, The sense amplifier s/A senses the cell sense current Isen flowing in the bit line L-BL<0> to read the Ln bit data. Figure 47 is a diagram showing a low-level data write operation of a semiconductor memory device in accordance with an embodiment consistent with the present invention. When the data '0' is written, the power supply voltage VDD greater than the threshold voltage Vc for changing the ferroelectric property is applied to the selected word line WL<0>, and the -49-200837930 is applied to the ground voltage GND to be unselected. The word line WL<1>, WL<2>. The ground voltage is applied to all of the pair of bit lines L-BL, R-BL connected to the n-th bit c of the cell. The read voltage V r d is less than the threshold voltage V c ' and the power supply voltage \^00 is greater than the threshold voltage Vc. The sense bias voltage Vsen is smaller than the read voltage Vrd. The ferroelectric material is polarized when the channel area of §5 is turned on; Therefore, the data '0 0 0 0...' is written in the memory cell. That is, when the power supply voltage VDD is applied to the sub-turn line WL<0>& applying a ground voltage to the pair of bit lines L-BL, ^R-BL, the channel region is turned on according to the polarization of the ferroelectric layer 4. So that the data '0000·.·' can be written into the memory cell. Figure 48 is a graphical representation of a 2n-bit data write operation of a semiconductor memory device in accordance with an embodiment consistent with the present invention. In the write mode of the 2n-bit material, the negative read voltage _Vrd is applied to the selected word line WL<0>, and the ground voltage is applied to the unselected word line WL<1>, WL<2>; The negative read voltage - Vrd has an absolute 値 of the size of the read voltage Vrd $ and is absolutely 値 a voltage 反 with an opposite phase. One of the write voltages VW1 VVWn is applied to the pair of bit lines L-BL, R-BL connected to the cell n-bit cell C. One of the write voltages VW1 VVWn is applied to the N-type drain/source regions 2, 3 of the pair of bit lines L-BL, R-BL to store the desired data. For example, a voltage less than the threshold voltage Vc is applied to the even bit line L-BL such that the material "0" remains in the Ln bit storage unit 10 of the memory cell, and the data "1" is written in the R - η bit storage. Unit 2 0. Figure 49 is a diagram of a current sense amplifier array and reference unit of a semiconductor memory -50-200837930 component in accordance with an embodiment consistent with the present invention. The semiconductor memory device includes an analog processor 400, a digital/analog ratio (D/A) converter 410, a sense amplifier array 500, a digital processor 510, and reference cells REF(0)~REF(n). The write voltage drive unit contains an analog processor 4 〇 〇 with a D / A converter 4 1 0. The data sensing unit includes a sense amplifier array 500, a digital processor 510, and reference cells REF(0)~REF(n). The analog processor 400 outputs an analog signal to the D/A converter 410. The D/A converter 410 converts the analog signal received from the analog processor 400 into a digital signal to generate 2n write (restore) voltages VW0 VVWn into the data bus DB. The sense amplifier array 500 includes a 2n-1 sense amplifier S/A. The complex sense amplifiers S/A compare and amplify the data current 値Idata applied from the data bus DB, which has reference reference applied from the reference cells REF(0) to REF(n) The bit current lref(0)~lref(m). The sense amplifier S/A requires a 2n-1 reference level current lref(0)~lref(m) for sensing the 2n data in the read mode. Therefore, the sense amplifier S/A is connected one-to-one to 2n-1 reference cells REF(0) to REF(n). The digital processor 5 10 outputs a digital signal received from the sense amplifier array 500. Figure 50 is a circuit diagram of the sense amplifier S/A of Figure 49. The sense amplifier S/A includes a precharge unit 501 and an amplification unit 502. The pre-charging unit 501 includes PMOS transistors P9-P11 having a common gate for receiving an equalized signal SEQ. The PMOS transistors P9 and P10 are connected between the power supply voltage terminal VDD and the output terminals OUT and /OUT. The PMOS transistor P1 1 is connected between the output terminals OUT and /OUT. When the SEQ ID NO: 51-200837930 is started, the precharge unit 501 makes the output terminals OUT, /OUT equal. The amplifying unit 502 includes PMOS transistors P12, P13 and NMOS transistors N16 to N19 forming a jumper latch amplifier. The PM0S transistor P12 and the NMOS transistors N16 to N18 are connected in series between the power supply voltage VDD terminal and the ground voltage terminal GND. The PMOS transistor P13 and the NMOS transistors N17 and N19 are connected in series between the power supply voltage VDD terminal and the ground voltage terminal GND. The common gate of the PMOS transistor P12 and the NMOS transistor N16 is connected to the output terminal /OUT. The common gate of the PMOS transistor P13 and the NMOS transistor N17 is connected to the output terminal 0 U T . The NMOS transistors N1 8 and N19 have a common gate to receive the sensed discharge enable signal SEN. The data current Idata output from the sense amplifier S/A is applied to the data bus DB. The reference level current Iref output from the sense amplifier S/A is applied to the reference unit REF. Fig. 5 is a timing chart showing a reading operation of the semiconductor memory device in accordance with an embodiment consistent with the present invention.

During the period t1, the selected word line WL<0> is converted from the ground level GND to the read voltage Vrd level, and the bit line L-BL is converted to the ground level GND as the sensing bias VSen level. To sense Rn bit data. The sense amplifier S/A senses and amplifies the cell sensing current Isen through the bit line L-BL, and reads and stores the cell data of the bit line R-BL in the register REG. During t2, the selected word line WL<0> is converted from the ground level GND to the read voltage Vrd level, and the bit line R-BL is converted to the ground level -52-200837930. GND is the sensing bias voltage Vsen Level to sense Ln bit data. The sensor S/A senses and amplifies the current sensing current through the bit line R-BL, and reads and stores the cell data of the bit line L-BL in the register 〇 52 A timing diagram of a read/update operation of a semiconductor element in accordance with an embodiment consistent with the present invention. During t1, the selected word line WL<0> is converted from the ground level to the read voltage Vrd level, and the bit line L-BL is switched to ground GND to the sense bias Vsen level. The sense amplifier S/A senses and lets the cell of the bit line l_bl in all the cells of the selected column sense Isen, and reads and stores the cell data of the bit line R-BL. In REG. During t2, the selected word line WL<0> is converted from the ground level to the read voltage Vrd level, and the bit line P?BL is converted to the ground GND as the sense bias Vsen level. The sense amplifier S/A senses and passes the cell sense of the bit line R-BL selected in all cells, and reads and stores the cell of the bit line L-BL. The information is in the temporary REG. During t3, the word line WL<0> is switched from the read voltage Vird level to the power supply voltage VDD level, and the bit line L-BL or the bit line R-BL is measured to the bias voltage Vsen level as the read voltage. Vrd or ground voltage GND is therefore accurate, the data '〇' can be written to all cells in the selected column. During t4, the selected word line WL<0> is converted from the power supply voltage level to the negative read voltage-Vrd level, and the bit line L-BL or the bit-sampling Isen REG memory GND level is stored in the current. The GND level of the GND is replaced by the sense bit. VDD : Element Line -53- 200837930 R-BL is maintained at the ground voltage GND level. The data stored in the scratchpad rEG is rewritten and re-stored in the memory cell, or the newly applied external data can be written. Since the data '〇' is written in advance during t3, the data is maintained in the period t4, and the 2n-bit data is written in accordance with the write voltages VW1 to VWn. Figure 5 3 is a diagram of a cell array of semiconductor memory devices in accordance with an embodiment consistent with the present invention. The cell array includes complex digital element lines WL arranged in a column direction. Complex Bits • The element line BL is arranged in a manner perpendicular to the complex digital element line WL (in the row direction). The complex unit cells C are each arranged in a region in which the complex digital element line WL intersects the complex bit line BL. The odd bit lines BL<1>, BL<3>, BL<5>, BL<7>, BL<9> are architectures to store R-bits. The even bit lines BL<0>, BL<2>, BL<4>, BL<6>, BL<8> are architectures for storing L bits. The f-digit BL line BL<1>, BL<3>, BL<5>, BL<7>, BL<9> and even bit line BL<0>, BL<2>, BL<4>, BL<;6>,BL<8> are alternately arranged in different layers. When the cell unit C is connected to the two bit lines B L , the area of the bit line BL is prevented from increasing. That is, even bit lines BL<0>, BL<2>, BL<4>, BL<6>, BL<8> on odd bit lines BL<1>, BL<3>, BL<5>;,BL<7>,BL<9> formed above or below. The odd bit lines BL<1>, BL<3>, BL<5>, BL<7>, BL<9> are based on even bit lines BL<0>, BL<2>, BL<4>, BL<lt;;6>,BL<8> is formed above or below. The unit n-bit cell C includes configuration word lines WL and -54-200837930 two bit lines BL in different layers. For example, the cell cell c includes a word line WL<0>, an even bit line 1^;^<2> and an odd bit line R-BL<3> which are connected through the bit line contact portion BLC. As described above, according to an embodiment consistent with the present invention, a T-FET type ferroelectric memory cell having non-volatile characteristics applied to a DRAM is subjected to an update operation at a given cycle to re-storage the reduced cell data and Improve data retention features without disrupting updated data, even when power is turned off. The 1T-FET type ferroelectric memory cell, which has non-volatile characteristics in DRAM, stores double bits in the cell to reduce the cell area. It is applied to a 1T-FET type ferroelectric memory cell with non-volatile characteristics in DRAM, and stores 2n bits in the cell to reduce the cell area. The 1T-FET type ferroelectric memory cell maintains the time with the data including the time of turning on/off the power source, and does not perform the update operation frequency, thereby reducing power consumption and improving performance. The 1T-FET type of memory cell performs an update operation based on the parameter information stored in the non-volatile register to maintain updated information even when the power source is turned off. The specific embodiments consistent with the present invention are as described above, but are not limited thereto. Various modifications and equivalent embodiments are possible. The invention is not limited to the types of deposition, etch honing, and patterning steps described herein. Moreover, the invention is not limited to the types of various specific semiconductor components. For example, the invention may be embodied in a dynamic random access memory (dram) component or a non-volatile memory component. Other additions, substitutions, and modifications are apparent to those skilled in the art and may be defined by the scope of the claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view showing a semiconductor memory device. Figures 2a and 2b are graphs showing the bit line currents of the read mode of the semiconductor memory device. Figure 3 is a timing diagram of the write cycle operation of the semiconductor memory device. Figure 4 is a timing diagram of the update cycle operation of the semiconductor memory device. Fig. 5 is a view showing a semiconductor memory device of the present invention. ® Fig. 6 is a graph showing the data retention characteristics of the semiconductor memory device of the present invention. Figure 7 is a plan view of a cell array of the semiconductor memory device of the present invention. Fig. 8 is a view showing the cell array structure and read operation of the semiconductor memory device of the present invention. Fig. 9 is a view showing the cell array structure of the semiconductor memory device of the present invention and the data '0' write operation. ® Figure 10 is a representation of the cell array structure of the semiconductor memory device of the present invention and the data '1' write operation. Figure 11 is a timing chart showing the read operation of the semiconductor memory device of the present invention. Fig. 12 is a timing chart showing the writing operation of the semiconductor memory device of the present invention. Fig. 13 is a view showing a cell array of the semiconductor memory device of the present invention. -56- 200837930 Figure 14 is a representation of the cell array structure of the semiconductor memory device of the present invention, the write drive unit, the sense amplifier, and the register. Fig. 15 is a circuit diagram showing a column decoder of the semiconductor memory device of the present invention. Fig. 16 is a waveform diagram showing the operation of the column decoder of Fig. 15 of the present invention. Fig. 17 is a circuit diagram of the write drive unit and the sense amplifier of Fig. 14 of the present invention. ® Fig. 18 is a waveform diagram of the write drive unit and the sense amplifier of Fig. 17 of the present invention. Fig. 19 is an explanatory view of a semiconductor memory device of the present invention. Fig. 20 is an explanatory view showing the writing operation of the material '〇〇' of the semiconductor memory element of the present invention. Fig. 2 is an explanatory view of the writing operation of the material ' 〇 1 ' of the semiconductor memory element of the present invention. Fig. 22 is an explanatory view showing the data '10' writing operation of the semiconductor memory element of the present invention. Fig. 23 is an explanatory view showing the writing operation of the material 'Π' of the semiconductor memory element of the present invention. Fig. 24 is an explanatory view showing a reading operation of the left bit data of the semiconductor device of the present invention. Fig. 25 is an explanatory view showing a reading operation of the right bit data of the semiconductor memory element of the present invention. Figure 26 is a timing diagram of the write cycle of the semiconductor memory device of the present invention -57-200837930. Figure 27 is a timing chart showing the update cycle of the semiconductor memory device of the present invention. Figure 28 is a plan view showing the cell array of the semiconductor memory device of the present invention. Fig. 29 is an explanatory view showing the cell array structure and the R-bit data reading operation of the semiconductor memory device of the present invention. Fig. 30 is a diagram showing the cell array structure of the semiconductor memory device of the present invention and the reading operation of the left bit data. Fig. 31 is an explanatory view showing the writing operation of the '0000···' of the semiconductor memory element of the present invention. Fig. 32 is an explanatory view of the writing operation of the material '0101...' of the semiconductor memory element of the present invention. Fig. 33 is an explanatory view of the writing operation of the '1010...' information of the semiconductor memory element of the present invention. [0001] Fig. 34 is a view showing the semiconductor memory device of the present invention. • An explanatory diagram of the '1111··· ' write operation. Figure 35 is a timing chart showing the read operation of the semiconductor memory device of the present invention. Fig. 3 is a timing chart showing the writing operation of the semiconductor memory device of the present invention. Figure 37 is a diagram showing the cell array of the semiconductor memory device of the present invention. Figure 38 is a representation of the semiconductor memory device of the present invention. -58- 200837930 Figure 39 is an explanatory diagram of the writing level of n-bU memory cells of the semiconductor memory device of the present invention. Figure 40 is an explanatory diagram of the sense current level of the n-bit memory cell of the semiconductor memory device of the present invention. Fig. 4 is an explanatory view showing a low data writing operation of the semiconductor device of the present invention. Fig. 42 is an explanatory view showing a 2n-bit writing operation of the semiconductor memory device of the present invention. Figure 43 is a timing chart showing the write cycle operation of the semiconductor memory device of the present invention. Figure 44 is a plan view of a cell array of the semiconductor memory device of the present invention. Fig. 45 is an explanatory view showing the cell array structure and the right nbit data reading operation of the semiconductor memory device of the present invention. Fig. 46 is an explanatory view showing the cell array structure and the left nbit data reading operation of the semiconductor memory device of the present invention. Fig. 47 is an explanatory view showing a low data writing operation of the semiconductor memory device of the present invention. Figure 48 is a representation of a 2n-bit data write operation of the semiconductor memory device of the present invention. Fig. 49 is a view showing a current sense amplifier array and a reference unit of the semiconductor memory device of the present invention. Fig. 50 is a circuit diagram showing a sense amplifier of Fig. 49 of the present invention. -59- 200837930 Figure 51 is a timing chart showing the read operation of the semiconductor memory device of the present invention. Fig. 5 is a timing chart showing the writing operation of the semiconductor memory device of the present invention. Fig. 53 is a view showing the cell array of the semiconductor device of the present invention. [Main component symbol description]

1 P-type substrate 2 N-type drain region 3 N-type source region 4 Ferroelectric layer 5 word line 6 Buffer insulation layer 10 Left bit memory unit 20 Right bit memory unit 100 Pad array 110 Update control unit 111 Update Controller 112 Update Counter 120 Column Address Register 130 Column Timing Logic 140 Column Decoder 150 Cell Array 160 Read/Write Control Unit 170 Row Decoder - 60 - 200837930

180 190 200 210 220 230 240 250 300 400 410 43 0 500 501 502 510 520 530 540 5 50 . 560 , 562 570 , 572 580 Vrd

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Claims (1)

200837930 X. Patent application scope: 1. A semiconductor memory device comprising: a channel region, a drain region and a source ferroelectric layer formed in a substrate formed above the channel region; and a word line formed on the iron Above the electrical layer, wherein when the gate resistance is caused by the polarity state of the ferroelectric layer, a read voltage is applied to the word line, and one of the drain region and the source region is used, the cell depending on the difference in the state Sensing the current 値 to perform a data read write operation is performed by applying a voltage to the word line, the polar region to change the polarity of the ferroelectric layer. 2. The maximum or minimum voltage of the semiconductor memory cell and the source region of claim 1 of the patent application range is the voltage 读取 of the read voltage of the channel region. 3. When the semiconductor memory element data of the first application of the patent scope is written into the ferroelectric layer, a power supply voltage is applied to the drain region and the source region. 4. When the semiconductor memory element data of the first application of the patent application is written into the ferroelectric layer, a negative read voltage is applied to apply the read voltage to the drain region and the source region. 5. A semiconductor memory device, comprising: a single transistor (1-T) field effect memory cell formed in a substrate, comprising a channel region, a drain region, and a source region ferroelectric layer, formed in the channel Above the district; and the district; The channel region is different from the polarity sensing operation to the polarity of the electrical layer, and the data drain region and the source, wherein the threshold is turned on or off, wherein when the word line is low and the mode is high, State to the word line and crystal (FET) type -64- • 200837930 word line formed above the ferroelectric layer, wherein different channel resistances are determined by channel regions depending on the polarity state of the ferroelectric layer Causing, wherein the ferroelectric element comprises: a complex digital element line arranged in a column direction; and a plurality of bit line lines arranged in a manner perpendicular to the complex digital element lines, wherein the memory cell is connected to the line One of the plurality of bit lines is between adjacent bit lines and is structured to read / ® write data by changing the polarity of the ferroelectric layer, wherein the polarity of the ferroelectric layer depends on the word applied to the word The voltage of the line and the pair of bit lines. 6. The semiconductor memory device of claim 5, wherein the plurality of bit lines comprise alternately configured odd bit lines and even bit lines, wherein the odd bit lines and the temple even number line are respectively 7. The semiconductor memory device of claim 5, wherein the data is applied to the word line and the sensing bias is applied to one of the pair of bit lines. When a ground voltage is applied to another bit line of the pair of bit lines in the memory cell, the current is sensed by the cell flowing in the pair of bit lines. 8. The semiconductor memory device of claim 5, wherein the cell comprises: a sense amplifier configured to amplify data sensed through the plurality of bit lines; and a register, a frame To store the data amplified by the sense amplifier. 65-200837930. The semiconductor memory device of claim 8, wherein the sense amplifier comprises a select unit, and the frame is configured to connect the register to the input. /output line 9 equalization unit, the frame is configured to equalize the register; the pull-up unit, the frame constitutes a complex node that pulls up the register; the amplifying unit, the frame constitutes an amplified cell voltage and a reference voltage; The unit and the frame constitute a control for starting the amplifying unit; the load unit, the frame constituting the cell voltage and the reference voltage; and the bias control unit, the frame forming a current and a reference current for controlling the plurality of bit lines. 10. The semiconductor memory device of claim 8, further comprising a write drive unit, the frame constituting the data stored in the register or the data of the input/output lines to the plurality of bit lines. 11. The semiconductor memory device of claim 5, wherein when low state data is written into the memory cell, a power supply voltage is applied to the word line and a ground voltage is applied to the pair of bit lines. 1 2. The semiconductor memory device of claim 5, wherein when a high state data is written into the memory cell, a negative read voltage is applied to the word line and a positive read voltage is applied to the pair of bits. Yuan line. 1 3 The semiconductor memory device of claim 5, further comprising a column decoder, the frame composition being controlled by the input of the column address to the voltage level supplied to the word line. -66-200837930 14. The semiconductor memory device of claim 13, wherein the column decoder comprises: a column address decoding unit, wherein the frame is configured to be output depending on a column address output enable signal; a voltage supply unit, The frame constitutes a response voltage control signal, and supplies a corresponding voltage to the word line; and the word line driving unit, the frame is configured to respond to the enable signal, and the voltage level of the control word line is controlled depending on the voltage applied to the voltage supply unit Bit. ® 15. A semiconductor memory device having a ferroelectric element, the memory element comprising a transistor (1-Τ) field effect transistor (FET) type memory cell comprising a single channel region, a drain formed in the substrate a region and a source region; a ferroelectric layer formed over the channel region; and a word line formed above the ferroelectric layer, wherein different channel resistances are determined by a channel region depending on a polarity state of the ferroelectric layer Resulting, the complex digital element line is arranged in the column direction; ^ the complex bit line is arranged perpendicular to the complex digital element lines, and the update control unit is configured to perform an update operation with a specific update period to improve the memory a retention characteristic of data stored in a cell, wherein the memory cell is connected between one of the plurality of bit lines and between adjacent bit lines, and the frame composition is read by changing the polarity of the ferroelectric layer The data is fetched/written, wherein the polarity of the ferroelectric layer is dependent on the voltage applied to the word line and the pair of bit lines. The semiconductor memory device of claim 15, wherein the update control signal generating unit comprises: an update status information register, and the frame constitutes a non-volatile parameter information for controlling the update operation and outputs Updating the control signal; updating the control signal generating unit, the frame is configured to respond to the update control signal, outputting the update signal and the update enable signal for performing the update operation; updating the counter, the frame is configured to respond to the update signal, and counting the update period for outputting the meter The address of the address; and the column address register, the frame is configured to respond to the update enable signal, and the count address is selected to output the count address to the column decoder. 1 7 . The semiconductor memory device of claim 15 of the patent application, further comprising a register, the frame constituting the supply update data to the memory cell. 1 8 _ The semiconductor memory device of claim 17 of the patent application, further comprising a line sequential logic device, the frame forming a register in the start update operation. 19. A method of updating a semiconductor memory device having a ferroelectric component, the memory component comprising: ®, complex digital element lines arranged in a column direction; and complex bit lines arranged in a manner perpendicular to the complex digital element lines; And a single transistor (1 - T) field effect transistor (FET) type memory cell, comprising: a channel region, a drain region and a source region formed in the substrate; a ferroelectric layer formed over the channel region; And a word line 'formed above the ferroelectric layer, wherein the polarity state of the ferroelectric layer depends on a pair of bit lines applied to the word line and connected to the memory cell -68--200837930 And changing, the method comprises: causing different channel resistances for the channel region of the 1T-FET type memory cell to read and/or write data; and updating the memory cells stored in the memory cell with a specific update period Information to improve the retention characteristics of the data stored in the memory cell. 20. The method of claim 19, wherein the updating step comprises: reading data stored in the memory cell to store the data in a temporary memory; writing in the memory. And entering the low-level data; and writing the data stored in the temporary memory to the memory cell to maintain the low-level data stored in the memory cell, or writing the high-level data to the memory cell. 2 1. A semiconductor memory device having a ferroelectric element, the memory element comprising a ^1-T FET type memory cell; and a complex even bit line and an odd bit line, perpendicular to the complex digital line Arranging that the even and odd bit lines are alternately arranged, wherein the memory cell is connected between the plurality of even bit lines and one of the plurality of odd bit lines to adjacent even/odd bit lines And forming a data current of the memory cell by sensing the polarity of the ferroelectric layer. The polarity of the ferroelectric layer depends on the voltage of the word line and the pair of even/odd bit lines. Changing, and by storing the polarity of the ferroelectric-69-200837930 layer depending on the complex write voltage applied to the pair of even/odd bit lines applied to the word line, storing 2n-bit data (n is a natural number) ). 22. The semiconductor memory device of claim 21, further comprising a write voltage driving unit configured to supply a plurality of write voltages to the pair of even/odd bit lines; and the data sensing unit 'frame formation A data sense current is applied to the word line and the pair of even/odd bit lines. 23. The semiconductor memory device of claim 21, wherein the write voltage driving unit comprises: an analog processor, the frame constitutes an output analog signal; and a D/A converter, the frame constitutes an output of the analog processor. The signal is a digital signal to output a complex write voltage. 24. The semiconductor memory device of claim 21, wherein the data sensing unit comprises: a sense amplifier array, the frame constitutes a comparison and simplifies a complex reference level current having a data current; ^ a digital processor, the frame constitutes an output The output signal of the sense amplifier array, and the plurality of reference units, each unit frame is configured to generate the plurality of reference level currents. 25. The semiconductor memory device of claim 21, wherein the memory cell comprises: a left n-bit memory cell, the frame constituting storing left n-bit data applied through the even bit lines; and 70- 200837930 Right η-bit storage unit, the frame constitutes the right η-bit data applied by the odd-numbered bit lines. -71-