200837912 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種半導體晶片結構，特別係有關 於一種凸塊指化之晶片結構。 【先前技術】 金屬凸塊，例如金凸塊，是製作於積體電路晶片之 銲墊上，以利對外電性連接，便於應用在後續以玻璃覆 晶（COG，Chip On Glass)與薄膜覆晶封裝（COF，Chip On Film)等半導體產品。而電子訊號是經由位於該積體電 路晶片兩側之凸塊及基板引線傳送至搭配的裝置，例如 液晶顯示器，隨著顯示器所要求的高畫質、高解析度， 晶片所須之凸塊的數量相對增加。此外，其它電子產品 在微小化要求下，積體電路複雜與微小化亦會使得凸塊 間隔縮小。 請參閲第1及2圖所示，一種習知凸塊化晶片結構 100主要包含一晶片主體110以及複數個凸塊12〇與 140。該晶片主體110係具有一主動面ill及一表面保 護層1 1 3，該主動面11 1係形成有複數個接墊丨〗2。其 中該表面保護層11 3係形成於該主動面111並具有複數 個開孔114，其係顯露該些接墊112。請參閱第3圖所 示，該些開孔11 4之尺寸係小於該些接墊11 2之面積， 該些開孔11 4之尺寸係小於1 〇 μιη X ΙΟΟμηι，其中該些 接塾112之寬度約為21μιη至31μπι，長度約為ιι〇μ^η 至140μχη。請參閱第1及2圖所示，該些凸塊12〇係設 200837912 置且犬出於該晶片主體110之該主動面lu上並置於表 面保護層Π3之該些開孔114中，其中需要高密度排列 之該些凸塊120係鄰近該晶片主體11〇之一邊緣115。 請參閱第3圖所示，在以往的半導體製程之凸塊製作技 術中’該些凸塊1 20之底部覆蓋區係大於該些開孔u 4 之尺寸且小於該些接墊i i 2之面積，該些凸塊1 2〇之寬 度係約為15μπι至25μηι ;長度約為100μπι至ΐ3〇μπι。 一凸塊下金屬層130係形成於該表面保護層η3與該些 凸塊1 2 〇之間並連接該些接墊丨丨2，以供該些凸塊1 2 0 之接合。請參閱第2圖所示，該些凸塊1 40係設置於該 晶片主體110之該主動面111並位於該晶片主體n〇之 另一側，通常其排列密度係低於另一相對邊緣i丨5之該 些凸塊1 20之排列密度。當該些凸塊丨2〇的數量被要求 增加，該些凸塊1 20的尺寸係同步被縮小，導致凸塊接 合強度之弱化。 【發明内容】 本發明之主要目的係在於提供一種凸塊指化之晶片 結構，能在不增加晶片尺寸之條件下配置更多的指狀凸 塊’且不影響凸塊接合強度，以滿足凸塊高密度排列之 需求。 本發明的目的及解決其技術問題是採用以下技術方 案來實現的。依據本發明，一種凸塊指化之晶片結構主 要包含一晶片主體以及複數個指狀凸塊。該晶片主體係 具有複數個接墊及一表面保護層，其中該表面保護層係 6 200837912 具有複數個對應於該些接墊之開孔，每一開孔之尺寸係 小於對應接墊之面積，以局部顯露該些接墊。該些指狀 凸塊係突起狀設置於該晶片主體上，每一指狀凸塊係具 有一凸塊體與一延伸部’該些凸塊體之底部覆蓋區域係 位於該些接塾内且大於該些開孔’該些延伸部之底部覆 蓋區域係超出該些接墊之外。 本發明的目的及解決其技術問題還可採用以下技術 措施進一步實現。200837912 IX. DESCRIPTION OF THE INVENTION: FIELD OF THE INVENTION The present invention relates to a semiconductor wafer structure, and more particularly to a bump-directed wafer structure. [Prior Art] Metal bumps, such as gold bumps, are fabricated on pads of integrated circuit wafers for external electrical connection, which is convenient for subsequent application of COG (Chip On Glass) and film flip-chip. Semiconductor products such as COF (Chip On Film). The electronic signal is transmitted to the matching device via the bumps and the substrate leads on both sides of the integrated circuit chip, such as a liquid crystal display. With the high image quality and high resolution required by the display, the bumps of the wafer are required. The number has increased relatively. In addition, under the miniaturization requirements of other electronic products, the complexity and miniaturization of integrated circuits will also reduce the gap between bumps. Referring to Figures 1 and 2, a conventional bumped wafer structure 100 mainly includes a wafer body 110 and a plurality of bumps 12 and 140. The wafer body 110 has an active surface ill and a surface protective layer 113, and the active surface 11 1 is formed with a plurality of pads 丨2. The surface protection layer 113 is formed on the active surface 111 and has a plurality of openings 114 for revealing the pads 112. Referring to FIG. 3, the openings 11 4 are smaller than the area of the pads 11 2 , and the openings 11 4 are less than 1 〇 μιη X ΙΟΟ μηι, wherein the interfaces 112 are The width is about 21 μm to 31 μm, and the length is about ιι〇μ^η to 140 μχη. Referring to FIGS. 1 and 2, the bumps 12 are provided with 200837912 and the dogs are placed on the active surface of the wafer body 110 and placed in the openings 114 of the surface protective layer 3, wherein The bumps 120 of high density are adjacent to one of the edges 115 of the wafer body 11 . Referring to FIG. 3, in the prior art semiconductor manufacturing process, the bottom coverage area of the bumps 1 20 is larger than the size of the openings u 4 and smaller than the area of the pads ii 2 . The width of the bumps 1 2 系 is about 15 μπι to 25 μηι; and the length is about 100 μπι to ΐ3〇μπι. An under bump metal layer 130 is formed between the surface protection layer η3 and the bumps 1 2 并 and connects the pads 2 for bonding the bumps 120. Referring to FIG. 2, the bumps 140 are disposed on the active surface 111 of the wafer body 110 and on the other side of the wafer body n, generally having a lower density than the other opposite edge. The arrangement density of the bumps 1 20 of 丨5. When the number of the bumps 〇2〇 is required to be increased, the sizes of the bumps 126 are reduced in synchronization, resulting in weakening of the bump joint strength. SUMMARY OF THE INVENTION The main object of the present invention is to provide a bump-oriented wafer structure capable of arranging more finger bumps without increasing the size of the wafer and without affecting the bump bonding strength to satisfy the convexity. The need for high density arrangements of blocks. The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. In accordance with the present invention, a bump-oriented wafer structure primarily includes a wafer body and a plurality of finger bumps. The main system of the wafer has a plurality of pads and a surface protection layer, wherein the surface protection layer 6 200837912 has a plurality of openings corresponding to the pads, and the size of each opening is smaller than the area of the corresponding pads. The pads are partially exposed. The finger bumps are disposed on the wafer body, and each of the finger bumps has a bump body and an extension portion. The bottom cover regions of the bump bodies are located in the plurality of contacts. The bottom cover area of the extensions is larger than the openings, and the bottom cover areas of the extensions are beyond the pads. The object of the present invention and solving the technical problems thereof can be further realized by the following technical measures.
在前述的凸塊指化之晶片結構φ iL 傅甲，該些凸塊體與該 些延伸部係可具有一致等高之頂面。 在前述的凸塊指化之晶片結槿& 七 t 宁’該晶片主體係具 有一邊緣，該些指狀凸塊係鄰近於 ^ 、孩邊緣，而該Ab延# 4係可相對於該些凸塊體較為遠 7疋雕讀邊緣。 在前述的凸塊指化之晶片結構 /» ., 宁，該些延伸部之it 伸方向係可與該邊緣互為垂直向。 Till 該些凸塊體與該 在前述的凸塊指化之晶片結構中 些延伸部係可為等寬。 該些延伸部之延 在前述的凸塊指化之晶片結 佔且一 7 中，緣5 甲長度係可不小於該些凸塊體之 在前述的凸塊指化之晶片結構度四二之一」 塊下金屬層（UBM)，其係位於該此，匕δ有一凸 護層之間並連接至該些接塾，其^狀凸塊與該表面保 寸係實質相等於該些凸塊體之凸塊下金屬層之尺 伸部之底部覆蓋區域。 底部覆蓋區域與該些延In the foregoing bump-directed wafer structure φ iL Fu, the bumps and the extensions may have top surfaces of uniform height. In the foregoing bump-directed wafer crucible & 七t 宁', the wafer main system has an edge, the finger-like bumps are adjacent to the ^, child edge, and the Ab extension # 4 system is relative to the Some of the bumps are carved farther away from the edge. In the aforementioned bump-directed wafer structure, the extension direction of the extensions may be perpendicular to the edge. The bumps of the Till and the extensions of the wafer structure indicated by the bumps described above may be of equal width. The extensions are extended in the above-mentioned bump-directed wafer junctions, and the length of the edge 5 is not less than one of the two or two of the aforementioned bump structure of the bumps. The sub-block metal layer (UBM) is located here, and the 匕δ has a convex layer between and connected to the joints, and the ^-shaped bumps and the surface securing system are substantially equal to the bumps. The bottom cover area of the ruler of the metal layer under the bump. Bottom coverage area and the delay
200837912 在前述的凸塊指化之晶片結構中，該些接墊係可為 鋁墊，而該些指狀凸塊係為金凸塊。 在前述的凸塊指化之晶片結構中，可另包含有複數 個凸塊，其係突起狀設置於該晶片主體上且不具有超過 對應接墊之延伸部。 【實施方式】 依據本發明之一具體實施例，揭示一種凸塊指化之 晶片結構。第4圖係為該凸塊指化之晶片結構之截面示 意圖。第5圖係為該凸塊指化之晶片結構之頂面局部示 意圖。第6圖係為該凸塊指化之晶片結構之指狀凸塊頂 面示意圖。第7圖係為該凸塊指化之晶片結構接合至一 基板之截面局部示意圖。 請參閱第4及5圖所示，一種凸塊指化之晶片結構 2 00主要包含一晶片主體210以及複數個指狀凸塊220 或/與240。該晶片主體210係具有一主動面211以及複 數個形成於該主動面211之接墊212。在本實施例中， 該些接墊2 12係可為鋁墊。請參閱第6及7圖所示，該 些接塾212概呈矩形，寬度約為8μπι(微米）至ΐ4μηι(微 米）；長度約為110μπι至140μπι，且該些接墊212之厚 度係不大於1.2μιη。 此外，請參閱第4圖所示，該晶片主體21 〇更具有 一表面保護層2 1 3 (或稱鈍化層），該表面保護層2 1 3係 具有複數個對應於該些接墊2 1 2之開孔2 1 4，以局部_ 露該些接塾212(如第6圖所示）。其中，該些開孔 200837912 之尺寸係為狹長形，其寬度可不大於1 Ομιη，其長度可 不大於 100μπι。每一開孔214之尺寸係小於對應接墊 212之面積，故能局部顯露該些接墊212。通常該表面 保護層213之材質係可為磷矽玻璃、聚醯亞胺（ΡΙ)或苯 醯環丁烯（BCB)等等，通常該表面保護層213之厚度係 不大於3 μπι。 該些指狀凸塊220係突起狀設置於該晶片主體2 1 0 之該主動面211，每一指狀凸塊220係具有一凸塊體221 與一延伸部222，以使該些指狀凸塊220係可設計為平 行配置之長條指狀。其中，該凸塊體221之形狀可如同 習知凸塊之矩形體或其等比例的縮小。請參閱第6及7 圖所示，該些凸塊體221之底部覆蓋區域係位於該些接 塾212内且大於該些開孔214，即不超出對應之接墊 212。其中該些凸塊體221之寬度係不大於ι6μπ1，且長 度約為ΙΟΟμιη至ΐ3〇μιη。在本實施例中，該些指狀凸 塊220係可為金凸塊。此外，儘管在本實施例中，該些 指狀凸塊220係排列在該晶片主體2 i 〇之該主動面2 u 之單一側邊，但是不受局限地，該些指狀凸塊22〇亦可 排列在該晶片主體2 1 〇之該主動面2 11之兩相對側邊或 是四周側邊。 並且’該些延伸部222之底部覆蓋區域係超出該些 接塾21 2之外’以使該些指狀凸塊220為突出指狀，以 增加凸塊有效的接合面積。在本實施例中，該些延伸部 222之延伸長度係可不小於該些凸塊體221之長度四分 200837912 •之一，又以不小於該些凸塊體221之長度二分之一為尤 佳。其中，該些延伸部222之長度係不大於15〇μιη，以 使得該些指狀凸塊220之長度可介於13卟„1至2〇卟… 較佳地，該些延伸部222與該些凸塊體221係可為I 寬，以使該些指狀凸塊220具有整體外形。請參閱附件 所示，其係顯示設有指狀凸塊22〇之晶片結構2〇〇之幾 面實體照片圖，可知上述之該些指狀凸塊22〇係已能具 體實作在一半導體晶片上。 ' # 請再參閱第6圖所示，在本實施例中，該晶片主體 210係可具有一邊緣215，該些指狀凸塊22〇係鄰近於 該邊緣21 5,而該些延伸部222係相對於該些凸塊體a。 車父為遠離該邊緣2 1 5。該些延伸部2 2 2之延伸方向係可 與該邊緣215互為垂直向。因此，該些指狀凸塊22〇可 高密度地平行排列，達到凸塊微間距之功效。 在本實施例中，該晶片結構200係為一顯示器驅動 _ 晶片，該些指狀凸塊220可作為顯示器的高腳數高密度 之輪出端。請再參閱第5圖所示，該晶片結構2〇〇可Ζ 包含有複數個凸塊240，其係突起狀設置於該晶片主體 210上且不具有超過對應接墊之延伸部，其中該些凸塊2杣 之排列岔度係低於該些指狀凸塊220，可作為顯示器的 較低腳數之輸入端。該些凸塊24〇之形狀可與傳統的凸 塊相同，或者是可以與本發明之指狀凸塊22〇相同。 進一步說明該晶片結構200之應用方法，請參閱第 7圖所示，該些指狀凸塊22 0係可接合至一基板31〇之 10 200837912 複數個引線320，其中該些引線320之厚度係約為3，m 至18μπι。較佳地，該些凸塊體221與該些延伸部222 係可具有一致等高之頂面，以利接合該些引線32〇，其 中該凸塊體221與該些延伸部222之高度皆約為10μπι 至25 μπι。在本實施例中’該晶片結構200係可應用在 薄膜覆晶封裝（COF，Chip On Film)，該基板310係可為 一電路薄膜。除此之外，該晶片結構200亦可應用在其 他半導體產品中，例如玻璃覆晶（COG，Chip On Glass) 產品，則該基板3 1 0係可為一玻璃基板，如液晶面板， 該些引線320係可為ITO(氧化錫銦）導線。 具體而言，該晶片結構200可另包含有一凸塊下金 屬層 230(UBM，Under Bump Metallurgy)，其係位於該 些指狀凸塊220與該表面保護層2 1 3之間並連接至該些 接墊212，其中該凸塊下金屬層230之尺寸係實質相等 於該些凸塊體221之底部覆蓋區域與該些延伸部222之 底部覆蓋區域。通常該凸塊下金屬層230係為濺鍍形 成’其材質可為鈦鎢/金（Tiw/Au)、鈦鎢/銅/金 (TiW/Cu/Au)或鈦 /鎳 /金（Ti/Ni/Au)。 因此，本發明之晶片結構200利用該些指狀凸塊220 可更多數量地配置在受限的晶片邊緣長度内，並且不會 影響凸塊接合強度，亦不會有凸塊碰觸導致短路問題， 故能符合先進的凸塊高密度排列之需求。 以上所述，僅是本發明的較佳實施例而已，並非對 本發明作任何形式上的限制，雖然本發明已以較佳實施 200837912 例揭露如上，然而並非用以 仅化热▲丄 限疋本發明，任何熟悉本專 業的技術人員，在不脫離本路 今赞明技術方案範圍内，當可 利用上述揭示的技術内容 w π谷作出些許更動或修飾為等同 變化的等效實施例，但凡是去松缺士政αα & 疋未脫離本發明技術方案的内 容’依據本發明的技術實質對以上實施例所作的任何簡 單修改、等同變化與修飾’例如晶片之輸入端與輸出端 任何-個皆採用此發明的技術，均仍屬於本發明技術方 案的範圍内。 【圖式簡單說明】 第1圖：習知凸塊化晶片結構之截面示意圖。 第2圖：習知凸塊化晶片結構之頂面局部示意圖。 第3圖·習知凸塊化晶片結構之凸塊頂面示意圖。 第4圖：依據本發明之一具體實施例，一種凸塊指化之 晶片結構之截面示意圖。 第5圖：依據本發明之一具體實施例，該凸塊指化之晶 片結構之頂面局部示意圖。 第6圖··依據本發明之一具體實施例，該凸塊指化之晶 片結構之指狀凸塊頂面示意圖。 第7圖··依據本發明之一具體實施例，該凸塊指化之晶 片結構接合至一基板之截面局部示意圖。 附件：依據本發明之一具體實施例，顯示設有指狀凸 塊之晶片結構之截面實體照片圖。 【主要元件符號說明】 100晶片結構 12 200837912 110 晶 片主 體 111 主 動 面 112 接墊 113 表 面保 護層 114 開 孔 115 邊緣 120 凸 塊 130 凸 塊下金屬層 140 凸塊 200 晶 片結 構 210 晶 片主 體 211 主 動 面 212 接墊 213 表 面保 護層 214 開 孔 215 邊緣 220 指 狀凸 塊 221 凸 塊 體 222 延伸部 230 凸 塊下 金屬層 240 凸 塊 310 基板 320 引 線In the above-described bump-directed wafer structure, the pads may be aluminum pads, and the finger bumps are gold bumps. In the above-described bump-directed wafer structure, a plurality of bumps may be further disposed on the wafer body and have no extension beyond the corresponding pads. [Embodiment] According to an embodiment of the present invention, a bump-directed wafer structure is disclosed. Figure 4 is a cross-sectional view of the bump-directed wafer structure. Figure 5 is a top plan view of the bump-directed wafer structure. Figure 6 is a top plan view of the finger bump of the bump-directed wafer structure. Figure 7 is a partial cross-sectional view showing the bump structure of the wafer structure bonded to a substrate. Referring to FIGS. 4 and 5, a bump-directed wafer structure 200 mainly includes a wafer body 210 and a plurality of finger bumps 220 or/and 240. The wafer body 210 has an active surface 211 and a plurality of pads 212 formed on the active surface 211. In this embodiment, the pads 2 12 may be aluminum pads. Referring to FIGS. 6 and 7, the pads 212 are substantially rectangular, having a width of about 8 μm (micrometers) to ΐ4 μm (micrometers); a length of about 110 μm to 140 μm, and the thickness of the pads 212 is not greater than 1.2μιη. In addition, as shown in FIG. 4, the wafer main body 21 〇 further has a surface protective layer 2 1 3 (or a passivation layer) having a plurality of corresponding pads 2 1 . The openings 2 of 2 are partially exposed to the joints 212 (as shown in Fig. 6). The openings 200837912 are elongated and have a width of no more than 1 Ομιη and a length of not more than 100 μm. The size of each opening 214 is smaller than the area of the corresponding pad 212, so that the pads 212 can be partially exposed. Generally, the surface protection layer 213 may be made of phosphor bismuth glass, polyimide, or benzoquinone (BCB). Generally, the surface protection layer 213 has a thickness of not more than 3 μm. The finger bumps 220 are disposed on the active surface 211 of the wafer main body 2 1 0 , and each of the finger bumps 220 has a convex body 221 and an extending portion 222 to make the fingers The bumps 220 can be designed as long fingers in a parallel configuration. Wherein, the shape of the bump body 221 can be like a rectangular body of a conventional bump or its scale reduction. Referring to Figures 6 and 7, the bottom cover regions of the bumps 221 are located in the plurality of contacts 212 and larger than the openings 214, i.e., do not extend beyond the corresponding pads 212. The width of the bumps 221 is not more than ι6μπ1, and the length is about ΙΟΟμιη to ΐ3〇μιη. In this embodiment, the finger bumps 220 may be gold bumps. In addition, although in the present embodiment, the finger bumps 220 are arranged on a single side of the active surface 2 u of the wafer body 2 i , but not limited thereto, the finger bumps 22〇 It may also be arranged on the opposite side or the peripheral side of the active surface 2 11 of the wafer main body 2 1 . And the bottom cover area of the extension portions 222 is beyond the plurality of contacts 21 2 to make the finger bumps 220 be protruding fingers to increase the effective bonding area of the bumps. In this embodiment, the extension lengths of the extension portions 222 are not less than one of the lengths of the plurality of protrusions 221, 200837912, and are not less than one-half of the length of the plurality of the protrusions 221. good. The length of the extending portions 222 is not more than 15 μm, so that the lengths of the finger bumps 220 may be between 13 卟 1 and 2 〇卟... Preferably, the extending portions 222 and the The bumps 221 may be I wide so that the finger bumps 220 have an overall shape. Please refer to the attached drawings, which show the surface of the wafer structure 2 with the finger bumps 22〇. For the physical photo, it can be seen that the above-mentioned finger bumps 22 can be embodied on a semiconductor wafer. ' # Please refer to FIG. 6 again. In this embodiment, the wafer body 210 can be There is an edge 215, the finger bumps 22 are adjacent to the edge 21 5, and the extensions 222 are relative to the bumps a. The vehicle is away from the edge 2 1 5 . The extending direction of the portion 2 2 2 can be perpendicular to the edge 215. Therefore, the finger bumps 22 can be arranged in parallel at a high density to achieve the effect of the bump fine pitch. In this embodiment, The wafer structure 200 is a display driving_chip, and the finger bumps 220 can be used as a high-density wheel of the display. Referring to FIG. 5 again, the wafer structure 2 includes a plurality of bumps 240 disposed on the wafer body 210 and having no extension beyond the corresponding pads. The arrangement of the bumps 2 is lower than the finger bumps 220, and can be used as the input of the lower number of pins of the display. The shapes of the bumps 24 can be the same as the conventional bumps, or It can be the same as the finger bump 22 of the present invention. Further, the application method of the wafer structure 200 is further described. Referring to FIG. 7, the finger bumps 22 can be bonded to a substrate 31. A plurality of leads 320, wherein the leads 320 have a thickness of about 3, 18 to 18 μm. Preferably, the bumps 221 and the extensions 222 have uniform top surfaces for bonding. The lead 32 〇, wherein the height of the bump 221 and the extending portions 222 are both about 10 μm to 25 μm. In the embodiment, the wafer structure 200 can be applied to a film flip chip package (COF, Chip). On Film), the substrate 310 can be a circuit film. The wafer structure 200 can also be applied to other semiconductor products, such as a COG (Chip On Glass) product. The substrate 310 can be a glass substrate, such as a liquid crystal panel. The leads 320 can be ITO. In particular, the wafer structure 200 may further include an under bump metallization layer 230 (UBM), which is located on the finger bumps 220 and the surface protection layer 2 1 . The pads are connected to the pads 212. The under bump metal layers 230 are substantially equal in size to the bottom cover regions of the bumps 221 and the bottom cover regions of the extensions 222. Usually, the under bump metal layer 230 is formed by sputtering. The material may be titanium tungsten/gold (Tiw/Au), titanium tungsten/copper/gold (TiW/Cu/Au) or titanium/nickel/gold (Ti/ Ni/Au). Therefore, the wafer structure 200 of the present invention can be disposed in a limited number of the length of the edge of the wafer by using the finger bumps 220, and does not affect the bonding strength of the bumps, and does not cause bumps to cause short circuits. The problem is that it can meet the requirements of advanced bump high-density alignment. The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention in any way. Although the present invention has been disclosed above in the preferred embodiment of 200837912, it is not intended to be used only to heat up the present invention. Inventors, any person skilled in the art, without departing from the scope of the present invention, may use the above-disclosed technical content w π valley to make some modifications or modifications to equivalent embodiments, but The content of the above embodiments is any simple modification, equivalent change and modification of the above embodiments, such as any input and output of the chip. The techniques of the present invention are all within the scope of the technical solutions of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view showing a conventional bumped wafer structure. Figure 2: A top partial view of a conventional bumped wafer structure. Fig. 3 is a schematic view showing the top surface of a bump of a conventional bumped wafer structure. Figure 4 is a cross-sectional view showing a bump structure of a wafer structure in accordance with an embodiment of the present invention. Figure 5 is a partial top plan view of the bump-directed wafer structure in accordance with an embodiment of the present invention. Fig. 6 is a top plan view of the finger bump of the bump-directed wafer structure in accordance with an embodiment of the present invention. Figure 7 is a partial cross-sectional view of a bump-indicated wafer structure bonded to a substrate in accordance with an embodiment of the present invention. Attachment: In accordance with an embodiment of the present invention, a photograph of a cross-sectional entity of a wafer structure having finger bumps is shown. [Main component symbol description] 100 wafer structure 12 200837912 110 wafer body 111 active surface 112 pad 113 surface protection layer 114 opening 115 edge 120 bump 130 under bump metal layer 140 bump 200 wafer structure 210 wafer body 211 active surface 212 pad 213 surface protection layer 214 opening 215 edge 220 finger bump 221 bump body 222 extension 230 bump under metal layer 240 bump 310 substrate 320 lead
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