TW200836487A - I/O circuit - Google Patents

Abstract

The I/O circuit 1 is provided with a first NMOS driver 10 having a drain connected to a pad, a second NMOS driver 11 arranged in an active area which differs from the first NMOS driver 10 and having a drain connected to a source of the first NMOS driver 10 and a source connected to a ground potential, a level converter converting a level of an internal power source potential to a level of a power source potential, and a first NMOS transistor 26 having a drain connected to one output terminal of the level converter, a source connected to a ground potential, and a gate connected to another output of the level converter, and wherein the drain of the first NMOS transistor is connected to the gate of the second NMOS 11.

Description

</ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> <RTIgt; This is incorporated herein by reference. I: TECHNICAL FIELD OF THE INVENTION FIELD OF THE INVENTION The present disclosure relates to an input/output circuit in which a driver circuit separates a circuit voltage from an ESD protection circuit. 10 t Prior Art J Related Art Description 15 According to one of the "ECNMOS Output Buffer for Maximum Vtl" by James W. Miller, Michael G. Khazhinsky and James C. Weldon, 22nd EOS/ESD Symposium Paper, p.308 -317, It is known that if one of the first NMOS driver 10 and one of the second NMOS driver 11 are connected in series as shown in Fig. 5, an ESD collapse voltage is boosted. In addition, as shown in FIG. 6, the research on the ESD voltage is completed with respect to a driver circuit 21 in which one gate of a first NMOS driver 1〇 and a gate of a second NMOS driver 11 are connected. Up to a ground potential vss, and a gate of a second NMOS driver 11 is connected to an input/output (vq) pad, and a driver circuit 203, a gate of a first NMOS driver 1 is connected to a gate An I/O pad, and a gate of a second NMOS driver 11 is connected to a ground potential VSS, and a driver circuit 204, wherein the first 5 200836487 • NM〇S includes a gate and a gate of the body 10 Both of the _ gates of the second NMOS driver 11 are connected to an I/O pad. f

Figure 7 shows the results of a study on the ESD withstand voltages of the driver circuits 2〇1 to 2〇4. The graph shows the arrival points of the various characteristics of the circuits indicating the ESD breakdown voltage of the circuits, respectively. Crash current. When the driver circuit 202 and the driver 2〇4 collapse at nearly 82 V, the driver circuit 201 and the driver circuit 2〇3 maintain a tolerance against ESD collapse up to approximately 16V. At the common point between the driver circuit 201 and the driver circuit 2〇3, the gate of the first NMOS driver π is connected to the ground potential vss. Thus, it is clear that the ESD breakdown voltage is boosted to the ground potential by connecting the gate of the second NMOS driver 11 whose source is connected to the ground potential VSS side, The driver circuit of the series structure of "ECNM〇S 〇utput Buffer for Maximum Vtl". Figure 8 15 shows a conventional 1/0 circuit in which a capacitor 25 is placed between a gate terminal C of the second NMOS driver 11 and the ground potential, and the gate terminal C of the second NMOS driver 11 is held at The ground potential. Further, another related art is disclosed in the Japanese Japanese translation of PCT International Patent Publication No. 2003-510827. 20 SUMMARY OF THE INVENTION In accordance with an aspect of an embodiment of the present invention, an input/output (I/O) circuit is provided that includes: a first NMOS driver having a connection to an input/output pad a second NM0S driver, which is 6 200836487, j; in the active area of the NMOS driver, the second NM0S driver | Gu ^ /, has a source connected to the source of the first NM0S driver a pole and a source connected to a ground potential; a 10 (four) converter having a flash lock structure, the level converter being adapted to receive a first drive that is driven at a - power supply potential = internal power supply potential a control signal and a complementary two control signal, and converting the first control signal and the complementary/control signal to be in phase with the first control signal and being driven at the power supply potential a second control signal and a pseudo-number complementary to the first control signal; and a first NMOS transistor having a pole connected to an output of the level converter, the second control signal being outputted from the The output of the level converter a source connected to a ground potential and a gate connected to an output of the signal of the second control signal complementary to the second control signal; wherein the second pole of the crystal is connected to the second NM0S A gate of the driver. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram showing a 1/〇 circuit structure according to the present embodiment; FIG. 2 is a view showing an ESD test voltage applied to a 1/0 pad. Cross-sectional view of the PMOSESD protection element; 20 Figure 3 is a cross-sectional view showing the structure of the ESD protection element; Figure 4 is a characteristic diagram showing the ι_ν characteristic of the ESD protection element; Figure 5 is a A layout of a structure of a NMOS driver in a series configuration; FIG. 6 is a circuit diagram showing a connection 7 200836487 of a driver circuit having a different structure; and FIG. 7 is a view showing the ESD of the driver circuits having different structures. A characteristic diagram of the voltage characteristics of f; and Fig. 8 is a circuit diagram showing the structure of a conventional 1/〇 circuit. 5 [Implementation of the cold type] The detailed description of the preferred embodiment maintains the gate of the second _ still driving HU at the ground potential, and requires the use of a capacitor having a large capacitance value, and the use of a capacitor having a large capacitance value. A problem is that the layout surface is increased. If the signal level of the gate 10 is at the extreme, when the second NMOS driver becomes conductive, and is transferred from a ground potential to an "H" level, the capacitor needs to be charged. This transfer time becomes longer. Similarly, a problem occurs in that when the capacitor is used and charged via a PMOS transistor 17, the potential at the gate terminal of the second NMOS driver 11 increases. 15 provides a germanium circuit comprising NMOS drivers connected in series, wherein the NMOS drivers on the ground side have a small area, and the transition time of starting the NMOS drivers on the ground side is short, and at the place The gate voltages of the NMOS drivers on the side are more reliably set to the ground potential. An embodiment of the 20-1/0 circuit will be described in detail below with reference to Figs. 1 through 4.

Fig. 1 is a circuit diagram showing the structure of a circuit pack according to the present embodiment. The I/O circuit 1 is provided with a first NMOS driver 10 and a second NMOS driver 11, and the first NMOS driver 1 is arranged with the second NMOS 8 200836487 \1 • 5 driver 11 to divide an active region. In the meantime, as shown in Fig. 5, these drivers are surrounded by a guard ring 34 (a well plug of the back gate), a source of the first NMOS driver 10 and a glimpse of the second nmQS driver. The poles are connected to each other in a wiring layer. As illustrated, the first NMOS driver 1 and the second NMOS driver 11 are each surrounded by a protective layer 34 that reduces electrical interference through a body layer, thereby making it possible to further increase the esd. Resistance to voltage. Returning to Fig. 1, the I/O circuit 1 is provided with an NMOS transistor 12 having a gate connected to the VSS and a germanide block 13 connected in series with the NMOS transistor 12, Act as an ESD protection circuit. The I/O circuit 1 is also provided with a PMOS transistor 14 having a gate connected to an external power source VDE, and a PMOS transistor 15 forming an inverter together with the first NMOS driver 10 as a ESD protection circuit. The inverter constituted by the PMOS transistor 15 and the first NMOS driver 10 is driven by a signal output from an internal circuit 16. In addition, the I/O circuit 1 is also provided with a pM〇S transistor 17' having a source connected to an external power supply VDE and a pM〇S transistor 17' connected to another inverted output terminal xq, having a connection to the ground potential VSS. a source, a drain connected to the PMOS transistor 17 and an NMOS transistor 18 acting as a gate of the inverting input terminal XA, having a source connected to the external power supply VDE and a PMOS transistor 19 connected to the gate of an input terminal Q, and a drain having a source connected to the ground potential VSS, a drain connected to the PMOS transistor 19, and a The NMOS of the input terminal a is NMOS electric 200836487, j crystal 20. The PMOS transistor 17, the NMOS transistor ι8, the pm〇S transistor 19, and the NMOS transistor 2 are used as a signal level suitable for converting a signal level of an internal power source VDI to the external power source VDE. Level converter. Similarly, the I/O circuit 1 includes a gate having a connection to an inverting input terminal XQ, a gate connected to an input terminal Q, and a source connected to the ground potential VSS. NMOS transistor 26. The output of the level shifter terminal Q is connected to the gate terminal c of the second NMOS driver 11. The I/O circuit 1 is further provided with a PMOS transistor 21 and an NMOS transistor 22 constituting an inverter driven by the internal power supply VDI, and a composition 10 is driven by the internal power supply VDI. A pm 〇 transistor 23 of the phaser and an NMOS transistor 24. The PM s s transistor 23 constituting the inverter and the NMOS transistor 24 receive a control signal CNT that controls the gate terminal C of the second NMOS driver 11. When the ESD of the positive electrode 'to the I/O pad 32 is destroyed, the VSS is set to a base VSS, and a voltage is also from a parasitic diode 14Di, via a drain of the PMOS transistor 14. The 14D and the I/O pad 32, and a back gate 14BG of the PMOS transistor 14 and the parasitic diode 141) are applied to the external power source. The output of the inverter 20 composed of the PMOS transistor 21 and the NMOS transistor 22 and the output of the inverter composed of the PMOS transistor 23 and the NMOS transistor 24 are discharged in a parasitic capacitance. And, therefore, the outputs are a ground potential. Thus, both the input terminal A of the level shifter and the inverting input terminal XA receive a ground potential. In this level conversion, the output terminal q and the inverting 10 200836487 output terminal XQ are in a local % position before an ESD test voltage is applied. However, when a voltage is applied for an ESD test, The PMOS transistor 17 and the PMOS transistor 19 become conductive and the equipotential at the output terminal Q and the inverting output terminal XQ is boosted. If the potential of the inverting output terminal XQ exceeds a threshold voltage of the NMOS transistor 26, the NMOS transistor 26 is turned on. When the NM〇s. transistor 26 is turned on, the signal terminal of the output terminal Q and the gate terminal c becomes a ground potential. As a result, the PMOS transistor 19 becomes fully turned on, and the level of the inverted output terminal XQ shifts to an "H" level. As a result, the * pmos transistor becomes non-conductive, and the inverted output terminal is maintained at the 10 - Η level, and the output terminal Q is maintained at a ground potential state (latch operation). Next, an explanation will be given to the edge-side ESD protection circuit in which the lithochemical block 13 and the NMOS transistor 12 are connected in series from the ι/q塾μ. Figure 3 is a cross-sectional view showing the structure of the ESD protection element. Since the IGBT of the NMOS transistor 12 connected to the 1/0 pad 32 passes through the lithium block 13, the NMOS transistor 12 is connected to the I/O pad 32 by a main system. The drain 12D (n+) of the NMOS transistor 12, the body (p-) of the NMOS transistor 12, and the source of the NMOS transistor 12 constitute a parasitic npn transistor and a crystal 12TR. The parasitic NPN transistor 12TR does not become ^20 conductive at a low voltage, however, when the potential of the 1/0 pad 32 reaches approximately 9V due to a leakage current, it becomes conductive. In FIG. 4, which is a characteristic diagram showing the characteristics of the ESD protection circuit, if the parasitic NPN transistor 12TR is turned on once, the transistor is snapped back and the voltage drops to a holding voltage (about 6V). ), thus allowing a large current corresponding to the voltage to be subsequently boosted. With 11 200836487 • Record, according to the ESD voltage standard of the job _ type, if the current up to 3.0A (shown by the dotted line) can fly, the anti-voltage can be expected to become equal to or higher than 200V . In the I/O circuit according to the present embodiment, since the gate terminal C' of the second switch s driver 5 is held in a position by the lock operation, the first NM0S is used. The driver circuit formed by the driver 10 and the NMOS driver 11 has an -ESD voltage equal to or higher than approximately 9V, and the ESD voltage can be maintained by the first NMOS driver H) and the first: The NMOS driver 1 is configured to electrically connect the series-connected driver until the parasitic chip 12tr of the ESD protection circuit becomes conductive. In the I/O circuit 1 of the present embodiment, the position of the gate terminal C of the second NM 〇s driver is maintained, and no _ capacitor is required. Since a capacitor is not used, the entire layout of the I/O circuit 1 can be made more compact than the conventional circuit using a capacitor. 15 Because the conventional 1/0 circuit uses a capacitor 25 of a large capacitance, the φ is a transition time from the ground potential to an H” level, even when the internal power supply VDI is connected to the gate terminal c. In the case of being controlled, it is slow. However, since the I/O circuit of the present embodiment does not use a capacitor, the transfer operation from -ground potential to an "H" level can be quickly completed.

^ 20 In this conventional 1/0 circuit 1, a capacitor 25 is used to maintain the gate terminal C at a ground potential. Thus, a problem occurs in that the capacitor is charged to the crystal via the PMOS transistor 17 which causes the potential to increase. On the contrary, in the I/O circuit 1 of the present embodiment, the ground potential is maintained via the latch operation, which eliminates the risk of the potential at the gate terminal C rising. 12 200836487 The present disclosure is not limited to the above embodiments, and it is needless to say that different modifications and changes can be made without departing from the scope of the disclosure. For example, although the embodiment of the present embodiment in which the output of the first NMOS driver 1 having a phase structure is an inverter is given, the majority of the first NMOS driver is the same. The drives can be connected in series. For example, if the output driver has a NAND structure, a transistor having the same structure as the first NMOS driver can be connected in series in one stage. In this embodiment, the input terminal A and the inverting input terminal xa are controlled via 10 of the two inverters, one is composed of the PMOS transistor 21 and the NMOS transistor 22, and the other is composed of The PMOS transistor 23 is formed with the NMOS transistor 24. The PMOS transistor 21 and the NMOS transistor 22 can be removed so that the input terminal a can be directly controlled by an unillustrated control signal. The NMOS transistor 26 is taken as an example of a first NMOS transistor. The NMOS transistor 12 is an example of a second NMOS transistor. The PMOS transistor 14 is regarded as a first PMOS transistor. The example 'and the PMOS transistor 15 serves as an example of a second PMOS transistor. Similarly, the PMOS transistor is regarded as an example of a third pMOS transistor, and the 5 PMOS transistor 19 is taken as an example of a fourth transistor, and the NMOS transistor 18 is regarded as a third. An example of an NMOS transistor, and the NMOS transistor 2 is taken as an example of a fourth nm 〇S transistor. In addition, the PMOS transistor 21 and the NMOS transistor 22 are regarded as an example of a first inverter, and the PMOS transistor 23 and the NMOS transistor 13 200836487 谚5 body 24 are regarded as a second inverter. An example of this. In the present embodiment, when the ESD is applied to a pad, the output of the one-bit converter is set to a midpoint potential. As a result, the first NMOS transistor system is turned on, and the gate of the second NMOS driver is set to a ground potential. Thus, it is possible to prevent the collapse caused by the application of ESD to the pads of the first NMOS driver and the second NMOS driver. According to the present disclosure, it is possible to provide an I/O circuit including a NMOS driver connected in series, wherein the driver on the ground side has an area on the side to the NMOS An active 10 sad transition time of the driver is short, and the gate voltages of the NMOS drivers on the ground side are reliably maintained at a ground potential. [Circular Simple Description] Fig. 1 is a circuit diagram showing a 1/〇 circuit structure according to the present embodiment; 15 2 2 shows that an ESD test voltage is applied to an I/. A cross-sectional view of the PM0SESD protection element in the case of the case; Fig. 3 is a cross-sectional view showing the structure of the ESD protection element; - 20 Fig. 4 is a characteristic diagram showing the characteristics of the w of the brain protection element; Figure 5 is a layout diagram showing a structure of a Ν_driver in a-series structure; Figure 6 is a circuit diagram showing a driver circuit having a different structure; Figure 7 - shows that the structures have different structures A characteristic diagram for driving the ESD financial voltage characteristics; & 14 of the book path 200836487 Fig. 8 is a circuit diagram showing the structure of a conventional I/O circuit [Major component symbol description] 1...M) Circuit 24... NMOS Transistor 10...first NMOS driver 25...capacitor 11...second NMOS driver 26...NMOS transistor 12...NMOS transistor 31...VDE pass...汲32...I/O pad 33...VSS 12TR...Parasitic NPN transistor 34...Guard ring 13... Telluride block 100&quot; Conventional I/O circuit 14... PMOS transistor 201-204... Driver circuit 14D···极极C···gate extreme 14Di...parasitic diode A, Q...input 14BG···back gate XQ...inverting output 15...PMOS Crystal XA... Inverting input terminal 16... Internal circuit VSS... Ground potential 17... PMOS transistor VDE... External power supply 18... NMOS transistor VDI... Internal power supply 19... PMOS transistor CNT...control signal 20... NMOS transistor 23...PMOS transistor 15

Claims (1)

200836487 X. Patent application scope: 1. An input/round circuit comprising: an input/output NM〇S driver having a drain connected to the pad; a first NMOS driver arranged in a different_ In the active region of the first NMOS driver, the second nm 〇s driver has a 10 15 is connected to the drain of the source of the first wake-up os driver and - the source connected to a ground potential; a level-switch having a - off structure, the level converter is adapted to receive in-and a first control signal driven by the internal power supply potential separated by the power supply potential and a signal complementary to the first control signal, and converting the first control signal and the signal complementary to the first control signal into a first control signal that is in phase and driven at the power supply potential and a signal complementary to the second control signal; and φ a first NMOS transistor having a connection to the level a drain of an output of the converter, the second control signal being output from the output of the level converter, a source connected to a ground potential, and a connection to the level converter a dummy complementary to an output of the signal of the second control signal; wherein a drain of the first NMOS transistor is coupled to a gate of the second NMOS driver. 2. The input/output circuit of claim 1, further comprising an ESD protection circuit disposed between the input/output pad and the ground potential. 3. The input/output circuit of claim 2, wherein the ESD protection circuit is formed by a germanide block connected in series and a second NMOS transistor. The input/output circuit of claim 1, further comprising a first PMOS transistor having a drain connected to an input/output pad and a source connected to the power supply potential. The input/output circuit of claim 1, further comprising: a second PMOS transistor having a drain connected to the input/output pad and connected to the power source a source of potential and a gate connected to a gate of the first NMOS driver, and wherein the first NMOS driver is formed by an NMOS transistor. 6. The input/output circuit of claim 1, wherein a layout of the first NMOS driver and a layout of the second NMOS driver are surrounded by a guard ring of a back gate. . The input/output circuit of claim 1, wherein the level converter further comprises: a third NMOS transistor having an output connected to the second control signal a drain, a source connected to a ground potential, and a gate connected to an input of the first NMOS driver complementary to the signal of the first control signal; - a fourth NMOS transistor, And having a drain connected to the output of the signal complementary to the second control signal, a source connected to the ground, and a first connected to the first NM〇s driver: 17 200836487, a gate of an input terminal of the signal; a third PMOS transistor having a drain connected to an output terminal of the second control signal, a source connected to the power supply potential, and a connection a gate to an output terminal 5 complementary to the signal of the second control signal; and a fourth PMOS transistor having an output connected to a signal complementary to the signal of the 'second control signal a source connected to the power supply potential, And a gate connected to an output of the second control signal. The input/output circuit of claim 1, further comprising: a first inverter driven at the internal power supply potential, the first inverter having a connection to the level An output of an input of the first control signal in the converter; and a second inverter driven at the internal power supply potential, the second 15 inverter having a connection to the level converter An input complementary to an input of the signal of the first control φ signal and an input of the input of the first inverter. 18