TW200834849A - Land GRID array package - Google Patents

Abstract

A LGA (Land Grid Array) package mainly comprises a substrate, a chip, a soldering layer and a foot cover. The chip is disposed on an upper surface of the substrate and electrically connected to a plurality of metal pads on a lower surface of the substrate. The soldering layer is formed on the metal pads and has a first thickness protruding from the lower surface of the substrate. The foot cover is disposed on the substrate and has a second thickness protruding from the lower surface of the substrate. Therein, the second thickness is greater than the first thickness. Accordingly, the soldering layer will be free from scrape damage during transportation and storage and the LGA package can be mounted on a wiring board by SMT method so that the LGA package can extend its application to more products.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit package structure, and more particularly to a Land GHd Array package (LGA). [Prior Art]

According to the conventional planar grid array package structure, the bottom surface of the product is provided with a plurality of arrays of metal $ for external electrical connection. At present, the external electrical connection manner of the planar grid array package is a metal needle probe contact. The circuit board for bonding the planar grid array package structure must be provided with a cap-fixed socket, and the metal pins are arranged in the cover. In the seat of the seat, the "3" position and the crimping of the conventional thumb array package H. Please refer to Figure 1, the conventional planar grid array package structure: main body: including - substrate U0 and a wafer 12 . The substrate 11 has an upper surface 111 and a lower surface! 12 and a plurality of arrays of metal 塾u Feng 蛩 113 disposed on the lower surface 112. The wafer 12 is disposed on the upper surface 111 of the substrate 110 and can be electrically connected to the substrate 110 by a plurality of bumps i. The planar grid array package structure 1 further includes a glue 130 formed on the upper surface U1 of the substrate 110 to seal the 4 1 bumps 1 4G. In addition, the planar grid array package structure (10) may further include a plurality of passive components 15A disposed on the lower surface n2 of the substrate 110. A heat sink 16 is disposed on the upper surface 111 of the substrate. Therefore, in the conventional planar grid array package structure _, only the electrical contact method (4) material electrical connection difference 5 200834849 product application surface is narrow. In the micro-reverse 畀 storage process, the 袼 array sealing structure 100 is placed on a bearing surface 1 〇 η ^ ^ r- 'metal 塾 13 and passive components located on the bottom surface 勿 no scratches and collisions. SUMMARY OF THE INVENTION The main object of the present invention is to provide a ten-dimensional peach grid array package structure of a strong city, which can achieve electrical farness by surface adhesion, and does not need to be electrically connected to have a special socket. With metal I < circuit board, and can

To avoid the problem of scratching and collision of the metal pad or solder layer, there are six applications for expanding the planar grid array package type of electronic products. SUMMARY OF THE INVENTION A second object of the present invention is to provide a planar gate & grid array package structure that solves the problem of scratching passive components during placement and handling. Another object of the present invention is to provide a planar grid array package construction for reducing the cost of setting a foot. The object of the present invention and solving the technical problems thereof are achieved by the following technical methods. According to the present invention, a planar grid array package structure mainly comprises a substrate, a wafer, a solder layer, and a foot. The substrate has an upper surface and a lower surface, wherein the lower surface is provided with a plurality of arrays of metal pads. The wafer is disposed on the upper surface of the substrate and electrically connected to the metal pads. The solder layer is disposed on the metal pads and has a first thickness that protrudes slightly from the lower surface of the substrate. The foot is provided with the substrate and has a second thickness that protrudes from the lower surface of the substrate, wherein the second thickness is greater than the first thickness. The object of the present invention and solving the technical problems thereof can be further realized by the following techniques 6 200834849. The planar grid array capsule is formed on the upper surface of the substrate to seal at least a portion thereof. In the aforementioned planar gate (four) column package structure, the foot is integrally connected to the sealant. In the aforementioned plane (4) column seal (4) M mu

a plurality of symmetrically arranged through holes, wherein the planar grid array has a slot, and the foot is coupled to the through-package structure via the socket. The substrate is attached to the slot. The colloid one seals a plurality of bonding wires in the aforementioned planar grid array, passes through the slot plate, and is covered by the foot. The mounting structure may further comprise electrically connecting the wafer with

In the foregoing planar grid array package structure, a plurality of bumps are arranged to electrically connect the wafer to the substrate in the planar planar gate, the early column package structure, and the foot socket system A plurality of branch blocks are formed and decayed and located on the lower surface or edge of the substrate. In the above-described planar thumb-and-eye squid array structure, the foot is strip-shaped and located on a center line of the substrate in the planar planar grid array dry 5 Ί package structure, the foot system is dielectric . In the foregoing planar grid array dry package construction, a further wafer may be included and may be provided with holes. It can be connected to the body. The base can be complex. The corner can be used. It can be a complex. 7 200834849 A long time ~ 舔 The following table highlights the third degree of the lower surface of the substrate, which is greater than the third thickness. In the aforementioned planar grid array package configuration, the port fins ' are disposed on the upper surface ' of the substrate. Included in another embodiment is an embodiment of a planar grid array package structure

In accordance with a first embodiment of the present invention, an array package construction. Fig. 2 is a schematic cross-sectional view of the planar grid, Fig. 3 is an enlarged cross-sectional view of the planar grid portion, and Fig. 4 is a schematic view of the bottom surface of the flat. Referring to Fig. 2, the planar grid array package mainly comprises a substrate 21, a wafer 220, and a solder layer η a foot 240. The substrate 210 has an upper surface 2 with a 1 JsA-lower " surface 212, wherein the lower surface 212 is provided with a plurality of arrays of metal pads 2 1 3 . The substrate 210 can be a multilayer printed circuit board. In this embodiment, the substrate 210 can have a plurality of symmetrically arranged through holes 214, and the legs 240 are coupled to the through holes 214. The wafer 220 is disposed on the upper surface 211 of the substrate 210 and electrically connected to the metal pads 213. In this embodiment, the planar grid array package structure 200 can further include a plurality of bumps 26 形成 formed under the wafer 220 to electrically connect the wafer 220 to the substrate 210. The internal lines of the substrate 210 are electrically connected to the metal pads 2 13 . 8 200834849 Referring to FIG. 3, the solder layer 230 is disposed on the metal crucibles 213 and has a first thickness 231 that protrudes slightly from the lower surface 212 of the substrate 21''. The solder layer 23 can be a tin-lead solder or a lead-free solder that can be reflowed into a circular arc. Typically, the solder layer 230 provides insufficient enthalpy to reflow into a spherical shape. The foot holder 240 is provided with the substrate 210 and has a second thickness 241 protruding from the lower surface 212 of the substrate 210, wherein the second thickness 241 is greater than the first thickness 231. Therefore, the planar grid array package structure 2 can be placed on the bearing surface 20' of a carrier such as the bottom surface of the substrate or the carrier of the carrier by the foot 240, so that the solder layer 23 does not contact. To the bearing surface 2, the metal pad 213 or the solder layer 230 is prevented from being scratched and collided. Referring to Figures 3 and 4, the foot 240 is comprised of a plurality of support blocks and is located at the corner or edge of the lower surface 2 1 2 of the substrate 21 . In the present embodiment, the foot 240 can be dielectric. Referring to FIGS. 2 and 3, more specifically, the planar grid array package structure 200 may further include a plurality of passive components 27 〇 disposed on the lower surface of the substrate 2 1 0 2 1 2 has a third thickness 271 protruding from the lower surface 212 of the substrate 210, wherein the second thickness 241 is also greater than the third thickness 271. By using the second thickness 241 to be larger than the first thickness 231 and the second thickness 271, the passive components 270 can be prevented from contacting the bearing surface 20 during the placement to cause scratches. Specifically, the planar grid array package structure 2 can further include a colloid 250 formed on the upper surface 9 of the substrate 21, 200834849 211 to seal the wafer 22 to a portion. . In this embodiment, the encapsulant 250 can be a point a μ Χ colloid or an underfill, which seals the active surface of the enamel sheet 220 to the bumps 260. Preferably, the planar grid array package structure 2 # ^ ¥ % may further comprise a heat sink 280, which is placed on the upper surface 211 of the substrate 210 to enhance the heat dissipation effect. 1 , body embodiment, FIG. 5 discloses another planar grid array package structure, FIG. 6 is a schematic diagram of the wearing surface, and FIG. 6 is a planar grid array package structure.

^ & Referring to Figures 5 and 6, the planar array 4 assembly structure 300 mainly includes a substrate 310, a wafer 320, a soldering jade floor 330, and a foot 340. The substrate 3 10 has an upper surface J11 and a lower surface 312, wherein the lower surface 3 1 2 is provided with a metal pad 3 1 3 of a plurality of arrays. In this embodiment, the substrate 31 has a slot 314. The active surface 322 of the day/slice 3 is disposed on the upper surface s 311 of the substrate 310 in a pasting manner, and a plurality of pads 32 are disposed on the active surface 322 of the wafer 30 as a wafer electrode. The pads 321 are aligned in the slots 314 of the substrate 31, and the plurality of bonding wires 306 are electrically connected to the pads 321 through the slots 3丨4. The wire bonding terminal of 310 (not shown) is electrically connected to the metal pads 313 by internal wiring of the substrate 310. The solder layer 3 3 G is disposed on the metal pads 3 i 3 and has a first thickness 3 3 slightly protruding from the lower surface 3 2 of the substrate 310 . The foot 340 is not provided with the substrate 310 and has a second thickness 34丨 protruding from the lower surface 312 of the substrate 31〇, wherein the second thickness 34 i 10 200834849 is greater than the first thickness 331. In this embodiment, the first thickness 331 of the solder layer 330 is between about 80 and 120 microns; the second thickness 341 of the foot 340 is between about 160 and 200 microns. Referring to FIG. 5 again, the planar grid array package structure 300 can be placed horizontally. Since the second thickness 341 is greater than the first thickness 331, the solder layer 330 does not touch a bearing surface. 30, so the handling and storage process can avoid the problem that the solder layer 310 is scratched and contaminated. In this embodiment, the foot 340 can be strip-shaped and located on one of the center lines of the substrate 310. More specifically, the foot 340 can be I-shaped or otherwise shaped (see Figure 6). The planar grid array package structure 300 may further include a colloid 305 formed on the upper surface 3 of the substrate 3 to seal at least a portion of the wafer 320. In this embodiment, the encapsulant 305 is a molding compound that completely seals the wafer. Preferably, the foot 340 can be connected to the seal body through the slot 314 to reduce the installation cost of the foot 34. Moreover, the foot 340 can cover the bonding wires 360. Referring to Figure 7, the planar grid array package structure 3 can be soldered to a printed circuit board 41 by SMT (Sxirface Mount Technology). The surface of the printed circuit board 41 has a plurality of ball pads 411 for bonding a plurality of solder balls 42 or solder paste. The ball diameter of the solder ball 420 and the first thick product 33 i of the solder layer 33 are greater than the second thickness 341 of the foot 340, so during the reflow process, the solder layer 330 and the solder balls 42〇 can achieve reflow soldering, the plane = 11 200834849 grid array package structure 300 can be externally connected to the printed circuit board 4 1 0. The printed circuit board 4 10 does not need to be provided with a special solid housing and a metal pin, which greatly reduces the manufacturing cost of the printed circuit board used to join the planar grid array package. Therefore, the planar gate array n 1 package structure 300 can effectively expand the application range of the planar grid array package type electronic port product, and can prevent the solder layer 300 scratch and the venom, for example, applicable In the memory module, it is sealed for the conventional planar grid array! The clothes are made to benefit. ...

A planar grid array package structure defines a wafer 520 and a foot 530. Referring to FIG. 8, the other 500 mainly includes a substrate 510 having an upper surface. The lower surface 512 is provided with a plurality of embodiments. The substrate 5 10 is more than 530. Settings. 5 U and - lower surface 5 1 2, an array of metal pads 513. There is a slot 514 for the foot. The active surface 522 of the wafer 520 is attached to the substrate 51.

The upper surface 5U, the plurality of soldering pads 521 of the active surface 522 of the wafer 520 can be aligned in the slot 514, and the plurality of bonding wires 550 can be used to electrically connect the plurality of bonding wires 514. Solder 521 to the substrate 510. When the foot 530 is provided with a 兮π recognition 1 child substrate 5 1 〇, it protrudes from the lower surface 5 i 2 of the substrate 5 1 0, so as to be only a foreign person, and also protects the These metal pads 5 1 3 are protected from being rubbed or scratched. In addition, the foot life C, A ~ A chat 530 can also cover the wire 550 ° in addition, a solder layer (not shown and not more than the foot placed on the metal pad 513 such as nickel gold layer The system can be equipped with a 530 protrusion height of 12 200834849 degrees. Therefore, the plane grid array is proud of the m _ package structure 500 series can be placed horizontally

With the storage, you can also make the table I τ σ (SMT). In this embodiment, the tantalum grid array package M, the skin may further comprise a sealant "Ο" formed on the upper surface 511 of the substrate 51 to seal at least the crystal 520 A part of the film. Therefore, the planar grid Chen | early 歹 j package structure 500 compared to the conventional 阵列 grid array package structure, can reduce the ^ ^ ^ - human ball implantation required infrared reflow step, so Plane grid

The J package 500 prevents the generation of thermal stress from the rejuvenation process. In addition, the planar grid array package structure 500 is bonded to the surface of the metal pad 513 to bond the solder balls on the printed circuit board, which can reduce the metal diffusion and the gold embrittlement effect. Right treasure is from m. The function is to prevent the joint interface between the metal pads 5 13 and the solder balls from being broken. Furthermore, the feet of the present invention can have different shapes and numbers. Referring to FIG. 9 , in accordance with a fourth embodiment of the present invention, another planar peach array package structure 6 〇〇 mainly includes a substrate 61 〇, a 曰 片 620, and a plurality of feet 63 丨, 632. The substrate has an upper surface 611 and a lower surface 612, wherein the lower surface 612 is provided with a plurality of metal pads 613. In this embodiment, the substrate 610 further has a plurality of bonding holes 614, 615 for the arrangement of the legs 631 and 632. The wafer 620 has a surface 621 of a solder pad attached to the upper surface 611 of the substrate 610. A plurality of bonding wires 65 can be used to electrically connect the wafer 62 to the substrate 13 200834849 6 10 through the bonding holes 6 1 4 and 61 5 . When the legs 631, 632 are disposed, the substrate 610, for example, the bonding holes 614, 615 protrude from the lower surface 612 of the substrate 61 to protect the metal pads 613 from being rubbed or scraped. hurt. The legs 631 and 632 are divided into a central foot 631 and a plurality of side legs 632 located at a central position of the substrate 61, wherein the side legs 632 are disposed on the side of the substrate 610. And protruding from the lower surface 612 of the substrate 61 and the two metal pads 613 are located on the central foot 631 and the sides

Between the feet 632 to increase the effect of scratch protection. In addition, the central leg 63 丨 and the side leg 632 can cover the bonding wires 65 5 位于 located at the center and the side of the substrate 61 。. Therefore, the planar grid array package structure 6 can be horizontally placed and transferred 'more surface mountable (SMT) e. In this embodiment, the planar grid array package structure 600 can further include a colloid 64〇 - is formed on the upper surface 6 of the substrate 61, to seal the wafer 62, which is only a preferred embodiment of the present invention, and does not impose any form limitation on the present invention, although the present invention The preferred embodiment of the invention has been modified or modified to be a modification or modification of the technical content of the present invention without departing from the scope of the present invention. Equivalent Embodiments of Equivalent Two 'But any equivalents and modifications of the above embodiments according to the technical spirit of the present invention without departing from the technical scope of the present invention are still 14 of the technical solution of the present invention. 200834849 [Simplified description of the drawings] Fig. 1 is a schematic cross-sectional view showing a conventional planar grid array package structure. Figure 2 is a cross-sectional view showing a planar grid array package structure in accordance with a first embodiment of the present invention. Figure 3 is a partially enlarged cross-sectional view showing the planar grid array package structure in accordance with a first embodiment of the present invention. Figure 4 is a schematic illustration of the underside of the planar grid array package structure in accordance with a first embodiment of the present invention. Figure 5 is a cross-sectional view showing another planar peach array package structure in accordance with a second embodiment of the present invention. Figure 6 is a schematic illustration of the underside of the planar grid array package structure in accordance with a second embodiment of the present invention. Figure 7 is a cross-sectional view showing the planar grid array package structure in use in accordance with a second embodiment of the present invention. Figure 8 is a cross-sectional view showing another planar grid array package structure in accordance with a third embodiment of the present invention. Fig. 9 is a cross-sectional view showing another planar grid array package structure in accordance with a fourth embodiment of the present invention. [Main component symbol description] 10 bearing surface 20 bearing surface 30 bearing surface 1〇 (> planar grid array package structure 11 () substrate 111 upper surface 112 lower surface 113 metal pad 15 200834849

120 wafer 130 encapsulant 140 bump 150 passive component 160 heat sink 200 planar grid array package structure 210 substrate 211 upper surface 212 lower surface 213 metal pad 214 through hole 220 wafer 230 solder layer 231 first thickness 240 foot 241 second Thickness 250 Sealant 260 Bump 270 Passive Element 271 Third Thickness 280 Heatsink 300 Planar Grid Array Package Construction 310 Substrate 311 Upper Surface 312 Lower Surface 313 Metal Pad 314 Slot 320 Wafer 321 Pad 322 Active Surface 330 Solder Layer 331 First thickness 340 foot 341 second thickness 350 sealant 360 bonding wire 410 printing circuit board 411 ball pad 420 solder ball 500 planar grid array package structure 510 substrate 511 upper surface 512 lower surface 513 metal pad 514 slot 520 chip 521 pad 522 active surface 530 foot 540 sealing body 550 wire bonding 600 plane frame array structure 16 200834849 610 substrate 611 upper surface 612 613 metal pad 614 bonding hole 615 620 wafer 621 surface 631 central foot 632 side foot 640 6 50 wire bonding lower surface bonding hole sealing body

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Claims (1)

200834849 X. Patent application garden: 1. A planar grid array package structure comprising: a substrate having an upper surface and a lower surface, wherein the lower surface is provided with a plurality of arrays of metal pads; Provided on the upper surface of the substrate and electrically connected to the metal pads; a solder layer disposed on the metal pads and having a first thickness slightly protruding from the lower surface of the substrate; and a foot disposed on the substrate and having a lower surface protruding from the substrate a second thickness, wherein the second thickness is greater than the first thickness. 2. The planar grid array package structure of claim J, further comprising a gel formed on the upper surface of the substrate to seal at least a portion of the wafer. 3. The planar grid array package structure of claim 2, wherein the foot base is integrally connected to the sealant. 4. The planar grid array package structure of claim i, wherein the substrate has a plurality of symmetrically arranged through holes, the feet being coupled to the through holes β 5 , as in the scope of the patent application The planar gate array package structure of claim 3, wherein the substrate has a slot through which the foot is integrally connected to the sealant. 6. The planar grid array package structure of claim 5, further comprising a plurality of bonding wires through which the wafer and the substrate are electrically connected and covered by the foot . The planar grid array package structure of claim 1, further comprising a plurality of bumps electrically connecting the wafer to the substrate. 8. The planar gate array package structure of claim i, wherein the foot is composed of a plurality of support blocks and is located at a corner or edge of the lower surface of the substrate. 9. The planar grid array package structure of claim 1, wherein the foot is strip-shaped and located on a centerline of the substrate. A planar grid array package structure as described in claim 1 wherein the foot is dielectric. 11. The planar grid array package structure of claim 1, further comprising a plurality of passive components disposed on the lower surface of the substrate and having a protrusion protruding from the lower surface of the substrate The third thickness, wherein the second thickness is also greater than the third thickness. 12. The planar gate (four) column package structure of claim 1, further comprising a heat sink disposed on the upper surface of the substrate. 13. A planar grid array package structure comprising: the lower substrate having a plurality of metal pads on an upper surface and a lower surface; a wafer disposed on the substrate The upper surface is electrically connected to the metal pads; and to the "foot, which is provided with the substrate and has a thickness protruding from the lower surface. 4. The planar thumb-array package structure of claim 13 further comprising a sealant formed on the upper surface of the substrate, 19 200834849 to seal at least a portion of the wafer. 15. The planar grid array package structure of claim 14, wherein the foot mount is integrally connected to the sealant. 1 6 'A planar grid array package structure as described in claim 5, wherein the δ mysterious substrate has a slot through which the foot is integrally connected to the sealant. The planar grid array package structure of claim 16, further comprising a plurality of bonding wires through which the wafer and the substrate are electrically connected and covered by the foot . The planar grid array package structure of claim 13, wherein the foot is strip-shaped and located on a centerline of the substrate. 9. The planar grid array package structure of claim 13, wherein the foot is dielectric. 20. The planar grid array package structure of claim 13, wherein the foot system is a center (four), which is located at a central position of the substrate, and further includes a plurality of side legs, The side of the substrate is disposed and protrudes from the lower surface of the substrate. 21. The planar grid array package structure of claim 20, wherein the metal tethers are located between the center leg and the side legs. 22. The planar gate (four) column package structure according to the scope of claim 2G, wherein the substrate has a plurality of bonding holes; for the central foot and the side feet, and the plurality of Through the bonding wires of the bonding holes, the central foot and the side chatting system respectively cover the bonding wires located at the center and the side of the substrate at 20 200834849. twenty one