200834511 九、發明說明 【發明所屬之技術領域】 本發明是關於液晶顯示裝置、如同有機電致發光（ electro luminescence)顯示器或 LCOS( liquid crystal on silicon )顯不器之保持型的顯示裝置，尤其是關於適合用 於動畫顯示之顯示裝置以及顯示系統。 【先前技術】 顯示裝置依據動畫顯示的觀點來分類的話，大體上分 類成脈衝型顯示裝置及保持型顯示裝置。脈衝型顯示裝置 是指如例如同陰極射線管’僅在掃描的期間所被掃描的像 素提局亮度’掃描之後即降低亮度的型式，保持型顯示裝 置係指如同液晶顯示裝置，根據顯示資料直到下一次的掃 描爲止持續保持亮度的型式。 在美國公開專利2 004/ 0 1 55847 (專利2004 — 2403 17 號公報）中記載：將1圖框分割成第1期間及第2期間， 在第1期間，集中寫入圖框期間中所應寫入到像素的像素 資料，此時，使對於像素的寫入値成爲像素資料値的2倍 ，以使圖像整體的亮度不致於降低，只限於2倍的値超過 可顯示範圍的情況，在第2期間寫入其餘的像素資料，藉 由此方式，顯示亮度的變化接近於脈衝型顯示裝置，以改 善動畫像的視覺效果。 在專利2002 - 21 5 1 1 1號公報中記載：圖框記憶部記 憶1圖框量的輸入圖像訊號，圖框率變換訊號產生部則依 -5- 200834511 據與輸入圖像訊號同步的時脈訊號、水平同步訊號、垂直 同步訊號，分別生成：圖像訊號的圖框率以3倍以上的變 換倍率變換過後的時脈訊號、水平同步訊號、垂直同步訊 號，圖像訊號切換部根據從切換訊號產生部所輸出的切換 訊號，將圖框記憶部的輸出訊號與黑電平固定的圖像訊號 進行切換後予以輸出，然後將1圖框的的圖像之顯示期間 予以任意地縮短。 同樣，在專利2004 — 3 1 7M8號公報中記載：一種具 有以4倍的比率每4次將輸入的各圖框予以輸出之頻率變 換電路1 1、及顯示每2N次所輸出的各圖框之液晶顯示元 件1 5之液晶顯示裝置，將各變換圖框當中每隔1個的各 變換圖框之亮度等級，利用亮度控制電路，變換成低於每 隔1個之其餘的各變換圖框的亮度等級之等級，供應至液 晶顯示元件，降低原來的各圖框切換時所產生的動畫像之 移動遲滯。 以下’本提案書中’將這種驅動方式稱爲η倍速脈衝 型驅動。 【發明內容】 <發明所欲解決之課題> 美國公開專利2004/ 0 1 5 5 847中所記載的備有η倍速 脈衝型驅動之顯示裝置’必須在輸入顯示資料之丨圖框的 時間內進行η次掃描，即是進行輸出顯示資料的改寫，因 而必須要有用來將輸出顯示資料予以η倍速化之η倍速化 -6 - 200834511 手段。但是，η倍速化必須要有圖框記億體。即是備有n 倍速脈衝型驅動之顯示裝置與通常的顯示裝置作比較，圖 框記憶體的使用量會導致成本提高。美國公開專利2004/ 0 1 55 847係在顯示裝置內部生成第1期間的資料及第2期 間的資料，故當在顯示裝置外部生成第1期間的資料及第 2期間的資料才依序輸入至顯示裝置的情況，無法判別第 1期間的資料及第2期間的資料，這點則未考慮到。 本發明的目的係提供將η倍速化電路設置在顯示裝置 外部，以縮小電路規模之顯示裝置。 另外，本發明的目的係提供當η倍速化電路設置在顯 示裝置外部的情況，可以分別判別1圖框期間內的η個欄 位之顯示裝置。 - 專利2002 — 2 1 5 1 1 1號公報及專利2004 — 3 1 7928號公 報中，爲了要判別η倍速化的圖框，生成切換訊號，但對 圖框記憶體進行寫入及讀出所造成的延遲則未考慮到。 本發明的目的係提供可以正確地判別1圖框期間內的 欄位期間之顯示裝置。 <用以解決課題之手段> 本發明是設置：η倍速化電路不是在顯示裝置側而是 在訊號產生裝置側執行之手段，以構成顯示系統。從訊號 產生裝置來將原來的輸入顯示資料η倍速化過後之η倍速 化顯示資料輸出至顯示裝置，顯示裝置中設有：對所輸入 的η倍速化顯示資料施予資料變換處理，以執行η倍速脈 200834511 衝型驅動之電路。此時，爲了要防止資料變換處理的誤動 作’設有：不但將η倍速化顯示資料，還將用來識別原來 的圖像訊號之圖框的切換位置之圖框同步訊號輸入至顯示 裝置之手段。 或者設置欄位反覆檢測電路，該欄位反覆檢測電路則 是在顯示裝置內部，依據η倍速化顯示資料，生成用來識 別原來的輸入顯示資料之圖框的切換位置之欄位識別訊號 [發明效果] 依據本發明，是一種保持型的顯示裝置以及使用前述 顯示裝置之顯示系統，可以利用η倍速化脈衝型驅動來實 現脈衝型顯示裝置的顯示特性，以獲得很少動畫遲滯之良 好的顯示質感。進而，依據本發明，與顯示裝置實施η倍 速化脈衝型驅動的情況作比較，可以提供更低成本的顯示 裝置以及顯示系統。 也就是依據本發明，可以將η倍速化電路設置在顯示 裝置外部，以縮小顯示裝置的電路規模。 另外’依據本發明，即使將η倍速化電路設置在顯示 裝置外部的情況，顯示裝置仍可以分別判別1圖框期間內 的η個欄位期間。 另外’依據本發明，由於考慮到倍速化所導致的延遲 來識別欄位期間，故顯示裝置可以正確地判別1圖框期間 內的攔位期間。 -8- 200834511 【實施方式】 接著’舉例來說明本發明的顯示裝置以及顯示系統的 構成方法。 首先，利用第1圖、第2圖、第3圖來說明本發明所 實施之η倍速脈衝型驅動。 接著，利用第4圖來說明搭載有η倍速脈衝型驅動之 顯不裝置的2個構成例子’並針對各別的課題進行說明。 其次，利用第6圖來說明解決上述課題之本發明的第 1實施例。 實施例1中，爲了要以低成本來實現η倍速脈衝型驅 動’提供將η倍速化電路配置在訊號產生裝置側，從訊號 產生裝置來將同步訊號輸出至顯示裝置所構成之顯示裝置 以及顯示系統。 其次，利用第7圖、第8圖來說明解決上述課題之本 發明的第2實施例。 實施例2中，提供將圖框反覆檢測電路設置在顯示裝 置所構成之顯示裝置以及顯示系統。 此外，以下，η倍速化脈衝型驅動的說明中，針對η 二2的情況進行說明，不過η的値並不侷限於設定爲2， 還可以設定爲更大的値。 [實施例1] 第1圖爲表示η倍速化脈衝型驅動的處理順序的槪念 -9- 200834511 。如同前述，是一種η == 2的例子。橫軸表示經過時間。 桌1A圖爲表不輸入顯示資料。每隔1圖框期間依序 輸入抽樣的圖案資料。1圖框期間若爲例如NTSC規格的 電視訊號之圖像資料的話則爲16.6 ms，此時，圖框頻率 爲 6 0 Η z 〇 其次，將輸入顯示資料的圖框頻率予以η倍化。 弟1 Β圖爲表不將第1 Α圖所不之輸入顯不資料的圖框 頻率予以η倍速化過後之η倍速化顯示資料。例如輸入顯 示資料爲NTSC訊號，當η二2時，η倍速化顯示資料的圖 框頻率爲1 20 Hz。形成爲經過輸入顯示資料之1圖框期間 的時間反覆地輸出2次相同的輸入顯示資料。此時，顯示 資料的更新間隔爲1 / η圖框期間。 最後，對η倍速化顯示資料施予脈衝型驅動用的資料 變換，顯示在顯示面板。 第1 C圖爲η倍速脈衝型驅動的顯示之例子。對第i Β 圖所示之η倍速化顯示資料施予資料變換，生成並顯示第 1欄位訊號及第2欄位訊號。第1欄位訊號的顯示是比原 來的輸入顯示資料還要更亮，第2欄位訊號的顯示則是比 原來的輸入顯示資料還要更暗，顯示特性爲脈衝型。這時 候，以將第1欄位訊號及第2欄位訊號予以時間的積分則 感覺上會有相當於原來的輸入顯示資料的亮度的方式進行 控制，藉此來消除顯示特性變更所造成亮度的降低。 第1D圖爲η倍速脈衝型驅動的顯示之其他例子。對 第1Β圖所示之η倍速化顯示資料施予資料變換，生成並 -10- 200834511 顯示第1欄位訊號及第2欄位訊號。第1欄位訊號的顯示 是比原來的輸入顯示資料還要更暗，第2欄位訊號的顯示 則是比原來的輸入顯示資料還要更亮，顯示特性爲脈衝型 。這時候，以將第1欄位訊號及第2欄位訊號予以時間的 積分則感覺上會有相當於原來的輸入顯示資料的亮度的方 式進行控制，藉此來消除顯示特性變更所造成亮度的降低 〇 經過以上的順序來控制顯示裝置，能夠實現η倍速脈 衝型驅動，即使保持型的顯示裝置也會實現脈衝型的顯示 特性，可以獲得很少動畫遲滯之良好的顯示畫質。 第2圖爲表示η倍速脈衝型驅動中，相對於輸入顯示 資料之第1欄位的顯不亮度與第2欄位訊號的顯示亮度的 關係（所謂的7特性）的例子之圖。 橫軸爲輸入顯示資料的色調，縱軸爲顯示亮度。實線 2 0 1爲通常驅動情況的例子，虛線2 0 3及一點狀連鎖線 2 02分別爲η倍速脈衝型驅動時第1欄位的顯示亮度及第 2欄位的顯示亮度之例子。 通常驅動時，例如相對於色調Dp的輸入顯示資料之 顯示亮度爲Bp，相對於色調Dq的輸入顯示資料之顯示亮 度爲Bq。其他的色調也是如第2圖所示的例子，使色調 與顯示亮度分別予以相對應。 相對於此，η倍速脈衝型驅動時，相對於色調Dp的 輸入顯示資料’第1欄位的顯示亮度爲B Ip，第2欄位的 顯示亮度爲Bdp。第1欄位期間顯示顯示亮度Blp，接著 -11 - 200834511 第2欄位期間顯示顯示亮度Bdp，藉此來調整成感覺上顯 示亮度可以相當於橫跨1圖框期間來顯示顯示亮度Bp的 情況。另外，相對於色調Dq的輸入顯示資料，第1欄位 的顯示亮度爲Blp，將第2攔位的顯示亮度爲Bdp。第1 欄位期間顯示顯示亮度Blq，接著第2欄位期間顯示顯示 亮度Bdq，藉此來調整成感覺上顯示亮度可以相當於橫跨 1圖框期間來顯示顯示亮度Bp的情況。其他的各色調也 是如第2圖所示的例子，使第1欄位的顯示亮度與第2欄 位的顯示亮度予以相對應。 以上的例子中，針對第1欄位爲相對地進行亮的顯示 之亮欄位，第2欄位爲相對地進行暗的顯示之暗欄位之η 倍速脈衝型驅動的構成進行說明過，不過也可以是第1欄 位爲暗欄位，第2欄位爲亮欄位的構成。 第3 Α圖爲表示相對於顯示裝置的某一像素之輸入顯 示資料的變化的樣子的例子之圖形。橫軸表示圖框（即是 時間），縱軸表示色調。 第3A圖中表示第i—丨圖框以及第i圖框爲色調Dp， 第i+ 1圖框以及第i+ 2圖框爲色調Dp之輸入顯示資料 的例子。 對於這樣的輸入顯示資料，過去的顯示裝置係以第i - 1圖框以及第i圖框顯示相當於色調Dp的顯示亮度Bp 的方式進行驅動，以第i+1圖框以及第i+2圖框顯示相 當於色e周Dq的顯不売度Bq的方式進行驅動。 其次，針對η倍速脈衝型驅動的例子進行說明。 -12- 200834511 第3B圖、第3C圖、第3D圖爲表示對於第3A圖的 輸入顯示資料，實施η倍速脈衝型驅動時之顯示裝置以及 顯示系統的處理樣子之圖形。 第3 Β圖爲將第3Α圖所示的輸入顯示資料予以η倍速 化時之η倍速化顯示資料的例子。橫軸與第3 Α圖相同表 示圖框（即是時間），縱軸表示色調。η倍速化顯示資料 係相當於在輸入顯示資料之1圖框期間的時間反覆輸出η 次相同的輸入顯示資料之資料。 第3 C圖爲表示依據對於第3Β圖所示的η倍速化顯示 資料施予脈衝型驅動用的資料變換處理過之輸出顯示資料 來驅動顯示裝置時之顯示亮度的變化樣子的例子之圖。橫 軸與第3Α圖相同表示圖框（即是時間），縱軸表示色調 〇 第3C圖中表示第1欄位爲相對地進行亮的顯示之亮 欄位，第2欄位爲相對地進行暗的顯示之暗欄位的構成例 子。相當於第1 ( c )圖的例子。 對於第3 Β圖所示的η倍速化顯示資料，第i 一 1圖框 以及第i圖框的第1欄位以顯示與色調Dp相對應的顯示 亮度Blp的方式進行驅動，第i - 1圖框以及第i圖框的第 2欄位以顯示與色調Dp相對應的顯示亮度Bdp的方式進 行驅動。另外，第i + 1圖框以及第i + 2圖框的第1欄位 以顯示與色調Dq相對應的顯示亮度Blq的方式進行驅動 ，第i+Ι圖框以及第i+2圖框的第2欄位以顯示與色調 Dq相對應的顯示亮度Bdq的方式進行驅動。 -13- 200834511 第3D圖爲表示對於第3B圖所示的η倍速化顯示資料 施予資料變換處理過後之顯示裝置的顯示亮度的變化樣子 之與第3C圖不同的構造例子之圖。橫軸與第3Α圖相同表 示圖框（即是時間），縱軸表示色調。 第3D圖係表示第1欄位爲相對地進行暗的顯示之暗 欄位，第2欄位爲相對地進行明的顯示之亮欄位的構成例 子。相當於第1 ( d )圖的例子。 對於第3 B圖所示的η倍速化顯示資料，第i 一 1圖框 以及第i圖框的第1欄位以顯示與色調Dp相對應的顯示 亮度Bdp的方式進行驅動，第i一 1圖框以及第i圖框的 第2欄位以顯示與色調Dp相對應的顯示亮度Blp的方式 進行驅動。另外，第i+Ι圖框以及第i+2圖框的第1欄 位以顯示與色調D q相對應的顯示亮度B dq的方式進行驅 動，第i+Ι圖框以及第i+2圖框的第2欄位以顯示與色 調Dq相對應的顯示亮度Blq的方式進行驅動。 如第3C圖、第3D圖所示，n倍速脈衝型驅動的構成 ，會有依亮欄位及暗欄位的順序，顯示特性有所不同的複 數種變化。 以上，已說明了本發明的顯示裝置以及顯示系統之η 倍速脈衝型驅動的槪要。接著，利用第4圖來說明搭載有 η倍速脈衝型驅動之顯示裝置以及顯示系統的2個構成例 子，並針對各自的課題進行說明。 第4Α圖爲表示用來實現η倍速脈衝型驅動之顯示裝 置以及顯示系統的其中1個構成例子之圖。此外，第4圖 -14- 200834511 中雖是表不以液晶顯不裝置來作爲顯示裝置的例子，但也 可以是使用其他的顯示原理之顯示裝置。 顯示系統例如爲電視機主機或PC主機、行動電話主 機等。 顯示系統具備有訊號產生裝置4100及顯示裝置4000 〇 訊號產生裝置4100例如爲電視機或錄影機中的訊號 處理電路群或PC或行動電話中的圖形處理電路群。訊號 產生裝置4100具備有將輸出至顯示裝置4000的輸入顯示 資料4112及輸入控制訊號群4111予已產生之訊號產生電 路 4 1 1 0。 顯示裝置4000具備有η倍速化電路4010、及資料變 換電路4030、及時序生成電路4050、及圖框記憶體4020 、及參數保持電路4040、及資料線驅動電路4060、及掃 描線驅動電路4070、及液晶顯示面板4080、及參考電壓 生成電路4 0 9 0。 顯示裝置4000具備有受理輸入顯示資料4112及輸入 控制訊號群4111的輸入’對輸入顯示資料4112及輸入控 制訊號群4 1 1 1，應用η倍速脈衝型驅動來驅動液晶顯示面 板4 0 8 0的功能。 輸入控制訊號群4 1 1 1係由規定例如1圖框期間（顯 示1畫面量的期間）之垂直同步訊號、規定1水平掃描期 間（顯示1線量的期間）之水平同步訊號、規定顯示資料 的有效期間之資料有效期間訊號、以及與顯示資料同步之 -15- 200834511 基準時脈訊號等所構成。 輸入顯示資料4 1 1 2、輸入控制訊號群4 1 1 1係從訊號 產生裝置4100傳送給顯示裝置4000。該傳送則可以應用 例如LVDS電平、CMOS電平、LVTTL電平等的各種電訊 號電平。顯示系統中，訊號產生裝置4100與顯示裝置 40 0 0隔著很遠配置的情況，該傳送最好是採用雜訊少且能 長距離傳送的方式。 η倍速化電路4010爲對於輸入顯示資料4112的圖框 頻率，生成已將圖框頻率η倍速化的η倍速化顯示資料 4 0 1 2之電路。 更具體上，η倍速化電路則是將輸入的輸入顯示資料 41 12依序儲存至圖框記憶體4020。一方面，讀出儲存之i 圖框期間量的資料時，在1圖框期間已η分割過的時間內 讀出。進而，在1圖框期間實施η次前述讀出操作，可以 實現圖框頻率的η倍化。 第1次讀出的輸入顯示資料係作爲第1欄位用的η倍 速化顯示資料來使用，第2次讀出的輸入顯示資料則是作 爲第2欄位用的η倍速化顯示資料來使用。 圖號4021爲寫入至圖框記憶體4020之寫入資料，圖 號4022爲從圖框記憶體4G20讀出之讀出資料。 另外，η倍速化電路4010係生成欄位識別訊號4013 及η倍速控制訊號群40 11。 欄位識別訊號4 0 1 3係與η倍速化顯示資料4 0 1 2同步 ，用來辨識η倍速化顯示資料40 1 2是否爲第1欄位用的η -16- 200834511 倍速化顯示資料或爲第2欄位用的η倍速化顯示資料。也 就是欄位識別訊號40 13與來自圖框記憶體4020之顯示資 料的讀出時脈同步。 η倍速控制訊號群40 1 1係由規定例如1圖框期間之η 倍速垂直同步訊號、規定1水平掃描期間之η倍速水平同 步訊號、規定η倍速顯示資料的有效期間之資料有效期間 訊號、以及與η倍速顯示資料同步之η倍速時脈訊號等所 構成。 圖框記憶體4020爲備有可以儲存至少1圖框量的顯 示資料的容量之記憶元件，進行輸入顯示資料的寫入、η 倍速化顯示資料的讀出處理。 圖框記憶體 4020可以使用例如各種的 DRAM ( dynamic random access memory )等 〇 資料變換電路4030爲進行生成用來實施前述n倍速 脈衝驅動的攔位變換資料4032之電路，受理從前述η倍 速化電路4010所輸出的η倍速化顯示資料4012來作爲輸 入，將前述η倍速化顯示資料40 12依據預定的資料變換 規則，變換成各欄位用的襴位變換資料4032。 此處，前述資料變換規則是作爲η個的欄位變換參數 4041、4042，輸入至資料變換電路4030。 資料變換電路4030係藉由欄位識別訊號4013來識別 欄位，選出各自的欄位用的參數。 第1欄位變換參數4041決定第1欄位用的前述資料 變換規則。 -17- 200834511 第2欄位變換參數4042決定第2欄位用的前 變換規則。 藉由η倍速脈衝型驅動來將1個圖框分割成2 的攔位的情況，最好是各自的欄位用分別備妥第η 換參數。 資料變換規則係以衡量圖框的分割數η、顯示 環境溫度、液晶顯示面板的溫度、參考電壓的設笼 圖框期間的長度、各欄位期間的長度等的影響，並 的輪廓或色差不會發生，獲得良好的顯示品質的方 當地予以決定。 資料變換規則也可以藉由將上述各種的條件作 的運算式來規定，還可以藉由參考以上述各種的條 引的查找表（lookup table)來規定。 另外，資料變換電路403 0係將從前述η倍速 4010所輸入之η倍速控制訊號群4011予以與前述 換資料4032同步的方式調整時序，作爲欄位變換 制訊號群4032來輸出。 時序生成電路4050係受理從前述資料變換電S 所輸出之欄位變換資料控制訊號群403 1及欄位變 4032來作爲輸入，然後，是一種依據前述欄位變換 制訊號群4031及前述欄位變換資料4032，生成用 資料線驅動電路4 0 6 0之資料線驅動電路控制訊號I 、及輸出顯示資料群4 0 5 2、及用來控制掃描線驅 40 70之掃描線驅動電路控制訊號群4053之電路。 述資料 個以上 欄位變 裝置的 [量、1 使虛假 式，適 爲參數 件爲索 化電路 欄位變 資料控 各 4 0 3 0 換資料 資料控 來控制 洋 405 1 動電路 -18- 200834511 參數保持電路4040係將包含資料變換電路4030所使 用的欄位變換參數4041、4042之各種設定參數予以保持 之電路。另外，還具備有從外部的記憶電路（未圖示）來 讀出前述各種設定參數資料之功能。 參數保持電路4040具備有例如暫存器檔案（register file )或各種 RAM ( random access memory )等的記憶元 件群、及記憶電路的控制電路。 記憶電路（未圖示）爲用來記憶前述各種設定參數所 使用之電路。可以使用例如ROM (read only memory)或 EEPROM ( electrically erasable programmable ROM)快閃 記憶體等的各種不揮發記憶體等。 資料線驅動電路控制訊號群405 1係由規定例如根據 輸出顯示資料1 052之色調電壓的輸出時序之輸出時序訊 號及決定電源電壓的極性之交流化訊號、與顯示資料同步 之時脈訊號等所構成。 掃描線驅動電路控制訊號群4 0 5 3係由規定例如1線 的掃描期間之g位訊號、規定頭端線的掃描開始之垂直開 始訊號等所構成。 圖號4090爲參考電壓生成電路，圖號4091爲參考電 壓。 資料線驅動電路4 〇 6 0係從參考電壓4 0 9 1來生成與顯 示色調的數量相對應的電位，並且選出與輸出顯示資料 4052相對應之1電平的電位，作爲輸往液晶顯示面板 4 0 8 0的資料電壓來施加。圖號4 0 6 1爲經由資料線驅動電 -19- 200834511 路所生成之資料電壓。 圖號4 0 70爲掃描線驅動電路，圖號4071爲掃描 擇訊號。 掃描線驅動電路4070係根據掃描線驅動電路控 號群4053生成掃描線選擇訊號407 1，輸出至液晶顯 板4080的掃描線。 圖號4080爲液晶顯示面板，圖號408 1爲液晶顯 板的1個像素之模式圖。液晶顯示面板4080的1個 4〇81係由以源極、閘極、汲極所組成之TFT ( thin transistor)、及液晶層、對向電極所構成。將掃描訊 加至閘極，藉此來進行TFT的開關動作，TFT爲開狀 ，資料電壓經由源極寫入至與液晶層的其中一方相連 汲極電極，TFT爲閉狀態時，維持寫入至汲極的電壓 汲極的電壓爲 Vd，對向電極電壓爲 VC0M。液晶層 據汲極電壓Vd與對向電極電壓VC0M的電位差，改 光方向，並且隔著被配置在液晶層的上下之偏光板， 來變化來自被配置在背面之背光的透光量並進行色調 〇 以上，已利用第4A圖說明了用來實現η倍速脈 驅動之顯示系統的構成例子。但是，第4Α圖的構成 況，存在的課題爲必須在顯示裝置4000側設有η倍 電路4010及圖框記憶體4020，致使顯示裝置4000的 提筒。 一方面，第4Β圖爲表示用來實現η倍速脈衝型 線選 制訊 示面 示面 像素 f i lm 號施 態時 接之 。該 係根 變偏 藉此 顯不 衝型 的情 速化 成本 驅動 -20- 200834511 之顯不系統的另外構成例子之圖。 與第4A圖的構成作比較’其不同點爲將設在顯 置45 00側之n倍速化電路4510及圖框記憶體4520 在訊號產生裝置4 6 0 0側，將η倍速化顯示資料4 5 1 2 倍速控制訊號群4 5 1 1，從訊號產生裝置傳送至顯示 4500。η倍速化顯不貪料4512則爲相同的顯示資料。 其他方面則與第4Α圖的構成同等，其各部位的 則省略。 一般，訊號產生裝置必須要進行各種的格式變換 像的解像度變換、隔行（interlace ) -逐行（progre )變換）或圖像校正處理（端緣強化、色調校正）等 的訊號處理，所以搭載有比顯示裝置還高性能的訊號 電路。因而，在訊號產生裝置側搭載η倍速化電路或 記憶體所增加的成本，仍小於在顯示裝置側搭載η倍 電路或圖框記憶體所增加的成本。即是若是將η倍速 路或圖框記憶體配置在訊號產生裝置側的話，可以以 的成本來實現全體系統。 但是，第4(B)圖的構成的情況，對顯示裝置 側輸入η倍速化顯示資料45 12及η倍速控制訊號群 來取代輸入顯示資料4612及輸入控制訊號4611，故 裝置45 0 0側無法識別元來的輸入顯示資料4612之圖 段落。即是存在的課題爲無法使第1欄位及地2欄位 換與圖框的段落同步，且無法任意地控制使資料變換 4530之資料變換結果成爲第3C圖和第3D圖的其中 示裝 配置 及η 裝置 說明 (圖 s s i ν e 複雜 處理 圖框 速化 化電 更低 4500 45 11 顯示 框的 的切 電路 一方 -21 - 200834511 。即是無在某一狀態下，不論如同第3C圖第1欄位爲亮 欄位，第2欄位爲暗欄位，在其他的狀態下，如同第3D 圖弟1欄位成爲暗欄位，第2欄位成爲亮欄位的狀態隨 機產生而無法控制，有可能會陷入這樣的狀態。這樣的情 況，第3 C的情況及第3 D圖的情況，由於顯示特性不同， 故不論輸入顯示資料4612是否相同，仍會發生：顯示的 圖像受到顯示系統的狀態（例如電源投入時序）的影響而 隨機變動的缺陷。 另外，輸入顯示資料4612本身也會依據對訊號產生 裝置4600的操作等進行各種的變動。列舉有：例如電視 機的接收頻道或圖像源切換時的變動、或錄影機進行快速 再生或回捲再生等的不規則的顯示所造成的變動。進行這 樣的操作時也會發生顯示系統的顯示特性隨機切換成第 3C圖或第3D圖的其中一方，導致不確定的缺陷。 基於顯示的穩定性的觀點，顯示裝置最好是以可以任 意地控制顯示特性的方式來構成顯示系統。即是必須要有 識別輸入顯示資料之圖框的段落，並將欄位的切換予以同 步的機構。 以上，已說明了搭載有η倍速脈衝型驅動之顯示裝置 和顯示系統的2個構成例子、以及各別的課題。 其次，利用第5、6圖來說明用來解決上述課題之本 發明的顯示裝置及顯示系統。 第5圖爲表示用來解決上述的課題並實現η倍速脈衝 型驅動，採用本發明的一個實施形態之顯示系統及顯示裝 -22- 200834511 置5000的構成例子之圖。 與第4A圖的構成作比較，不同的點爲將設在顯示裝 置側5000之η倍速化電路5010及圖框記憶體5020配置 在訊號產生裝置5 1 00側。另外，不同的點爲將η倍速化 顯示資料5012及η倍速控制訊號群5011及輸入控置訊號 5111，從訊號產生裝置5100傳送至顯示裝置50 00。此外 ，不同的點爲不是經由η倍速化電路5010來生成用來識 別輸入顯示資料5 1 1 2之圖框的切換之攔位識別訊號輸入 至資料變換電路503 0，而是設置從原來的輸入控制訊號 5 1 1 1來生成欄位識別訊號5 0 1 3用之欄位識別訊號生成電 路5 20 0，依據前述輸入控制訊號5111來生成欄位識別訊 號 5013 。 其他方面與第4Α圖的構成相同，其各部位的說明則 省略。 另外，與第4Β圖的構成作比較，不同的點也是原來 的輸入顯示資料5 1 1 2的輸入控制訊號5 1 1 1，從訊號產生 裝置5100傳送至顯示裝置5000。 如同前述，基於顯示穩定性的觀點，顯示裝置5000 最少是以可以任意地控制η倍速脈衝型驅動的顯示特性的 方式構成。因而，必須要識別輸入顯示資料5 1 1 2之圖框 的段落，但爲了要進行識別，使用輸入顯示資料5 1 1 2的 輸入控制訊號5 1 1 1，既簡單又有效果。例如輸入控制訊號 群5111中其中一個的輸入垂直同步訊號爲規定輸入顯示 資料5 1 1 2的1圖框期間之訊號，故適合用來識別輸入顯 -23- 200834511 示資料5112之圖框的切換。 以前述輸入垂直同步訊號爲基準，利用欄位識別訊號 生成電路5200來生成欄位識別訊號5013，若是用來識別 欄位的話，可以解決前述顯示系統的顯示特性隨機變動的 缺陷，能夠進行穩定的顯示。 此外，也可以是使用輸入控制訊號群5 1 1 1的其他訊 號來取代輸入垂直同步訊號之構成。 以上，已利用第5圖說明了採用本發明的一個實施形 態之顯示裝置及顯示系統的構成例子。 第6圖爲表示採用本發明的一個實施形態之顯示裝置 及顯示系統的動作例子之圖，且是第5圖所示之顯示裝置 及顯示系統的動作時間圖的例子。第6圖中的橫軸表示時 間。 首先，從訊號產生電路 5110，輸出輸入顯示資料 5 11 2及輸入控制訊號群5 1 1 1。 第6圖的例子爲圖示輸入控制訊號群5 1 1 1中其中一 個的輸入垂直同步訊號601及輸入顯示資料5112。輸入垂 直同步訊號601爲規定1圖框期間的訊號，且與輸入顯示 資料5 1 1 2之圖框的切換同步產生事件。 另外，第6圖中，符號D(i)表示i圖框的輸入顯示 資料。同樣，例如D ( i + 1 )表示第i + 1圖框的輸入顯示 資料。 輸入顯示資料5 1 1 2係以1圖框期間單位，依照D ( i )、D(i+l) 、D(i+2) —一的順序，依序輸入各圖框 -24- 200834511 的資料。 其次，藉由前述η倍速化電路5010來實施前述η倍 速化處理。 第6圖的例子爲圖示藉由η倍速化電路5010所生成 之η倍速控制訊號群5011中其中一個的η倍速垂直同步 訊號6 1 1、及η倍速化顯示資料5 0 1 2、及經由欄位識別訊 號生成電路5 2G0而依據輸入垂直同步訊號601所生成之 欄位識別訊號5 0 1 3。η倍速垂直同步訊號6 1 1爲規定η倍 速化顯示資料5012的1欄位期間之訊號，且是與η倍速 化顯示資料5012之圖框的切換同步產生事件。 此外，如同第6圖的例子所示，在輸入垂直同步訊號 601和輸入顯示資料5112及η倍速垂直同步訊號611和η 倍速化顯示資料5012的期間，一般會因η倍速化處理而 造成延遲。輸入垂直同步訊號601的事件發生之後，從η 倍速垂直同步訊號6 1 1的最初事件發生的時間點才開始第 1項目的欄位期間，該延遲係因例如η倍速化電路5 0 1 0受 到對圖框記憶體5 0 2 0寫入顯式資料的時序與讀出的時序 之時間所導致。η倍速化電路5 010可以在將I/η圖框量 的顯示資料寫入圖框記憶體5 020的時序，接著就從圖框 記憶體5020讀出I/η圖框量的顯示資料。於是，η倍速 化電路501 0則可以在顯示資料寫入圖框記憶體5020開始 ’在短於1圖框期間的期間，開始從圖框記憶體5 0 2 0讀 出顯示資料。 £ 欄位識別訊號生成電路5 2 0 0係依據輸入垂直同步訊 25- 200834511 號6 01來生成欄位識別訊號5013。欄位識別訊號5013則 是用來判別欄位。本實施例爲表示將1圖框分割成第1攔 位及第2欄位的2個欄位的例子，故欄位識別訊號6 1 3可 以由在每一欄位期間，將例如表示第1欄位的訊號電平（ low)、及表示第2欄位的訊號電平（high)的2個値予 以反覆變化之訊號所構成。 η二2時的欄位識別訊號5013，例如依照以下的順序 來生成。 首先，設定：與η倍速垂直同步訊號611同步來將 low與high予以反轉之欄位識別準備訊號612。進而，欄 位識別準備訊號612係以與輸入垂直同步訊號601同步來 必定設定成high的方式所構成。接著，欄位識別訊號 50 1 3則是可以與η倍速垂直同步訊號6 1 1 1同步來鎖定欄 位識別準備訊號612，致使如第6圖所示，第1欄位爲 low，第2欄位爲high的方式所構成。 依據這樣的構成，因某種原因（例如顯示系統若爲 TV的話，進行頻道切換，若爲錄影機的話，進行快速回 捲操作等）而變動輸入控制訊號群5111或輸入顯示資料 5 1 1 2，致使欄位識別訊號5 0 1 3、欄位識別準備訊號6 1 2也 變成不穩定甚至於變成異常値，即使在正常地進行欄位識 別的狀態下，受理輸入垂直同步訊號60 1的輸入的話，仍 可以從下一個欄位，再度開始正常的欄位識別動作，故提 高顯示裝置之動作的穩定性。 以上，已列舉一個使用輸入垂直同步訊號6 0 1的構成 -26- 200834511 例子，說明了利用欄位識別訊號生成電路5200來生成攔 位識別訊號5 0 1 3的方法，不過本發明之欄位識別訊號的 生成方法並不侷限於此。 接著，藉由資料變換電路503 0，對前述η倍速化顯示 資料5 0 1 2，實施資料變換處理。 資料變換電路5030係受理從欄位識別訊號生成電路 5 20 0所輸出的欄位識別訊號5 013、及從η倍速化電路 5010所輸出的η倍速化顯示資料5012來作爲輸出。資料 變換電路5030則根據欄位識別訊號5013來識別第1欄位 或第2欄位，當η倍速化顯示資料爲第1欄位時（即是欄 位識別訊號5 01 3爲low時），根據第1欄位變換參數 5 04 1來進行資料變換，當n倍速化顯示資料爲第2欄位時 (即是欄位識別訊號5013爲high時），根據第2欄位變 換參數5042來進行資料變換。 此外，此處已說明了了 η = 2時之η倍速脈衝型驅動 的例子，故前述欄位識別訊號變成2個値的反覆變化訊號 ’當η爲3以上時，前述欄位識別訊號最好是藉由計數欄 位數之計數値等來實現。 第6圖中，圖示藉由資料變換電路503 0所生成之欄 位變換控制訊號群5031中其中一個的欄位變換垂直同步 訊號621、及攔位變換資料5 03 2。欄位變換垂直同步訊號 621爲規定欄位變換資料5032的1欄位期間之訊號。 另外，第6圖中，符號FI (i)表示已對第i圖框的η 倍速化顯示資料施予亮欄位用的資料變換過之資料。同樣 -27- 200834511 ，例如符號FI ( i + 1 )表示已對第i + 1圖框的η倍 顯示資料施予亮欄位用的資料變換過之資料。一方面 6圖中，符號F d ( i )表示已對第i圖框的η倍速化顯 料施予暗欄位用的資料變換過之資料。同樣，例如 Fd(i+1)表示已對第i+l圖框的η倍速化顯示資料 暗欄位用的資料變換過之資料。 此外’第6圖中，表示第1欄位爲亮欄位，第2 爲暗欄位的例子，不過也可以是第1欄位爲暗欄位， 欄位爲亮欄位的構成。 最後，時序生成電路5050，依據欄位變換資料 來生成輸出顯示資料5032(第6圖中沒有圖示）。 另外，時序生成電路5 0 5 0係依據資料變換電路 所生成之欄位變換控制訊號群5 03 1，生成輸出控制訊 505卜 此外，如第6圖所示，η倍速垂直同步訊號6 1 1 倍速化顯示資料5012及欄位變換垂直同步訊號621 位變換資料5 032的期間，一般會因資料變換處理而 延遲。 如同以上方式構成顯示裝置，藉此可以實現 速脈衝型驅動，又可以獲得動畫像的動畫遲滯減少： 的畫質。 [實施例2] 接著，利用第7、8圖來說明本發明的第2實ϊ 速化 ，第 示資 圖號 施予 欄位 第2 5032 5030 號群 和η 和欄 造成 η倍 良好 形態 -28- 200834511 第7圖爲表示用來解決先前說明過的上述的課題 現η倍速脈衝型驅動，採用本發明的一個實施形態之 系統及顯示裝置的構成例子之圖。 與第4Α圖的構成作比較，不同的點爲在顯示 700 0側設置欄位反覆檢測電路72 10，以取代將原來 入顯示資料7112之控制訊號7111，從訊號產生裝置 輸入至顯示裝置7000。另外，不同的點爲將η倍速化 資料70 12及η倍速控制訊號群701】，從訊號產生 7100傳送至顯示裝置7000。其他的點則與第4Α圖相 故各部位的說明則省略。先前說明過第4Β圖的構成 已針對課題中無法識別原來的輸入顯示資料7 1 1 2之 的切換的這點加以說明過。第7圖的構成則是提供解 課題的手段。 第7圖的例子中，顯示裝置7 0 0 0設有欄位反覆 電路7210。欄位反覆檢測電路7210所具備有爲輸入 速化顯示資料7012及η倍速控制訊號群701 1，檢測 速化顯示資料7012之欄位的反覆，當同樣內容的欄 覆時，識別出原來輸入顯示資料7112爲相同的圖框 相同內容的欄位未返覆時，識別出欄位切換了，將識 果作爲欄位識別訊號70 1 3來輸出。 第8圖爲欄位反覆檢測電路72 1 0的構成例子之圈 攔位反覆檢測電路72 1 0具備有：欄位特徵量抽 路810、欄位特徵量乖離度運算電路830、欄位反覆 並實 顯示 裝置 的輸 7100 顯示 裝置 同， 中， 圖框 決該 檢測 η倍 η倍 位反 ，當 別結 丨。 出電 識別 -29- 200834511 電路840、記憶體820。 欄位特徵量抽出電路8 1 0係抽出表示n倍速化顯示資 料7012之各欄位的特徵之特徵量811。特徵量811爲表示 圖像資料的特徵指標，可以應用：例如平均亮度等級、最 大亮度等級、亮度分布直方圖 '頻譜分布、資料的無意義 値、資料的巡迴冗長符號、圖像資料的縮小影像等。另外 ’也可以將這些中複數所組合之向量作爲特徵量來使用。 另外’前述特徵量的資料量最好是少於n倍速化顯示資料 之1欄位量的資料量。 記憶體820具備有寫入經由前述欄位特徵量抽出電路 8 1 〇所抽出之現欄位的特徵量8 1 1，讀出1個之前的欄位 的特徵量821的功能。記憶體820具備有至少1欄位期間 之間保持前述特徵量的記憶容量。此處，如同前述，前述 特徵量的資料量少於1欄位量的資料量，故前述記憶體 820以少於圖框記憶體的容量就可以實現，能夠低成本化 〇 記憶體 820可以使用例如各種的 DRAM ( dynamic random access memory)等 ° 欄位特徵量乖離度運算電路830爲現欄位的特徵811 與1個之前的欄位的特徵量821進行比較、運算，算出前 述2個欄位的乖離度8 3 1之電路。例如’可以將前述2個 欄位的特徵量之差分値作爲2個欄位的乖離度831。或者 前述特徵量爲有複數個次元的向量時，可以將例如現欄位 的特徵量向量與1個之前的攔位的特徵量向量之夾角的餘 -30 - 200834511 弦値作爲2個欄位的乖離度83 1。 欄位反覆識別電路840係從欄位特徵量之乖離 小831，識別：前述2個欄位一致，即是是否反覆 位、或者前述2個欄位不一致，即是是否切換原來 。例如乖離度83 1小於特定的閾値時，可以識別出 個欄位要反覆、或者在乖離度831大於前述特定的 ，可以識別出原來的圖框要切換。藉由此方式，可 欄位識別訊號7 0 1 3。 接收該欄位識別訊號701 3，第7圖所示的資料 路703 0則可以適時地選擇適當欄位的參數來進行 換。 此外，第7圖所示的顯示裝置及顯示系統的動 與第6圖所示之時間圖的例子相同，故其說明省略 圖中，欄位識別訊號70 1 3相當於欄位識別訊號6 1 3 以上，已說明了應用本發明的一個實施形態之 置的構成例子。 如同以上構成顯示裝置及顯示系統，藉此可以 同第1圖所示的η倍速脈衝型驅動，又可以獲得很 遲滯之良好的顯示畫質。 [實施例3] 其次，利用第2、5、6及9、· 1 〇圖來說明針對 框率變換裝置之訊號產生裝置，採用本技術時的例 框率變換裝置是一種如同例如日本專利特開2003 - 度的大 相同欄 的圖框 前述2 閾値時 以生成 變換電 資料變 作，因 。第6 〇 顯示裝 實現如 少動畫 含有圖 子。圖 333540 -31 - 200834511 號公報中所述，從圖框間的圖象訊號應用移動向量等來生 成圖框間的圖像訊號之裝置，經由將前述所揭示的技術應 用在液晶顯示裝置，可以如同日本專利特開2003 — 3 3 3 540 號公報中所述，在PAL - NTSC變換的情況，達到減少動 作抖動。進而，進行例如6 0 Η z — 1 2 0 Η z變換，能夠達到 動畫遲滯的改善。變換成60 Hz— 120 Hz時，如第9Α圖 所示，依據由i— 1、i、i+Ι所示之 60 Hz所組成的輸 入顯示資料，生成第9B圖所示的— 0.5 —所示之120 Hz的倍速化顯示資料。以下，第9A和 9B圖中，附註i— 1、i、i+Ι的數字，整數所示的顯示資 料稱爲實圖框顯示資料，附註i一 〇·5、i一 0.5的數字，非 整數所不的顯不資料稱爲插補圖框顯不資料。.實圖框顯示 資料中，A及B的附加數字相同的圖框則爲相同顯示資料 〇 含有以上的圖框率變換裝置之訊號產生裝置，可以含 有第5圖的η倍速化電路5 0 1 0。 此情況，應用第i圖框項的實圖框顯示資料及第i + 1 圖框項的實圖框顯示資料，生成第i + 0 · 5圖框項的插補圖 框顯示資料時，輸入顯示資料與2倍速化顯示資料的時序 關係，成爲如同第1 〇圖所示實圖框圖像的顯示開始位置 延遲1圖框期間量。此情況，第5圖所示的顯示系統，在 欄位識別訊號50 13的訊號電平爲Low時’該圖框則可稱 爲插補圖框顯示資料。 資料變換電路5 0 3 0係受理從欄位識別訊號生成電路 -32- 200834511 52 00所輸出之欄位識別訊號5013、及從2倍速化電路 5 0 1 0所輸出之2倍速化顯示資料5 0 1 2來作爲輸入。資料 變換電路5 〇 3 0則根據欄位識別訊號5 0 1 3，識別實圖框或 插補圖框，若2倍速化顯示資料爲實圖框顯示資料時（即 是欄位識別訊號5 0 1 3爲H i g h時），進行應變成第2圖之 亮欄位的特性203之資料變換，若2倍速化顯示資料爲插 補圖框顯示資料時（即是欄位識別訊號5013爲Low時） ，進行應會變成第2圖之暗欄位的特性202之資料變換。 如此，本實施例中，以實圖框顯示資料變成亮圖框， 插補圖框顯示資料變成暗圖框的方式進行變換。插補圖框 顯示資料係依據實圖框顯示資料來生成，故輸入圖框顯示 資料與同等的實圖框顯示資料作比較，理論上正確性會降 低。對於此點，如同實施例1所記載，本發明的脈衝型驅 動方式，由於對η圖框（本實施例的情況，n = 2 )，觀測 平均化的亮度，故正確性較低的插補圖框顯示資料爲暗欄 位，藉此即使沒有進行正確的插補時，仍可以抑制因該不 正確所導致圖像的散亂，進而，由於進行添加了視線的移 動方向之脈衝變換，故能夠減少脈衝回應所變成課題的所 謂疑似輪廓。 [產業上的可利用性] 本發明可以應用於電視機的顯示裝置。 【圖式簡單說明】 -33- 200834511 第1圖爲說明本發明的η倍速脈衝型驅動的槪念之圖 〇 第2圖爲表示本發明的η倍速脈衝型驅動的色調與顯 示亮度的相對應的例子之圖。 第3圖爲表示對本發明的η倍速脈衝型驅動的輸入顯 示資料及前述輸入顯示資料實施過η倍速脈衝型驅動的情 況之顯示亮度的變化樣子的例子之圖形。 第4圖爲表示具備有本發明的η倍速脈衝型驅動之顯 示裝置及顯示系統的構成例子之圖。 第5圖爲表示本發明的第1實施例之顯示裝置及顯示 系統的構成例子之圖。 第6圖爲表示本發明的第1實施例之顯示裝置及顯示 系統的動作例子之圖。 第7圖爲表示本發明的第2實施例之顯示裝置及顯示 系統的構成例子之圖。 第8圖爲表示本發明的第2實施例之顯示裝置的欄位 反覆檢測電路的構成例子之圖。 第9圖爲表示本發明的第3實施例之2倍速脈衝驅動 的槪念之圖。 第10圖爲表示本發明的第3實施例之顯示裝置及顯 示系統的動作例子之圖。 【主要元件符號說明】 4 1 1 2、46 1 2、5 1 1 2、7 1 1 2 :輸入顯示資料 -34- 200834511 4 1 1 1、46 1 1、5 1 1 1、7 1 1 1 :輸入控制訊號群 4 010、4510、5010、7010: η 倍速化電路 401 1、45 1 1、50 Η、7011 : η倍速控制訊號群 4012、 45 12、5012、7012 : η倍速化顯示資料 4021、 4521、502 1、7021 ：寫入資料 4022、 4522、5022、7022 ：讀出資料 4013、 5013、7013 :欄位識別訊號 4030、4530、5 030、703 0 ：資料變換電路 4032、4532、5032、7032 ： ff邊位變換資料 4041、 4242、 4541、 4542、 5041、 5042、 7041、 7042 :欄位變換參數 4050、 455 0、5050、7050:時序生成電路 4051、 4551、5051、7051:資料線驅動電路控制訊號 洋 4052、 4552、5052、7052:輸出顯示資料 4070、4570、5070、7070:掃描線驅動電路 4080、 4580、 5080、 7080:液晶顯示面板 408 1、45 8 1、508、708 1 :液晶顯示面板像素 4 0 6 0、4 5 6 0、5 0 6 0、7 0 6 0 :資料線驅動電路 4061、4561、5 0 61、70 6 1 ：資料電壓 4070、4570、5070、7070:掃描線驅動電路 407 1、457 1、507 1、707 1 :掃描線選擇訊號 4 0 9 0、4 5 9 0、5 0 9 0、7 0 9 0 :參考電壓生成電路 4091、 4591、 5091、 709 ：參考電壓 -35- 200834511 4020 ^ 452 0、5020、7020 ：圖框記憶體 4021 、 4521 、 5021 、 7021 ：寫入資料 402 2、452 2、5 022、7022 :讀出資料 4040、4540、5040、7040 :設定參數保持電路 4041 、 4042 、 4541 、 4542 、 5041 、 5042 、 7041 ' 7042 :各種設定參數 5200 :欄位識別訊號生成電路 72 10 :欄位反覆檢測電路 ® 810:攔位特徵量抽出電路 8 1 1、8 2 1 :特徵量 830 :欄位特徵量乖離度運算電路 8 3 1 :乖離度 840 :欄位反覆識別電路 -36-200834511 IX. Description of the Invention [Technical Field] The present invention relates to a liquid crystal display device, a display device such as an organic electroluminescence display or an LCOS (liquid crystal on silicon) display, in particular A display device and a display system suitable for use in an animation display. [Prior Art] When the display device is classified according to the viewpoint of animation display, it is roughly classified into a pulse type display device and a hold type display device. The pulse type display device refers to a type in which, for example, the brightness of the pixel scanned by the cathode ray tube is scanned only during the scanning period, the brightness is reduced, and the holding type display device is like a liquid crystal display device, according to the display data until The type of brightness that continues to be maintained until the next scan. It is described in the U.S. Patent No. 2,004,0,0,058, the disclosure of which is incorporated herein by reference to the entire disclosure of the entire disclosure of The pixel data written to the pixel, at this time, the write 値 for the pixel is twice as large as the pixel data ,, so that the brightness of the entire image is not reduced, and only 2 times 値 exceeds the displayable range. In the second period, the remaining pixel data is written, and in this way, the change in display luminance is close to that of the pulse type display device to improve the visual effect of the moving image. Patent Publication No. 2002-21 5 1 1 1 discloses that the frame memory unit memorizes the input image signal of one frame amount, and the frame rate conversion signal generation unit is synchronized with the input image signal according to the -5-200834511 The clock signal, the horizontal synchronizing signal, and the vertical synchronizing signal respectively generate: a clock signal, a horizontal synchronizing signal, and a vertical synchronizing signal after the frame rate of the image signal is converted by a conversion ratio of more than 3 times, and the image signal switching unit is configured according to The switching signal outputted by the switching signal generating unit switches the output signal of the frame memory unit and the image signal fixed at the black level, and then outputs the image, and then the display period of the image of the frame is arbitrarily shortened. . Similarly, Patent Publication No. 2004-37A8 discloses a frequency conversion circuit 1 1 that outputs each frame input every four times at a ratio of four times, and displays each frame output every 2N times. In the liquid crystal display device of the liquid crystal display device 15, the brightness level of each of the conversion frames in each of the conversion frames is converted to a lower one of each of the other conversion frames by the brightness control circuit. The level of the brightness level is supplied to the liquid crystal display element, and the movement lag of the moving picture generated when the original frame is switched is reduced. In the following 'this proposal', this driving method is referred to as an η-speed pulse type driving. [Summary of the Invention] <Problems to be Solved by the Invention> The display device equipped with the η-speed pulse type drive described in the U.S. Patent No. 2004/0 1 5 5 847 must be subjected to n times in the time frame of inputting the display data. Scanning, that is, the rewriting of the output display data, it is necessary to have a η-speed -6-200834511 means for η-speeding the output display data. However, the η speed-up must have a picture frame. That is, a display device equipped with an n-times pulse type drive is compared with a normal display device, and the amount of use of the frame memory causes an increase in cost. In the US Patent Publication No. 2004/0 1 55 847, the data of the first period and the data of the second period are generated inside the display device. Therefore, when the data of the first period and the data of the second period are generated outside the display device, the data is sequentially input to In the case of the display device, the data of the first period and the data of the second period cannot be discriminated, and this is not considered. SUMMARY OF THE INVENTION An object of the present invention is to provide a display device in which an n-times speed increasing circuit is provided outside a display device to reduce the circuit scale. Further, an object of the present invention is to provide a display device capable of discriminating n columns in a frame period when the n-speed-speed circuit is provided outside the display device. - Patent No. 2002 - 2 1 5 1 1 1 and Patent No. 2004 - 3 1 7928, in order to determine the frame of the η speed-up, a switching signal is generated, but the frame memory is written and read. The delay caused is not taken into account. SUMMARY OF THE INVENTION An object of the present invention is to provide a display device which can accurately discriminate a period during a frame period of one frame. <Means for Solving the Problem> The present invention provides a means for arranging the n-speed-speed circuit to be performed not on the display device side but on the signal generating device side. The η-speed-speed display data obtained by multiplying the original input display data η by the signal generating device is output to the display device, and the display device is provided with: performing data conversion processing on the input η-speed-speed display data to perform η Double speed pulse 200834511 The drive circuit of the punch type. At this time, in order to prevent the malfunction of the data conversion processing, there is provided a method of inputting the frame synchronization signal for switching the position of the frame of the original image signal to the display device instead of displaying the data at a speed of η. . Or setting the field repeat detection circuit, the field repeat detection circuit is inside the display device, according to the η speed-up display data, generating a field identification signal for identifying the switching position of the original input display data frame [invention [Effects] According to the present invention, it is a holding type display device and a display system using the same, which can realize display characteristics of a pulse type display device by using n-times speed pulse type driving to obtain a good display with little animation lag. Texture. Further, according to the present invention, in comparison with the case where the display device performs the n-times multiplying pulse type driving, it is possible to provide a lower cost display device and display system. That is, according to the present invention, the n-speed-speed circuit can be disposed outside the display device to reduce the circuit scale of the display device. Further, according to the present invention, even if the n-speed-speed circuit is provided outside the display device, the display device can discriminate the n field periods in the frame period. Further, according to the present invention, since the field period is recognized in consideration of the delay caused by the double speed, the display device can correctly discriminate the time period during the frame period. -8- 200834511 [Embodiment] Next, a display device and a method of constructing a display system of the present invention will be described by way of example. First, the n-speed pulse type driving to which the present invention is applied will be described using Figs. 1, 2, and 3. Next, two configuration examples of the display device equipped with the n-speed pulse type drive will be described with reference to Fig. 4, and the respective problems will be described. Next, a first embodiment of the present invention for solving the above problems will be described with reference to Fig. 6. In the first embodiment, in order to realize the η-speed pulse type driving at a low cost, the display device and the display device are provided by arranging the n-speed-speed circuit on the signal generating device side and outputting the synchronization signal from the signal generating device to the display device. system. Next, a second embodiment of the present invention for solving the above problems will be described with reference to Figs. 7 and 8 . In the second embodiment, a display device and a display system including a frame repeat detection circuit provided in a display device are provided. In the following description of the η-speed-speed pulse type driving, the case of η 2 may be described. However, η is not limited to being set to 2, and may be set to be larger. [Embodiment 1] Fig. 1 is a view showing the processing procedure of the η-speed-speed pulse type driving -9-200834511. As before, it is an example of η == 2. The horizontal axis represents the elapsed time. Table 1A shows that the display data is not entered. The sampled pattern data is sequentially input every 1 frame period. If the frame data is, for example, the image data of the TV signal of the NTSC specification, it is 16. 6 ms, at this time, The frame frequency is 60 Η z 〇 second, The frame frequency of the input display material is n-time multiplied. The 1st map is a data showing the η-speed-speed display after the η-speed is not used to input the frame frequency of the data that is not displayed in the first map. For example, input the display data to NTSC signal. When η is 2, The frame frequency of the η speed-up display data is 1 20 Hz. It is formed that the same input display data is output twice in a time period of one frame period during which the input data is input. at this time, The update interval of the display data is 1 / η frame period. At last, For the η-speed-speed display data, the data conversion for the pulse type driving is performed, Displayed on the display panel. Fig. 1C is an example of display of an η-times pulse type drive. For the data conversion of the η speed-up display data shown in the figure i, Generate and display the first field signal and the second field signal. The display of the first field signal is even brighter than the original input display data. The display of the second field signal is even darker than the original input display data. The display characteristics are pulse type. At this moment, By integrating the time of the first field signal and the second field signal, it is felt that there is a way to control the brightness of the original input display data. Thereby, the reduction in brightness caused by the change in display characteristics is eliminated. Fig. 1D is another example of the display of the η-times pulse type drive. Data conversion is performed on the η-speed-speed display data shown in Fig. 1 Generate and -10- 200834511 Display the first field signal and the second field signal. The display of the first field signal is darker than the original input display data. The display of the second field signal is even brighter than the original input display data. The display characteristics are pulse type. At this moment, By integrating the time of the first field signal and the second field signal, it is felt that there is a way to control the brightness of the original input display data. Thereby, the brightness reduction caused by the change of the display characteristics is eliminated. 〇 The display device is controlled in the above order. Can realize η-speed pulse driving, Even a hold type display device realizes a pulse type display characteristic, Good display quality with very little animation lag. Figure 2 shows the η-speed pulse type drive. A diagram showing an example of the relationship between the brightness of the first field of the input display data and the display brightness of the second field signal (so-called 7 characteristics). The horizontal axis is the hue of the input display data. The vertical axis is the display brightness. The solid line 2 0 1 is an example of a normal driving situation. The dotted line 2 0 3 and the dot-shaped chain line 2 02 are examples of the display brightness of the first field and the display brightness of the second field when the η-speed pulse type is driven. Usually when driving, For example, the display brightness of the input data relative to the tone Dp is Bp, The display brightness of the input data relative to the tone Dq is Bq. Other tones are also examples as shown in Figure 2. Match the hue and display brightness separately. In contrast, When the η-speed pulse type is driven, The display brightness of the first field relative to the input of the tone Dp is B Ip, The display brightness of the second field is Bdp. The display brightness Blp is displayed during the first field. Then -11 - 200834511 shows the display brightness Bdp during the second field, By this, it is adjusted to sensibly display the brightness, which is equivalent to the case where the display brightness Bp is displayed across the frame period. In addition, Display data relative to the input of the tone Dq, The display brightness of the first field is Blp. The display brightness of the second block is Bdp. The display brightness Blq is displayed during the first field. Then the display brightness Bdq is displayed during the second field. By this, it is possible to adjust the sensation display brightness to correspond to the case where the display brightness Bp is displayed across the frame period. The other colors are also the examples shown in Fig. 2. The display brightness of the first field is made to correspond to the display brightness of the second field. In the above example, A bright field for the first field to be relatively brightly displayed, The second field is a configuration of the η double-speed pulse type driving of the dark field in which the dark display is relatively dark. However, it can also be that the first field is a dark field. The second field is the composition of the bright field. The third diagram is a diagram showing an example of a change in the input display material with respect to a certain pixel of the display device. The horizontal axis represents the frame (that is, time). The vertical axis represents the hue. In Fig. 3A, the i-th frame and the i-th frame are represented by the hue Dp. The i+1 frame and the i+2 frame are examples of the input of the tone Dp. For such input display materials, In the past, the display device was driven such that the i-th frame and the i-th frame display the display brightness Bp corresponding to the hue Dp. The i+1th frame and the i+2th frame are displayed in such a manner as to be displayed in a manner similar to the display degree Bq of the color e week Dq. Secondly, An example of the η-speed pulse type driving will be described. -12- 200834511 Figure 3B, Figure 3C, The 3D figure shows the input display data for the 3A image. A pattern of a display device and a processing state of the display system when the η-speed pulse type driving is performed. The third diagram is an example of the η-speed-speed display data when the input display data shown in Fig. 3 is n-speed-speeded. The horizontal axis shows the frame (that is, time) as in the third diagram. The vertical axis represents the hue. The η-speed-speed display data is equivalent to the data of the same input display data that is output n times in the period of the frame of the input display data. Fig. 3C is a view showing an example of a change in display luminance when the display device is driven by the data display processing for the pulse-type driving for the η-speed-speed display data shown in Fig. 3 . The horizontal axis represents the frame (that is, time) as in the third diagram. The vertical axis indicates the hue 〇 In Fig. 3C, the bright field in which the first field is relatively bright is displayed. The second field is an example of the configuration of the dark field in which the dark display is relatively dark. Equivalent to the example of Figure 1 (c). For the η speed-up display data shown in Figure 3, The i-th frame and the first field of the i-th frame are driven in such a manner as to display the display brightness Blp corresponding to the hue Dp. The i-th frame and the second field of the i-th frame are driven in such a manner as to display the display brightness Bdp corresponding to the hue Dp. In addition, The i + 1 frame and the first field of the i + 2 frame are driven in such a manner as to display the display brightness Blq corresponding to the hue Dq. The i-th frame and the second field of the i+2 frame are driven to display the display brightness Bdq corresponding to the hue Dq. -13-200834511 Fig. 3D is a view showing a structural example different from the 3Cth diagram in the case where the display luminance of the display device after the data conversion processing has been performed on the η-speed-speed display data shown in Fig. 3B. The horizontal axis shows the frame (that is, time) as in the third diagram. The vertical axis represents the hue. The 3D figure shows the dark field in which the first field is a relatively dark display. The second field is an example of the configuration of a bright field in which the display is relatively clear. Equivalent to the example of Figure 1 (d). For the η speed-up display data shown in Figure 3B, The i-th frame and the first field of the i-th frame are driven in such a manner as to display the display brightness Bdp corresponding to the hue Dp. The i-th frame and the second field of the i-th frame are driven in such a manner as to display the display brightness Blp corresponding to the hue Dp. In addition, The i+th frame and the first field of the i+2 frame are driven in such a manner as to display the display brightness B dq corresponding to the hue D q . The i-th frame and the second field of the i+2 frame are driven in such a manner as to display the display brightness Blq corresponding to the tone Dq. As shown in Figure 3C, As shown in Figure 3D, The composition of the n-speed pulse type drive, There will be an order of bright and dark fields. Multiple changes in display characteristics are different. the above, The outline of the n-speed pulse type driving of the display device of the present invention and the display system has been described. then, Four configuration examples of a display device and a display system equipped with an η-speed pulse type drive will be described with reference to FIG. And explain each topic. Fig. 4 is a view showing one of the configuration examples of the display device and the display system for realizing the η-speed pulse type driving. In addition, In Fig. 4 -14-200834511, although the LCD is not used as an example of a display device, However, it may be a display device using other display principles. The display system is, for example, a television host or a PC host, Mobile phone host, etc. The display system is provided with a signal generating device 4100 and a display device 4000. The signal generating device 4100 is, for example, a signal processing circuit group in a television or video recorder or a graphics processing circuit group in a PC or a mobile phone. The signal generating device 4100 is provided with a signal generating circuit 4 1 1 0 for inputting the input display data 4112 outputted to the display device 4000 and the input control signal group 4111. The display device 4000 is provided with an n-speed increasing circuit 4010, And data conversion circuit 4030, And timing generation circuit 4050, And frame memory 4020, And a parameter holding circuit 4040, And data line drive circuit 4060, And scan line drive circuit 4070, And a liquid crystal display panel 4080, And the reference voltage generating circuit 4 0 9 0. The display device 4000 is provided with an input input input data 4112 and an input control signal group 4111. The input display data 4112 and the input control signal group 4 1 1 1 The η-speed pulse type drive is used to drive the function of the liquid crystal display panel 4 0 80 . The input control signal group 4 1 1 1 is a vertical sync signal that defines, for example, a frame period (a period in which one screen amount is displayed), A horizontal sync signal that specifies a period of one horizontal scan (a period in which one line is displayed), A valid period signal for the validity period of the data to be displayed, And the -15-200834511 reference clock signal synchronized with the display data. Enter display data 4 1 1 2. The input control signal group 4 1 1 1 is transmitted from the signal generating device 4100 to the display device 4000. The transmission can be applied, for example, to LVDS levels, CMOS level, Various signal levels such as LVTTL level. In the display system, When the signal generating device 4100 and the display device 40 0 0 are far apart from each other, The transmission is preferably a method that uses less noise and can be transmitted over long distances. The η speed-up circuit 4010 is a frame frequency for the input display material 4112, A circuit for generating an η-speed-speed display data 4 0 1 2 that has doubled the frame frequency η is generated. More specifically, The η speed-up circuit sequentially stores the input input display data 41 12 to the frame memory 4020. on the one hand, When reading the amount of data stored in the i frame period, Read out during the time that η has been divided during the 1 frame. and then, Performing the aforementioned read operation n times during the frame period, It is possible to achieve η multiplication of the frame frequency. The input display data read out for the first time is used as the η multi-speed display data for the first field. The input display data read out for the second time is used as the n-times speed display data for the second field. The figure 4021 is a write data written to the frame memory 4020. The reference numeral 4022 is read data read from the frame memory 4G20. In addition, The η speed-up circuit 4010 generates a field identification signal 4013 and an η-speed control signal group 40 11 . The field identification signal 4 0 1 3 is synchronized with the η speed-up display data 4 0 1 2 , It is used to identify whether the η-speed-speed display data 40 1 2 is the η -16-200834511 double-speed display data for the first field or the η-speed display data for the second field. That is, the field identification signal 40 13 is synchronized with the read clock from the display data of the frame memory 4020. The η-speed control signal group 40 1 1 is defined by, for example, a η-times vertical synchronization signal during a frame period, Specify a η-speed horizontal synchronization signal during 1 horizontal scanning, Specify the effective period of the data for the valid period of the η-speed display data. And an η-speed clock signal synchronized with the η-speed display data. The frame memory 4020 is a memory element having a capacity for storing at least one frame of display material. Write input data, η Speed-up display data readout processing. The frame memory 4020 can use, for example, various DRAM (dynamic random access memory) data conversion circuits 4030 to generate a circuit for performing the above-described n-speed pulse driving block change data 4032. The η speed-up display data 4012 outputted from the η-speed increasing circuit 4010 is received as an input. The aforementioned n-speed-speed display data 40 12 is based on a predetermined data conversion rule. The unit transformation data 4032 for each field is converted. Here, The foregoing data transformation rule is as n field transformation parameters 4041, 4042, It is input to the data conversion circuit 4030. The data conversion circuit 4030 identifies the field by the field identification signal 4013. Select the parameters for the respective fields. The first field conversion parameter 4041 determines the aforementioned data conversion rule for the first field. -17- 200834511 The second field transformation parameter 4042 determines the pre-transformation rule for the second field. A case where a frame is divided into 2 blocks by η-speed pulse type driving, It is best to prepare the η for each field separately. The data transformation rule is to measure the number of divisions η of the frame, Display ambient temperature, The temperature of the liquid crystal display panel, The reference voltage is set to the length of the frame period, The length of each field period, etc., And the outline or color difference does not occur, The party that obtains good display quality is determined locally. The data conversion rule can also be specified by an arithmetic expression of the above various conditions. It can also be specified by referring to a lookup table in the above various indexes. In addition, The data conversion circuit 403 0 adjusts the timing from the manner in which the η-speed control signal group 4011 input from the η-times 4010 is synchronized with the change data 4032. It is output as the field conversion signal group 4032. The timing generation circuit 4050 receives as input the field conversion data control signal group 403 1 and the field change 4032 outputted from the data conversion electric S. then, Is based on the foregoing field conversion signal group 4031 and the aforementioned field transformation data 4032, Generating data line drive circuit 4 0 6 0 data line drive circuit control signal I, And output display data group 4 0 5 2 And a circuit for controlling the scan line driver circuit of the scan line driver 40 70 to control the signal group 4053. The data of more than one field change device 1 make false, Appropriate parameter is the circuitized circuit field variable data control each 4 0 3 0 change data control to control ocean 405 1 moving circuit -18- 200834511 parameter holding circuit 4040 will contain the field conversion used by data conversion circuit 4030 Parameter 4041 The circuit of the 4042 is set to maintain various parameters. In addition, Further, it is provided with a function of reading out the aforementioned various setting parameter data from an external memory circuit (not shown). The parameter holding circuit 4040 is provided with a memory element group such as a register file or a random access memory. And the control circuit of the memory circuit. A memory circuit (not shown) is a circuit used to memorize the various setting parameters described above. Various non-volatile memories such as a ROM (read only memory) or an EEPROM (Electrical erasable programmable ROM) flash memory can be used. The data line drive circuit control signal group 405 1 is an output timing signal that specifies, for example, an output timing of the tone voltage of the output display data 1 052 and an alternating current signal that determines the polarity of the power supply voltage, It is composed of a clock signal synchronized with the displayed data. The scanning line driving circuit control signal group 4 0 5 3 is a g-bit signal which is specified by, for example, a 1-line scanning period, A vertical start signal or the like for specifying the start of scanning of the head end line. Figure 4090 is a reference voltage generation circuit. Figure 4091 is the reference voltage. The data line drive circuit 4 〇 6 0 generates a potential corresponding to the number of displayed hue from the reference voltage 4 0 9 1 . And selecting a potential of 1 level corresponding to the output display data 4052, It is applied as a data voltage to the liquid crystal display panel 4 0 80 . Figure 4 0 6 1 is the data voltage generated by the data line driven by the data line -19- 200834511. Drawing No. 4 0 70 is a scanning line driving circuit, Figure 4071 is the scan selection signal. The scan line driving circuit 4070 generates a scan line selection signal 407 1 according to the scan line driving circuit control group 4053. It is output to the scanning line of the liquid crystal display panel 4080. Drawing No. 4080 is a liquid crystal display panel. Figure 408 1 is a schematic diagram of one pixel of the liquid crystal display. One 4〇81 of the liquid crystal display panel 4080 is made up of a source, Gate, TFT (thin transistor) composed of bungee And the liquid crystal layer, The counter electrode is constructed. Add the scan to the gate, Thereby switching the TFT, The TFT is open, The data voltage is written via the source to the drain electrode connected to one of the liquid crystal layers, When the TFT is in the closed state, Maintain the voltage written to the drain. The voltage at the drain is Vd. The counter electrode voltage is VC0M. The liquid crystal layer is based on a potential difference between the drain voltage Vd and the counter electrode voltage VC0M, Change the direction of light, And via a polarizing plate disposed above and below the liquid crystal layer, To change the amount of light transmitted from the backlight disposed on the back side and perform a hue 〇 An example of the configuration of a display system for realizing η-times-speed pulse driving has been described using FIG. 4A. but, The composition of Figure 4, There is a problem in that it is necessary to provide an n-times circuit 4010 and a frame memory 4020 on the display device 4000 side. The lift of the display device 4000 is caused. on the one hand, The fourth figure is shown to be used to realize the η-times pulse line selection signal display surface pixel f i lm number. This is a diagram of another example of the configuration of the system that is not biased by the speed-changing cost driving -20-200834511. Comparing with the configuration of Fig. 4A, the difference is that the n-speed-speed circuit 4510 and the frame memory 4520 provided on the side of the display 45 00 are on the side of the signal generating device 460 0, η speed-up display data 4 5 1 2 speed control signal group 4 5 1 1, It is transmitted from the signal generating device to the display 4500. The η speed-up is not the same as the 4512, which is the same display data. Other aspects are the same as the composition of Figure 4. The parts of the parts are omitted. general, The signal generating device must perform various format conversions, image resolution conversion, Interlace - progressive (progre) transformation or image correction processing (end edge enhancement, Signal processing such as tone correction), Therefore, a signal circuit having higher performance than the display device is mounted. thus, The cost of loading the n-speed-speed circuit or memory on the signal generator side, It is still less than the cost of mounting the n-fold circuit or frame memory on the display unit side. That is, if the η-speed circuit or the frame memory is placed on the signal generating device side, The entire system can be implemented at a cost. but, In the case of the composition of Fig. 4(B), The input display data 4612 and the input control signal 4611 are input to the display device side by inputting the η speed-speed display data 45 12 and the η-speed control signal group. Therefore, the device 470 0 side cannot recognize the entry of the input data 4612. That is, there is a problem in that it is impossible to synchronize the first field and the second field with the paragraph of the frame. It is not possible to arbitrarily control the data conversion result of the data conversion 4530 to be the display arrangement and the η device description of the 3Cth and 3Dth drawings (Fig. ssi ν e complex processing frame speeding lower 4500 45 11 display frame The cut circuit side of the-21 - 200834511. That is, there is no state, Regardless of the bright field in the first column of Figure 3C, The second field is a dark field. In other states, Like the 3D Tudi 1 field becomes a dark field, The status of the second field becomes a bright field and cannot be controlled randomly. It is possible to fall into such a state. Such a situation, In the case of the third C and the case of the third D, Due to different display characteristics, Therefore, regardless of whether the input display data 4612 is the same, Still happening: The displayed image is randomly changed due to the state of the display system (such as the power-on timing). In addition, The input display data 4612 itself also undergoes various changes in accordance with the operation of the signal generating device 4600 and the like. Listed are: For example, when the receiving channel or image source of the TV is switched, Or the video recorder performs changes caused by irregular display such as fast reproduction or rewinding. When such an operation is performed, the display characteristics of the display system are randomly switched to one of the 3C map or the 3D map. Lead to uncertain defects. Based on the stability of the display, Preferably, the display device constitutes the display system in such a manner that the display characteristics can be arbitrarily controlled. That is, there must be a paragraph that identifies the frame in which the input data is displayed. And the organization that synchronizes the switching of the fields. the above, Two configuration examples of a display device and a display system equipped with an η-speed pulse type drive have been described. And individual topics. Secondly, Use the fifth, Fig. 6 is a view showing a display device and a display system of the present invention for solving the above problems. Fig. 5 is a view showing that the above problem is solved and the η-speed pulse type driving is realized. A diagram showing a configuration example of a display system and a display device -22-200834511 of an embodiment of the present invention. Compared with the composition of Figure 4A, The different points are that the η multiplying circuit 5010 and the frame memory 5020 provided on the display device side 5000 are disposed on the signal generating device 5 1 00 side. In addition, The different points are η speed-up display data 5012 and η-speed control signal group 5011 and input control signal 5111, It is transmitted from the signal generating device 5100 to the display device 50 00. In addition, The different points are the interception identification signal input to the data conversion circuit 503 0 which is not used to generate the switching of the frame for identifying the input display data 5 1 1 2 via the η speed increasing circuit 5010. Instead, the field identification signal generating circuit 5 20 0 is generated from the original input control signal 5 1 1 1 to generate the field identification signal 5 0 1 3, The field identification signal 5013 is generated based on the input control signal 5111. The other aspects are the same as those of Figure 4, The description of each part is omitted. In addition, Compared with the composition of Figure 4, The different points are also the original input display data 5 1 1 2 input control signal 5 1 1 1, It is transmitted from the signal generating device 5100 to the display device 5000. As mentioned above, Based on the view of display stability, The display device 5000 is constructed at least in such a manner that the display characteristics of the η-speed pulse type driving can be arbitrarily controlled. thus, It is necessary to recognize the paragraph of the frame where the input data 5 1 1 2 is entered. But in order to identify, Input control signal 5 1 1 2 using the input display data 5 1 1 2 It's both simple and effective. For example, the input vertical sync signal of one of the input control signal groups 5111 is a signal of a frame period of the specified input display data 5 1 1 2, Therefore, it is suitable for identifying the switching of the input frame -23- 200834511. Based on the aforementioned input vertical sync signal, The field identification signal generating circuit 5200 is used to generate the field identification signal 5013. If it is used to identify the field, The defect that the display characteristics of the display system are randomly changed can be solved. A stable display is possible. In addition, It is also possible to use the other signals of the input control signal group 5 1 1 1 instead of the input vertical sync signal. the above, A configuration example of a display device and a display system using an embodiment of the present invention has been described using Fig. 5. Figure 6 is a view showing an operation example of a display device and a display system according to an embodiment of the present invention. Further, it is an example of an operation time chart of the display device and the display system shown in Fig. 5. The horizontal axis in Fig. 6 indicates the time. First of all, From the signal generation circuit 5110, Output input display data 5 11 2 and input control signal group 5 1 1 1. The example of Fig. 6 shows an input vertical sync signal 601 and an input display material 5112 of one of the input control signal groups 5 1 1 1 . Input vertical sync signal 601 is the signal during the specified frame period. And the event is generated in synchronization with the switching of the frame of the input display data 5 1 1 2 . In addition, In Figure 6, The symbol D(i) represents the input display material of the i frame. same, For example, D ( i + 1 ) indicates the input display data of the i + 1 frame. Input display data 5 1 1 2 is in units of 1 frame period, According to D ( i ), D(i+l), D(i+2) - the order of one, Enter the data for each frame -24- 200834511 in order. Secondly, The above-described n-speed-speed processing is performed by the above-described n-speed increasing circuit 5010. The example of Fig. 6 is an illustration of the n-times vertical sync signal 6 1 1 of one of the n-times multiple speed control signal groups 5011 generated by the n-times speed increasing circuit 5010, And η speeding display data 5 0 1 2 And the field identification signal 5 0 1 3 generated according to the input vertical synchronization signal 601 via the field identification signal generating circuit 5 2G0. The η-times vertical sync signal 6 1 1 is a signal for specifying a period of 1 column of the data display 5012. And the event is generated in synchronization with the switching of the frame of the n-times speed display data 5012. In addition, As shown in the example in Figure 6, During the input of the vertical sync signal 601 and the input display data 5112 and the n-times vertical sync signal 611 and the η speed-up display data 5012, Generally, delays are caused by the η-speed processing. After the event of inputting the vertical sync signal 601 occurs, During the period from the initial event of the η-times vertical sync signal 6 1 1 to the beginning of the field of the first item, This delay is caused, for example, by the timing at which the n-times speed increasing circuit 5 0 1 0 is written to the frame memory 5 0 2 0 and the timing of the read timing. The η-speed-speed circuit 5 010 can write the display data of the I/η frame amount to the timing of the frame memory 5 020. Next, the display data of the I/η frame amount is read from the frame memory 5020. then, The η-times speed increasing circuit 501 0 can start at the time when the display material is written in the frame memory 5020, and is shorter than one frame period. Start reading the data from the frame memory 5 0 2 0. The field identification signal generating circuit 5 2 0 0 generates the field identification signal 5013 according to the input vertical synchronization signal 25-200834511 No. 6 01. The field identification signal 5013 is used to identify the field. This embodiment is an example showing division of one frame into two fields of the first and second fields. Therefore, the field identification signal 6 1 3 can be used during each field. For example, the signal level (low) indicating the first field, And the two signals indicating the signal level (high) of the second field are composed of signals that change over time. Field identification signal 5013 when η 2 is 2, For example, it is generated in the following order. First of all, set up: The field identification ready signal 612 is synchronized with the n-times vertical sync signal 611 to invert low and high. and then, The field identification preparation signal 612 is constructed in such a manner as to be set to high in synchronization with the input vertical synchronization signal 601. then, The field identification signal 50 1 3 can be synchronized with the η-speed vertical sync signal 6 1 1 1 to lock the field identification ready signal 612. As shown in Figure 6, The first field is low, The second field is composed of high. According to such a configuration, For some reason (for example, if the display system is a TV, Switch channels, If it is a video recorder, Performing a fast rewind operation, etc.) and changing the input control signal group 5111 or inputting the display material 5 1 1 2, Resulting in the field identification signal 5 0 1 3, The field recognition preparation signal 6 1 2 also becomes unstable or even becomes abnormal. Even in the normal state of field identification, When the input of the vertical sync signal 60 1 is accepted, Still available from the next field, Start the normal field recognition action again. Therefore, the stability of the operation of the display device is improved. the above, An example of using the input vertical sync signal 6 0 1 has been cited -26- 200834511, A method for generating a block identification signal 5 0 1 3 by using the field identification signal generating circuit 5200 is described. However, the method of generating the field identification signal of the present invention is not limited thereto. then, By the data conversion circuit 503 0, For the aforementioned η speed-speed display data 5 0 1 2, Implement data transformation processing. The data conversion circuit 5030 accepts the field identification signal 5 013 outputted from the field identification signal generating circuit 5 20 0, And the η speed-up display data 5012 output from the η speed increasing circuit 5010 is output. The data conversion circuit 5030 identifies the first field or the second field based on the field identification signal 5013. When the η speed-up display data is the first field (that is, when the field identification signal 5 01 3 is low), Data conversion is performed according to the first field transformation parameter 5 04 1 , When the n-speed display data is the second field (that is, when the field identification signal 5013 is high), Data conversion is performed according to the second field conversion parameter 5042. In addition, An example of a η-speed pulse type drive with η = 2 has been described here. Therefore, the above-mentioned field identification signal becomes two 反 repeated change signals ’ when η is 3 or more, Preferably, the aforementioned field identification signal is realized by counting the number of column digits, etc. In Figure 6, The field conversion vertical synchronization signal 621 of one of the field conversion control signal groups 5031 generated by the data conversion circuit 5030 is illustrated. And the block change data 5 03 2. The field change vertical sync signal 621 is a signal for specifying one field of the field change data 5032. In addition, In Figure 6, The symbol FI (i) indicates the data that has been transformed by the data for the η multi-speed display data of the i-th frame. Same -27- 200834511, For example, the symbol FI (i + 1) indicates the data that has been transformed by the data for the n-th display of the i-th frame. On the one hand, in the picture, The symbol F d ( i ) indicates the data that has been transformed with the data for the dark field of the n-th speed frame of the i-th frame. same, For example, Fd(i+1) indicates the data that has been transformed by the data for the dark field of the n-th speed frame of the i+1 frame. In addition, in Figure 6, Indicates that the first field is a bright field. The second is an example of a dark field. However, it can also be that the first field is a dark field. The field is the composition of the bright field. At last, Timing generation circuit 5050, The output display data 5032 is generated based on the field conversion data (not shown in Fig. 6). In addition, The timing generation circuit 5 0 5 0 is based on the field conversion control signal group 5 03 1 generated by the data conversion circuit. Generate output control message 505 Bu In addition, As shown in Figure 6, Η-times vertical sync signal 6 1 1 speed-up display data 5012 and field change vertical sync signal 621 bit change data 5 032 period, It is generally delayed due to data conversion processing. Forming the display device as in the above manner, Thereby, the speed pulse type driving can be realized. The animation hysteresis of the moving portrait can be reduced: The quality of the picture. [Embodiment 2] Next, Use the seventh, Figure 8 is a view showing the second embodiment of the present invention, The first picture number is given to the field. No. 2 5032 5030 group and η and column cause η times good form -28- 200834511 Figure 7 shows the above-mentioned problem for solving the above-mentioned problem. A diagram showing a configuration example of a system and a display device according to an embodiment of the present invention. Compared with the composition of Figure 4, The different point is to set the field repeat detection circuit 72 10 on the display 700 0 side, To replace the control signal 7111 that will be entered into the display data 7112, The signal generating device is input to the display device 7000. In addition, The different points are η speeding data 70 12 and η-speed control signal group 701], The signal generation 7100 is transmitted to the display device 7000. The other points are the same as those in the fourth drawing. The configuration of the fourth diagram has been described above. The explanation of the fact that the original input display data 7 1 1 2 cannot be recognized in the subject has been described. The structure of Fig. 7 is a means of providing a solution to the problem. In the example in Figure 7, The display device 7000 is provided with a field repeating circuit 7210. The field repeat detection circuit 7210 is provided with an input speed display data 7012 and an η-speed control signal group 701 1, Detecting the repetition of the field of the accelerated display data 7012, When the same content is overlaid, Recognizing that the original input display data 7112 is the same frame. When the same content field is not returned, Recognized that the field has been switched, The result is output as the field identification signal 70 1 3 . Fig. 8 is a diagram showing a configuration example of the field overlap detecting circuit 72 1 0. The block repeat detecting circuit 72 1 0 is provided with: Field feature quantity pumping 810, Field feature quantity deviation degree operation circuit 830, The field is reversed and the display device's input 7100 display device is the same. in, The frame should be checked for η times η times the bit position, When you don't end up. Power-on identification -29- 200834511 circuit 840, Memory 820. The field feature quantity extracting circuit 8 1 0 extracts the feature quantity 811 indicating the feature of each field of the n-speed-speed display data 7012. The feature quantity 811 is a characteristic indicator indicating image data. Can be applied: Such as the average brightness level, Maximum brightness level, Luminance distribution histogram 'spectral distribution, The meaning of the information is 値, The lengthy symbol of the tour of the data, Reduction of image data, etc. Alternatively, a vector in which these plural numbers are combined may be used as a feature quantity. Further, the amount of data of the aforementioned feature amount is preferably less than the amount of data of one field of the n-speed display data. The memory 820 is provided with a feature amount 8 1 1 in which the current field extracted by the aforementioned field feature amount extracting circuit 8 1 写入 is written. The function of the feature amount 821 of one previous field is read. The memory 820 is provided with a memory capacity that maintains the aforementioned feature amount for at least one field period. Here, As mentioned above, The amount of data of the aforementioned feature quantity is less than the amount of data of one field amount, Therefore, the memory 820 can be realized by less than the capacity of the frame memory. The memory 820 can be reduced in cost. For example, various DRAM (dynamic random access memory) and the like can be used. The field feature quantity degree deviation calculation circuit 830 performs the feature 811 of the current field and the feature quantity 821 of the previous field. Comparison, Operation, Calculate the circuit of the above two fields with a degree of deviation of 8 3 1 . For example, the difference 特征 of the feature amounts of the above two fields can be used as the degree of deviation 831 of the two fields. Or when the aforementioned feature quantity is a vector having a plurality of dimensions, For example, the remainder -30 - 200834511 of the angle between the feature quantity vector of the current field and the feature quantity vector of one previous block can be used as the deviation of the two fields 83 1 . The field repeat recognition circuit 840 is separated from the field feature quantity by 831, Identification: The above two fields are consistent, Is it a reversal, Or the above two fields are inconsistent, That is whether to switch to the original. For example, when the degree of deviation 83 1 is smaller than a specific threshold, Can identify that the fields are to be repeated, Or at a degree of deviation 831 greater than the aforementioned specific one, It is possible to recognize that the original frame is to be switched. In this way, The field identification signal 7 0 1 3 can be used. Receiving the field identification signal 701 3, The data path 703 0 shown in Fig. 7 can be changed by appropriately selecting the parameters of the appropriate fields in a timely manner. In addition, The operation of the display device and the display system shown in Fig. 7 is the same as the example of the time chart shown in Fig. 6, Therefore, the explanation is omitted. The field identification signal 70 1 3 is equivalent to the field identification signal 6 1 3 or more. A configuration example to which an embodiment of the present invention is applied has been described. As the above constitutes the display device and the display system, Thereby, it can be driven by the η-speed pulse type shown in FIG. 1 . A good display quality with very late lag can be obtained. [Embodiment 3] Secondly, Use the second 5, 6 and 9, · 1 to illustrate the signal generation device for the frame rate conversion device, The example frame rate converting means in the case of the present technique is a frame which is as large as the same column as the Japanese Patent Laid-Open 2003-degree, and the second threshold is used to generate the transformed electric data. Because. The sixth item shows the device implementation, such as less animation, containing the image. As described in Figure 333540 -31 - 200834511, a device for generating an image signal between frames by applying a motion vector or the like from an image signal between frames. By applying the aforementioned technology to a liquid crystal display device, It can be as described in Japanese Patent Laid-Open Publication No. 2003-0333. In the case of PAL-NTSC transformation, Reduced motion jitter is achieved. and then, For example, 6 0 Η z — 1 2 0 Η z transformation, Can achieve an improvement in animation lag. When converted to 60 Hz - 120 Hz, As shown in Figure 9, According to i-1, i, The display data consisting of 60 Hz as shown by i+Ι, Generated as shown in Figure 9B - 0. 5 — The 120 Hz double speed display data shown. Hereinafter, in the figures 9A and 9B, the numbers denoted by i-1, i, i+Ι, and the display materials indicated by the integers are referred to as real frame display materials, and notes i 〇·5, i_0. The number of 5, the non-integer does not show the data is called the interpolation frame. . In the real frame display data, the same frame with the same number of A and B is the same display data, and the signal generating device including the above frame rate converting device may contain the n-speed increasing circuit 5 0 1 0 of FIG. . In this case, the real frame of the i-th frame item is displayed and the real frame display data of the i + 1 frame item is generated, and when the interpolation frame of the i + 0 · 5 frame item is generated, the input is input. The timing relationship between the display data and the 2x speed display data is such that the display start position of the real frame image shown in Fig. 1 is delayed by 1 frame period amount. In this case, in the display system shown in Fig. 5, when the signal level of the field identification signal 50 13 is Low, the frame can be referred to as an interpolation frame display material. The data conversion circuit 5 0 3 0 accepts the field identification signal 5013 outputted from the field identification signal generation circuit -32-200834511 52 00 and the double speed display data 5 outputted from the double speed improvement circuit 5 0 1 0 0 1 2 is used as input. The data conversion circuit 5 〇3 0 identifies the real frame or the interpolation frame according to the field identification signal 5 0 1 3, and if the data is displayed in a real frame at 2 times speed (ie, the field identification signal 5 0 When 1 3 is H igh, the data conversion of the characteristic 203 which should become the bright field of the second figure is performed, and if the data of the double-speed display is the information of the interpolation frame display (that is, when the field identification signal 5013 is Low) ), the data transformation of the characteristic 202 which should become the dark field of the second figure is performed. In this way, in the present embodiment, the data is displayed in a real frame to be a bright frame, and the interpolation frame is displayed in such a manner that the data becomes a dark frame. Interpolation frame The display data is generated based on the actual frame display data. Therefore, the input frame display data is compared with the equivalent real frame display data, and the theoretical correctness will be reduced. In this regard, as described in the first embodiment, in the pulse type driving method of the present invention, since the average luminance is observed for the η frame (n = 2 in the case of the present embodiment), the interpolation with low accuracy is low. The frame display data is a dark field, so that even if the correct interpolation is not performed, the image can be suppressed from being scattered due to the incorrectness, and further, since the pulse direction of the moving direction in which the line of sight is added is performed, It is possible to reduce the so-called suspected contour that becomes the subject of the impulse response. [Industrial Applicability] The present invention can be applied to a display device of a television set. BRIEF DESCRIPTION OF THE DRAWINGS -33- 200834511 FIG. 1 is a view illustrating the η-speed pulse type driving of the present invention, and FIG. 2 is a view showing the corresponding color and display brightness of the η-speed pulse type driving of the present invention. A diagram of the example. Fig. 3 is a view showing an example of a change in the display luminance of the input display data of the η-times pulse type driving of the present invention and the case where the input display data is subjected to the η-speed pulse type driving. Fig. 4 is a view showing an example of a configuration of a display device and a display system including the n-times multiply pulse type driving of the present invention. Fig. 5 is a view showing an example of the configuration of a display device and a display system according to the first embodiment of the present invention. Fig. 6 is a view showing an operation example of the display device and the display system according to the first embodiment of the present invention. Fig. 7 is a view showing an example of the configuration of a display device and a display system according to a second embodiment of the present invention. Fig. 8 is a view showing an example of the configuration of a field overlap detecting circuit of the display device according to the second embodiment of the present invention. Fig. 9 is a view showing the concept of the double-speed pulse driving of the third embodiment of the present invention. Fig. 10 is a view showing an operation example of a display device and a display system according to a third embodiment of the present invention. [Description of main component symbols] 4 1 1 2, 46 1 2, 5 1 1 2, 7 1 1 2 : Input display data -34- 200834511 4 1 1 1 , 46 1 1 , 5 1 1 1 , 7 1 1 1 : Input control signal group 4 010, 4510, 5010, 7010: η speed-up circuit 401 1 , 45 1 1 , 50 Η, 7011 : η-speed control signal group 4012, 45 12, 5012, 7012 : η speed-up display data 4021 4521, 502 1, 7021: write data 4022, 4522, 5022, 7022: read data 4013, 5013, 7013: field identification signals 4030, 4530, 5 030, 703 0: data conversion circuits 4032, 4532, 5032 , 7032: ff edge conversion data 4041, 4242, 4541, 4542, 5041, 5042, 7041, 7042: field conversion parameters 4050, 455 0, 5050, 7050: timing generation circuits 4051, 4551, 5051, 7051: data lines Drive circuit control signals 4052, 4552, 5052, 7052: output display data 4070, 4570, 5070, 7070: scan line drive circuits 4080, 4580, 5080, 7080: liquid crystal display panels 408 1, 45 8 1, 508, 708 1 : LCD panel pixel 4 0 6 0, 4 5 6 0, 5 0 6 0, 7 0 6 0 : data line driver circuit 4 061, 4561, 5 0 61, 70 6 1 : data voltage 4070, 4570, 5070, 7070: scan line drive circuit 407 1 , 457 1 , 507 1 , 707 1 : scan line selection signal 4 0 9 0, 4 5 9 0, 5 0 9 0, 7 0 9 0 : reference voltage generating circuits 4091, 4591, 5091, 709: reference voltage -35- 200834511 4020 ^ 452 0, 5020, 7020: frame memory 4021, 4521, 5021, 7021 : Write data 402 2, 452 2, 5 022, 7022: Read data 4040, 4540, 5040, 7040: Set parameter holding circuits 4041, 4042, 4541, 4542, 5041, 5042, 7041 ' 7042: various setting parameters 5200 : Field identification signal generation circuit 72 10 : Field repeat detection circuit ® 810 : Intercept feature quantity extraction circuit 8 1 1 , 8 2 1 : Feature quantity 830 : Field feature quantity deviation degree operation circuit 8 3 1 : Deviation degree 840: Field recognizing circuit -36-