TW200822821A - Method for fabricating punch type leadless IC packages - Google Patents
Method for fabricating punch type leadless IC packages Download PDFInfo
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- TW200822821A TW200822821A TW95142008A TW95142008A TW200822821A TW 200822821 A TW200822821 A TW 200822821A TW 95142008 A TW95142008 A TW 95142008A TW 95142008 A TW95142008 A TW 95142008A TW 200822821 A TW200822821 A TW 200822821A
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- lead frame
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- 238000000034 method Methods 0.000 title claims abstract description 24
- 238000004080 punching Methods 0.000 claims abstract description 46
- 238000007747 plating Methods 0.000 claims abstract description 18
- 235000012431 wafers Nutrition 0.000 claims description 27
- 238000004519 manufacturing process Methods 0.000 claims description 23
- 238000007789 sealing Methods 0.000 claims description 17
- 239000000565 sealant Substances 0.000 claims description 14
- 238000005520 cutting process Methods 0.000 claims description 5
- 238000010276 construction Methods 0.000 claims description 4
- 238000009713 electroplating Methods 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 3
- 101150095744 tin-9.1 gene Proteins 0.000 claims 1
- 239000008393 encapsulating agent Substances 0.000 abstract description 9
- 238000007373 indentation Methods 0.000 abstract 3
- 238000005336 cracking Methods 0.000 abstract 1
- 230000000903 blocking effect Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- 239000000969 carrier Substances 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000005242 forging Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000000178 monomer Substances 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 238000012858 packaging process Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000084 colloidal system Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000001066 destructive effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- JEIPFZHSYJVQDO-UHFFFAOYSA-N iron(III) oxide Inorganic materials O=[Fe]O[Fe]=O JEIPFZHSYJVQDO-UHFFFAOYSA-N 0.000 description 1
- 235000013372 meat Nutrition 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- -1 tin-hetero Chemical compound 0.000 description 1
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
200822821 九、發明說明: 【發明所屬之技術領域】 本發明係有關於半導體封裝技術之 * 化分離 (singulation),特別係有關於一種沖裁式 之製造方法。 .,、、外引腳封裝構造 【先前技術】 在目前的半導體封裝製造技術中,先將複數個載體單元 集成在-基材以供進行封裝製程,是相當常見的且符合細 效率。當大部份的封裝製程完成之後,方進行單體分離:以 分離出複數個半導體封裝構造。譬如說,使用導線架作為美 材製作出無外引腳封裝構造(leadless IC帅㈣亦是: 此’在製程最後進行單體分離。就已知的分離種類無外引 腳封震構造可進-何別為沖裁式(punehing t㈣與錯切式 (sawing type)。其中在沖裁式無外引腳封裝構造中,複數個 ㈣體係個別形成,以沖裁導線架㈣之方法便可達到單體 ^離之效果°而_式則是以-封膠體連續覆蓋所有載體單 多頁 古、由 、巧迷疑轉的鋸切刀同時切斷封膠體與引腳,對於 刀具的磨損影響較大且較耗時。 人第1圖所不’習知沖裁式無外引腳封裝構造是以一次 '的動作凡成單體分離,導線架110固定在一沖裁設備 之栽台11上,拍、 座以沖裁刀12 —次切斷該導線架110之引腳 1置1 而不會士刀$|f 預疋形狀之封膠體130。配合參閱第2圖,200822821 IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention relates to singulation of semiconductor packaging technology, and more particularly to a method of manufacturing a punching type. .,,, and external pin package construction [Prior Art] In the current semiconductor package manufacturing technology, it is quite common and consistently to integrate a plurality of carrier units on a substrate for a packaging process. After most of the packaging process is completed, the cell separation is performed to separate a plurality of semiconductor package structures. For example, using a lead frame as a US material to make an external lead-free package structure (leadless IC handsome (4) is also: This is the final separation of the monomer at the end of the process. The known separation type has no external pin seal structure can enter - What is punehing t (four) and sawing type. In the blanking type external package structure, a plurality of (four) systems are formed separately, and the method of punching the lead frame (4) can be achieved. The effect of the monomer ^° is _ type is that the sealant continuously covers all the carriers, and the single-page, ancient, and singular sawing cutter cuts the sealant and the pin at the same time, which affects the wear of the cutter. It is large and time consuming. The first figure does not have a conventional punching type external lead package structure which is separated by a single action, and the lead frame 110 is fixed on a table 11 of a punching device. The squeegee and the squeegee are cut into 12 times, and the lead 1 of the lead frame 110 is cut off, and the sealing body 130 of the pre-cut shape is not used. Referring to FIG. 2,
習知沖裁式I …、1" 5丨腳封裝構造100主要包含該導線架110之 一部位、一 a 日乃120、以及一封膠體13〇。該晶片12〇係設 5 200822821 置於該導線架110並藉由複數個銲線121電性連接至該些引 腳ill。模封形成該封膠體130,其係密封該晶片12〇並結 合該些引腳1 1 i,但該些引腳u丨之上表面應稍露出,以供 沖裁。該些引腳丨丨〗之下表面亦必須為顯露狀,可供表面接 合。在沖裁之前,一電鍍層14〇係先形成於該些引腳之 稍露出上表面與下表面,以避免引腳ln銹化並有助於銲The conventional ramming type I ..., 1 " 5 foot package structure 100 mainly comprises a portion of the lead frame 110, a day 120, and a gel 13 〇. The wafer 12 is placed on the lead frame 110 and electrically connected to the pins ill by a plurality of bonding wires 121. The encapsulant forms the encapsulant 130, which seals the wafer 12 and bonds the pins 1 1 i, but the upper surface of the pins u should be slightly exposed for punching. The surface under these pins must also be exposed for surface bonding. Before the blanking, a plating layer 14 is formed on the upper surface and the lower surface of the pins to avoid rusting of the pins and to facilitate soldering.
接。然而如第1圖所示,在習知的沖裁過程中,沖裁刀U 對該些引腳111之沖切力量會導致引腳1U容易由該封膠體 13 0剝離,甚至掉落的問題發生。此外,如第2圖所示,在 該些引腳111之沖裁面會有毛邊現象,容易刮傷人體或電子 元件。 【發明内容】 本發明之主要目的係在於提供一種沖裁式無外引腳封裝 構造之製造方法,用以解決習知單程沖裁的製程中會引起沖 裁式無外引腳封裝構造之引腳剝離、掉落與毛邊等問題,故 能提昇製程良率,更可增加引腳之電鍍面積。 本發明的目的及解決其技術問題主要是採用以下 技術方案來實現的。依據本發明揭示一種沖裁式無外引 腳封裳構造之製造方法。首先,提供一具有複數個載體單元 之導線架,每一載體單元内係形成有複數個⑽,在相鄰载 體單元之間係可形成有一堵住桿(dambar)。再將複數個晶片 設置至該導線架,並以適當方式使該些晶片電性連接至該此 引腳。之後,個別形成複數個封膠體於對應之該些載·體: 元,以結合該些引腳但顯露該些堵住桿。在封膠之後,進= 6 200822821 一半沖裁步驟,沿著該些封膠體之外周緣形成複數個半凹缺 口於該些引腳。之後,進行—電❹驟,形成―電鑛層於該 些引腳包含該些半凹缺口之外露表面。最後,進行一全沖裁 步驟,沿著該些半凹缺口切斷該些引腳,而分離成個別之封 膠體。另揭示依上述製程所製成之沖裁式無外引腳封裝構Pick up. However, as shown in FIG. 1, in the conventional blanking process, the punching force of the punching knife U on the pins 111 causes the pin 1U to be easily peeled off by the sealing body 130, and even falls. occur. Further, as shown in Fig. 2, there is a burr phenomenon on the punched faces of the pins 111, which easily scratches the human body or electronic components. SUMMARY OF THE INVENTION The main object of the present invention is to provide a manufacturing method of a blanking type external lead package structure, which is used to solve the problem that a conventional one-way blanking process causes a blanking type external lead package structure. Problems such as peeling, falling and burrs of the foot can improve the process yield and increase the plating area of the pins. The object of the present invention and solving the technical problems thereof are mainly achieved by the following technical solutions. SUMMARY OF THE INVENTION In accordance with the present invention, a method of manufacturing a blanking type outer legless skirting structure is disclosed. First, a lead frame having a plurality of carrier units is provided, each of which is formed with a plurality of (10), and a dambar is formed between adjacent carrier units. A plurality of wafers are then placed to the leadframe and the wafers are electrically connected to the pins in a suitable manner. Thereafter, a plurality of encapsulants are separately formed on the corresponding carriers: to combine the pins but to expose the plugging rods. After the sealant, enter = 6 200822821 Half-punching step, forming a plurality of semi-recessed openings along the periphery of the sealant on the pins. Thereafter, an electrical process is performed to form an "electrode ore layer" on the pins that includes the exposed surfaces of the semi-concave notches. Finally, a full blanking step is performed to cut the pins along the semi-concave notches and separate into individual encapsulants. Another disclosure of the blanking type external lead package made by the above process
在前述的製造方法中 些引腳之上表面。 該些半凹缺 係可形成於該 在前述的製造方法中 些引腳之下表面。 該些半凹缺 口係可形成於該 在前述的製造方法中,該些 線以電性連接至該些引腳。 ’、可藉自複數個銲 在前述的製造方法中,該些半 , 該些引腳之厚度三分之一至二分之2 口之深度可約為 在前述的製造方法中,上述之In the aforementioned manufacturing method, the upper surface of the pins. The semi-recessed portions may be formed on the lower surface of the pins in the foregoing manufacturing method. The semi-recessed openings can be formed in the aforementioned manufacturing method, and the wires are electrically connected to the pins. In the foregoing manufacturing method, the thickness of the one-half to two-half of the thickness of the pins may be about the same as in the foregoing manufacturing method.
鍛或是電解電鍵。 驟係為化學電 在前述的製造方法中,該電 錯、錫_ Μ之其中之一。 、可選自於錫、锡- 【實施方式】 在本發明之第一具體實施例中, 3G圖,揭示一種沖裁式無外引腳、配合參閱第3Α至 第4圖則為製程中使一 封裝構造之製造方法, 首先,如第3A及4圖所示,提、頂面示意圖。 線架210係具有複數個載體單元2^:〜導線架210,該導Forging or electrolytic key. The system is a chemical power. In the aforementioned manufacturing method, the electrical fault, tin Μ, is one of them. In the first embodiment of the present invention, the 3G diagram reveals a blanking type without external pins, and the reference to the third to fourth figures is made in the process. A manufacturing method of a package structure, first, as shown in Figs. 3A and 4, a schematic view of the top and bottom surfaces. The wire frame 210 has a plurality of carrier units 2^: lead frame 210, the guide
’每一栽體單元2l〇A 7 200822821 内係形成有複數個引腳211,且在相鄰載體單元21〇a之間 係形成有一堵住桿212(dam bar),以連接該些引腳211。在 本實施例中’每一載體單元210A内可另形成有至少一晶片 承座213 °通常該導線架210係為全金屬材質並具有約〇.2 宅米(mm)之厚度。但該些引腳211係不具有習知可形成I、j 或海鷗形外引腳之長度。每一引腳211係具有一上表面211A 與一下表面2 11B。 如第3B圖所示,設置複數個晶片220至該導線架210, 可利用已知的黏晶技術將該些晶片22〇之一表面黏貼至該導 線架210之該些晶片承座213。此外,在不同類型的導線架 中,其引腳亦可供黏晶之用。 為使該些晶片220可電性連接至該些引腳211。如第3c 圖所不,利用打線技術形成複數個銲線22丨,該些晶片 220係藉由該些銲線221以電性連接至該些引腳2ΐι之上表 面211A。此外,亦可利用内引腳接合與覆晶接合等技術達 到晶片220與導線架21 〇之電性互連。 之後,如第3D圖所示,可利用壓模、印刷或點膠方式 212。換言之,每一載體 210A,以結'Each body unit 2l〇A 7 200822821 is formed with a plurality of pins 211, and a blocking rod 212 is formed between adjacent carrier units 21〇a to connect the pins. 211. In this embodiment, at least one wafer holder 213 may be additionally formed in each of the carrier units 210A. Generally, the lead frame 210 is made of an all-metal material and has a thickness of about 〇.2 house meters (mm). However, the pins 211 do not have the length of a conventional I, j or seagull-shaped outer pin. Each pin 211 has an upper surface 211A and a lower surface 2 11B. As shown in FIG. 3B, a plurality of wafers 220 are disposed to the leadframe 210, and one of the wafers 22 can be adhered to the wafer holders 213 of the leadframe 210 by a known die bonding technique. In addition, in different types of lead frames, the pins are also available for die bonding. The wafers 220 are electrically connected to the pins 211. As shown in Fig. 3c, a plurality of bonding wires 22 are formed by a wire bonding technique, and the wafers 220 are electrically connected to the upper surface 211A of the pins 2 through the bonding wires 221. In addition, the electrical interconnection of the wafer 220 and the lead frame 21 can be achieved by techniques such as internal pin bonding and flip chip bonding. Thereafter, as shown in Fig. 3D, a stamper, a printing or dispensing method 212 can be utilized. In other words, each carrier 210A, with a knot
220,更密封該些引腳211 形成複數個封膠體230於對應之該些載體單元 合該些引腳211但顯露該些堵住桿2 ^ 2。換言二 單元210A皆可對應到一個封膠體23〇。 β蚵對應載體單元21 0A上的晶片 之大部份的上表面211Α。但在本 8 200822821 實施例中,該導線架21G之堵住桿212、引腳2ιι之 211B、曰曰片承座213之下表面以及引腳211之些許上表面 2 11A係不被該些封膠體23〇所覆蓋。 如第3E圖所示,在該些封膠體23〇形成之後方進行一半 沖裁步驟。將該導線架21〇固定在一沖裁設備之載台Η上。 利用複數個冲裁刀22沿著該些封膠體謂之外周緣加形 成複數個半凹缺口 211C於該些引腳2ΐι,值得注意的是^220, sealing the pins 211 to form a plurality of sealing bodies 230 to correspond to the plurality of pins 211 but exposing the blocking rods 2^2. In other words, the unit 210A can correspond to a sealant 23〇. The ? 蚵 corresponds to a large portion of the upper surface 211 of the wafer on the carrier unit 210A. However, in the embodiment of the present invention, the wire rod 21G blocking rod 212, the pin 2 ι 211B, the lower surface of the cymbal holder 213, and the upper surface 2 11A of the pin 211 are not sealed. The colloid is covered by 23 inches. As shown in Fig. 3E, a half-punching step is performed after the formation of the sealant 23 is formed. The lead frame 21 is fixed to the stage of the punching apparatus. A plurality of semi-concave notches 211C are formed on the outer circumferences of the plurality of punching knives 22 along the outer periphery of the encapsulants, and it is noted that
於半冲裁^驟後所形成的該半凹缺口 2iic,其形狀並不限 定’可以是凹型或者是U型等其他幾何形狀。在本實施例 中該二半凹缺口 211C係形成於該些引腳211之上表面 211A。該些凹 υ,1 1 r 、<n? 一 一 缺口 21 lc之深度約為該些引腳211之厚度 刀之至一分之一。即是在半沖裁步驟中不可切斷該些引 腳211,以利電鍍。 如第3F圖所示,進行一電鍍步驟,其係形成一電鍍層 2:於該些引腳211包含該些半凹缺口 2uc之外露表面。 其中’在本實施例巾,該些引腳211可供電鍍層240形成之 外露表面係包含上述顯露在該些封膠體230之外的堵住桿 212、引腳211之下表面2UB、晶片承座213之下表面以及 引腳211之些許上表面2ua及半凹缺口 2iic。此外,該電 鍛步驟係可為化學電㈣是電解電料其他方式。而該電鍍 曰240之材質係可選自於錫、錫-雜、錫_叙之其中之一。 最後如第圖所示,進行一全沖裁步驟,經過封膠 ^電鍍之導線架2 1 〇係固定在另一沖裁設備之載台3 1上, 該載台具有沖切槽道以提供沖裁刀32之全沖裁行程。並利 200822821 用該些沖裁刀32沿著該些半凹缺口 211C切斷該些引腳 211,而分離成個別的封膠體230。在本實施例中,該些引腳 211係被該些封膠體230結合而與該些堵住桿212分離。在 本發明並不局限沖裁設備之種類’在半沖裁步驟與全沖裁步 驟中使用的沖裁設備可為相同或不相同。 如第5圖所示,藉由該全沖裁步驟可得到複數個沖裁式The semi-recessed notch 2iic formed after the half-punching process is not limited in shape and may be concave or U-shaped or other geometric shapes. In the embodiment, the two semi-recessed notches 211C are formed on the upper surface 211A of the pins 211. The recesses, 1 1 r , <n? a notch 21 lc have a depth of about one-tenth of the thickness of the pins 211. That is, the pins 211 cannot be cut in the half-punching step to facilitate plating. As shown in Fig. 3F, a plating step is performed which forms a plating layer 2: the pins 211 include the semi-concave notches 2uc exposed surfaces. In the embodiment of the present invention, the pins 211 are available for the plating layer 240 to form an exposed surface comprising the plugging rod 212 exposed outside the sealing bodies 230, the lower surface 2UB of the pin 211, and the wafer holder. The lower surface of 213 and some of the upper surface 2ua and the semi-recessed notch 2iic of the pin 211. In addition, the electrical forging step can be chemical electricity (four) is other ways of electrolytic electricity. The material of the electroplating crucible 240 may be selected from one of tin, tin-hetero, and tin. Finally, as shown in the figure, a full blanking step is performed, and the lead frame 2 1 which is sealed by electroplating is fixed on the stage 3 1 of another punching device, and the stage has a punching channel to provide The full stroke of the punching knife 32. And the 200802221 uses the punching knives 32 to cut the pins 211 along the semi-recessed notches 211C to separate into individual sealing bodies 230. In this embodiment, the pins 211 are combined with the sealing bodies 230 to be separated from the blocking rods 212. The invention is not limited to the type of blanking apparatus'. The blanking apparatus used in the half blanking step and the full blanking step may be the same or different. As shown in Fig. 5, a plurality of punching types can be obtained by the full blanking step.
無外引腳封裝構造200,利用上述半沖裁步驟實施在封膠步 驟與電鍍步驟之間並在全沖裁步驟之前,以降低全沖裁步驟 時對引腳211和封膠體23〇結合處所造成破壞性的沖切應 力。故能防止該些引腳211由與封膠體23〇結合界面產生裂 不會有I知因-次全沖裁造成引腳剝離與引腳掉落之問 題,並進-步解決了 5丨腳毛邊問題。並且,如第6圖所示, 原在半凹缺口 211C内之電錢層_可增加產品中引腳2ιι :切側緣之電鍍面積’減少該些引腳2ιι之銹化以及 板時對焊球或錫膏的接合能力。 本心月之第-具體實施例中另揭示了上述包含 兩段式沖裁方式製成之沖尜々么al 、成之冲裁式無外引腳封裝構造。如第5及 田丁該冲裁式無外引腳封裝構造2〇〇主要包含一 架加之複數個引腳211、一曰y …導線 一電鑛層240。每_引 日日。、一封谬體230以及 以兩段式沖裁形成之第一顯露於封膠體外之外端係具有 其中該第一切面2 :面2UD與-第二切面211E’ 211Γ ^ 係由刖述半沖裁步驟形成之半凹缺口 211C之一側壁所構 干缺 所覆蓋(如第冗圖 $ 3E圖所示)’且被該電鍍層240 不 該第二切面211E係為由前述全沖 200822821 裁步驟所形成之引腳外露端面。在本實施例中,該些引腳2ιι 之第一切面211D係與對應引腳211之上表面2nA相連接。 在不同實施例中’該些引腳211之第一切面211D亦可與對 應引腳211之下表面相連接。該晶片220係設置於該導線架 210之晶片承座213並以形成複數個銲線221之打線技術或 疋覆晶接合方式使該晶片220與該些引腳211電性連接。該 封膠體23 0係形成於該導線架21〇上並與該些引腳2ιι結 合。較佳地,該些引腳211亦可具有一稍突出於該封膠體23〇 • 側邊之上表面211A以及下表面2ΠΒ。該電鍍層240係至少 形成於該些引腳211之該些第一切面2UD,更可形成在該 些稍突出於該封膠體230側邊之引腳211之上表面211八與 引腳下表面211B以及該晶片承座213之下表面。 在本發明之第二具體實施例中,揭示另一種沖裁式無外 引腳封裝構造之製造方法。在半沖裁步驟之前的封裝步驟, 如導線架提供、黏晶與封膠等等,其係大致與第一具體實施 鲁 例相同,不再贅述。 之後,進行一半沖裁步驟。如第7A圖所示,在半沖裁步 驟之前,複數個晶片320已設置於一導線架31〇,並以複數 個銲線321電性連接至該導線架31〇之複數個引腳η!。一 封膠體330係形成於該導線架31〇之對應載體單元,以結合 該些引腳311但顯露該導線架31〇之複數個堵住桿312。在 半沖裁步驟中,該導線架31〇係可反向固定於一沖裁設備之 載台31,並利用複數個沖裁刀42沿著該些封膠體33〇之外 周緣331形成複數個半凹缺口 311C於該些引腳311。在本 11 200822821 實施例中,該導線架 —▼、艰科石:Μ,肉1¾坚平 凹缺口 311C係形成於該些引腳311之下表面sub。 如第7B圖所示,在半沖裁之後進行一電錄步驟,其係形 成-電鐘層340於該些引腳311包含該些半凹缺口 me之 外露表面,即該些引腳311之部分上表面3UA、下表面Ha 以及該些半凹缺口 311C。 如第7C圖所示,進行一全沖裁步驟,該導線架31〇可改 為正向放置於-沖裁設備之載台51,並利用複數個沖裁刀 52沿著該些半凹缺口取切斷該些引腳扣,而分離成個 別之封膠體330。因此,本發明之半凹缺口無論是形成在引 腳之上表面或下表面皆能解冰羽A 丄 白此解决I知早程沖裁的製程中引起 沖裁式無外引腳封裝槿造> a 輯以引腳剝離、掉落與毛邊等_, 曰以提昇製程良率,更可增加引腳之電鍍面積。 明/上所述,僅是本發明的較佳實施例而已,並非對本發 任何形式上的限制,雖然本發明已以較佳實施例揭露如 脫離=Γ㈣以限定本發明,任何熟悉本項技術者,在不 2本發明之巾請專利範圍内,所作的任㈣ 性變化與修飾,皆涵蓋於本發明的技術範圍内。 【圖式簡單說明】 Α圖f知冲裁式無外5ί腳封裝構造在沖裁單離時之截面 示意圖。 :2圖:習知沖裁式無外引腳封裝構造之截面示意圖。 3Α至3G圖:依捸本發明之第-具體實施例,-種沖裁 、卜引聊封裝構造在製造過程t之截面示意 12 200822821 圖。 第4圖•·依據本發明之坌θ 月之第-具體實施例,使用於該沖裁式無 卜引腳封農構造之導線架 之俯視示意圖。 第5圖:依據本發明之第-具體實施例,該沖裁式無外引腳 封裝構造之截面示意圖。 第圖·依據本發明之第一具體實施例,該沖裁式無外引腳 封裝構造之側面示意圖。 第7Α至7C圖··依據本發明之第二具體實施例,另一種沖 裁式無外引腳封裝構造在製造過程之兩沖裁步驟 中之截面示意圖。 【主要元件符號說明】 11 载台 12 沖裁刀 21 載台 22 沖裁刀 31 载台 32 沖裁刀 41 載台 42 沖裁刀 51 載台 52 沖裁刀 100 沖裁式無外引 腳封裝構造 110 導線架 111 引腳 120 晶片 121 銲線 130 封膠體 140 電鍍層 2〇〇沖裁式無外引腳封裝構造 210導線架 210Α載體單元 211引腳 211Α上表面 211Β下表面 211C半凹缺口 211D第一切面 211Ε第二切面 13 200822821 212堵住桿 220晶片 230封膠體 240電鍍層 310導線架 3 11B下表面 312堵住桿 320晶片 330封膠體 340電鍍層 213晶片承座 221銲線 231外周緣 311引腳 311C半凹缺口 321銲線 331外周緣 311A上表面The outer lead package structure 200 is implemented by the above-described half blanking step between the sealing step and the plating step and before the full blanking step to reduce the bonding position of the pin 211 and the sealing body 23 when the full blanking step is performed. Destructive punching stress. Therefore, it is possible to prevent the pins 211 from being cracked at the interface with the sealing body 23, and there is no problem that the pin is peeled off and the pins are dropped due to the I-known full-punching, and the 5-foot burrs are further solved. problem. Moreover, as shown in Fig. 6, the electric money layer _ in the semi-recessed notch 211C can increase the plating area of the pin 2 ιιι: cut side edge in the product 'reduce the rust of the pin 2 ι and the butt welding of the plate The bonding ability of the ball or solder paste. In the first embodiment of the present invention, the above-mentioned two-stage punching method is also disclosed, and the punched type external lead package structure is formed. For example, the fifth and the field of the punched external lead package structure 2 〇〇 mainly include a plurality of pins 211, a y ... conductor - an electric ore layer 240. Every _ cited day. a first body 230 and a first two-section blank formed on the outside of the sealant have a first face 2: a face 2UD and a second face 211E' 211 Γ The sidewall of one of the semi-recessed notches 211C formed by the half-punching step is covered by the dry space (as shown in the second figure of FIG. 3E) and is not covered by the second layer 211E of the plating layer 240 by the aforementioned full-blown 200822821 The exposed end face of the pin formed by the cutting step. In this embodiment, the first slice 211D of the pins 2 ι is connected to the upper surface 2nA of the corresponding pin 211. In a different embodiment, the first slice 211D of the pins 211 may also be connected to the lower surface of the corresponding pin 211. The wafer 220 is disposed on the wafer holder 213 of the lead frame 210 and electrically connected to the pins 211 by a wire bonding technique or a flip chip bonding method for forming a plurality of bonding wires 221 . The encapsulant 230 is formed on the lead frame 21A and joined to the pins 2ι. Preferably, the pins 211 may also have a surface 211A and a lower surface 2ΠΒ slightly protruding from the side of the sealing body 23〇. The plating layer 240 is formed on at least the first cut surface 2UD of the pins 211, and may be formed on the upper surface 211 of the pin 211 slightly protruding from the side of the sealant 230. Surface 211B and the lower surface of wafer holder 213. In a second embodiment of the invention, another method of fabricating a blanked external lead package construction is disclosed. The packaging steps before the half-punching step, such as lead frame supply, die bonding and encapsulation, etc., are substantially the same as in the first embodiment, and will not be described again. After that, half the punching step is performed. As shown in FIG. 7A, before the half-punching step, a plurality of wafers 320 are disposed on a lead frame 31A, and are electrically connected to the plurality of pins η of the lead frame 31 by a plurality of bonding wires 321! . A sealant 330 is formed on the corresponding carrier unit of the lead frame 31 to bond the pins 311 but expose the plurality of plug bars 312 of the lead frame 31. In the semi-punching step, the lead frame 31 can be reversely fixed to the stage 31 of a punching device, and a plurality of punching blades 42 are used to form a plurality of outer peripheral edges 331 along the sealing bodies 33. The semi-recessed notch 311C is on the pins 311. In the embodiment of the present invention, the lead frame - ▼, the hard stone: Μ, the meat 13⁄4 flat recessed notch 311C is formed on the lower surface sub of the pins 311. As shown in FIG. 7B, an electro-recording step is performed after the half-punching, which forms an electric clock layer 340, and the pins 311 include the exposed surfaces of the semi-concave notches, that is, the pins 311 Part of the upper surface 3UA, the lower surface Ha, and the semi-recessed notches 311C. As shown in FIG. 7C, a full blanking step is performed, and the lead frame 31 can be placed in the positive direction on the stage 51 of the punching apparatus, and the plurality of punching blades 52 are used along the semi-recessed notches. The pin buckles are cut and separated into individual sealants 330. Therefore, the semi-concave notch of the present invention can be formed on the upper surface or the lower surface of the lead to solve the ice plume A 丄 white. This solution causes the punching type without external lead package fabrication in the process of early-stage blanking > a series of pin peeling, drop and burrs, etc. _, 曰 to improve the process yield, but also increase the plating area of the pin. The present invention is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Although the present invention has been disclosed in the preferred embodiments as the invention Any changes and modifications made by the invention within the scope of the invention are covered by the technical scope of the present invention. [Simple diagram of the diagram] Figure 知 shows the schematic diagram of the cross-section of the blanking package structure when punching out. Fig. 2 is a schematic cross-sectional view showing a conventional punched-out external lead package structure. 3Α to 3G图: According to the first embodiment of the present invention, the cross-sectional illustration of the blanking and packaging structure in the manufacturing process t 12 200822821. Fig. 4 is a top plan view of a lead frame used in the blanking type of the agricultural structure according to the present invention. Figure 5 is a cross-sectional view showing the blanked outer package structure in accordance with a first embodiment of the present invention. Figure 1 is a side elevational view of the blanked outer lead package construction in accordance with a first embodiment of the present invention. 7A to 7C are cross-sectional views showing another blanking type outer package structure in the two blanking steps of the manufacturing process in accordance with the second embodiment of the present invention. [Description of main component symbols] 11 Stage 12 Punching knife 21 Stage 22 Punching knife 31 Stage 32 Punching knife 41 Stage 42 Punching knife 51 Stage 52 Punching knife 100 Blanking type external lead package Structure 110 Lead frame 111 Pin 120 Wafer 121 Bond wire 130 Sealant 140 Plating layer 2 〇〇 Blanking no external lead package structure 210 Lead frame 210 Α Carrier unit 211 Pin 211 Α Upper surface 211 Β Lower surface 211C Semi-recessed notch 211D The first surface 211 Ε second cutting surface 13 200822821 212 blocking rod 220 wafer 230 sealing body 240 plating layer 310 lead frame 3 11B lower surface 312 blocking rod 320 wafer 330 sealing body 340 plating layer 213 wafer bearing 221 welding line 231 outer circumference Edge 311 pin 311C semi-recessed notch 321 bonding wire 331 outer peripheral edge 311A upper surface
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| TW95142008A TWI309541B (en) | 2006-11-14 | 2006-11-14 | Method for fabricating punch type leadless ic packages |
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| TWI618585B (en) * | 2015-02-04 | 2018-03-21 | 新日鐵住金股份有限公司 | Cutting apparatus and cutting method |
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| TWI618585B (en) * | 2015-02-04 | 2018-03-21 | 新日鐵住金股份有限公司 | Cutting apparatus and cutting method |
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