[go: up one dir, main page]

TW200822345A - NAND flash memory devices having 3-dimensionally arranged memory cells and methods of fabricating the same - Google Patents

NAND flash memory devices having 3-dimensionally arranged memory cells and methods of fabricating the same Download PDF

Info

Publication number
TW200822345A
TW200822345A TW096137829A TW96137829A TW200822345A TW 200822345 A TW200822345 A TW 200822345A TW 096137829 A TW096137829 A TW 096137829A TW 96137829 A TW96137829 A TW 96137829A TW 200822345 A TW200822345 A TW 200822345A
Authority
TW
Taiwan
Prior art keywords
source
semiconductor layer
plug
layer
flash memory
Prior art date
Application number
TW096137829A
Other languages
Chinese (zh)
Other versions
TWI423430B (en
Inventor
Yang-Soo Son
Young-Seop Rah
Won-Seok Cho
Soon-Moon Jung
Jae-Hoon Jang
Young-Chul Jang
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of TW200822345A publication Critical patent/TW200822345A/en
Application granted granted Critical
Publication of TWI423430B publication Critical patent/TWI423430B/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices
    • H10D88/01—Manufacture or treatment
    • H10W20/0234—
    • H10W20/0253—
    • H10W20/069—
    • H10W20/0698—
    • H10W20/20—
    • H10W20/2125—
    • H10W20/2134—
    • H10W20/218—
    • H10W20/40—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices

Landscapes

  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Read Only Memory (AREA)

Abstract

A NAND flash memory device includes a lower semiconductor layer and an upper semiconductor layer located over the lower semiconductor layer, a first drain region and a first source region located in the lower semiconductor layer, and a second drain region and a second source region located in the upper semiconductor layer. A first gate structure is located on the lower semiconductor layer, and a second gate structure is located on the upper semiconductor layer. A bit line is located over the upper semiconductor layer, and at least one bit line plug is connected between the bit line and the first drain region, where the at least one bit line plug extends through a drain throughhole located in the upper semiconductor layer.

Description

200822345 25735pif 九、發明說明： ί發明所屬之技術領域】 本發明是有關於一種半導體裝置的製造方法，且特別 是有關於一種具有三維排列記憶胞之NAND快間記憶體 裝置的製造方法。 本申請案主張於2006年1〇月η日向韓國智慧財產 局提出申請之韓國專利申請案第2〇〇6_99〇15號的優先BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating a NAND flash memory device having a three-dimensional array of memory cells. This application claims priority to Korean Patent Application No. 2〇〇6_99〇15, which was filed with the Korea Intellectual Property Office on January 1st, 2006.

權，該專利申請案所揭露之内容系完整結合於本說明書中。 I先前技術】 省大多數現代化電子設備都會包括半導體裝置。這些丰 導體裝置包括-些元件。這些半導體裝置制包括例如電 ，：電阻H、電容料#的電子元件。在最佳情況下， ，些電子7G件在其被輯錢㈣子絲㈣定功能之後 體基片上。例如，像是電腦與數位相解 的片:儲訊的記憶晶 的處理曰曰片。这些§己憶晶片與 在分別被設絲執行:#聰心a子兀件，其 導體基U。 料鱗理魏之集成於半 為了起上各戶對於低價、有效 的需求，越來越需要高声隹成 ’、寸的裝 導體製程中存在某4b會；燮古产隹：版裝置。然而，在 一曰衫％«同度集成的丰逡舻狀 的缺點。例如’需要用到先進的處理技衣勺效 技術。然而，先進的處 要’像^ 支出，而且在其可商業 ，竹而要大ί育金 化衣μ度集成的轉體裳置之 200822345 25735pif 可能長時間受困於研發週期。 為了在目前的製造技術所定的限制附近運作，已經有 人建議在半導體裝置中使用三維排列電晶體。例如，韓國 專利申請案第2006-73858號揭露_種具有三維排列電晶 肢之NAND快閃記憶體裝置。此種半導體裝置的製造方法 包括，由磊晶（epitaxial)技術在作為半導體基片的晶圓上 形成單晶半導體層，之後便在半導體層上形成電晶體。 士此外，當記憶胞電晶體的源極及沒極電極是三維排列 =’需要用連接這些源極及沒極電極的插塞(plugs)來電性 ^子取記憶胞電㈣。㈣，可能Μ形成這些插塞於三維 +導體裝置中。例如，在韓國專利申請案第·6_頂 ^露的NAND㈣減體裝置中，形成於不同層 Ϊ:=由以不同製程形成的堆一域互i 可能有許多與使用不同程序m 有關的問題。這些問題可能包括例如整個製程的複= ^及製造成本的增加。藉由減少有效晶片面積 = +導體裝複。然而，晶片面積有效㈣ = 降低半導體裝置的集成密度。這特徵與 導體= 重要目標之-相反。 置的 【發明内容】 如在本發料-方面，提供-種nand 夏，包括：下半導體層及位於下半導體層上方的上=二 層；位於下半導體層中的第-汲極區及第—源極區；以及 8 200822345 / J^pif 位於上半導體層中的第二汲極區及第二源極區。第_閘極 結構位於下半導體層上，而第二閘極結構則位於上半導體 層上。位元線(bit line)位於上半導體層的上方，並且至少 一個位元線插塞連接在位元線與第一汲極區之間，其中上 述至少一個位元線插塞經由位於上半導體層中的汲極通孔 (throughhole)延伸。 在本發明的另一方面，提供一種NAND快閃記憶體裝 置的製造方法，包括··在下半導體層中形成下源極區及^ 汲極區，在下半導體層的上方形成上半導體層，上半導體 層包括汲極通孔、上源極區、以及上汲極區；以及形成至 少一個位元線插塞，其經由汲極通孔延伸且連接上及下汲 極區。 【實施方式】 以下將參考附圖更詳細地說明本發明的較佳實施 例。然而，本發明可能以不同的形式來實施，因此不應視 為侷限於在此所述之實施例。相反地，提供這些實施例將 使知此揭露更為徹底且完全，並將完整地傳達本發明的觀 念給熟習此技藝者。 須知當提到一分層（或薄膜)位於另一分層或基片的，， 上方”時，可能直接位於此另一分層或基片上，或者也可能 I子在中介層。並且，須知當提到一分層位於另一分層的，， 下方”時，可能直接位於此另一分層的下方，或者也可能存 在一層或多層中介層。此外，須知當提到一分層位於兩分 層之間時，可能是此兩分層之間的唯一分層，或者也可 200822345 25735pif 能存在一層或多層中介 連接，，另—元件二層_地’須知當提到-元件” 彼此操作上(例:電===== ===咐：娜猜， 作是^此^弟—料m㈣各觀域、分層等等， 僅等等不應受限於這些術語。糊 Γ中= 二物層區分彼此。因此，當可稱-實施 / 、弟刀層為另一實施例中所提及的第二分 曰。在此所述的每—實施例可能包括其互補實施例。 圖1Α至1D是根據較佳實施例之nand快閃記憶體 二置= 意胞陣列的平面圖。並且，圖2A至％是根據 4貝他例之NAND快閃記憶體裝置的記憶胞陣列的斷 面圖九其，圖2A至2C分別是沿著圖1A至1D的虛線 I - I ’所截取的斷面圖。The contents disclosed in this patent application are fully incorporated in the present specification. I Prior Art] Most modern electronic devices in the province include semiconductor devices. These abundance conductor devices include a number of components. These semiconductor devices include electronic components such as electric, resistor H, and capacitor #. In the best case, some of the electronic 7G pieces are placed on the body substrate after they have been priced (four). For example, a piece of computer and digital phase solution: the memory chip of the memory. These § recalled wafers are executed in separate wires: #聪心 a sub-piece, its conductor base U. In order to get up to the low-cost and effective demand of all households, it is increasingly necessary to make a loud voice. In the process of the installation of the inch, there is a certain 4b meeting; the ancient production: the device. However, in a Sweatshirt, the %« is the same as the abundance of the same. For example, 'the need to use advanced processing technology scooping technology. However, the advanced department has to be 'expenditure', and it is likely to be trapped in the R&D cycle for a long time in its commercial, bamboo and large-scale cultivating. In order to operate in the vicinity of the limits set by current manufacturing techniques, it has been proposed to use a three-dimensional array of transistors in a semiconductor device. For example, Korean Patent Application No. 2006-73858 discloses a NAND flash memory device having a three-dimensional array of electro-crystal limbs. A method of manufacturing such a semiconductor device includes forming a single crystal semiconductor layer on a wafer as a semiconductor substrate by an epitaxial technique, and then forming a transistor on the semiconductor layer. In addition, when the source and the electrodeless electrode of the memory cell are three-dimensionally arranged, it is necessary to use a plug that connects these source and the electrode to electrically access the memory cell (4). (d) It is possible to form these plugs in a three-dimensional + conductor arrangement. For example, in the NAND (fourth) reduction device of the Korean Patent Application No. 6_Top, it is formed in different layers: = There may be many problems related to the use of different programs m by the heap-domains formed by different processes. . These problems may include, for example, a complex of the entire process and an increase in manufacturing costs. By reducing the effective wafer area = + conductor assembly. However, the chip area is effective (4) = reducing the integration density of the semiconductor device. This feature is the opposite of conductor = important target. [Invention] For example, in the present invention, a nand summer is provided, including: a lower semiconductor layer and an upper=two layer above the lower semiconductor layer; a first-drain region in the lower semiconductor layer and a source region; and 8 200822345 / J^pif being located in the second drain region and the second source region in the upper semiconductor layer. The first gate structure is on the lower semiconductor layer and the second gate structure is on the upper semiconductor layer. a bit line is located above the upper semiconductor layer, and at least one bit line plug is connected between the bit line and the first drain region, wherein the at least one bit line plug is located via the upper semiconductor layer The through hole in the middle extends. In another aspect of the present invention, a method of fabricating a NAND flash memory device includes: forming a lower source region and a drain region in a lower semiconductor layer, and forming an upper semiconductor layer over the lower semiconductor layer, upper semiconductor The layer includes a drain via, an upper source region, and an upper drain region; and at least one bit line plug is formed that extends through the drain via and connects the upper and lower drain regions. [Embodiment] Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the accompanying drawings. However, the invention may be embodied in different forms and should not be construed as being limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be more thorough and complete, and the concept of the invention will be fully conveyed to those skilled in the art. It should be noted that when a layer (or film) is located on top of another layer or substrate, it may be directly on the other layer or substrate, or it may be in the interposer. When it is mentioned that one layer is located under another layer, "below", it may be directly below the other layer, or there may be one or more interposers. In addition, it should be noted that when a layer is mentioned between two layers, it may be the only layer between the two layers, or there may be one or more layers of intermediaries connected to 200822345 25735pif, and another component layer _ The ground 'know when referring to - components" operate with each other (eg: electricity ===== ===咐: Na guess, do ^^^^^^^^^^^^^^^^^^^^^^^^^ These terms should not be limited. In the paste, the two layers distinguish each other. Therefore, when it can be called-implemented, the second layer is the second branch mentioned in another embodiment. Each embodiment may include complementary embodiments thereof. Figures 1A through 1D are plan views of a nand flash memory two-position = cell array in accordance with a preferred embodiment. And, Figures 2A through % are NAND based on 4 beta examples. Sectional view of the memory cell array of the flash memory device. Fig. 2A to Fig. 2C are cross-sectional views taken along the broken line I - I ' of Figs. 1A to 1D, respectively.

Lj 麥照圖1A及2A，較佳實施例之NAND快閃記 裳置^括下半導體層丨⑻，以及位於下半導體層⑽:的 亡半導體層2GG。為求簡潔明暸，將讀示較佳實施例之 一層上半導體層。然而，熟習此技藝者應當理解在不脫離 =發明的範’的情況下可能有多層上半導體層位於下半導 體層100上。並且，下半導體層1〇〇可能是由單晶半導體 材料所構成的晶圓。此外，上半導體層200最好是由單晶 半導體材料所構成的，稍後將予以詳述。 下閘極結構120與上閘極結構220分別位於下半導體 層100與上半導體層2〇〇的上方。並且，下及上閘極結構 10 200822345 25735pif 120及220荨兩者都包括字串選擇線（血丨邱seiecy〇n lme)SSL、接地選擇線(gr〇und selecii〇n line)GSL、以及多 條位於字串選擇線SSL與接地選擇線GSL之間的字元線 (word lme)WL。此外，下閘極絕緣層1〇5可能位於下閘極 結構120與下半導體層1〇〇之間，且上閘極絕緣層2〇5可 能位於上閘極結構220與上半導體層200之間。 在一較佳實施例中，下閘極結構12()包括下浮動電極 121、下閘極層間絕緣層122、以及下控制電極123，以上 皆依序堆疊。同樣地，上閘極結構220包括上浮動電極 22卜上閘極層間絕緣層222、以及上控制電極223。此外， 下及上覆蓋圖案124及224可能附帶地分別位於下及上控 制電極123及223上。 在字元線WL中，下及上浮動電極丨21及221並未分 別電性連接下及上控制電極123及223。下及上浮動電極 121及221分別與下及上控制電極123及223之間的這種 缺乏電性連接是因為下及上閘極層間絕緣層丨22及222介 於其間。相對地，在字串選擇線SSL及接地選擇線GSL 中，下及上浮動電極121及221分別電性連接下及上控制 電極123及223。為此，可能形成下及上閘極層間絕緣層 122及222以使下及上浮動電極12ι及221的頂面部分: 露出來。 在另一較佳實施例中，下及上閘極結構12〇及22〇(以 下，稱之為閘極結構）可能具有電荷操取型快閃記憶體 (charge trap type flash memory)的記憶胞閘極結構。例如， 200822345 25735pif 閘極結構m及22G可能是知名的參氧切·氮切 石夕-石夕（SONOS)或叙·氧化銘_氮化物 ^ . · …-一... ，.. 在下半導體層100中，下雜質區11〇分別形成 選擇線SSL與相鄰的字元、線脱之間、字元線机之間、 以及接地選擇線GSL與相鄰的字元線WL之間。並且 下閘極結構120的任-邊，將形成下源極區11〇 涵聰。尤其，下源極區腕將與接地選擇線脱相 郴’且下没極區110D將與字串選擇、線弧相鄰。並且， 在上半導體層200中，上雜質區21()、上源極區2i〇s、以 及上汲極區210D分別形成於下雜質區u〇 '下源择區 二以及下没極區聰的上方。此外，雜質區具有不 同於卜及上半導體層100及2〇〇的導電類型。 閘極間隙壁(gate spacer)129及229可能位於字串選擇 線SSL、接地選擇線GSL、以及字元、線肌的每一條線的 侧邊。在-較佳實施例中，如圖2B所示，閉極間隙壁129 及229可能由氧化矽或氮化矽所構成。並且，回到圖2a， 下層間絕緣層140形成於下半導體層刚與上半導體層 200之間’而上層間絕緣層·則形成於上半導體層2〇θ〇 士。在二較佳實施例中，下及上層間絕緣層 140及240可 能包括氧化矽或氮化矽當中至少一種。 並且，上韻刻終止層（upper etch stop layer)230可能形 成於上半導體層200上。尤其，具有預定厚度的上钱刻終 12 200822345 25735pif 止層230可能覆蓋用以形成上 200。上钱刻終止層23〇 # 傅U的上牛^體層 ^ 取好由相對於上層間絕緣層240 具有蝕刻运擇性的材料所構成。LJ is shown in Figs. 1A and 2A, and the NAND flash memory of the preferred embodiment includes a semiconductor layer (8) and a semiconductor layer 2GG located on the lower semiconductor layer (10). For the sake of brevity, the upper semiconductor layer of the preferred embodiment will be read. However, those skilled in the art will appreciate that there may be multiple layers of upper semiconductor layers on the lower semiconductor layer 100 without departing from the invention. Further, the lower semiconductor layer 1 may be a wafer composed of a single crystal semiconductor material. Further, the upper semiconductor layer 200 is preferably composed of a single crystal semiconductor material, which will be described in detail later. The lower gate structure 120 and the upper gate structure 220 are located above the lower semiconductor layer 100 and the upper semiconductor layer 2, respectively. Moreover, the lower and upper gate structures 10 200822345 25735pif 120 and 220荨 both include a string selection line (Blood Qie seiecy〇n lme) SSL, a ground selection line (gr〇und selecii〇n line) GSL, and more The strip is located at the word line WL between the string selection line SSL and the ground selection line GSL. In addition, the lower gate insulating layer 1〇5 may be located between the lower gate structure 120 and the lower semiconductor layer 1〇〇, and the upper gate insulating layer 2〇5 may be located between the upper gate structure 220 and the upper semiconductor layer 200. . In a preferred embodiment, the lower gate structure 12() includes a lower floating electrode 121, a lower gate interlayer insulating layer 122, and a lower control electrode 123, all of which are sequentially stacked. Similarly, the upper gate structure 220 includes an upper floating electrode 22, an upper gate insulating layer 222, and an upper control electrode 223. In addition, lower and upper cover patterns 124 and 224 may be incidentally located on lower and upper control electrodes 123 and 223, respectively. In the word line WL, the lower and upper floating electrodes 21 and 221 are not electrically connected to the lower and upper control electrodes 123 and 223, respectively. The lack of electrical connection between the lower and upper floating electrodes 121 and 221 and the lower and upper control electrodes 123 and 223, respectively, is due to the lower and upper gate interlayer insulating layers 22 and 222 interposed therebetween. In contrast, in the string selection line SSL and the ground selection line GSL, the lower and upper floating electrodes 121 and 221 are electrically connected to the lower and upper control electrodes 123 and 223, respectively. For this reason, the lower and upper gate interlayer insulating layers 122 and 222 may be formed so that the top surface portions of the lower and upper floating electrodes 12 and 221 are exposed. In another preferred embodiment, the lower and upper gate structures 12A and 22A (hereinafter referred to as gate structures) may have a memory cell of a charge trap type flash memory. Gate structure. For example, 200822345 25735pif gate structure m and 22G may be well-known oxygen-cutting nitrogen-cutting stone Xi-Shi Xi (SONOS) or Syrian oxidation _ nitride ^ . · ...- a..., in the lower semiconductor layer In 100, the lower impurity regions 11〇 are formed between the selection line SSL and the adjacent word elements, the line lines, between the word line machines, and between the ground selection line GSL and the adjacent word lines WL. And any side of the lower gate structure 120 will form a lower source region 11 涵 Han Cong. In particular, the lower source region wrist will be out of phase with the ground selection line and the lower polarity region 110D will be adjacent to the string selection and line arc. Further, in the upper semiconductor layer 200, the upper impurity region 21 (), the upper source region 2i 〇 s, and the upper drain region 210D are respectively formed in the lower impurity region u 〇 ' under the source region 2 and the lower electrode region Above. Further, the impurity region has a conductivity type different from that of the upper and lower semiconductor layers 100 and 2. The gate spacers 129 and 229 may be located on the side of each of the string selection line SSL, the ground selection line GSL, and the character and line muscles. In the preferred embodiment, as shown in FIG. 2B, the closed gap walls 129 and 229 may be composed of tantalum oxide or tantalum nitride. Further, referring back to Fig. 2a, the lower interlayer insulating layer 140 is formed between the lower semiconductor layer and the upper semiconductor layer 200, and the upper interlayer insulating layer is formed on the upper semiconductor layer 2??. In the second preferred embodiment, the lower and upper interlayer insulating layers 140 and 240 may include at least one of ruthenium oxide or tantalum nitride. Also, an upper etch stop layer 230 may be formed on the upper semiconductor layer 200. In particular, the end layer 230 having a predetermined thickness may be covered to form the upper 200. The end layer 23〇 of the money engraving layer is formed by a material having an etching property with respect to the upper interlayer insulating layer 240.

Tmm±M(loWer etch stop iayer)i30 成於下半導體層loo的上方。十1目二y ) 了月"形 ^ 石尤其，具有預定厚度的下鉦 刻終止層130可能保形霸芸田 b1示办後盍用以形成下閘極結構120的下 半導體層100。在最佳情汉下 丨^ 卜 下’下姓刻終止層130由相對 於上層間絕緣層240具有麵刻選擇性的材料所構成。當 及上侧終止層130及230由彼此不具有侧選擇性的材 料所構成時(例如’若其由相同的材料所構成），所形成的 上钱刻終止層230最好是比下儀刻終止層13〇厚，以避免 造成上半導體層遍的侧損害，這些紐將予以說明。 參fc、圖1A，多條跨越字元線的位元線bl形成於 上層間絕緣層240上。此外，與字元線WL平行的共同源 極線CSL位於上半導體層2〇〇上。依據垂直高度，共同源 極線CSL可能位於上半導體層2〇〇與位元線BL之間。此 外’參知、圖2A ’位元線BL藉由位元線插塞400電性連接 下及上没極區Π0D及210D。因此，位元線插塞4〇〇穿過 下及上層間絕緣層140及240。並且，共同源極線CSL藉 由源極插塞300連接下及上源極區nos及210S。源極插 塞300穿過下及上層間絕緣層140及.240。 如圖2A所示，上層間絕緣層240可能包括圍繞共同 源極線CSL的第一上層間絕緣層241，以及位於共同源極 線CSL上的第二上層間絕緣層242。並且，在一較佳實施 200822345 25735pif 例中，穿過上半導體層200的汲極通孔501與源極通孔5〇2 形成於位在下汲極區110D與下源極區11〇s上方的上半導 體層200。並且，位元線插塞400通過汲極通孔5〇1以便 連接下没極區110D，而源極插塞30Ό則通適藏極通礼5〇2 以便連接下源極區110S。此外，如圖1A所示，一條位元 線BL經由一個位元線插塞400連接一個下汲極區n〇D， 而共同源極線CSL與源極插塞卻連接多個下源極區11〇s。 在一較佳實施例中，位元線插塞4〇〇可能由其導電類 型與下及上汲極區ll〇D及210D相同的多晶矽所組成 p例中，位元線插基40Q可能在没極通孔的侧壁與上 =導體層.200接觸。此時，因為上半導體層2〇〇與位元線 插塞400具有不同的導電類型，所以其形成pN二極體。 ^^7、二極體可能當作整流器(reCtifier)。結果，當施加反 二电壓至位元線插塞4〇〇時，此電壓並未被施加至上半導 =層200。亦即，位元線插塞400與上半導體層2〇〇可能 疋電性獨立的。 在另一較佳實施例中，位元線插塞400可能由金屬材 鎢斤構成，例如鎢、鈦、钽、氮化鈦、氮化钽、以及氮化 :在此例中，為了互相電性隔離位元線插塞4〇〇與上半 ^靉層2〇〇,如圖2B所示之汲極絕緣層155可能形成於位 =線插塞400的侧壁上。汲極絕緣層155可能利用知名的 間隙壁形成製程來形成。 八在一較佳實施例中，位元線插塞400可能分為兩部 刀，其中一部分是位於上半導體層200上方的上位元線插 200822345 25735pif 塞’而另-部分則是穿過上半導體層·的下位元線插 塞。並且，所形成的上位元線插塞的寬度可能大於汲極通 孔501的寬度G1，如圖1A、1B、1D、以及2A所示。因 此，上位元線插塞將連接到形成於没極通孔501的任一邊 的上汲極區210D。此外，所形成的下位元線插塞的寬度可 ，小於或等於汲極通孔501的寬度G1。並且，下位元線插 塞由上位元線插塞的底面接續地延伸以致連接到下汲極區 110D。 在另一較佳實施例中，參照圖1(：；及2(：，位元線插塞 400可能被設定為具有上位元線插塞4〇2及下位元線插塞 401。在此，上位元線插塞4〇2彼此隔離。在此例中，上位 元線插塞402電性連接位元線bl與上汲極區210D，而下 位元線插塞401則電性連接位元線B£與下汲極區n〇D。 並且，雖然上位元線插塞402與下位元線插塞々οι在實體 上彼此分離，但是因為其共同連接位元線BL所以其形成 等電位。 在一較佳實施例中，源極插塞300可能由其導電類型 與下及上源極區110S及210S相同的多晶石夕所構成。在此 例中，源極插塞300可能在源極通孔502的侧壁與上半導 脰層200接觸。因為上半導體層2〇〇與源極插塞3〇〇具有 不同的導電類型，所以其形成當作整流器的PN二極體。 因此，當施加反向電壓至源極插塞300時，並未施加此電 壓至上半導體層200。亦即，源極插塞300與上半導體層 20〇可能是電性獨立的。 200822345 25735pif 在另二較佳實施例中，源極插塞300可能由例如鎢、 鈦、鈕、氮化鈦、氮化鈕、以及氮化鎢的金屬材料之一所 ， 構成。在此例中，源極絕緣層156可能形成於源極插塞3⑽ 的侧壁上，以便電性隔離源極插塞300與上半導體層200。 ‘ 源極絕緣層156可能利用知名的間隙壁形成製程來S形成。 在另一較佳實施例中，上半導體層2〇〇與下半導體層 100 了此利用下及上源極區11⑽及21 〇s來形成等電位。 『 在此例中，並未形成源極絕緣層156，而且源極插塞3⑻ 可能包括位障金屬層以便與下及上半導體層1〇〇及2⑻產 生歐姆接觸。 在一較佳實施例中，源極插塞3⑻可能分為兩部分， ，中一部分是位於上半導體層200上方的上源極插塞，而 另一部分則是穿過上半導體層2⑻的下源極插塞。並且， 所开>成的上源極插塞的寬度可能大於源極通孔:5〇2的寬度 如圖ΙΑ、IB、1D、以及2A所示。因此，上源極插 塞將連接到形成於源極通孔502的任一邊的上源極區 I’ 210S。此外，所形成的下源極插塞的寬度小於或等於源板 通孔=02的寬度G2。並且，下源極插塞由上源極插塞的底 面接績地延伸以便連接到下源極區110S。 在另一較佳實施例中，如圖1C及2C所示，源極插塞 300可能被設定為具有多個上源極插塞302及下源極插塞 301，其中上源極插塞彼此隔離。在此例中，上源極插 基302電性連接共同源極線CSL與上源極區210S，而下 源極插塞301則電性連接共同源極線CSL與下源極區 200822345 25735pif U並且，可走利用鑲嵌製程(damascene process)同時形 成共同源極線CSL與下及上源極插塞3〇1及3〇2。在此例 中，上源極插塞302與下源極插塞301形成等電位，如 2C·所示'。…..................…. 圖3A至3D是根據一較佳實施例之NAND快閃記憶 體裝置的製造方法的斷面圖。以下，將參考圖3A至3D詳 細說明形成位元線插塞4〇〇及源極插塞3⑻的方法。 麥照圖3A，下閘極結構12〇形成於下半導體層1〇〇 上。其後，將利用下閘極結構12〇執行離子植入（i〇n implantation)製程作為用以形成下半導體層1〇〇中的下雜 質區110、下源極區11〇s、以及下汲極區n〇D的離子光 罩(ion mask)。接著，下蝕刻終止層13〇與下層間絕緣層 140依序形成於其中形成下閘極結構120的合成結構上。 此外’上半導體層200形成於下層間絕緣層140上。 如上所述，上半導體層200具有汲極通孔5〇1及源極通孔 502。在一較佳實施例中，可能利用各種方法來形成上半導 體層200。以下，在說明形成位元線插塞4〇〇及源極線插 塞300的方法之前，將參考圖5A、5B、6A至6C、7八及 7B來說明形成上半導體層2〇〇的方法。Tmm±M (loWer etch stop iayer) i30 is formed above the lower semiconductor layer loo. In particular, the lower etch stop layer 130 having a predetermined thickness may be used to form the lower semiconductor layer 100 of the lower gate structure 120. In the best case, the lower-order stop layer 130 is made of a material having a surface selectivity with respect to the upper interlayer insulating layer 240. When the upper end stop layers 130 and 230 are composed of materials having no side selectivity with each other (for example, if they are composed of the same material), the formed stop-cut layer 230 is preferably inferior to the lower one. The termination layer 13 is thick to avoid side damage to the upper semiconductor layer, as will be explained. Referring to fc, Fig. 1A, a plurality of bit lines b1 crossing the word line are formed on the upper interlayer insulating layer 240. Further, a common source line CSL parallel to the word line WL is located on the upper semiconductor layer 2A. Depending on the vertical height, the common source line CSL may be located between the upper semiconductor layer 2A and the bit line BL. Further, the reference numeral 2A' bit line BL is electrically connected to the lower and upper non-polar regions Π0D and 210D by the bit line plug 400. Therefore, the bit line plug 4 is passed through the lower and upper interlayer insulating layers 140 and 240. Further, the common source line CSL is connected to the lower and upper source regions nos and 210S by the source plug 300. The source plug 300 passes through the lower and upper interlayer insulating layers 140 and .240. As shown in FIG. 2A, the upper interlayer insulating layer 240 may include a first upper interlayer insulating layer 241 surrounding the common source line CSL, and a second upper interlayer insulating layer 242 on the common source line CSL. Moreover, in a preferred embodiment 200822345 25735 pif, the gate via 501 and the source via 5 穿过 2 passing through the upper semiconductor layer 200 are formed over the lower drain region 110D and the lower source region 11 〇 s. The upper semiconductor layer 200. Also, the bit line plug 400 passes through the drain through hole 5〇1 to connect the lower gate region 110D, and the source plug 30Ό is generally adapted to connect the lower source region 110S. In addition, as shown in FIG. 1A, one bit line BL is connected to one lower drain region n〇D via one bit line plug 400, and the common source line CSL and the source plug are connected to a plurality of lower source regions. 11〇s. In a preferred embodiment, the bit line plug 4〇〇 may be composed of polysilicon having the same conductivity type as the lower and upper drain regions 11〇D and 210D. In the example of p, the bit line interposer 40Q may be The sidewall of the gateless via is in contact with the upper = conductor layer .200. At this time, since the upper semiconductor layer 2 and the bit line plug 400 have different conductivity types, they form a pN diode. ^^7, the diode may be used as a rectifier (reCtifier). As a result, when a reverse voltage is applied to the bit line plug 4, this voltage is not applied to the upper semiconductor layer 200. That is, the bit line plug 400 and the upper semiconductor layer 2 may be electrically independent. In another preferred embodiment, the bit line plug 400 may be composed of a metal material such as tungsten, titanium, tantalum, titanium nitride, tantalum nitride, and nitride: in this case, for mutual electricity The isolation isolation bit line plug 4 〇〇 and the upper half 叆 layer 2 〇〇, the gate insulating layer 155 as shown in FIG. 2B may be formed on the sidewall of the bit = line plug 400. The drain insulating layer 155 may be formed using a well-known spacer forming process. In a preferred embodiment, the bit line plug 400 may be divided into two knives, one of which is an upper bit line above the upper semiconductor layer 200 and a 200822345 25735 pif plug' and the other part is a semiconductor. The lower bit line of the layer is plugged. Also, the width of the formed upper bit line plug may be larger than the width G1 of the drain hole 501 as shown in Figs. 1A, 1B, 1D, and 2A. Therefore, the upper bit line plug will be connected to the upper drain region 210D formed on either side of the stepless via 501. Further, the width of the lower bit line plug formed may be less than or equal to the width G1 of the drain via 501. Also, the lower bit line plug is continuously extended by the bottom surface of the upper bit line plug so as to be connected to the lower drain region 110D. In another preferred embodiment, referring to FIG. 1 (:; and 2 (:, the bit line plug 400 may be set to have the upper bit line plug 4〇2 and the lower bit line plug 401. Here, The upper bit line plugs 4〇2 are isolated from each other. In this example, the upper bit line plug 402 is electrically connected to the bit line bl and the upper drain region 210D, and the lower bit line plug 401 is electrically connected to the bit line. B£ and the lower drain region n〇D. And, although the upper bit line plug 402 and the lower bit line plug 々οι are physically separated from each other, they form an equipotential because they are commonly connected to the bit line BL. In a preferred embodiment, the source plug 300 may be formed of the same polycrystalline as the lower and upper source regions 110S and 210S. In this example, the source plug 300 may be at the source. The sidewall of the via 502 is in contact with the upper semiconductor layer 200. Since the upper semiconductor layer 2 and the source plug 3 are of different conductivity types, they form a PN diode which acts as a rectifier. When a reverse voltage is applied to the source plug 300, this voltage is not applied to the upper semiconductor layer 200. That is, the source plug 300 is The semiconductor layer 20 〇 may be electrically independent. 200822345 25735pif In another preferred embodiment, the source plug 300 may be made of a metal such as tungsten, titanium, a button, a titanium nitride, a nitride button, and a tungsten nitride. One of the materials is formed. In this example, the source insulating layer 156 may be formed on the sidewall of the source plug 3 (10) to electrically isolate the source plug 300 from the upper semiconductor layer 200. 'Source insulating layer 156 may be formed using a well-known spacer formation process. In another preferred embodiment, the upper semiconductor layer 2 and the lower semiconductor layer 100 are formed using the lower and upper source regions 11 (10) and 21 〇 s, etc. Potential. In this example, the source insulating layer 156 is not formed, and the source plug 3 (8) may include a barrier metal layer to make ohmic contact with the lower and upper semiconductor layers 1 and 2 (8). In the example, the source plug 3 (8) may be divided into two parts, one of which is an upper source plug above the upper semiconductor layer 200 and the other part is a lower source plug that passes through the upper semiconductor layer 2 (8). , opened > into the upper source plug The degree may be greater than the source via: the width of 5 〇 2 is shown in Figure IB, IB, 1D, and 2A. Therefore, the upper source plug will be connected to the upper source formed on either side of the source via 502. In addition, the width of the formed lower source plug is less than or equal to the width G2 of the source plate through hole =0. And, the lower source plug is extended by the bottom surface of the upper source plug so as to be Connected to the lower source region 110S. In another preferred embodiment, as shown in FIGS. 1C and 2C, the source plug 300 may be configured to have a plurality of upper source plugs 302 and lower source plugs 301. The upper source plugs 302 are electrically connected to the common source line CSL and the upper source region 210S, and the lower source plugs 301 are electrically connected to the common source. The line CSL and the lower source region 200822345 25735pif U can also form a common source line CSL and lower and upper source plugs 3〇1 and 3〇2 simultaneously using a damascene process. In this example, the upper source plug 302 and the lower source plug 301 form an equipotential, as shown by 2C·. Fig. 3A to Fig. 3D are cross-sectional views showing a method of manufacturing a NAND flash memory device in accordance with a preferred embodiment. Hereinafter, a method of forming the bit line plug 4 〇〇 and the source plug 3 (8) will be described in detail with reference to Figs. 3A to 3D. In Fig. 3A, a lower gate structure 12A is formed on the lower semiconductor layer 1A. Thereafter, an ion implantation process is performed using the lower gate structure 12A as a lower impurity region 110, a lower source region 11〇s, and a lower jaw for forming the lower semiconductor layer 1〇〇. An ion mask of the pole region n〇D. Next, the lower etch stop layer 13A and the lower interlayer insulating layer 140 are sequentially formed on the resultant structure in which the lower gate structure 120 is formed. Further, the upper semiconductor layer 200 is formed on the lower interlayer insulating layer 140. As described above, the upper semiconductor layer 200 has the drain via 5 〇 1 and the source via 502. In a preferred embodiment, various methods may be utilized to form the upper semiconductor layer 200. Hereinafter, before the method of forming the bit line plug 4 〇〇 and the source line plug 300 will be described, a method of forming the upper semiconductor layer 2 将 will be described with reference to FIGS. 5A, 5B, 6A to 6C, 7 8 and 7B. .

在一較佳實施例中，可能利用以下半導體層1〇〇作為 晶種層（seed layer)的蟲晶技術(epitaxial technology)來形成 上半導體層200。尤其，在形成下層間絕緣層14〇之後， 可能形成種晶孔(seed hole)88於下層間絕緣層140中以使 下半導體層100的預定區域曝露出來，如圖1A、1C、5A 17 200822345 25735pif 以及5B所示。在此，，圖5A及5B分別是沿著圖1A及1C 的虛線I - I ’及Π-Π’所截取的斷面圖。接著，利用許多磊 晶技術當中一種來形成充填種晶孔88的種晶插塞(seed plug)99,以及覆蓋下層間絕緣層140的磊晶半導體層199。 並且，蠢晶半導體層199由種晶插塞99延伸。遙晶製程的 結果是蟲晶半導體層199可能具有單晶結構。其後，表昭 夕 “、、 圖5B ’將圖案化蟲晶半導體層199以形成具有没極通孔 501及源極通孔502的上半導體層200。在一較佳實施例 中，在圖案化磊晶半導體層199之前，可能利用例如化學 機械研磨（chemical mechanical polishing，CMP)等等的平面 化技術來額外執行平面化磊晶半導體層199頂面的製程。 在另一較佳實施例中，可能利用晶圓接合 (wafer-bonding)技術來形成上半導體層2〇〇。尤其，參照^ 6A，在形成下層間絕緣層14〇之後，由單晶半導體所構: 的晶圓WF可能與下層間絕緣層14〇接合。尤其，可能在 晶圓WF與下層間絕緣層14〇之間額外形成附^屄 (adhesive layer)以便接合晶圓WF與下層 二 且，參照圖紐政，將侧晶圓卿以形成m = 199’ ’之後將圖案化薄半導體層199，以形 通θ 501及源極通孔观的上+ #_ _ ^ _ St孔 不’在此實施例巾並不需要上述W 7 種晶孔88的额外區域。 而之用以形成 18 200822345 25735pif (m〇ld paifn)195以劃定汲極通孔5〇1及源極通孔502的 位置。接著，將沈積半導體層m於包括鑄模圖案⑼的 5成、、、σ構上尤"可施利用化學氣相沈積vap〇r deposition, CVD)^(at〇mic deposition, ALD)MM ftm 成半層198。在較佳實施例中，半導體層198可能是 非晶石夕、多晶石夕、以及單晶石夕其中之一。並且，可能額外 執打預定結晶製程使半導體層198具有單晶結構。其後， c 圖7B_’將在半導體層198上執行平面化侧直到使鱗 松圖案19：)的了頁面曝露出來為止。因此，上半導體層· 形成於鑄模圖案！95所劃定的空間。在此例巾，因為利用 鑄模圖案195作為鑄模來形成上半導體層2〇〇，所以不需 要額外的圖案化製程就可形成穿過上半導體層200的没極 通札及源極通孔5〇2。 回頭參照圖3Α，上閘極結構22〇形成於上半導體層 200上。其後’將利用上閘極結構220作為離子光罩來執 行離子植入製程，以便在上半導體層2〇〇中形成上雜質區 .210、上源極區210S、以及上汲極區21〇d。接著，上蝕 終止層230與第一上層間絕緣層241依序形成於包括上閘 極結構.220的合成結構上。 亚且，將圖案化第一上層間絕緣層241及下層間絕緣 '140以形成源極接觸孔15〇。這些源極接觸孔⑽穿 且使下源極區11GS曝露.出來。並且，源極 接觸孔150形成於上半導體層2〇〇的上方使得其寬度大於 源極通孔：>〇2的寬度，因而使上源極區的頂面曝露出來。 19 200822345 25735pif 此外，將形成上蝕刻終止層230以避免在源極接觸孔i5〇 的形成期間造成上半導體層2GG (例如，特別是上源極區 210S)的蝕刻損害。亦即，源極接觸孔15〇的形成包括利用 相對於上蝕刻終止層23Ό具有蝕刻選擇性的蝕刻配方(etch recipe)來蝕刻第一上層間絕緣層241及下層間絕緣層 140。此外，所形成的上蝕刻終止層23〇最好是比下蝕刻二 止層130厚，以避免在下蝕刻終止層i3〇的蝕刻期間損害 上半導體層.200的頂面。 ' 口In a preferred embodiment, the upper semiconductor layer 200 may be formed using the following semiconductor layer 1 as an epitaxial technology of a seed layer. In particular, after the lower interlayer insulating layer 14 is formed, a seed hole 88 may be formed in the lower interlayer insulating layer 140 to expose a predetermined region of the lower semiconductor layer 100, as shown in FIGS. 1A, 1C, 5A 17 200822345 25735pif and 5B are shown. Here, Figs. 5A and 5B are cross-sectional views taken along the broken lines I - I ' and Π - Π ' of Figs. 1A and 1C, respectively. Next, a seed plug 99 filling the seed hole 88 and an epitaxial semiconductor layer 199 covering the lower interlayer insulating layer 140 are formed using one of a plurality of epitaxial techniques. Also, the stray semiconductor layer 199 is extended by the seed crystal plug 99. As a result of the telecrystal process, the insect crystal semiconductor layer 199 may have a single crystal structure. Thereafter, Table 5B, the patterned germanic semiconductor layer 199 is patterned to form the upper semiconductor layer 200 having the via via 501 and the source via 502. In a preferred embodiment, the pattern Prior to the epitaxial semiconductor layer 199, a planarization technique such as chemical mechanical polishing (CMP) or the like may be utilized to additionally perform the process of planarizing the top surface of the epitaxial semiconductor layer 199. In another preferred embodiment It is possible to form the upper semiconductor layer 2 by using a wafer bonding technique. In particular, referring to ^6A, after forming the lower interlayer insulating layer 14?, the wafer WF constructed by the single crystal semiconductor may be The lower interlayer insulating layer 14 is bonded. In particular, an additional adhesive layer may be formed between the wafer WF and the lower interlayer insulating layer 14 以便 to bond the wafer WF and the lower layer 2, and referring to FIG. After wafer formation to form m = 199'', the thin semiconductor layer 199 will be patterned to form θ 501 and the source via view + #_ _ ^ _ St hole is not required in this embodiment. An additional area of the above-mentioned W crystal holes 88. It is used to form 18 200822345 25735pif (m〇ld paifn) 195 to define the positions of the drain via 5 〇 1 and the source via 502. Next, the semiconductor layer m is deposited on the mold including the mold pattern (9), The σ structure may be applied by chemical vapor deposition vap〇r deposition, CVD) MM mic MM ftm into a half layer 198. In a preferred embodiment, the semiconductor layer 198 may be amorphous. One of the eve, the polycrystalline stone, and the single crystal stone. Also, it is possible to additionally perform a predetermined crystallization process to have the semiconductor layer 198 have a single crystal structure. Thereafter, cFig. 7B_' will perform planarization on the semiconductor layer 198. The side is exposed until the page of the scales pattern 19:) is exposed. Therefore, the upper semiconductor layer is formed in the space defined by the mold pattern! 95. In this case, the upper semiconductor is formed by using the mold pattern 195 as a mold. Since the layer 2 is formed, the pass-through and source via 5s2 passing through the upper semiconductor layer 200 can be formed without an additional patterning process. Referring back to FIG. 3, the upper gate structure 22 is formed on the upper layer. On the semiconductor layer 200. Thereafter, the upper gate will be utilized. The pole structure 220 performs an ion implantation process as an ion mask to form an upper impurity region .210, an upper source region 210S, and an upper drain region 21〇d in the upper semiconductor layer 2〇〇. The layer 230 and the first upper interlayer insulating layer 241 are sequentially formed on the composite structure including the upper gate structure .220. Further, the first upper interlayer insulating layer 241 and the lower interlayer insulating layer 140 are patterned to form a source contact. Hole 15〇. These source contact holes (10) are passed through and the lower source region 11GS is exposed. Also, the source contact hole 150 is formed over the upper semiconductor layer 2'''''''''''''''''''''''''''''''''' 19 200822345 25735pif In addition, an upper etch stop layer 230 will be formed to avoid etch damage of the upper semiconductor layer 2GG (e.g., particularly the upper source region 210S) during formation of the source contact hole i5?. That is, the formation of the source contact hole 15A includes etching the first upper interlayer insulating layer 241 and the lower interlayer insulating layer 140 with an etch recipe having an etch selectivity with respect to the upper etch stop layer 23A. Further, the formed upper etch stop layer 23 is preferably thicker than the lower etch stop layer 130 to avoid damaging the top surface of the upper semiconductor layer .200 during the etching of the lower etch stop layer i3. ' mouth

參照圖3Β，在一較佳實施例中，將形成充填源極接 觸孔150的源極插塞300以及共同源極線CSL。因此，將 利用鑲嵌製程來形成源極接觸孔及源極插塞3〇〇。另一方 面，根據另一較佳實施例，可能利用雙鑲嵌製程（duaI damascene process)來形成源極插塞3⑽，如圖4A至4C所 示。參照圖4A至4C，第一上層間絕緣層241可能包括依 序堆®的第一至第三絕緣層241a、241b、以及241c。將圖 案化第一上層間絕緣層241以形成用以劃定源極接觸孔 150 的初步接觸孔(preuminary contact hole)149。此外，預 定光罩圖案(mask pattern)5 0接著形成於合成結構上以便使 初步接觸孔149曝露出來。並且，將利用光罩圖案50作為 钱刻光罩來圖案化第一上層間絕緣層241及下層間絕緣層 140。並且，在雙鑲嵌製程期間使用第二絕緣層241b作為 儀刻終止層，而其用，以轉移初步接觸孔149所劃定的接觸 孔結構至下層140及240。因此，第二絕緣層241b可能由 相對於第一及第三絕緣層241a及241c具有蝕刻選擇性的 20 200822345 25735pif 材料所構成。例如，第二絕緣層241b可能由氮化矽所構成。 參照圖3C，第二上層間絕緣層242形成於包括源極 插塞300的合成結構上。尤其，第二上層間絕緣層242連 同第一上層間絕緣層241構成上層間絶緣層240。隨後， 將圖案化上及下層間絕緣層240及140以形成穿過汲極通 孔501且使下汲極區11〇〇曝露出來的汲極接觸孔151。在 此例中，汲極接觸孔151形成於上半導體層2〇〇的上方使 得其寬度大於汲極通孔501的寬度，以便使上汲極區21〇d 的頂面曝露出來。並且，將形成上蝕刻終止層23〇以避免 ，形成汲極接觸孔151時造成上半導體層2〇〇(例如，特別 疋上汲極區210D)的蝕刻損害。亦即，汲極接觸孔15丨的 形成包括利用相對於上蝕刻終止層23〇具有蝕刻選擇性的 蝕刎配方來蝕刻上層間絕緣層240及下層間絕緣層14〇。 此外，所形成的上蝕刻終止層230最好是比下蝕刻終止層 uo厚，以避免在下蝕刻終止層130的蝕刻期間損害上^ 導體層200的頂面。 " 芩照圖3D，將形成位元線插塞4〇〇以充填汲極接觸 孔151。隨後，與位元線插塞4〇〇接觸且跨越字元線 的位元線BL形成於上層間絕緣層24〇上。在一較佳實施 例中，汲極絕緣層（見圖2B的參考數字155) 於 ，妾觸麵的侧壁上。同勝 削，源極絕緣層（見圖2B的156)可能形成於源極接觸孔15〇 的侧壁上。汲極及源極絕緣層155及156可能利用典 間隙壁形成製程來形成。 200822345 25735pif 施例ί述以製造任何半導體裝置。在-較佳實 ㈣區的上 1 土 ::體層=其在下半導體層的下源極 工將形成源極及位元線插塞使得其通過通孔。因士 ，J性連接三維排列記憶胞的源極及汲極電極 : 及日日片面積有效性。 才貝 、揭鉻的主要内容應視為用以說明而非限定太 :因此;附之申請專利範圍將包含所有此種符= 白jj精神二乾’的修改、加強以及其他實施例。因此 最大化法料賦與_獅護麵，本剌的範圍將取 於了列，請專利範圍及其等效的最廣可允許解釋，;、 定或侷限於前面的詳細說明。 义 【圖式簡單說明】 包含附圖是為了提供對本發明的進一步理解，其併入 真構成本說明書的-部分。附圖繪示本發明的較佳實施 例，並且連同其說明用以解釋本說明書的原理。在圖中： 圖1A至1D是根據較佳實施例之NAND快閃記憶 ί/; 裝置的記憶胞陣列的平面圖。 心 圖2Α至2C是根據較佳實施例之NAND快閃記憶體 装置的記憶胞陣列的斷面圖。 〜 圖3Α至3D是根據一較佳實施例之NAND快閃記憶 : 雜裝置的製造方法的斷面圖。 : 圖4A至4C疋根據另—較佳實施例之NAND快閃記 慎體裝罝的製造方法的斷面圖。 200822345 25735pif 圖5A及5B是根據又另一較佳實施例之NAND快閃 記憶體裝置的製造方法的斷面圖。 圖6A至6C是根據又另一較佳實施例之NAND快閃 記憶體裝置的製造方法的斷面圖。................ .............—........ 圖7A及7B是根據又另一較佳實施例之NAND快閃 記憶體裝置的製造方法的斷面圖。 【主要元件符號說明】 50 預定光罩圖案 88 種晶孔 99 種晶插塞 100 下半導體層 105 下閘極絕緣層 110 下雜質區 110D 下汲極區 110S 下源極區 120 下閘極結構 121 下浮動電極 12.2 下閘極層間絕緣層 123 下控制電極 124下覆蓋圖案 129 閘極間隙壁 130 下钱刻終止層 140 下層間絕緣層 149 初步接觸孔 23 200822345 25735pif 150 151 155 15 6 • 195 198 199 , 199, i 200 205 210 210D 210S 220 221 222 i / 223 224 229 230 ； 240 - 241 241a 241b 源極接觸孔 汲極接觸孔 汲極絕緣層 源極絕緣層 鑄模圖案 半導體層 蠢晶半導體層 薄半導體層 上半導體層 上閘極絕緣層 上雜質區 上;及極區 上源極區 上閘極結構 上浮動電極 上閘極層間絕緣層 上控制電極 上覆蓋圖案 閘極間隙壁 上钱刻終止層 上層間絕緣層 第一上層間絕緣層 第一絕緣層 第二絕緣層 24 200822345 25735pif 241c 242 300 301 302 400 401 r 402 501Referring to Fig. 3A, in a preferred embodiment, a source plug 300 filling the source contact hole 150 and a common source line CSL will be formed. Therefore, the source contact hole and the source plug 3 are formed by the damascene process. On the other hand, according to another preferred embodiment, it is possible to form the source plug 3 (10) using a dual damascene process, as shown in Figs. 4A to 4C. Referring to FIGS. 4A to 4C, the first upper interlayer insulating layer 241 may include first to third insulating layers 241a, 241b, and 241c of the sequential stack®. The first upper interlayer insulating layer 241 is patterned to form a preliminary contact hole 149 for delineating the source contact hole 150. Further, a predetermined mask pattern 50 is then formed on the composite structure to expose the preliminary contact hole 149. Further, the first upper interlayer insulating layer 241 and the lower interlayer insulating layer 140 are patterned by using the mask pattern 50 as a money mask. Also, the second insulating layer 241b is used as an etch stop layer during the dual damascene process, and is used to transfer the contact hole structure defined by the preliminary contact holes 149 to the lower layers 140 and 240. Therefore, the second insulating layer 241b may be composed of 20 200822345 25735 pif material having an etch selectivity with respect to the first and third insulating layers 241a and 241c. For example, the second insulating layer 241b may be composed of tantalum nitride. Referring to FIG. 3C, a second upper interlayer insulating layer 242 is formed on the composite structure including the source plugs 300. In particular, the second upper interlayer insulating layer 242 and the first upper interlayer insulating layer 241 constitute the upper interlayer insulating layer 240. Subsequently, the upper and lower interlayer insulating layers 240 and 140 are patterned to form a drain contact hole 151 which passes through the drain via 501 and exposes the lower drain region 11A. In this example, the drain contact hole 151 is formed over the upper semiconductor layer 2〇〇 such that its width is larger than the width of the gate via 501 to expose the top surface of the upper drain region 21〇d. Also, the upper etch stop layer 23 is formed to avoid etching damage of the upper semiconductor layer 2 (e.g., particularly the upper drain region 210D) when the drain contact hole 151 is formed. That is, the formation of the drain contact hole 15A includes etching the upper interlayer insulating layer 240 and the lower interlayer insulating layer 14 by using an etching recipe having an etch selectivity with respect to the upper etch stop layer 23A. In addition, the formed upper etch stop layer 230 is preferably thicker than the lower etch stop layer uo to avoid damage to the top surface of the upper conductor layer 200 during etching of the lower etch stop layer 130. " Referring to Fig. 3D, a bit line plug 4 将 will be formed to fill the drain contact hole 151. Subsequently, a bit line BL which is in contact with the bit line plug 4 and which spans the word line is formed on the upper interlayer insulating layer 24A. In a preferred embodiment, the drain insulating layer (see reference numeral 155 of Figure 2B) is on the sidewall of the tantalum contact. In the same manner, the source insulating layer (see 156 of Fig. 2B) may be formed on the sidewall of the source contact hole 15?. The drain and source insulating layers 155 and 156 may be formed using a typical spacer formation process. 200822345 25735pif Example to make any semiconductor device. In the upper-earth region of the preferred (four) region: the bulk layer = its lower source in the lower semiconductor layer will form a source and bit line plug such that it passes through the via. Instinct, J-connected three-dimensional array of memory cell source and drain electrode: and day area effective. The main content of the jewellery and the chrome shall be deemed to be illustrative and not limiting: therefore, the scope of the patent application will include all such modifications, enhancements and other embodiments. Therefore, the maximum material is given to the _ lion's face, the scope of this book will be taken from the list, the scope of the patent and its equivalent are the most widely allowed interpretation;; or limited to the previous detailed description. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings are included to provide a further understanding of the invention The drawings illustrate the preferred embodiments of the invention and, together with In the drawings: Figures 1A through 1D are plan views of a memory cell array of a NAND flash memory device in accordance with a preferred embodiment. Figures 2A through 2C are cross-sectional views of a memory cell array of a NAND flash memory device in accordance with a preferred embodiment. ~ Figures 3A through 3D are cross-sectional views of a method of fabricating a NAND flash memory according to a preferred embodiment. 4A to 4C are cross-sectional views showing a method of manufacturing a NAND flash memory device according to another preferred embodiment. 200822345 25735pif Figures 5A and 5B are cross-sectional views showing a method of fabricating a NAND flash memory device in accordance with still another preferred embodiment. 6A through 6C are cross-sectional views showing a method of fabricating a NAND flash memory device in accordance with still another preferred embodiment. .............................................. Figures 7A and 7B are according to yet another preferred embodiment. A cross-sectional view showing a method of manufacturing a NAND flash memory device. [Main component symbol description] 50 predetermined mask pattern 88 kinds of crystal holes 99 kinds of crystal plugs 100 lower semiconductor layer 105 lower gate insulating layer 110 lower impurity region 110D lower drain region 110S lower source region 120 lower gate structure 121 Lower floating electrode 12.2 Lower gate interlayer insulating layer 123 Lower control electrode 124 Lower cover pattern 129 Gate spacer 130 Lower stop layer 140 Lower interlayer insulating layer 149 Preliminary contact hole 23 200822345 25735pif 150 151 155 15 6 • 195 198 199 , 199, i 200 205 210 210D 210S 220 221 222 i / 223 224 229 230 ; 240 - 241 241a 241b source contact hole drain contact hole drain insulating layer source insulating layer mold pattern semiconductor layer amorphous semiconductor layer thin semiconductor On the impurity layer on the gate insulating layer of the upper semiconductor layer; and on the upper gate region of the upper gate region of the floating region on the upper electrode layer of the floating electrode on the floating electrode on the gate electrode layer Interlayer insulating layer first upper interlayer insulating layer first insulating layer second insulating layer 24 200822345 25735pif 241c 242 300 301 302 400 401 r 402 501

502 BL CSL G1 G2 GSL SSL502 BL CSL G1 G2 GSL SSL

I WFI WF

WL 第三絕緣層 第二上層間絕緣層 源極插塞 下源極插塞 上源極插塞 位元線插塞 下位元線插塞 上位元線插塞 没極通孔 源極通孔 位元線 共同源極線 汲極通孔501的寬度 源極通孔502的寬度 接地選擇線 字串選擇線 晶圓 字元線 25WL third insulating layer second upper interlayer insulating layer source plug lower source plug on source plug bit line plug lower bit line plug upper bit line plug no pole through hole source through hole bit Width of Line Common Source Line Bipolar Through Hole 501 Width of Source Through Hole 502 Ground Selection Line String Selection Line Wafer Word Line 25

Claims (1)

200822345 25735pif 十、申請專利範圍： 1·一種NAND快閃記憶體裝置，包括·· 下丁¥體層及上半導體層，所述上半導體層位於所述 下半導體層的I方·；......................... 、 第一汲極區及第一源極區，位於所述下半導體層中，· 弟一及極區及第.一源極區，位於所述上半導體層中； 第一閘極結構，位於所述下半導體層上； 第二閘極結構，位於所述上半導體層上； 位元線，位於所述上半導體層的上方；以及 至少一個位元線插塞，連接在所述位元線與所述第一 汲極區之間，其中所述至少一個位元線插塞經由位於所述 上半導體層中的没極通孔延伸。 ^ 2·如=請專利範圍第1項所述之NAND快閃記憶體裝 直，其中母一個所述閘極結構包括：與所述第一或第二汲 f區相鄰的字串選擇線；與所述第一或第二源極區相鄰的 接地選擇線；以及多條位於所述字串選擇線與所述接地選 擇線之間的字元線，其中所述位元線以跨越所述字元線的 方向延伸。 3·如申請專利範圍第丨項所述之NAND快閃記憶體裝 置，其中所述上半導體層中的所述第二汲極區與所述汲極 通孔相鄰。 4·如申明專利範圍第3項所述之NAND快閃記憶體裝 置，其中所述至少一個位元線插塞包括： 上位元線插塞，位於所述上半導體層的上方，並且連 26 200822345 25735pif 接，與所述汲極通孔相鄰的所述上半導體層的所述第二汲 極區其巾所述上位元線插塞的寬度大於所述1極通孔的 寬度；以及 、、下位兀線插塞，其由所述上位元線插塞延伸且通過所 述汲極通孔，並連接到所述下半導體層的所述第一汲極區。 5·如申請專利範圍第i項所述之NAND快閃記憶體裝 直’其中所述至少-個位元線插塞包括： 、、斤上位兀線插塞，在所述位元線與所述上半導體層的所 述弟^一卩及極區之間延伸；以及 、—下位元線插基，在所述位元線與所述下半導體層的所 述第一汲極區之間延伸， 其中所述r位7L線插塞通過所述汲極通孔且與所述 上位元線插塞分離。 6·如申清專利範圍第1項所述之NANd快閃記憶體裝 置，其，所述至少一個位元線插塞由包含鎢、鈦、鈕、氮 化鈦、氮化叙、氮化鎢、以及多晶石夕的群組中選出的 一種材料所構成。 7·如申請專利範圍第1項所述之NAND快閃記憶體裝 置’、更包括汲極絕緣層，位於所述汲極通孔的内壁上且其 所述至少—個位讀插塞與所述上半導體層_壁隔離Γ 8·如申請專利範圍第丨項所述之NAND快閃記憶體裝 置，更包括上蝕刻終止層，位於所述上半導體層的上^ 覆蓋所述第二閘極結構。 9·如申請專利範圍帛8項所述之NAm快閃記憶體裝 21 200822345 25735pif 置，更包括下银刻終止層，位於所述下半導體層的上方且 覆蓋所述第一閘極結構，其中所述上蝕刻終止層比所述下 . 蝕刻終止層厚。 • ί0·如申請專利範圍第2項所述之ΝΑΝϋ快閃記憶體 裝置，更包括： 共同源極線，位於所述位元線的下方且與所述第一及 第二閘極結構的所述接地選擇線互相平行地延伸；以及 Γ) 至少一個源極插塞，電性連接所述共同源極線與所述 下及上半導體層各自的所述第一及第二源極區。 士 11 ·如申請專利範圍第10項所述之N AND快閃記憶體 二i其中所返上半導體層更包括源極通孔，位於所述下 半導體層的所述第一源極區的上方，並且其中所述至少一 個源極插塞通過所述源極通孔。 U·如申请專利範圍第11項所述之NAND快閃記憶體 裝1，其中所述上半導體層的所述第二源極區與所述源極 通孔相鄰。 i) 士 I3·如申請專利範圍第12項所述之NAND快閃記憶體 I置，其中所述至少一個源極插塞包括： 上源極插塞，位於所述上半導體層的上方，且連接到 • 與所述源極通孔相鄰的所述上半導體層的所述第二源極 • 品/、中所述上源極插塞的寬度大於所述源極通孔的寬 - 度，以及 、丁源極插塞，由所述上源極插塞延伸且通過所述源極 通孔’並連接到所述下半導體層的所述第一源極區。 28 200822345 25735pif 寻利範圍第u項所述之财叫夫閃記 裝置’其中所述源極插塞包括·· 〜 上源極插塞，在所述共同源極線與所述 所述第二源極區之間延伸；:以犮一層的 下源極插塞，在所述共同源極線與 所述第-雜區之間延伸， f 的 其中所述下源極插塞通過所述源極通孔且200822345 25735pif X. Patent Application Range: 1. A NAND flash memory device comprising: a body layer and an upper semiconductor layer, the upper semiconductor layer being located at the I side of the lower semiconductor layer; ....................., the first drain region and the first source region are located in the lower semiconductor layer, · the first and the polar regions and the first a source region in the upper semiconductor layer; a first gate structure on the lower semiconductor layer; a second gate structure on the upper semiconductor layer; a bit line on the Above the semiconductor layer; and at least one bit line plug connected between the bit line and the first drain region, wherein the at least one bit line plug is located in the upper semiconductor layer The immersed through hole extends. ^2. If the NAND flash memory described in claim 1 is straight, wherein one of the gate structures includes: a string selection line adjacent to the first or second 汲f region a ground selection line adjacent to the first or second source region; and a plurality of word lines between the string selection line and the ground selection line, wherein the bit line crosses The direction of the word line extends. 3. The NAND flash memory device of claim 2, wherein the second drain region in the upper semiconductor layer is adjacent to the drain via. 4. The NAND flash memory device of claim 3, wherein the at least one bit line plug comprises: an upper bit line plug located above the upper semiconductor layer, and connected 26 200822345 25735pif, the second drain region of the upper semiconductor layer adjacent to the drain via, the width of the upper bit line plug of the towel is greater than the width of the 1-pole via; and, the lower position a line plug extending from the upper bit line plug and passing through the drain via and connected to the first drain region of the lower semiconductor layer. 5. The NAND flash memory device as described in claim i of the scope of the invention, wherein the at least one bit line plug comprises: a pinch plug, in which the bit line and the place An extension between the gate and the drain region of the semiconductor layer; and a lower bit line interposer extending between the bit line and the first drain region of the lower semiconductor layer Wherein the r-bit 7L line plug passes through the drain via and is separated from the upper bit line plug. 6. The NANd flash memory device of claim 1, wherein the at least one bit line plug comprises tungsten, titanium, a button, a titanium nitride, a nitride, and a tungsten nitride. And a material selected from the group of polycrystalline stone eves. 7. The NAND flash memory device as claimed in claim 1, further comprising a drain insulating layer on the inner wall of the drain via and the at least one bit read plug and the ground The NAND flash memory device as described in claim 2, further comprising an upper etch stop layer on the upper semiconductor layer covering the second gate structure. 9. The NAm flash memory device 21 200822345 25735pif according to claim 8 further includes a lower silver engraving stop layer over the lower semiconductor layer and covering the first gate structure, wherein The upper etch stop layer is thicker than the lower etch stop layer. Ί0. The flash memory device of claim 2, further comprising: a common source line, located below the bit line and with the first and second gate structures The ground selection lines extend parallel to each other; and 至少) at least one source plug electrically electrically connecting the common source line and the first and second source regions of the lower and upper semiconductor layers, respectively. 11. The N AND flash memory 2 as described in claim 10, wherein the returned semiconductor layer further includes a source via, located above the first source region of the lower semiconductor layer, And wherein the at least one source plug passes through the source via. U. The NAND flash memory device 1 of claim 11, wherein the second source region of the upper semiconductor layer is adjacent to the source via. The NAND flash memory I set according to claim 12, wherein the at least one source plug comprises: an upper source plug, located above the upper semiconductor layer, and Connecting to the second source of the upper semiconductor layer adjacent to the source via, the width of the upper source plug is greater than the width of the source via, and a Ding source plug extending from the upper source plug and passing through the source via hole 'and connected to the first source region of the lower semiconductor layer. 28 200822345 25735pif The profit-seeking device of claim 5, wherein the source plug includes an upper source plug, the common source line and the second source Extending between the pole regions; extending from the common source line and the first-of-staff region by a lower source plug of a layer, wherein the lower source plug of f passes through the source Through hole 源極插塞分離。 ^ 15·如申睛專利範圍第！ 〇項所述之NAND快閃記憶體 裝置，，中所述至少-個源極插塞由包含鶴、欽、趣、氮 化敛氮化!旦、氮化鎢、以及多晶石夕的君夢組中選出的至少 一種封料所構成。 16·如申請專利範圍第1〇項所述之ναν〇快閃記憶體 裝| ,更包括源極絕緣層，位於所述源極通孔的内壁上且 將所述至少一個源極插塞與所述上半導體層的侧壁隔離。 17·—種NAND快閃記憶體裝置的製造方法，包括·· 在下半導體層中形成下源極區及下汲極區； 在所述下半導體層的上方形成上丰導體層，所述上半 導體層包括汲極通孔、上源極區、以及上汲極區；以及 形成至少一個位元線插塞，經由所述汲極通孔延伸且 連接到所述上及下汲極區。 18·如申請專利範圍第〗7項所述之NAND快閃記憶體 裝置的製造方法，其中所述上半導體層更包括源極通孔， 且/、中所述方法更包括形成至少一個源極插塞，經由所述 29 200822345 25735pif 源極通孔延伸且連接到所述上及下源極區。 伙如申請專利範圍第18項所述之_0快閃記憶體 裝置的製造方法’其中所述上半導體層的形成包括： 藉由利用職下半導體層作為晶-糧層·行羞晶製 程以形成蟲晶梦層於所述下半導體層上· Γ 平面化所述蟲晶石夕層以形成所述上半導體層；以及 圖案化所述上半導體層以形成穿過所述上半導體層 的所述源極通孔與蹄通孔，其中所述源極通孔與没極通 孔分別排列在所述下源極區及汲極區的上方。 2 〇 ·如申請專利範圍第i 8項所述之Nand快閃記情體 衣置的製造方法，其情述上半賴層_彡成包括·， 形成下層間絕緣層於包括所述下半導體層的結構上； 接合晶圓與所述下層間絕緣層； 蝕刻所述晶圓以形成半導體層； 圖案化所述半導體層以形成所述上半導體層；以及 圖案化所述上半導體層以形成穿過所述上半導 、所述源極通孔與所述汲極通孔， ^ 其中所述源極通孔與汲極通孔分職列在所述 趣區及沒極區的上方。 ’、 教置=3土專利範圍第18項所述之Ν娜快閃記憶體 的衣仏方法，其中所述上半導體層的形成包括： 形成間絕緣層於包括所述下半導體層的結構上； 形成禱模圖案於所述下層間絕緣層上； 沈積半導體層於包括所述鑄模圖案的結構上；以及 30 200822345 25735pif 平面化所述半導體層直到曝露出使所述鑄模圖案為 止以形成所述上半導體層， 其中所述鑄模圖案位於所述源極與没極通孔的位置。 22·如申請專利範圍第21項所述之NAND快閃記憶體 裝置的製造方法，更包括在沈積所述半導體層之後結晶化 所述半導體層。 23·如申請專利範圍第17項所述之NAND快閃記憶體 裝置的製造方法，更包括：、 α 形成下閘極結構於所述下半導體層上，其中所述下閘 逐、7^籌包括·與所述下汲極區相鄰的字串選擇線；與所述 :源摄區相鄰的接地選擇線；以及多條位於所述字串選擇 線與所=接地選擇線之_字元線； ϋ a上閘極結構於所述上半導體層上，其中所述上閘 :、、；§』舟匕姑·與所返上汲極區相鄰的字串選擇線；與所逑 =禋區相鄰的接地選擇線，·以及多條位於字串選擇 線_述接地選擇線之_衫線；以及 位元ϋίΓ線，跨越所述字元線且連接到所述至少一個 F 如申凊專利範圍第18項所述2 NAND快閃記憶體 衣置的製造方法，更包括： 下層^述下半導體層與所述上半導體層之間的 圖於所述上半導體層上的上層間絕緣層； 木所述上及下層間絕緣層以形成曝露出所述下 200822345 25735pif 及上源極區的源極接觸孔；以及 及上、、==述上及下層間絕緣層以形成曝露出所述下 及上/及極區的位元線接觸孔。 k下 ^ ^ ® % 24 ΝΑΝϋ ^ 叙置的製造方法，其中所述上層n、體 源極區及所述上汲極區的上_終2 L所迹上 斤ί上|刻終止層的厚度是形成為能夠避免在所述 接觸孔及所述源極接觸孔當中至少-個的形成期門 造成所述上半導體層的侧損害。 1月間 26. 如申請專利範圍第25項所述之NAND快閃記情雕 裝f的製造方法，其中所述下層縣緣層包括覆蓋所 源極區及所述下汲極區的下蝕刻終止層，所述上蝕刻終止 層所开/；^的厚度比所述下射彳終止層厚。 27. 如申請專利範圍第24項所述之NAND快閃記憶體 裝置的製造方法，更包括：The source plug is separated. ^ 15·If the scope of the patent application is the first! The NAND flash memory device according to the above aspect, wherein the at least one source plug is composed of a crane, a hexadium, a nitriding nitride, a tungsten nitride, and a polycrystalline stone. At least one type of seal selected in the dream group. The ναν〇 flash memory device as described in claim 1 further includes a source insulating layer on the inner wall of the source via and the at least one source plug The sidewalls of the upper semiconductor layer are isolated. 17. A method of fabricating a NAND flash memory device, comprising: forming a lower source region and a lower drain region in a lower semiconductor layer; forming an upper conductor layer above the lower semiconductor layer, the upper semiconductor The layer includes a drain via, an upper source region, and an upper drain region; and forming at least one bit line plug extending through the drain via and connecting to the upper and lower drain regions. 18. The method of fabricating a NAND flash memory device according to claim 7, wherein the upper semiconductor layer further comprises a source via, and the method further comprises forming at least one source. A plug extends through the 29 200822345 25735 pif source via and is connected to the upper and lower source regions. The method for manufacturing a flash memory device as described in claim 18, wherein the forming of the upper semiconductor layer comprises: using a lower semiconductor layer as a crystal-grain layer and a shading process Forming a cryptic dream layer on the lower semiconductor layer Γ planarizing the cryptic layer to form the upper semiconductor layer; and patterning the upper semiconductor layer to form a region through the upper semiconductor layer The source through hole and the hoist through hole, wherein the source through hole and the bottomless through hole are respectively arranged above the lower source region and the drain region. 2 〇 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 N N N N N N N N N Structurally: bonding the wafer and the lower interlayer insulating layer; etching the wafer to form a semiconductor layer; patterning the semiconductor layer to form the upper semiconductor layer; and patterning the upper semiconductor layer to form a through Passing through the upper semiconductor, the source via and the drain via, wherein the source via and the drain via are listed above the interesting region and the non-polar region. The method for fabricating a flash memory according to the invention of claim 18, wherein the forming of the upper semiconductor layer comprises: forming an interlayer insulating layer on the structure including the lower semiconductor layer Forming a prayer pattern on the lower interlayer insulating layer; depositing a semiconductor layer on the structure including the mold pattern; and 30 200822345 25735pif planarizing the semiconductor layer until exposing the mold pattern to form the An upper semiconductor layer, wherein the mold pattern is located at a position of the source and the via hole. The method of fabricating a NAND flash memory device according to claim 21, further comprising crystallizing the semiconductor layer after depositing the semiconductor layer. The method of manufacturing a NAND flash memory device according to claim 17, further comprising: forming a lower gate structure on the lower semiconductor layer, wherein the lower gate is 7 a string selection line adjacent to the lower drain region; a ground selection line adjacent to the source region; and a plurality of word lines located between the string selection line and the ground selection line a top line; ϋ a upper gate structure on the upper semiconductor layer, wherein the upper gate:,,; § 舟 匕 匕 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 字 字 字 字 字 字 字 字 字 字a grounding selection line adjacent to the buffer area, and a plurality of _shirt lines located in the string selection line _ describing the ground selection line; and a bit ϋ Γ Γ line crossing the word line and connected to the at least one F The method for manufacturing a 2 NAND flash memory device according to the 18th aspect of the patent, further comprising: lowering an upper interlayer insulating layer on the upper semiconductor layer between the lower semiconductor layer and the upper semiconductor layer The upper and lower interlayer insulating layers of the wood are formed to expose the underlying 200822345 25735pif And a source contact hole of the upper source region; and an upper, lower and lower interlayer insulating layer to form a bit line contact hole exposing the lower and upper/polar regions. k under ^ ^ ® % 24 ΝΑΝϋ ^ The manufacturing method is described, wherein the upper layer n, the body source region and the upper 终2 L of the upper drain region are traced to the thickness of the etched layer It is formed to be able to avoid formation of a gate at least one of the contact hole and the source contact hole to cause side damage of the upper semiconductor layer. The manufacturing method of the NAND flash embossing f as described in claim 25, wherein the lower county edge layer includes a lower etch stop layer covering the source region and the lower drain region The thickness of the upper etch stop layer is thicker than the lower shot stop layer. 27. The method of manufacturing a NAND flash memory device according to claim 24, further comprising: 在形成所述至少一個源極插塞之前，形成源極絕緣層 於所述源極通孔的側壁上，其中所述源極絕緣層將所述至 少一個源極插塞與所述源極通孔的侧壁隔離；以及 在形成所述至少一個位元線播寨之前，形成汲極絕緣 層於所述汲極通孔的侧壁上，其^所述沒極絕緣層將所述 至少一個位元線插塞與所述汲極通孔的侧壁隔離。 28·如申請專利範圍第％項所述之NAND快閃記憶體 衣里的製造方法，其中利用雙镶嵌製輕來形成所述源極接 觸孔及所述源極插塞。 32Forming a source insulating layer on sidewalls of the source vias before forming the at least one source plug, wherein the source insulating layer connects the at least one source plug to the source Separating the sidewalls of the holes; and forming a drain insulating layer on the sidewalls of the drain vias before forming the at least one bit line, the non-polar insulating layer of the at least one The bit line plug is isolated from the sidewall of the drain via. 28. The method of fabricating a NAND flash memory device according to the above aspect of the invention, wherein the source contact hole and the source plug are formed by double damascene. 32
TW096137829A 2006-10-11 2007-10-09 Nand flash memory devices having 3-dimensionally arranged memory cells and methods of fabricating the same TWI423430B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020060099015A KR100806339B1 (en) 2006-10-11 2006-10-11 Nand flash memory devices having 3-dimensionally arranged memory cells and methods of fabricating the same

Publications (2)

Publication Number Publication Date
TW200822345A true TW200822345A (en) 2008-05-16
TWI423430B TWI423430B (en) 2014-01-11

Family

ID=39297603

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096137829A TWI423430B (en) 2006-10-11 2007-10-09 Nand flash memory devices having 3-dimensionally arranged memory cells and methods of fabricating the same

Country Status (5)

Country Link
US (1) US7602028B2 (en)
JP (1) JP2008098641A (en)
KR (1) KR100806339B1 (en)
CN (1) CN101162721A (en)
TW (1) TWI423430B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI587484B (en) * 2010-02-05 2017-06-11 半導體能源研究所股份有限公司 Semiconductor device
TWI787080B (en) * 2022-02-10 2022-12-11 旺宏電子股份有限公司 3d flash memory device

Families Citing this family (56)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080067554A1 (en) * 2006-09-14 2008-03-20 Jae-Hun Jeong NAND flash memory device with 3-dimensionally arranged memory cell transistors
US20080273390A1 (en) * 2007-05-04 2008-11-06 Promos Technologies Inc. NAND flash memory cell array and method of fabricating the same
US20090026524A1 (en) * 2007-07-27 2009-01-29 Franz Kreupl Stacked Circuits
KR100939409B1 (en) * 2008-01-21 2010-01-28 주식회사 하이닉스반도체 Method for forming damascene pattern of semiconductor device
KR100978911B1 (en) * 2008-02-28 2010-08-31 삼성전자주식회사 Semiconductor device and formation method thereof
JP4600576B2 (en) * 2008-05-08 2010-12-15 株式会社デンソー Semiconductor device and manufacturing method thereof
KR101483531B1 (en) * 2008-06-24 2015-01-20 삼성전자주식회사 Nonvolatile memory device
KR20100004770A (en) * 2008-07-04 2010-01-13 삼성전자주식회사 Memory semiconductor device
KR100991220B1 (en) 2008-07-21 2010-11-04 삼성전자주식회사 Contact structure in a substrate having an bonded interface, a semiconductor device having the same and methods of manufacturing the same
KR101032500B1 (en) 2009-01-06 2011-05-04 오영주 Memory device with three-dimensional structure
US8178396B2 (en) 2009-03-11 2012-05-15 Micron Technology, Inc. Methods for forming three-dimensional memory devices, and related structures
JP2010238747A (en) * 2009-03-30 2010-10-21 Toshiba Corp Nonvolatile semiconductor memory device
KR20110001063A (en) * 2009-06-29 2011-01-06 주식회사 하이닉스반도체 Semiconductor device and manufacturing method thereof
KR101155279B1 (en) * 2009-09-01 2012-06-18 에스케이하이닉스 주식회사 Semiconductor memory device
US8569829B2 (en) 2009-12-28 2013-10-29 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device
US8355281B2 (en) * 2010-04-20 2013-01-15 Micron Technology, Inc. Flash memory having multi-level architecture
TWI427744B (en) * 2010-09-01 2014-02-21 Macronix Int Co Ltd Three-dimensional array memory architecture with diodes in memory strings
US8659944B2 (en) 2010-09-01 2014-02-25 Macronix International Co., Ltd. Memory architecture of 3D array with diode in memory string
JP2012064854A (en) * 2010-09-17 2012-03-29 Toshiba Corp Semiconductor device
DE102011084603A1 (en) 2010-10-25 2012-05-16 Samsung Electronics Co., Ltd. Three-dimensional semiconductor device
CN103915113A (en) * 2010-12-14 2014-07-09 桑迪士克3D有限责任公司 Three-dimensional non-volatile storage with dual layers of select devices
US8630114B2 (en) * 2011-01-19 2014-01-14 Macronix International Co., Ltd. Memory architecture of 3D NOR array
CN102637692B (en) * 2011-02-10 2014-08-20 旺宏电子股份有限公司 Flash memory structure and methods of manufacture and operation thereof
US20120327714A1 (en) * 2011-06-23 2012-12-27 Macronix International Co., Ltd. Memory Architecture of 3D Array With Diode in Memory String
KR101857681B1 (en) 2011-07-07 2018-05-14 삼성전자주식회사 3-dimensional semiconductor memory devices and methods for fabricating the same
JP2013069932A (en) 2011-09-22 2013-04-18 Toshiba Corp Nonvolatile semiconductor storage device and manufacturing method of the same
FR2986371B1 (en) 2012-01-31 2016-11-25 St Microelectronics Sa METHOD OF FORMING A VIA CONTACTING MULTIPLE LEVELS OF SEMICONDUCTOR LAYERS
KR101370509B1 (en) 2012-02-24 2014-03-06 서울대학교산학협력단 3d stacked nand flash memory array enabling lsm and operation method thereof
JP2013201306A (en) * 2012-03-26 2013-10-03 Toshiba Corp Nonvolatile semiconductor storage device and manufacturing method of the same
JP6147480B2 (en) 2012-09-26 2017-06-14 株式会社日立国際電気 Semiconductor device manufacturing method, substrate processing apparatus, and program
KR102025339B1 (en) * 2013-03-07 2019-09-26 삼성전자 주식회사 Semiconductor device having a conductive plug
US9147472B2 (en) 2013-08-19 2015-09-29 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device having stacked memory cell layers and a control circuit controlling write or read based on parameters according to a selected memory cell layer
JP6139370B2 (en) * 2013-10-17 2017-05-31 株式会社東芝 Nonvolatile semiconductor memory device
US9698156B2 (en) * 2015-03-03 2017-07-04 Macronix International Co., Ltd. Vertical thin-channel memory
TW201629955A (en) * 2014-10-26 2016-08-16 Neo半導體股份有限公司 Method and apparatus for providing three-dimensional integrated memory device for volatile memory and dynamic random access memory
US9281305B1 (en) * 2014-12-05 2016-03-08 National Applied Research Laboratories Transistor device structure
US9570392B2 (en) * 2015-04-30 2017-02-14 Kabushiki Kaisha Toshiba Memory device and method for manufacturing the same
FR3037437B1 (en) * 2015-06-09 2018-06-01 Commissariat Energie Atomique REALIZING SELF-ALIGNED INTERCONNECTION ELEMENTS FOR INTEGRATED 3D CIRCUIT
US9437612B1 (en) 2015-08-21 2016-09-06 Macronix International Co., Ltd. Three-dimensional memory
FR3062236A1 (en) * 2017-01-23 2018-07-27 Stmicroelectronics (Rousset) Sas CONNECTION BAR
JP2018148071A (en) * 2017-03-07 2018-09-20 東芝メモリ株式会社 Storage device
CN107068687B (en) * 2017-03-08 2018-10-12 长江存储科技有限责任公司 A kind of 3D nand memories part and its manufacturing method
CN106910746B (en) 2017-03-08 2018-06-19 长江存储科技有限责任公司 A kind of 3D nand memories part and its manufacturing method, packaging method
CN106920794B (en) * 2017-03-08 2018-11-30 长江存储科技有限责任公司 A kind of 3D nand memory part and its manufacturing method
JP6978645B2 (en) 2017-03-08 2021-12-08 長江存儲科技有限責任公司Yangtze Memory Technologies Co., Ltd. Through array contact structure of 3D memory device
US11329077B2 (en) * 2017-03-31 2022-05-10 Sony Semiconductor Solutions Corporation Semiconductor device with a through electrode reception part wider than a through electrode, solid-state imaging device, and electronic equipment
US10354987B1 (en) 2018-03-22 2019-07-16 Sandisk Technologies Llc Three-dimensional memory device containing bonded chip assembly with through-substrate via structures and method of making the same
US10354980B1 (en) 2018-03-22 2019-07-16 Sandisk Technologies Llc Three-dimensional memory device containing bonded chip assembly with through-substrate via structures and method of making the same
US10381362B1 (en) 2018-05-15 2019-08-13 Sandisk Technologies Llc Three-dimensional memory device including inverted memory stack structures and methods of making the same
US11410928B2 (en) 2018-06-07 2022-08-09 Intel Corporation Device layer interconnects
KR102665246B1 (en) 2018-07-03 2024-05-09 삼성전자주식회사 Semiconductor device and method for fabricating thereof
JP2020047642A (en) * 2018-09-14 2020-03-26 キオクシア株式会社 Semiconductor storage device
US10879260B2 (en) 2019-02-28 2020-12-29 Sandisk Technologies Llc Bonded assembly of a support die and plural memory dies containing laterally shifted vertical interconnections and methods for making the same
KR102746120B1 (en) * 2019-03-11 2024-12-23 삼성전자주식회사 Semiconductor device and method for fabricating the same
KR102679561B1 (en) * 2020-01-07 2024-07-01 에스케이하이닉스 주식회사 Semiconductor memory device and manufacturing method thereof
US11901363B2 (en) 2021-05-14 2024-02-13 Samsung Electronics Co., Ltd. Resistance measuring structures of stacked devices

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01268151A (en) * 1988-04-20 1989-10-25 Sharp Corp Semiconductor device
US5321286A (en) * 1991-11-26 1994-06-14 Nec Corporation Non-volatile semiconductor memory device having thin film memory transistors stacked over associated selecting transistors
JP3178052B2 (en) * 1991-12-13 2001-06-18 ソニー株式会社 Semiconductor device and manufacturing method thereof
DE4314913C1 (en) * 1993-05-05 1994-08-25 Siemens Ag Method for producing a semiconductor component with a contact structuring for vertical contacting with further semiconductor components
JP3445495B2 (en) * 1997-07-23 2003-09-08 株式会社東芝 Semiconductor device
JPH11186528A (en) * 1997-12-25 1999-07-09 Sony Corp Nonvolatile semiconductor memory device and method of manufacturing the same
JP2003133437A (en) * 2001-10-24 2003-05-09 Hitachi Ltd Semiconductor device manufacturing method and semiconductor device
KR20040058990A (en) * 2002-12-27 2004-07-05 주식회사 하이닉스반도체 Method of manufacturing a flash memory device
AU2003300007A1 (en) * 2002-12-31 2004-07-29 Matrix Semiconductor, Inc. Programmable memory array structure incorporating series-connected transistor strings and methods for fabrication and operation of same
US7505321B2 (en) * 2002-12-31 2009-03-17 Sandisk 3D Llc Programmable memory array structure incorporating series-connected transistor strings and methods for fabrication and operation of same
KR20050010260A (en) * 2003-07-18 2005-01-27 주식회사 하이닉스반도체 Method of manufacturing NAND flash memory device
KR100539247B1 (en) * 2004-02-04 2005-12-27 삼성전자주식회사 Split gate type non-volatile semiconductor memory device and method of fabricating the same
US7498641B2 (en) * 2004-05-28 2009-03-03 Taiwan Semiconductor Manufacturing Company, Ltd. Partial replacement silicide gate
KR100604871B1 (en) * 2004-06-17 2006-07-31 삼성전자주식회사 Complementary nonvolatile memory device, operation method thereof, fabrication method thereof, logic device and semiconductor device including same
JP4571454B2 (en) * 2004-07-16 2010-10-27 株式会社アドバンテスト Semiconductor integrated circuit
JP2006073939A (en) * 2004-09-06 2006-03-16 Toshiba Corp Nonvolatile semiconductor memory device and method for manufacturing nonvolatile semiconductor memory device
EP1638142A3 (en) * 2004-09-20 2006-09-13 Samsung Electronics Co.,Ltd. SRAM cell with stacked thin-film transistors
JP4535845B2 (en) * 2004-10-29 2010-09-01 富士通セミコンダクター株式会社 Semiconductor device
KR100684875B1 (en) 2004-11-24 2007-02-20 삼성전자주식회사 Semiconductor device and manufacturing method thereof
JP4654671B2 (en) * 2004-11-29 2011-03-23 ソニー株式会社 Semiconductor memory device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI587484B (en) * 2010-02-05 2017-06-11 半導體能源研究所股份有限公司 Semiconductor device
US9793276B2 (en) 2010-02-05 2017-10-17 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having transistor and capacitor
TWI787080B (en) * 2022-02-10 2022-12-11 旺宏電子股份有限公司 3d flash memory device

Also Published As

Publication number Publication date
CN101162721A (en) 2008-04-16
JP2008098641A (en) 2008-04-24
TWI423430B (en) 2014-01-11
KR100806339B1 (en) 2008-02-27
US7602028B2 (en) 2009-10-13
US20080087932A1 (en) 2008-04-17

Similar Documents

Publication Publication Date Title
TW200822345A (en) NAND flash memory devices having 3-dimensionally arranged memory cells and methods of fabricating the same
TWI693704B (en) Hybrid bonding contact structure of three-dimensional memory device
TWI665785B (en) Through array contact structure of three-dimensional memory device
KR102669053B1 (en) 3D memory device with drain selection gate cut structure and method of forming the same
TWI674666B (en) Structure and method for reducing stress in a three-dimensional memory device
CN105981171B (en) Multilevel contacts to three-dimensional memory arrays and methods of making the same
CN111739792B (en) Bonded memory device and method of making the same
CN111937148A (en) Three-dimensional memory device
WO2020000365A1 (en) Three-dimensional memory device having a shielding layer and method for forming the same
TW202027258A (en) 3 dimension storage device with through stair contact and method of forming same
CN109844949A (en) The source contact structures of three-dimensional storage part and the manufacturing method of the memory device
JP2000307084A5 (en)
JP2022535022A (en) Methods and structures for forming staircases in three-dimensional memory devices
US9953995B2 (en) Independent vertical-gate 3-D NAND memory circuit
CN111801802B (en) Three-dimensional memory device
TW202125776A (en) An integrated chip
TW202207430A (en) Semiconductor device and method of forming the same
TWI296145B (en) Non-volatile memory and fabricating method thereof
US12027463B2 (en) Memory device and fabrication method thereof
TWI756781B (en) Method for forming three-dimension memory device
CN208923148U (en) L-type transistors and semiconductor memories
CN208923087U (en) Semiconductor device
TW202221908A (en) Method for forming three-dimensional memory device
TW202203421A (en) Methods for forming three-dimensional memory devices
CN113366638B (en) Three-dimensional memory device and method for forming the same