200821880 九、發明說明： 【發明所屬之技術領域】 本發明係有關於積體電路設計，尤指—種依據時脈偏移成本 函數來進行邏輯單元分群以產生一時脈樹（dGektree)的方法與 系統。 【先前技術】 如熟習此項技藝者所周知，時脈樹係用來緩衝—時脈訊號，其 中撕脈峨係自-時脈源輸出並傳遞至由時脈驅_邏輯單元 (例如正反器），而對於每一個正反器來說，輸入至各個正反器之時 脈訊號的傳遞延遲量不餘同，而時脈訊號之_相位差便稱之 為時脈偏移（doek skew)，換㈣說，由於時脈樹的設計不良， 口此便往往叾存在日守脈偏移的問題*影響正反器的設定時間 (setuptime)與保持時間（㈣―）。於設計數位邏輯積體電路 生#個問題是：時脈偏移過大而使得電路元件的同步操 作無法於所要㈣脈頻衬執行。因此，對於設計積體電路來說， 降低時脈偏移便極為重要，而明顯地，此時便需要—個創新的解 決方案來適當且有效率地產生出所要的時脈樹。 【發明内容】 口此，本發明的目的之一在於提供一種依據時脈偏移成本函 數來進行邏輯單元分群以產生-時脈樹的方法與系統 ，以解決上 述問題。 200821880 、依，本發明之實_，露—觀生減_時脈源與複數 個邏輯早①之間之—時脈獅方法。該複油賴單元係依據該 ，脈源所產生之—時脈訊號來運行。該方法包含有··依據一第一 時脈偏移成本函數而將該複數個邏輯單元分類為複數個第一階層 群組’·=配置至少一第—階層時脈緩衝器予該複數個邏輯單^ 中-邏輯早疋’以緩衝由該時脈源輪出至該邏輯單元之該時脈訊 依據本發明之實施例，其另揭露—種產生_於—時脈源盘 複數個邏料元之狀—__ _。賴數觸輯單元係依 據該時脈源所產生之一時脈訊號來運行。該系統包含有··一分類 杈組’用來依據-第—時脈偏移成本函細賴魏麵輯單 分類為複數個第1層群組；以及—緩衝器設置模組，用來 至少-第，層時脈緩衝器予該複數個邏輯單元中―邏輯單元， 以緩衝由該時脈_出至該邏輯單元之_脈訊號。早7^ 依據本發狀實_，其另揭露—鋪體電路，其 ^ 數個邏輯單元’每-邏輯單元係依據—時脈源所產生之—時财 號來運行，其中該複數個邏輯單元係分類為複數個第—“ 組，以及該複數個第-階層群組另分類為複數個第二階層^ 以及-時脈樹’祕於該時脈源以及簡_賴單元之、、兮 時脈樹包含有：-時脈樹結構，包含有至少—底树脈_了 200821880 其中該時脈樹結構係具有一特定繞線長度，·至* ★ 緩衝器，配置予每-第-階層群組， 二第—階層時脈 -相對應第-P#層群組之該時脈訊號；至少二辦脈源輸出至 器，配置予每H層群組，二—階層時脈緩衝 對應第二階層群組之該時脈訊號及♦脈源輪出至—相 用來橋接該第二階層時脈緩衝器與該 層時脈緩衝器與該底層時脈緩衝器之間的連二 槐線長度，以聽第二階树脈緩衝轉該第三_日 為之間的連麟長度亦是等㈣蚊繞線長度。 【實施方式】 在說明書及後續的申請專利範圍當中使用了某些詞彙來指稱 特定的耕。賴領域巾具有通f知識者射理解，製造商可妒 抑不關名詞來稱詞—個元件。本_書及賴㈣請補 耗圍亚不以名稱的差異來作為區分元件的方式，而是以元件在功 能上縣異來作輕分的物。在通篇朗書及後續的請求項當 中所提及的「包含」係為—開放式的用語，故應解釋成「包含但 不限定於」。此外’「|隨」—詞在此係包含任何直接及間接的電 乳連接手段，因此，若文中描述―第—裝置祕於—第二裝置， 則代表該第H可直接電氣連接於該第二裝置，或透過其他裝 置或連接手段來間接地電氣連接至該第二裝置。 睛參閱第1圖’第1圖係為本發明時脈樹產生系統10之一實 7 200821880 施例的示意圖。如第i圖所示，時脈樹產生系統】0包含有一氕敕 模組12、一分類模組14以及一緩衝器設置模組】6。於本發明： 實施例中，時脈樹產生系統10係透過一電腦系統來加以實作，其 中調整模組12、分類模組μ以及緩衝器設置模組〗6均為可由二 微處理器（未顯示）所執行以實現所制訂之功能的可執行程式碼· 然而，，時脈樹產生系統10亦可僅由硬體元件來加以實作，其中 調整模組I2、分麵組Μ以及緩衝器設置模組1ά均為硬體電路 以實現所制訂的功能，而這些變化均屬本發明之範疇。 於本發明中，分類模組14係用來依據一時脈偏移成本函數 (clock skew cost function)而將複數個邏輯單元分類成複數個群 組；緩衝器設置模組16係用來配置至少一時脈緩衝器予每一群 組，以便緩衝由時脈源所產生並傳遞至相對應群組之一時脈訊 號；以及調整模組12則用來於分類模組14對同一時脈源所驅動 j輯單元進行分類之前，調整邏輯單元的分佈或者加入虛設邏 輯單7L (dummy loglc umt)。調整模組12、分類模組14與緩衝器 a又置模組16的操作係詳述於後。 士月同日才多閱第1圖與第2圖，第2圖係為本發明方法產生一 時脈樹以連結-時脈源與多個邏輯單元之—實施例的流程圖。時 脈祕產生方法係、由第i圖所示之時脈樹產生系統川來加以執行， 並包含以下步驟： 200821880 步驟100 ·開始； 步驟102 :辨識出由同一時脈源所驅動之複數個邏輯單元； 步驟104 ··針對該複數個邏輯單元而選取出一預定時脈樹結構(tree skeleton)，其中該預定時脈樹結構設定有一特定繞線長 度（net leng1;h ); 步驟106:依據一第一時脈偏移成本函數而將該複數個邏輯單元分 類為複數個苐一階層群組（jf|rst_ievei gr〇Up ); 步驟108 :配置一第一階層時脈緩衝器（first_leveld〇ckbuffer)予 每一第一階層群組； 步驟110·依據-第二時脈偏移成本函數而將對應該複數個邏輯單 凡之該複數個第-階層群組分類為複數個第二階層群 組（second-level group ); 步驟112 :配置—第二階層_緩衝器（_d如d心㈣版） 予每一第二階層群組； 步驟114 :設置—第三階層時脈緩衝器（細如心減祕⑷ 以橋接複數個第二階树脈緩衝器與該預定時脈樹結 構之一底層時脈緩衝器（b〇ttom-leveld()ekbuf^，1 中該第三階層時脈緩衝器與該底層時脈緩衝器之間的 連接線長度係設定為接近該峡繞線長度，以及一第二 階層時脈緩衝器_第三階層時脈緩衝ϋ之間的連接 線長度亦設定為接近該特定繞線長度； 步驟116 :結束。 & ’ 200821880 請注意，假若可大致上獲得相同的結 的執行順序係可以改變的，舉例來說，分類邏輯==频 於選擇___辣之較输。的步驟可以 於步驟100中，上述流程開始運作。於 組Η便會啟動而辨識出由類模 邏輯單元(例如積體電路中的正反哭)二8=虎所驅動的 別針對不t本發明方法係分 =虞-特卿輸爾_時亀射選取出一預 於—Γ例中，該預㈣脈樹結制選取係根據 、刀布，而連接線長度需設定為多接近該特定繞線長 ^則因連接線長度可能會影響到電氣特性參數累加後的成本 望所以若成本值非常接近於特定值，連接線長度則可非常接近 =於特定繞線長度，若成核略高於特紐，則可使連接線長 度適當少於特定繞縣度，當然，若成本值略低於特定值，即可 適當增加連接線長度。請參閱第3圖，其中圖⑻至圖⑹係分別顯 不出複數個不同的預設時脈樹結構，於本發明此一實施例中， Η伽組態係被採用，如第3圖中圖⑻所示，此一時脈樹結構係 包含單-底層日械緩衝器，且具有—繞線長度a，而端點α係被 2來設置底層時脈緩衝器的所在位置。就第3圖中圖⑻的邏輯 單:刀佈巾’此端點Α接近於共用同—時脈源0丨。ek·㈣的邏 j單το刀佈位置的巾心點；而時脈_先將時脈減傳至此底層 寸脈、、爰衝杰，再經由此底層時脈緩衝器與其他的時脈緩衝器傳輸 200821880 到各邏輯單兀。其巾，底層時脈緩衝频定祕為位於「由上而 下的設計流程」中㈣脈緩衝器，且最接近「由下而上的設計流 程」裡取7¾層時脈緩衝器。「由上而下的設計流程」與「由下而上 的設計流程」的定義於第4圖中有所解釋。如第3圖中圖⑼至圖 ⑻所示’每-雜樹結構皆包含兩個底科脈緩衝賴位於較上 層的時脈緩衝器，且具有—繞線長度a，端點A係被定義為底層 時脈緩衝器的所在位置，而端點㈣是被定義為高層時脈緩衝器 所在位置’而若選用第3圖中_的邏輯單元分佈，此端點B係 接近共關—時脈源的邏輯單元分佈位置的中心點；而時脈源則 先將時脈訊號傳至此高树脈緩衝^，再經由底層時脈緩衝器與 其他的時脈緩衝器傳輸到各邏輯單元。如第3圖中圖⑹所示，此 日守脈树、、，。構包含四個底層時脈緩衝器，兩個高層時脈緩衝哭， =一個頂層時脈緩衝器（邮如繞k喊〇，且具有一麟 二=^外’底層時脈緩衝器的位置是端點A，較高階層時脈緩 ‘二則為端點β’而端點⑽蚊義為設置頂層時脈緩衝 即為…詈^接近共用同—時脈源的邏輯單元分佈位置中心點的 的頂層時脈緩衝器。本實施例中，於第3圖中 表嶋咖術賴係代 選取出4 以’依據邏輯單元的分佈便可隨之 例說明之用7結構。請注意，上述之時脈樹結構的選取僅為舉 他實_來作為本發明醜制條件，舉例來說，於其 门夺脈源之邏輯單元的數目、時脈緩衝器的驅動能力 200821880 範 (driving strength)或者是所使用的半導體製程，均屬本發明之200821880 IX. Description of the Invention: [Technical Field] The present invention relates to an integrated circuit design, and more particularly to a method for performing logical unit grouping to generate a clock tree (dGektree) according to a clock offset cost function. system. [Prior Art] As is well known to those skilled in the art, the clock tree is used to buffer the clock signal, wherein the tearing pulse is output from the clock source and passed to the clock drive_ logical unit (for example, positive and negative). For each flip-flop, the amount of delay of the clock signal input to each flip-flop is not the same, and the phase difference of the clock signal is called the clock offset (doek skew) ), (4) said that due to the poor design of the clock tree, the mouth often has the problem of offset of the day-to-day pulse* affecting the setup time and hold time of the flip-flop ((4)-). The problem with designing a digital logic integrated circuit is that the clock offset is too large and the synchronous operation of the circuit components cannot be performed on the desired (four) pulse lining. Therefore, it is extremely important to design the integrated circuit to reduce the clock offset, and obviously, an innovative solution is needed to generate the desired clock tree appropriately and efficiently. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a method and system for logical unit grouping to generate a clock tree based on a clock offset cost function to solve the above problem. 200821880, according to the invention _, dew - Guansheng reduction _ clock source and complex logic between 1 - the time lion method. The refueling unit operates according to the clock signal generated by the pulse source. The method includes: classifying the plurality of logical units into a plurality of first hierarchical groups according to a first clock offset cost function, and configuring at least one first-level clock buffer to the plurality of logics Single-medium-logic early 疋' to buffer the time pulse from the clock source to the logic unit according to an embodiment of the present invention, which further discloses generating a plurality of ____clock source disk The shape of the yuan - __ _. The Lay Touch unit operates according to one of the clock signals generated by the clock source. The system includes a classification group 用来 used to classify a plurality of first layer groups according to a -first clock offset cost function; and a buffer setting module for at least - a layer buffer to the "logic" of the plurality of logic cells to buffer the pulse signal from the clock to the logic unit. Early 7^ according to the hairline _, which additionally discloses a paving circuit, wherein the number of logical units 'per-logic unit is operated according to the time-of-day source generated by the clock source, wherein the plurality of logics The unit is classified into a plurality of "-groups, and the plurality of first-level groups are further classified into a plurality of second levels ^ and - the clock tree is secretive to the clock source and the simple unit, 兮The clock tree contains: - a clock tree structure, containing at least - a bottom tree vein _ 200821880 where the clock tree structure has a specific winding length, · to * ★ buffer, configured to each - level Group, the second-level clock-corresponding to the clock signal of the first-P# layer group; at least two pulse source output to the device, configured for each H-layer group, and the second-level clock buffer corresponding to the first The clock signal of the two-level group and the pulse source-to-phase are used to bridge the second-level clock buffer and the second line between the layer clock buffer and the bottom clock buffer Length, to listen to the second-order tree buffer to the third _ day is the length of the lining is also equal (four) mosquito winding length [Embodiment] Some vocabulary is used in the specification and subsequent patent application to refer to a specific plough. The ray field towel has a knowledge of the knowledge, and the manufacturer can suppress the noun to the word - a component This _Book and Lai (4) Please make up for the difference between the name and the name of the sub-Asian as the way to distinguish the components, but the components that are lightly divided according to the function of the county. In the entire book and subsequent claims The "containment" mentioned in the article is an open-ended term and should be interpreted as "including but not limited to". In addition, the word ""|" includes any direct and indirect connection of the electric milk. Therefore, if the second device is described as "the first device", it means that the H can be directly electrically connected to the first The second device is indirectly electrically connected to the second device through other devices or connection means. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view showing an embodiment of a clock tree generating system 10 of the present invention. As shown in the figure i, the clock tree generation system 0 includes a module 12, a classification module 14, and a buffer setting module. In the embodiment of the present invention, the clock tree generating system 10 is implemented by a computer system, wherein the adjusting module 12, the sorting module μ, and the buffer setting module 6 are all configurable by two microprocessors ( Executable code executed to implement the functions developed. However, the clock tree generation system 10 can also be implemented only by hardware components, wherein the adjustment module I2, the faceted group, and the buffer are implemented. The device setting modules 1 are all hardware circuits to implement the functions defined, and these variations are within the scope of the present invention. In the present invention, the classification module 14 is configured to classify a plurality of logical units into a plurality of groups according to a clock skew cost function; the buffer setting module 16 is configured to configure at least one time. The buffer is buffered to each group to buffer the clock signal generated by the clock source and transmitted to one of the corresponding groups; and the adjustment module 12 is used to drive the same clock source to the classification module 14 Before the unit is classified, adjust the distribution of the logical unit or add the dummy loglc umt. The operation of the adjustment module 12, the classification module 14 and the buffer a and the module 16 is detailed later. The first and second figures are read on the same day, and the second figure is a flow chart of an embodiment in which the method of the present invention generates a clock tree to link a clock source with a plurality of logic units. The clock generation method is performed by the clock tree generation system shown in the figure i, and includes the following steps: 200821880 Step 100 · Start; Step 102: Identify a plurality of clocks driven by the same clock source a logical unit; step 104: selecting a predetermined tree skeleton for the plurality of logical units, wherein the predetermined clock tree structure is set to have a specific winding length (net leng1; h); The plurality of logical units are classified into a plurality of hierarchical groups (jf|rst_ievei gr〇Up) according to a first clock offset cost function; Step 108: configuring a first-level clock buffer (first_leveld〇) Ckbuffer) to each of the first hierarchical groups; Step 110: classifying the plurality of first-level hierarchical groups corresponding to the plurality of logical units into a plurality of second hierarchical groups according to the second clock offset cost function Group (second-level group); Step 112: Configuration - second level_buffer (_d such as d heart (four) version) to each second level group; Step 114: set - third level clock buffer (fine If the heart is reduced (4) to bridge a plurality of second-order tree buffers and an underlying clock buffer of the predetermined clock tree structure (b〇ttom-leveld() ekbuf^, 1 of the third-level clock buffer and the underlying clock buffer The length of the connecting line between the devices is set to be close to the length of the isvel winding, and the length of the connecting line between the second-level clock buffer_third-level clock buffer 亦 is also set to be close to the specific winding length; Step 116: End. & '200821880 Please note that if the order of execution of the same knot can be roughly changed, for example, the classification logic == frequency can be selected in the ___ spicy comparison. In the step 100, the above process starts to operate. After the group is started, it is recognized that the method is driven by the analog logic unit (for example, the positive and negative crying in the integrated circuit).分=虞-特卿输尔_时亀射出出一预— In the example, the pre-(four) vein tree is selected according to the knife and the cloth length, and the length of the connecting line needs to be set to be close to the specific winding length. ^The length of the connection line may affect the accumulation of electrical characteristics The cost is so if the cost value is very close to a specific value, the length of the connecting line can be very close to = the length of the specific winding. If the nucleation is slightly higher than the special nucleus, the length of the connecting line can be appropriately less than the specific winding degree. Of course, if the cost value is slightly lower than a specific value, the length of the connecting line can be appropriately increased. Please refer to FIG. 3, wherein FIG. 8(8) to FIG. 6(6) respectively show a plurality of different preset clock tree structures, which are in the present invention. In this embodiment, the Sangha configuration is employed. As shown in Figure 8 (8), the clock tree structure includes a single-bottom mechanical buffer with a winding length a and an endpoint. The alpha system is set by 2 to set the position of the underlying clock buffer. For the logic of Figure (8) in Figure 3: the knife cloth 'this end point Α is close to the shared same - clock source 0 丨. Ek·(4) Logic j single το knife position of the towel point; and the clock _ first pass the clock to the bottom of the pulse, 爰 杰 ,, then through the underlying clock buffer and other clock buffer Transfer 200821880 to each logical unit. Its towel, the underlying clock buffer frequency secret is located in the "four-up design flow" (four) pulse buffer, and the closest to the "bottom-up design process" takes the 7⁄4 layer clock buffer. The definitions of "top-down design flow" and "bottom-up design flow" are explained in Figure 4. As shown in Fig. 3 (9) to (8), the 'every-hetero tree structure contains two base buffers located in the upper layer of the clock buffer, and has a winding length a, and the end point A is defined. The location of the underlying clock buffer, and the endpoint (four) is defined as the location of the high-level clock buffer'. If the logical unit distribution of _ in Figure 3 is selected, the endpoint B is close to the common-time-cycle. The source logical unit distributes the center point of the location; and the clock source first transmits the clock signal to the high tree buffer, and then transmits it to each logical unit via the underlying clock buffer and other clock buffers. As shown in Figure (6) in Figure 3, this day is a tree, and. The structure consists of four underlying clock buffers, two high-level clock buffers crying, = a top-level clock buffer (the mail is shouting around, and has a lining = ^ outer 'the bottom clock buffer position is End point A, the higher level clock slows 'two is the end point β' and the end point (10) mosquito sense is set to the top layer clock buffer is ... 詈 ^ close to the shared same - clock source logical unit distribution position center point The top-level clock buffer. In this embodiment, in the third figure, the table is selected to be 4, according to the distribution of the logical unit, the 7-structure can be used as an example. Please note that the above The selection of the clock tree structure is only for the sake of the ugly condition of the present invention. For example, the number of logic cells in the gate source, the driving capacity of the clock buffer 200821880 driving strength or Is the semiconductor process used, which belongs to the present invention.
轉。 X 於本實施例中，時脈樹結構_取係提供了—種由上而下的 設計流程以便建立最終所要的時脈樹。舉例來說，麵取第頂 中圖⑼所示的預設時脈樹結構，則底層時脈緩衝器與高層時麟 衝器的所在位置便蚊出來了，此即為第4圖的由上而下的設叶 流程。而要被設置於下方㈣脈緩衝器，其位置便需經由本發明 所揭露之由下社的設計流縣純蚊。由下 的運作詳述於下。 之叹计机耘 舉例來說，若步驟104選取镇3岡+ _、— —時脈緩衝器搬便會設置於_ A圖以中便示之時脈樹結構， - “ ^ U Α以便接收由，脈源（例如 、產生為）所產生之一時脈訊號CLK (如 =下而上的設計流程㈣，分類模組14係依據== =)數:t將複數:邏輯單元分類為複數個第-階層群組(步 個邏輯一心料"^脈偏移成本函數侧來累計複數 個璉輯早7G的電氣特性參數（ T是數 本值（⑽㈤ue)，而當該第_i 負載值）以計算出一成 、r& 時脈偏移成本函數累古畲+你)4大+ =單元之_性參數所產 ,=疋 數個特定邏輯單元便被分類為—第 / ‘值化，该複 者所知，偏移的大小係正二：:如熟習此項技藝 偏移的可允許範_知時，便可心’因此’當時脈 更了適§地決疋出上述的特定值， 12 200821880 舉例=說，該特定值於—實施例中係被設定為珊㈣電容值，所 以’當累計1G個邏輯單元之電容值的結果等於該特定值（亦即 300ίΤ)時’騎1G個邏輯單元便歸類聚集為—群組。請注意，於 執仃上述之分_作時，繞線本身的電容值 、 的累計計算中。 正股电谷值 請同時參閱第2圖與第4m ^ . 依據第2円所目’弟4圖係為具有-時脈樹(其係 而建立)之-積體電路的示意圖。如圖所 不，邏軏早7L 2114、...、211_Μ 汀 邏輯單元212心、212…係刀類為—弟―階層群組216七 輯單元2叫、’、.213 ^分類為一第—階層群組216-2 ;邏 輯單元叫·！、.、214 j係:貞為—第—階層群組21W ;以及邏 -第-階層群組中所有邏輯;類為一第一階層群組216_4’其中每 述之特紐⑻卩贿值;-和均等於前 階層時脈緩衝器208_1、规, 受有刀糊己置弟一 2W、216t G8.3、2G8-4 衫-階層群組 b_4 (步驟 108)。 當決定出第-階層時脈緩衝器 之後，分麵組14另依據1 ± 208-3 2〇8'4 群組3 )禮偏移成本函數來將第—階層 2职、謂（步驟11〇) 1M分類為複數個第二階層群組 第二時脈偏移成本函數係累^料―時脈偏移成本函數的運作， 件的電氣特性參數（例如電^第一階層鮮組中複數個邏輯元 U性負載值）來產生-成本值，若該 13 200821880 第另特疋值，則相對應的第一階層群組便被分類為一 屬於一二如第4圖所示’第—階層群組2164與216-2係隸 隸胁 ^=^^料^_216_3與216-4 則 別配晋笛 8_2。接著，緩衝器設置模組16便分 21…階層時脈緩衝器孤1备2予第二階層群組218]、 21心2 (步驟U2)。 士:决疋出第二階層時脈緩衝器2〇6_卜2〇6_2之後，所選取之 ^的相對應特定繞線長度便會被參照，以便橋接底層時 峨衝益202以及第二階層時脈緩衝器2〇6一卜·(步驟工⑷。 f實關巾’緩魅設置模組16會決定—緩魅位置，以使得一 弟/白層¥脈緩衝器2()4與底層時脈緩衝器搬之間的連接線長 度=於雜（繞線長度以及每—第二階層時脈緩衝器施小挪_2 2第三P_械緩衝器綱之間的連接線長度等於該特定繞線長 二，接者，便將第三階層時脈緩衝器綱設置於所決定出的緩衝 ^位置來完成最終所要的時脈樹，換句話說，於本㈣之實施例 中’其係應用-種搜尋最短且長度相同之路徑的方法 ===me_distanee_path _d) 第三階層時脈緩 衝益204的ά又置位置〇 階層群組的個 並非為本發明 •檢查經由累 清注思，於第4圖中，邏輯元件的個數、第〜 數以及第二階層群組的個數僅作為範例說明之用， 的限制條件。此外，步驟1〇6/步驟11〇可以修改為 14 200821880 積複數個特定邏輯單元之電氣特性參數生之—成本值是否落 入特定範圍，以及當計算出來的成本值落入該特定範圍，將哕 複數個特定邏輯單元分類為第一階層群組/第二階層群組。所以， 萬實際上的繞線長度過長而無法符合時脈偏移的限制條件時， 該特定範圍便可提供一偏差容許量（tolerance)。 才 再者，請注意，於所建立之時脈樹中設置的所有時脈緩衝器 均對應同-緩衝器類型，舉例來說，第4圖所示之每一時脈緩衝 态 202、204、206-；1、206-2、208-1、208_2、208-3、208·4 均具有 相同的驅動能力。此外，於本實施财，只要能使得輸入至相對 應祕單元之雜訊號仍轉原本所要的極性，麟脈緩衝器係 可以利㈣反向（__inverting)緩_或反向（丨_^)緩衝 為（一般稱之為反向器），抑或兩者的組合來加以實作。 對於上述的分_作而言，本發明之實補另提供與時脈樹 細有關的-些技術特徵。於分類模組14觸輯單元進行分類之 前，調整模組12係可預先調整邏輯單元的分佈或者是依據邏輯單 兀的7刀佈而將至少—虛設邏輯單元加人原本的邏輯單元中。舉 來祝’當邏輯早凡的分佈不均勻時，調整模組⑴更將位於一密集 分佈區域中的-些邏輯單元移到一稀疏分佈區域中；另外，者不 容易依據所定義之特定值或特定綱來將所有的邏輯單元分二為 .複數個群組時，调整模組12會加入一些虛設邏輯單元至稀疏分佈 區域中’以使得邏輯單元的群組分類能順利完成。此外，為了降 15 200821880 低時脈緩衝n的驅動能力需求，調顏組12另會將—特定群組進 -步地劃分成複數個子群組，並分別_複數個時脈緩衝器至該 複數個子群組，舉例來說，緩衝器設_組16將第—階層群組 216-1劃分成複數個子群組，並分別配_數個第一階層時脈緩衝 為予雜數個子群組，因此，相較於原本第一階層時脈緩衝器 208-1所要求的驅動能力，這些第一階層時脈緩衝器的驅動能力需 求便可降低；同樣地，緩衝ϋ設置模組16亦可將第二p皆層群組 218-1劃分成複數個子群組，並分別配置複數個第二階層時脈緩衝 器予。亥複數個子群組，因此，相較於原本第二階層時脈緩衝器 206]所要求的驅動能力，這些第二階層_緩衝器的驅動能力需 求便可降低，上述變化均屬本發明之範疇。 本發明亦可應用於低功率設計（lGW_p_rdesign)的應用中。 於低功率設計的實施例巾，本發明之時脈樹輯流程可利用習知 的正口型時脈閘電路單元（integrated d〇ck㈣哗喊腦⑶U )來 取代特疋層中所设置之部分或全部的時脈緩衝器，而於此低功 率汉计的實施例中，分賴組14_開辦先依據邏輯料屬性來 將積體電路中複數個目標邏輯單元分別劃分為複數個邏輯單元 群組’舉例來說’該複數個目標邏輯單聽根據不同的功能或其 他已4參數而分類為該複數個邏輯單元群組，其巾當該積體電路 運乍才位於同一邏輯單元群組的目標邏輯單元係允許於同一時 間被關閉。對於由分類模組14所分類產生的每一邏輯單元群組而 。第2圖所示之時脈樹產生方法係會被執行以產生一相對應的 16 200821880 ·!====特絲中—做位置之至少—___由 白=正5型時脈間電路單元所替代以實現所要的低功率設 者·Γ :習知整合型時脈開電料 ί所Γ 為了_起見，相_細節摇述便不另於此費^ 二二有關於以習知整合辦脈問電路單元來取辦脈緩 衝益的㈣步難作為制之用，此外，騎參考第2圖所 :之教導與任何f知的低功率設計技術，實習此徽藝者亦可推 導出其他可行的變化’而這些變化均符合本發明之精神並落入本 發明之範疇。 以上所述本發日狀錄實_，凡财發日种請專利範 圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖係為本發明時脈樹產生系統之一實施例的示意圖。 第2圖係為本發明方法產生—時脈樹以連結—時脈源與多個邏輯 單元之一實施例的流程圖。 第3圖中圖⑻〜圖⑹係分別為預設時脈樹結構之一第一實施例、一 第二實施例、一第三實施例、一第四實施例以及一第五實施 例的示意圖。 第4圖係為具有一時脈樹(其係依據第2圖所示之方法而建立)之一 積體電路的示意圖。 17 200821880 【主要元件符號說明】 10 時脈樹產生系 統 12 調整模組 14 分類模組 16 緩衝器設置模組 202 底層時脈緩衝 器 204 第三階層時脈緩 衝器 206-1、206-2 第二階層時脈 2084、208-2、 第一階層時脈緩 緩衝器 208-3、208-4 衝器 211-1 >211-M> 2124、212·Ν、 2134、213-1、 214-1 > 214J 邏輯單元 216·卜 216-2、 216-3、216-4 第一階層群組 218-1 ^ 218-2 第二階層群組 18turn. X In this embodiment, the clock tree structure provides a top-down design flow to establish the final desired clock tree. For example, if the preset clock tree structure shown in the top (9) of the top is taken, the position of the bottom clock buffer and the high-level time punch is released, which is the top of Figure 4. And the next leaf setting process. However, it is to be placed in the lower (four) pulse buffer, and its position needs to be transmitted through the design of the lower body of the company. The operation below is detailed below. For example, if step 104 selects the town 3 + _, - the clock buffer will be set in the _ A map to show the clock tree structure, - ^ ^ Α to receive By the pulse source (for example, generated as) one of the clock signals CLK (such as = bottom-up design flow (four), the classification module 14 is based on == =) number: t the plural: logical unit is classified into a plurality of The first-level group (step logic) is used to accumulate the electrical characteristic parameters of the complex number 7G (T is the number value ((10)(f) ue)), and when the _i load value ) to calculate the 10%, r & clock offset cost function 累古畲+ you) 4 large + = unit _ sex parameters produced, = 疋 a number of specific logical units are classified as - / / value As far as the multiplex is concerned, the magnitude of the offset is two: if you are familiar with the allowable paradigm of the art offset, you can make the above-mentioned specific value more appropriate. , 12 200821880 Example = say that the specific value is set to the (four) capacitance value in the embodiment, so 'when the capacitance of 1G logic cells is accumulated When the result of the value is equal to the specific value (that is, 300 Τ), '1G logical units are categorized into groups--group. Please note that the capacitance value of the winding itself is accumulated when the above-mentioned points are executed. In the calculation, please refer to Fig. 2 and 4m ^ at the same time. According to the second item, the figure 4 is a schematic diagram of the integrated circuit with the - clock tree (established by the system). As shown in the figure, the logic is as early as 7L 2114, ..., 211_Μ 汀 逻辑 unit 212 heart, 212... is a knife type - brother - class group 216 seven series unit 2, ', .213 ^ classified as a - hierarchical group 216-2; logical unit called ·!, ., 214 j system: 贞 is - the first hierarchical group 21W; and all logic in the logical-first hierarchical group; the class is a first hierarchical group 216_4' each of the special New Zealand (8) bribes; - and are equal to the former class clock buffer 208_1, rules, received a knife, a brother, a 2W, 216t G8.3, 2G8-4 shirt - class group B_4 (step 108). After determining the first-level clock buffer, the facet group 14 further divides the first-level level according to the 1 ± 208-3 2〇8'4 group 3) Said Step 11〇) 1M is classified into a plurality of second hierarchical groups. The second clock offset cost function is the operation of the accumulative-clock offset cost function, and the electrical characteristic parameters of the pieces (for example, the electric first-class fresh group) The logical element U load value) is used to generate the cost value. If the 13 200821880 is the special value, the corresponding first hierarchical group is classified as one and the second is as shown in Figure 4. The hierarchical group 2164 and 216-2 are attached to the threat ^=^^^^216_3 and 216-4 are not equipped with the jingle 8_2. Next, the buffer setting module 16 divides the 21-level clock buffers 2 into the second hierarchical groups 218] and 21 (step U2).士: After the second-level clock buffer 2〇6_卜2〇6_2 is determined, the corresponding specific winding length of the selected ^ will be referred to, so as to bridge the bottom layer when the buffer is 202 and the second level Clock buffer 2〇6一卜·(step work (4). f real close towel 'slow charm setting module 16 will determine the slow position, so that a brother / white layer ¥ pulse buffer 2 () 4 and the bottom layer The length of the connection line between the clock buffers is mixed (the length of the windings and the length of the connection between each of the second-level clock buffers) and the length of the connection line between the third P_mechanical buffers is equal to The specific winding length is two, and then the third-level clock buffer is set to the determined buffer position to complete the final desired clock tree. In other words, in the embodiment of the present invention, The application - the method of searching for the shortest and the same length of the path ===me_distanee_path _d) The third level of the clock buffer benefit 204 is also set to the position of the hierarchical group is not the invention • Check through the clear thinking, In Figure 4, the number of logical elements, the number of the first and the number of the second hierarchical group are only used as an example. In addition, step 1〇6/step 11〇 can be modified to 14 200821880. The electrical characteristic parameters of a plurality of specific logic units are generated—whether the cost value falls within a specific range, and when the calculated cost value Falling into the specific range, the plurality of specific logical units are classified into the first hierarchical group/second hierarchical group. Therefore, when the actual winding length is too long to meet the limitation of the clock offset, This particular range provides a tolerance tolerance. Again, note that all clock buffers set in the established clock tree correspond to the same-buffer type, for example, 4th. Each of the clock buffer states 202, 204, 206-; 1, 206-2, 208-1, 208_2, 208-3, 208·4 shown in the figure has the same driving capability. It can make the noise signal input to the corresponding secret unit still turn to the original polarity, and the pulse buffer can be used to facilitate (4) reverse (__inverting) slow _ or reverse (丨 _ ^) buffering (generally called reverse , or a combination of the two For the above, the actual addition of the present invention provides some technical features related to the clock tree. Before the classification module 14 is classified, the adjustment module 12 can be Pre-adjust the distribution of the logic unit or add at least the dummy logic unit to the original logic unit according to the 7-knife of the logic unit. It is suggested that when the logic is unevenly distributed, the adjustment module (1) is more Move some logical units located in a densely distributed area into a sparsely distributed area; in addition, it is not easy to divide all logical units into two groups according to a specific value or a specific level defined. The adjustment module 12 will add some dummy logic units to the sparse distribution area to enable the group classification of the logic units to be successfully completed. In addition, in order to reduce the driving capability requirement of the low clock buffer n of 200821880, the face group 12 further divides the specific group into a plurality of subgroups, and respectively _ a plurality of clock buffers to the plural For example, the buffer set_group 16 divides the first-level group 216-1 into a plurality of sub-groups, and respectively allocates a number of first-level clock buffers to a plurality of sub-groups. Therefore, the driving capability requirements of the first-level clock buffers can be reduced compared to the driving capability required by the original first-level clock buffer 208-1; likewise, the buffer setting module 16 can also The second p-layer group 218-1 is divided into a plurality of sub-groups, and a plurality of second-level clock buffers are respectively allocated. The plurality of subgroups are separated, so that the driving capability requirements of the second level buffers can be reduced compared to the driving capability required by the original second level clock buffer 206], and the above variations are within the scope of the present invention. . The invention can also be applied to applications of low power design (lGW_p_rdesign). In the embodiment of the low power design, the clock routing process of the present invention can replace the part set in the special layer by using a conventional positive port type pulse gate circuit unit (integrated d〇ck (4) shouting brain (3) U). Or all of the clock buffers, and in the embodiment of the low-power Han meter, the group 14_ starts to divide the plurality of target logical units in the integrated circuit into a plurality of logical unit groups according to the logic attribute The group 'for example, the plurality of target logical single listeners are classified into the plurality of logical unit groups according to different functions or other four parameters, and the towel is located in the same logical unit group when the integrated circuit is operated. The target logical unit is allowed to be closed at the same time. For each logical unit group generated by the classification module 14. The clock tree generation method shown in Fig. 2 will be executed to generate a corresponding 16 200821880 ·!====specials - at least the position -___ by white = positive type 5 inter-pulse circuit The unit is replaced to achieve the desired low power set. Γ: The well-known integrated clock power-on material Γ Γ For the sake of _, the details of the _ _ _ _ _ _ _ _ _ _ _ It is difficult to use the integration of the pulse circuit unit to take care of the pulse buffer. In addition, riding the reference to Figure 2: the teachings and any low-power design techniques, the internship can also be derived. Other possible variations have been made and these variations are in accordance with the spirit of the invention and fall within the scope of the invention. The above-mentioned daily report of the present invention, the equivalent changes and modifications made by the patent scope, should be within the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view showing an embodiment of a clock tree generating system of the present invention. Figure 2 is a flow diagram of an embodiment of the method of the present invention for generating a clock-to-clock source and a plurality of logic units. FIG. 3 is a schematic diagram showing a first embodiment, a second embodiment, a third embodiment, a fourth embodiment, and a fifth embodiment of a preset clock tree structure, respectively. . Figure 4 is a schematic diagram of an integrated circuit having a clock tree (which is established in accordance with the method illustrated in Figure 2). 17 200821880 [Description of main component symbols] 10 Clock tree generation system 12 Adjustment module 14 Classification module 16 Buffer setting module 202 Underlying clock buffer 204 Third-level clock buffers 206-1, 206-2 Two-level clocks 2084, 208-2, first-level clock buffers 208-3, 208-4 buffers 211-1 >211-M> 2124, 212·Ν, 2134, 213-1, 214- 1 > 214J Logic Unit 216·Bu 216-2, 216-3, 216-4 First Level Group 218-1 ^ 218-2 Second Level Group 18