200820436 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種半導體元件，特別係有關於一 種金氧半導體（metal-〇xide_semiconductor，MOS)元件，又 特別係有關於一種高壓MOS元件的結構及其製造方法。 【先前技術】 高 壓金氧 半導體 （high-voltage metal-oxide-semiconductor，HVM0S)元件係廣泛地應用 於例如中央處理器電源供應器（CPU power supply)、電源 管理系統（power management)、交流/直流轉換器（AC/DC converter)等許多電子元件中。HVMOS元件典型地包括 汲極區和包圍汲極區的橫向擴散汲極區。橫向擴散汲極 區典型為井區，其具有較汲極區低的摻雜濃度，因此具 有南崩潰電場。 第1圖係顯示習知的高壓η型金氧半導體(HVNMOS) 元件2，其包括閘極氧化層10、位於閘極氧化層10上的 閘極12、位於η型井（n-well)區4中的沒極區6以及位於 p型井（p-well)區7中的源極區8。淺溝槽隔離（shallow trench isolation，STI)區14係隔開没極區6和閘極12，所 以可外加高的没極對閘極電壓（drain-to-gate voltage)。 可以知道的是，高電場典型地產生於介面區域 (interface region)。對於HVNMOS元件2來說，當没極6 和源極8之間施加一電壓時，在接近p型-η型接面（ρ-η 0503-A32732TWF/ianchen 5 200820436 jrnict1〇n)16會產生一高電場，其會變成ΗνΝΜ〇§元件2 的弱點。高電場的產生會導致HVNM0S元件2崩潰電嬋 的下降。當元件尺寸變小時，電場會變得更高，會：： 上述問題。 “ 因此有需要一種新的方法，其可降低p型^型接面 的電場，以改善HVM0S元件的崩潰電壓。 【發明内容】 為達成發明的上述目的，本發明提供一種半導體結 構，包括一基板；一第一井區，位於上述基板上，上^ 第一井區具有一第一導電類型；一第二井區，位於上述 基板上，上述第二井區具有相反於上述第一導電類型的 二第二導電類型，·一緩衝區，介於上述第一井區和上述 第二井區之間，且鄰接於上述第一井區和上述第二井 區；一隔離區，位於一部分上述第一井區中，從上述第 一井區的一頂面延伸至上述第一井區中；一閘極介電 質，從上述第一井區的上方延伸至上述第二井區的上 方，其中一部分上述閘極介電質位於上述隔離區的上 方；一閘極，位於上述閘極介電質上。 為達成發明的另一目的，本發明提供一種半導體結 ，，包括一基板；一第一井區，位於上述基板上，上述 第一井區具有一第一導電類型；一第二井區，位於上述 基板上，上述第二井區具有相反於上述第一導電類型的 一第二導電類型，其中上述第一井區和上述第二井區具 〇503-A32732TWF/ianchen 6 200820436 . 有重$區，一絕緣區，從上述笛 dt Μ 至上述第一并F由 、弟一井£的一頂面延伸 上方狃心一閘極介電質，從上述第-井區的 上方延伸至上述第- 的-邊緣<…：其中上述間極介電質 間極介電質上。 方，間極，位於上述 ，達成發明的又一目的，本發明提供一種半導體結 第二：ί一基f第一井區，位於上述基板上，上述 井品具有一第—導電類型的一第一不純物；一第二 、，品位於上述基板上，上述第二井區具有一第二 類型的一第二不純物，卜、十、楚— 、电 物上述弟二導電類型相反於上述第 W類型’其中上述第一井區和上述第二井區且有一 ，隔區’其介於兩者之間；—絕緣區，位於—部分上述 第井區中，從上述第一井區的一頂面延伸至上述第一 井區中；-閘極介電質，從上述第—井區的上方延伸至 上述第二井區的上方，其中上述閘極介電質的一邊緣位 於上述、、緣區的正上方，—閘極，位於上述閉極介電質 上。 、 為達成發明的又一目的，本發明提供一種半導體結 ，的形成方法，包括提供—基板；於上述基板上形成一 第一井區，上述第一井區具有一第一導電類型；於上述 ，板上形成一第二井區，上述第二井區具有相反於上述 第一導電類型的一第二導電類型，其中形成一緩衝區， 上述緩衝區鄰接上述第一井區和上述第二井區；於一部 分上述第一井區中形成一隔離區，且上述隔離區從上述 〇503-A32732TWF/ianchen 7 200820436 入♦:頂面延伸至上述第-井區中；形成-閘極 ”电二’上述閘極介電質從上述第一井區的上方延伸至 上述第二井區的上方，其卜部分上述閘極介電質位於 上述隔離區的上方·’於上述閘極介電質上形成一閘極。 椹沾為f成發明的又一目的，本發明提供-種半導體結 :1: 、:ί括提供一基板；於上述基板上形成- :11’上述弟一井區具有-第-導電類型；於上述 :板^成-第二井區，上述第二井區具有相反於上述 弟一導電類型的一第一逡 7乐一¥电颂型，其中上述第一井區和 \一井£之間具有—重疊區；於-部分上述第一井 品形成-隔離區，且上述隔離區從上述第一井區的一 二面延伸至上述第一井區中；形成一閉極 =電質從上述第-井區的上方延伸至上述第二井； 於f中—部分上述閘極介電質位於上述隔離區的 上方，於上述閘極介電質上形成_閘極。 ，於13型井區和η型井區之間的緩衝區係提升p型 ^和η型輕介㈣域的崩潰電場。因此分別提 壓7G件的崩潰電壓。 升同 【實施方式】 每^下彻第2至7圖’以更詳細地說明本發明 貝轭例。接著會討論本發明不同 土 明各實施例中，相同的符號表示相^元貝;^列。在本發 請參考第2圖’提供—基板加，其較佳包括-例如 〇503-A32732TWF/iancb 8 200820436 矽、鍺化矽（SiGe)或例如III-V族元素的半導體材料。基 底 20可為一塊狀材料或具有絶緣層上覆石夕 (silicon_on-insulator5 SOI)的結構。較佳以ρ型不純物輕 摻雜（lightly doped)基板20，然而基板20也可摻雜η型 不純物。 第2圖也顯不η型井區24的形成。首先塗佈且圖案 化光阻22。在較佳實施例中，η型井區24為植入η型不 純物形成。舉例來說，可植入鱗（phosphorous)及/或钟 f (arsenic)。η型井區24較佳為高壓η型井區，其具有較 低的不純物濃度。在另一實施例中，η型井區24為低壓 η 型井（low-voltage n_well，LVNW)區，其係與低壓 PMOS 元件（圖未顯示）的η型井區同時形成。在一實施例中，η 型井區24的不純物濃度介於1014i〇ns/Cm3至1017 ions/cm3之間。形成η型井區24之後，移除光阻22。 請參考第3 Α圖’塗佈光阻26，且植入例如 (boron) 及/或銦（indium)的ρ型不純物以形成ρ型井區28和30。 ί :: ρ型井區2 8和3 0為局壓ρ型井區，其具有較低的不純物 濃度。在另一實施例中，ρ型井區28和30為低壓ρ型井 (low-voltage p-well，LVPW)區，其係與低壓 NMOS 元件 (圖未顯示）的ρ型井區同時形成。在一實施例中，ρ型井 區28和30的不純物濃度介於1〇14 i〇ns/cm3至1〇17 ions/cm3之間。形成ρ型井區28和30之後，移除光阻 26 〇 上述討論中，ρ型井區28和30和η型井區24係利 0503-A32732TWF/ianchen 9 200820436 用離子植入基板20形成。在另一實施例中，係以磊晶成 長形成井區。如第3B圖所示，在一實施例中，於基板 20的頂部區域中形成N+埋層（n+ buried layer，NBL)23。 N+埋層23較佳於基板20的頂面中植入不純物或即時摻 雜（in-situ doping)不純物形成。舉例來說，可植入或即時 摻雜磷（phosphorous)及/或钟（arsenic)，其不純物濃度介於 1016ions/cm3 至 1018ions/cm3 之間。 f 於N+埋層23上磊晶成長磊晶層25。磊晶層25較佳 包括例如矽的半導體，且更佳為與基板20相同的材料， 且較佳推雜p型或η型其中之一的不純物。假設換雜 型不純物，其不純物濃度和ρ型井區28和30預期的Ρ 純物濃度相同。然後，形成且圖案化一光阻層（圖未_ 示），暴露出區域24。接著進行η型不純物植入步騍。〜 入的η型不純物係中和磊晶層25中的ρ型不純物玉 區域24為η型井區24。而未摻雜的磊晶層區域形成， 井區28和30。在另一實施例中，可於成長磊晶厣罜 Α 曰〇時 摻雜η型不純物，且植入ρ型不纯物。 具 C 之 在第3Α及3Β圖中，ρ型井區28和η型井區24 有一重疊區32,之後稱為緩衝區32。緩衝區32的寬声 較佳介於10Α至3μπι之間，更佳介於〇·3μπι至〇.5ρ= 間。 弟4圖係頒示絕緣區（insuiaHng regi〇n)44的形成 在較佳實施例中，係以形成淺溝槽，填入例如高密度二 漿氧化物（HDP oxide)的介電材料於溝槽中，且進 ^ $ 1 丁化學 0503-A32732TWF/ianchen 10 200820436 機械研磨以移除過量介電材料的方式形成絕緣區44。最 後形成的淺溝槽隔離（shallow trench isolation，STI)區為 絕緣區44。在其他實施例中，於前述形成的結構上方形 成例如氮化矽的遮罩層。然後圖案化遮罩層以形成開 口。接著進行氧化步驟，以於開口中形成絕緣區（也可稱 為場氧化物）44。 請參考第5圖，塗佈且圖案化光阻48。進行p型不 純物植入步驟以形成P+區52。P+區52較佳包括硼及/或 其他p型不純物’且以約大於1 〇2G i〇ns/cm3的不純物濃 度重摻雜（heavily doped)形成。p+區52可做為p型井區 28的拾取區（pick-up regi〇n)。不純物植入後，移除光阻 48 °200820436 IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor device, and more particularly to a metal-oxide-semiconductor (MOS) device, and more particularly to a high-voltage MOS device. Structure and its manufacturing method. [Prior Art] High-voltage metal-oxide-semiconductor (HVM0S) components are widely used, for example, in CPU power supply, power management, AC/DC. Many electronic components such as converters (AC/DC converters). The HVMOS device typically includes a drain region and a laterally diffused drain region surrounding the drain region. The laterally diffused drain region is typically a well region that has a lower doping concentration than the drain region and therefore has a south collapse electric field. Figure 1 shows a conventional high voltage n-type metal oxide semiconductor (HVNMOS) device 2 comprising a gate oxide layer 10, a gate 12 on the gate oxide layer 10, and an n-well region. The non-polar region 6 in 4 and the source region 8 in the p-well region 7 are. The shallow trench isolation (STI) region 14 separates the non-polar region 6 and the gate 12, so that a high drain-to-gate voltage can be applied. It will be appreciated that high electric fields are typically generated in the interface region. For the HVNMOS device 2, when a voltage is applied between the pole 6 and the source 8, a near p-type-n junction (ρ-η 0503-A32732TWF/ianchen 5 200820436 jrnict1〇n) 16 is generated. A high electric field will become a weakness of ΗνΝΜ〇§ component 2. The generation of a high electric field causes a drop in the crash of the HVNMOS component 2. When the component size becomes smaller, the electric field becomes higher and will:: The above problem. "Therefore there is a need for a new method which can reduce the electric field of the p-type junction to improve the breakdown voltage of the HVM0S device. SUMMARY OF THE INVENTION To achieve the above object of the invention, the present invention provides a semiconductor structure including a substrate a first well region on the substrate, the first well region has a first conductivity type; a second well region is located on the substrate, and the second well region has a conductivity opposite to the first conductivity type a second conductivity type, a buffer region between the first well region and the second well region, adjacent to the first well region and the second well region; and an isolation region located in a portion of the foregoing a well region extending from a top surface of the first well region to the first well region; a gate dielectric extending from above the first well region to above the second well region, wherein a part of the gate dielectric is located above the isolation region; a gate is located on the gate dielectric. To achieve another object of the invention, the invention provides a semiconductor junction, comprising a substrate; a well region located on the substrate, the first well region having a first conductivity type; a second well region on the substrate, the second well region having a second conductivity type opposite to the first conductivity type Wherein the first well zone and the second well zone are 〇503-A32732TWF/ianchen 6 200820436. There is a weight zone, an insulation zone, from the above flute dt Μ to the first and the F and the brother of a well a top surface extending above the first gate of a gate dielectric extending from the upper portion of the first well region to the first-edge----: wherein the inter-electrode dielectric is on the dielectric level. According to another aspect of the invention, the present invention provides a semiconductor junction second: a first well region of the first substrate, located on the substrate, the well product having a first impurity of a first conductivity type a second, the product is located on the substrate, the second well region has a second type of second impurity, the Bu, the ten, the Chu-, the electrical material, the second conductivity type is opposite to the above-mentioned W-type The first well zone and the second And the partition is 'between the two; the insulating zone is located in the above-mentioned first well zone, extending from a top surface of the first well zone to the first well zone; - the gate a dielectric extending from above the first well region to above the second well region, wherein an edge of the gate dielectric is located directly above the edge region, and the gate is located at the closed gate In order to achieve another object of the invention, the present invention provides a method for forming a semiconductor junction, comprising: providing a substrate; forming a first well region on the substrate, the first well region having a first a conductivity type; in the above, a second well region is formed on the board, the second well region has a second conductivity type opposite to the first conductivity type, wherein a buffer region is formed, and the buffer region is adjacent to the first well region And the second well region; forming an isolation region in a portion of the first well region, and the isolation region extends from the 〇503-A32732TWF/ianchen 7 200820436 into the top surface to the first well region; forming - Gate "electric two" The gate dielectric extends from above the first well region to above the second well region, and the gate dielectric is located above the isolation region and is formed on the gate dielectric. A gate. According to still another object of the invention, the present invention provides a semiconductor junction: 1: a substrate is provided, and a substrate is formed on the substrate: -11' wherein the well region has a -first conductivity type; In the above: the board-forming-second well area, the second well area has a first type of the first one, which is opposite to the above-mentioned first conductivity type, wherein the first well area and the first well area Between the first and the first well forming-isolation zone, and the isolation zone extending from one or two sides of the first well zone to the first well zone; forming a closed pole=electricity from The upper portion of the first well region extends to the second well; wherein a portion of the gate dielectric is located above the isolation region, and a gate is formed on the gate dielectric. The buffer zone between the 13-well zone and the η-well zone enhances the collapse electric field of the p-type ^ and η-type light-mediated (four) domains. Therefore, the breakdown voltage of the 7G piece is separately increased. The same applies to the embodiment of the present invention. The embodiment of the present invention will be described in more detail. In the various embodiments of the present invention, the same reference numerals will be used to refer to the elements. In the present invention, reference is made to Fig. 2 to provide a substrate, which preferably includes, for example, 〇503-A32732TWF/iancb 8 200820436 矽, bismuth telluride (SiGe) or a semiconductor material such as a group III-V element. The substrate 20 may be a piece of material or a structure having a silicon-on-insulator 5 SOI. The substrate 20 is preferably lightly doped with a p-type impurity, however, the substrate 20 may also be doped with an n-type impurity. Figure 2 also shows the formation of the n-type well region 24. The photoresist 22 is first coated and patterned. In the preferred embodiment, the n-type well region 24 is formed by implanting an n-type impurity. For example, phosphorous and/or arsenic can be implanted. The n-type well region 24 is preferably a high pressure n-type well region having a relatively low impurity concentration. In another embodiment, the n-type well region 24 is a low-voltage n-well (LVNW) region that is formed simultaneously with the n-type well region of a low voltage PMOS device (not shown). In one embodiment, the n-type well region 24 has an impurity concentration between 1014 i〇ns/cm3 and 1017 ions/cm3. After forming the n-type well region 24, the photoresist 22 is removed. Referring to Figure 3, the photoresist 26 is coated and p-type impurities such as boron and/or indium are implanted to form p-type well regions 28 and 30. ί :: ρ-type wells 2 8 and 30 are local pressure ρ-type wells with low impurity concentrations. In another embodiment, the p-type well regions 28 and 30 are low pressure p-well (LVPW) regions that are formed simultaneously with the p-type well region of the low voltage NMOS device (not shown). In one embodiment, the p-type well regions 28 and 30 have an impurity concentration between 1 〇 14 i ns / cm 3 and 1 〇 17 ions / cm 3 . After the formation of the p-type well regions 28 and 30, the photoresist is removed. 26 〇 In the above discussion, the p-type well regions 28 and 30 and the n-type well region 24 are formed by the ion implantation substrate 20 with the 0503-A32732TWF/ianchen 9 200820436. In another embodiment, the well region is formed by epitaxial growth. As shown in Fig. 3B, in one embodiment, an n+ buried layer (NBL) 23 is formed in the top region of the substrate 20. The N+ buried layer 23 is preferably formed by implanting impurities or in-situ doping impurities in the top surface of the substrate 20. For example, phosphorous and/or arsenic can be implanted or imposited with an impurity concentration between 1016 ions/cm3 and 1018 ions/cm3. f epitaxially growing the epitaxial layer 25 on the N+ buried layer 23. The epitaxial layer 25 preferably includes a semiconductor such as germanium, and more preferably is the same material as the substrate 20, and is preferably a dummy which is one of p-type or n-type. Assuming a heterogeneous impurity, the impurity concentration is the same as the expected plutonium concentration of the p-type wells 28 and 30. A photoresist layer (not shown) is then formed and patterned to expose regions 24. Next, an η-type impurity implantation step is performed. The n-type impurity phase in the n-type impurity phase and the p-type impurity jade region 24 in the epitaxial layer 25 are the n-type well region 24. The undoped epitaxial layer regions are formed, well regions 28 and 30. In another embodiment, the n-type impurity may be doped while the epitaxial 成长 成长 is grown, and the p-type impurity is implanted. In the third and third figures, the p-type well region 28 and the n-type well region 24 have an overlap region 32, hereinafter referred to as a buffer zone 32. The wide sound of the buffer 32 is preferably between 10 Α and 3 μπι, more preferably between 〇·3μπι and 〇.5ρ=. Figure 4 shows the formation of an insulating region (insuia Hng regi〇n) 44. In a preferred embodiment, a shallow trench is formed to fill a dielectric material such as a high density dipoxide oxide (HDP oxide) in the trench. In the tank, and into the ^ 1 1 chemistry 0503-A32732TWF / ianchen 10 200820436 mechanical grinding to form an insulating region 44 in a manner to remove excess dielectric material. The resulting shallow trench isolation (STI) region is the insulating region 44. In other embodiments, the previously formed structure is squared into a mask layer such as tantalum nitride. The mask layer is then patterned to form an opening. An oxidation step is then performed to form an insulating region (also referred to as a field oxide) 44 in the opening. Referring to Figure 5, the photoresist 48 is coated and patterned. A p-type impurity implantation step is performed to form a P+ region 52. P+ region 52 preferably includes boron and/or other p-type impurities' and is heavily doped at a concentration of impurities greater than about 1 〇2 G i〇ns/cm3. The p+ region 52 can be used as a pick-up regi〇n of the p-type well region 28. After impure implantation, remove the photoresist 48 °
請參考第6圖，塗佈且圖案化光阻54，且進行n型 不純物植入步驟以形成N+區56和58。植入的不純物可 包括磷(phosphorous)及/或钟（arsenic)。較佳以約大於丨〇2〇 ions/cm3的不純物濃度重摻雜n型不純物形成n+區56和 58。讲區56和58係分別做為汲極接觸區（_η region)和源極區（source regi〇n)。然後 在另一實施例中，以區56和58可於 之前形成，或於閘極介電質、閘極和閘極間隙壁形成之 後形成。熟於此技術之人士可了解各別的製程步驟。 第7圖係顯示閘極介電f⑼、閘極62和閘極_壁 6 4的形成。熟於此技術之人士可知閘極介電質6 〇較佳包 括氧㈣，然而也可使用例如氮㈣，♦切，氮氧化 0503-A32732TWF/ianchen 11 200820436 石夕或其組合等其他介電材料。閘極62較佳包括換雜 二在：：實施例中，閘極62可使用金屬、金屬氮化物曰： 五屬石夕化物或其他導電材料。可較佳全面性沉積介 和移除不需要的部分以形成閘極間隙壁64。閑極介= 60、閘極62和閘極間隙壁64的詳細製程係為習知-二 此在此不做重覆敍述1極6 2的—邊緣係位於η 24中絕緣區44的正上方。因此形成高壓心 三 (HVNMOS)元件66。 乳千V脰 第8至9圖係顯示本發明的第二實施例。此 係類似於如第7圖所示的實施例，除了緩衝區32=於 Ρ型井區28和η型井區24之間的—間隔區之外。在“ 施例中，、形成如第2圖所示的結構。接著，如第8圖二 不’形成用來形成ρ型井區28和3〇的光阻％。 型t區28和η型井區24係被隔開以形成緩衝區32。可 了解η型井區24和ρ型井區28中的不純物很 ί 散進入緩衝區32中。然而，擴散的不純物濃度會分^ :二型:區：和ρ型井區28不純物濃度。在—實施例 、i和Ρ 31不砘物係擴散進入緩衝區32且於其中形 成- P型-η型接面π型和p型不純物濃度的比例很可能 分別小於η型井區24和？型井區28不純物的五分之一， 甚至小於（U。藉由緩衝區32具有適當的寬度％， 比例可甚至小於G G1。類似於第—實施例 寬度W較佳介請、之間， = 0·5μηι 之間。 主 0503-A32732TWF/ianchen 12 200820436 前述實施例係具有非對稱結構（asymmetric structure)，其中位於井區中的源極區和没極區係具有不 同的導電類型。第10圖係顯示一實施例之具有對稱結構 (symmetric structure)的 HVNMOS，其中 HVNMOS 元件 包括兩個η型井區70、72和介於兩者之間的p型井區74。 類似於第7圖顯示的實施例，形成緩衝區76和78，其中 每一個緩衝區76和78可為相鄰ρ型井區和η型井區的 重疊區或間隔區。在另一實施例中，ρ型井區74僅重疊 f 於（或隔開）η型井區70和72的其中之一，因此當ρ型井 區74與其他相鄰的η型井區形成習知介面時，僅會形成 緩衝區76和78的其中之一。 雖然上述較佳實施例係顯示HVNMOS元件的形 成，熟於此技術之人士可了解形成高壓P型金氧半導體 (HVPMOS)元件各別的形成步驟，其具有與η型井區24、 ρ型井區26和30、Ν+區56和58等相反的導電類型（請 參考第7和9圖）。可以了解高壓MOS元件具有各種不 f ' 同的佈局。然而，仍可應用本發明實施例的形成概念。 類似地，可利用反轉第10圖中摻雜區的導電類型以形成 具有對稱結構的HVPMOS元件。 除了形成HVMOS元件之外，形成缓衝區以影響電 場分佈的概念，可以應用於例如二極體（diode)之其他元 件的形成。藉由介於P型區和η型區之間的ρ型-η型接 面形成缓衝區，可以提升崩潰電壓。 本發明實施例的一項優點為利用缓衝區32隔開η型 0503-A32732TWF/ianchen 13 200820436 井區24和p型井區28。在緩衝區32内部的淨不純物濃 度（net impurity concentration)低。如第7圖所示的一實施 例中，缓衝區32中的p型不純物和η型不純物係互相中 和，因此降低淨不純物濃度。如第9圖所示的一實施例 中，缓衝區32並非由形成井區時的摻雜形成，因此淨不 純物濃度低。所以，於介面形成的缓衝區32的淨不純物 濃度較低，且因此改善HVMOS元件的性能。實驗結果 顯示，本發明實施例的崩潰電壓係提升超過具有類似結 構的習知HVMOS元件（除了沒有缓衝區形成之外）3V至 5V的崩潰電壓。另外，如第11圖所示，本發明實施例 的基板電流（ISUb)係明顯低於習知的HVMOS元件。線80 係顯示本發明實施例的基板電流（Isub)，其最大值約為 2E-6 Α/μπι。線82係顯示習知HVMOS元件的基板電流 (Isub)，其最大值約為6·5Ε_όΛ/μιη〇熟於此技術之人士可 知，HVMOS元件的壽命係與基板電流強烈相關。當基板 電流降低，HVMOS元件的壽命就會增加。 雖然本發明已以較佳實施例揭露如上，然其並非用 以限定本發明，任何熟悉此項技藝者，在不脫離本發明 之精神和範圍内，當可做些許更動與潤飾，因此本發明 之保護範圍當視後附之申請專利範圍所界定者為準。 0503-A32732TWF/ianchen 14 200820436 【圖式簡單說明】 第1圖為習知的HVNMOS元件。 第2、3A、3B及4〜7圖為本發明第一實施例的製程 剖面圖，其中係利用重疊η型井和p型井以形成一缓衝 區。 第8、9圖為本發明第二實施例的製程剖面圖，其中 係利用隔開η型井和ρ型井以形成一緩衝區。 第10圖為對稱結構的實施例。 / 第11圖為習知高壓MOS元件和本發明一實施例的 基板電流的比較圖。 【主要元件符號說明】 2〜習知HVNMOS元件； 4〜η型井區， 6〜〉及極區， 7〜ρ型井區， 8〜源極區， 10〜閘極氧化層； 12〜閘極； 14〜淺溝槽隔離區； 16〜ρ型-η型接面； 20〜基板； 22、26、48、54〜光阻； 23〜Ν+埋詹； 24、70、72〜n型井區， 25〜蟲晶層， 28、30、74〜ρ型井區； 32、76、78〜缓衝區； 44〜絕緣區； 52〜Ρ+區； 56、58〜N+區， 60〜閘極介電質； 62〜閘極； 64〜閘極間隙壁； 66〜HVNMOS元件； 80、82〜線； 92、94〜低壓ρ型井區； 0503-A32732TWF/ianchen 15Referring to Figure 6, the photoresist 54 is coated and patterned, and an n-type impurity implantation step is performed to form N+ regions 56 and 58. Implanted impurities may include phosphorous and/or arsenic. Preferably, the n-type impurity is heavily doped to form n+ regions 56 and 58 at an impurity concentration greater than about 〇2 〇 ions/cm3. The lecture areas 56 and 58 are respectively used as a drain contact region (_η region) and a source region (source regi〇n). Then, in another embodiment, regions 56 and 58 may be formed before or after the gate dielectric, gate, and gate spacers are formed. Those skilled in the art will be aware of the various process steps. Figure 7 shows the formation of gate dielectric f(9), gate 62 and gate_wall 464. Those skilled in the art will appreciate that the gate dielectric 6 〇 preferably includes oxygen (IV), however other dielectric materials such as nitrogen (tetra), ♦ dicing, oxynitridation 0503-A32732TWF/ianchen 11 200820436, or combinations thereof may also be used. . The gate 62 preferably includes a second impurity. In the embodiment: the gate 62 can be made of a metal or a metal nitride: five genus or other conductive materials. It is preferable to deposit and remove unnecessary portions to form the gate spacers 64. The detailed process of the idle junction = 60, the gate 62 and the gate spacer 64 is conventionally known. The second edge is not repeated here. The edge is located directly above the insulating region 44 of the η 24 . . Thus, a high voltage core (HVNMOS) element 66 is formed.乳千V脰 Figures 8 to 9 show a second embodiment of the present invention. This is similar to the embodiment shown in Figure 7, except that the buffer zone 32 = is outside the space between the 井-type well region 28 and the η-type well region 24. In the "example", the structure as shown in Fig. 2 is formed. Next, as shown in Fig. 8, the photoresist is formed to form the p-type well regions 28 and 3, and the type t region 28 and the n-type are formed. The well regions 24 are separated to form a buffer zone 32. It can be understood that the impurities in the n-type well region 24 and the p-type well region 28 are very diffused into the buffer zone 32. However, the concentration of the diffused impurity is divided into two types: : Zone: and p-type well zone 28 impurity concentration. In the examples, i and Ρ 31, the non-degenerate system diffuses into the buffer zone 32 and forms - P-type-n junction π-type and p-type impurity concentration The ratio is likely to be less than one-fifth of the impurity of the n-type well region 24 and the ?-well region 28, respectively, even less than (U. By the buffer zone 32 having an appropriate width %, the ratio may even be less than G G1. Similar to the first - The width W of the embodiment is preferably between, between, and between 0. 5μηι. Main 0503-A32732TWF/ianchen 12 200820436 The foregoing embodiment has an asymmetric structure in which the source region is located in the well region and The polar regions have different conductivity types. Figure 10 shows a symmetric structure of an embodiment ( a HVNMOS of a symmetric structure, wherein the HVNMOS element includes two n-type well regions 70, 72 and a p-type well region 74 therebetween. Similar to the embodiment shown in FIG. 7, buffer regions 76 and 78 are formed, Each of the buffer zones 76 and 78 may be an overlap zone or a spacer zone of an adjacent p-type well zone and an n-type well zone. In another embodiment, the p-type well zone 74 only overlaps f (or separate) η One of the well zones 70 and 72, such that when the p-well zone 74 forms a conventional interface with other adjacent n-well zones, only one of the buffer zones 76 and 78 is formed. The embodiment shows the formation of HVNMOS elements, and those skilled in the art will be aware of the separate formation steps for forming high voltage P-type metal oxide semiconductor (HVPMOS) elements having n-type well regions 24, p-type well regions 26 and 30. The opposite conductivity types of Ν+ regions 56 and 58 (please refer to Figures 7 and 9). It can be understood that the high voltage MOS device has various layouts which are not the same. However, the formation concept of the embodiment of the present invention can still be applied. Ground, the conductivity type of the doped region in FIG. 10 can be reversed to form a symmetric junction HV PMOS element. In addition to forming a HVMOS element, the concept of forming a buffer to affect the electric field distribution can be applied to the formation of other elements such as diodes, between the P-type region and the n-type region. The p-type-n junction forms a buffer to increase the breakdown voltage. An advantage of an embodiment of the invention is that the buffer zone 32 is used to separate the n-type 0503-A32732TWF/ianchen 13 200820436 well region 24 and the p-well District 28. The net impurity concentration inside the buffer zone 32 is low. In an embodiment as shown in Fig. 7, the p-type impurity and the n-type impurity in the buffer zone 32 are mutually neutralized, thereby reducing the net impurity concentration. In an embodiment as shown in Fig. 9, the buffer zone 32 is not formed by doping when forming a well region, and thus the net impurity concentration is low. Therefore, the buffer 32 formed at the interface has a lower net impurity concentration and thus improves the performance of the HVMOS device. Experimental results show that the breakdown voltage of the embodiment of the present invention is boosted by a breakdown voltage of 3V to 5V over a conventional HVMOS device having a similar structure (except for no buffer formation). Further, as shown in Fig. 11, the substrate current (ISUb) of the embodiment of the present invention is significantly lower than that of the conventional HVMOS device. Line 80 shows the substrate current (Isub) of an embodiment of the invention having a maximum value of about 2E-6 Α/μπι. Line 82 shows the substrate current (Isub) of a conventional HVMOS device having a maximum value of about 6.5 Ε όΛ μ μ μ 〇 〇 可 可 可 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 As the substrate current decreases, the lifetime of the HVMOS component increases. While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application. 0503-A32732TWF/ianchen 14 200820436 [Simple description of the drawing] Fig. 1 is a conventional HVNMOS device. 2, 3A, 3B and 4 to 7 are process cross-sectional views showing a first embodiment of the present invention in which an n-type well and a p-type well are used to form a buffer region. Figures 8 and 9 are cross-sectional views of a process according to a second embodiment of the present invention, in which a buffer zone is formed by separating an n-type well and a p-type well. Figure 10 is an embodiment of a symmetrical structure. / Fig. 11 is a comparison diagram of a conventional high voltage MOS device and a substrate current according to an embodiment of the present invention. [Main component symbol description] 2 ~ conventional HVNMOS component; 4~η type well region, 6~> and polar region, 7~ρ type well region, 8~ source region, 10~ gate oxide layer; 12~ gate 14~ shallow trench isolation region; 16~ρ-n-type junction; 20~substrate; 22,26,48,54~ photoresist; 23~Ν+buried; 24,70,72~n type Well area, 25~ insect layer, 28, 30, 74~ρ type well area; 32, 76, 78~ buffer zone; 44~ insulation zone; 52~Ρ+ zone; 56, 58~N+ zone, 60~ Gate dielectric; 62~ gate; 64~ gate spacer; 66~HVNMOS component; 80, 82~ line; 92, 94~ low voltage p-well; 0503-A32732TWF/ianchen 15