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TW200828548A - Wafer-level interconnect for high mechanical reliability applications - Google Patents

Wafer-level interconnect for high mechanical reliability applications Download PDF

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Publication number
TW200828548A
TW200828548A TW096137172A TW96137172A TW200828548A TW 200828548 A TW200828548 A TW 200828548A TW 096137172 A TW096137172 A TW 096137172A TW 96137172 A TW96137172 A TW 96137172A TW 200828548 A TW200828548 A TW 200828548A
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TW
Taiwan
Prior art keywords
solder
nickel
copper
tin
silver
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TW096137172A
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Chinese (zh)
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TWI360211B (en
Inventor
Anthony Curtis
Guy F Burgess
Michael Johnson
Ted Tessier
Yuan Liu
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Flipchip Int Llc
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Publication of TW200828548A publication Critical patent/TW200828548A/en
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Publication of TWI360211B publication Critical patent/TWI360211B/en

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    • H10W72/012

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Abstract

The structure described herein incorporates an interconnect positioned between to spaced electrical contacts. The interconnect comprises a lead (Pb)-free solder alloy consisting essentially of Nickel (Ni), Tin (Sn), Silver (Ag), and Copper (Cu). The Nickel (Ni) in the lead (Pb)-free solder alloy is in a range of 0.01 to 0.20 percent by weight (wt%). An embodiment of the structure described herein is a device comprising a substrate, a first metal layer disposed on the substrate, a bulk solder body disposed on the metal layer; and a wafer device connected to the metal layer through the bulk solder body. The bulk solder body comprises of Nickel (Ni), Tin (Sn), Silver (Ag), and Copper (Cu). The Nickel (Ni) is in a range of 0.01 to 0.20 percent by weight (wt%).

Description

200828548 九、發明說明: 【發明所屬之技術領域】200828548 IX. Description of the invention: [Technical field to which the invention belongs]

本揭示大體而言係有M 2 ^ 育關於半導體元件之姓槿釦古、土 並且更明確地說,係有關 構和方法’ 晶封裝及組件之結構和方法。 寸封裝和覆 【先前技術】 ΟThe present disclosure is generally related to the structure and method of the semiconductor package, the structure and method of the semiconductor device, and more specifically, the structure and method. Inch package and overlay [Prior technology] Ο

U 電子封裝產業對於改呈I力 望存在已H俜i(pb)焊料之機械效能的想 者。先 鋅。先前努力也包含研究捧雜(例如,摻雜心:如 銦和鎳)對於無鉛焊料之機械性質的影響。 、、U Electronics packaging industry is eager to change the mechanical performance of H俜i(pb) solder. First zinc. Previous efforts have also included research on the effects of doping (eg, doping: such as indium and nickel) on the mechanical properties of lead-free solders. ,

觀察到現存内連結構之一 M 問靖疋來自個別、 系列的機械損壞事件的早期内遠姓 " ^ ^ ^ 構失效’例如掉落衝擊 (drop shock)、震動、和剪力。头此 什备衡單 則技藝解決此門 接合點機械強度的嘗試包含 ^通並〜加 modulus)及硬度較低的無鉛焊料,以藉由’、致(Y〇Mg s 來輔助降低脆弱的内連線結構斷 焊料更具繞性 嘢裂(例如,銦基益妒焊粗 錫一銅無鉛焊料、或銀含量較少 “、、於坪枓、 W鑷一銀〜鋼入 、士 先前技藝嘗試並無法令人滿意地除本 ° &二 古早期内連線失效。 據此’期望在使用焊料來製造晶圓級曰 圓、及日曰片尺寸封裝或 覆晶元件時擁有改善的接合點機械強度。 【發明内容】 5 200828548 在此所述之結構包含設置在隔開之電氣接觸之間的内 連結構。該内連結構含有實質上由鎳(Ni)、錫(Sn)、銀(Ag) 和銅(Cu)所組成的無鉛(Pb)焊料合金。該無鉛(pb)焊料合金 内的鎳(Ni)係在重量百分比(wt%)〇.〇i至〇·2〇範圍内。 在此所述之結構之一實施例係一元件,其含有基材、 設置在該基材上之第一金屬層、設置在該金屬層上之焊料塊 材主體;以及透過該焊料塊材主體與該金屬層連結的晶圓元 件。該焊料塊材主體係由錄(Ni)、锡(Sn)、銀(Ag)和銅(Cu) 所組成。鎳(Ni)係在重量百分比(wt%)〇.〇i至〇·2〇範圍内。 【實施方式】 如下描述和圖式示出足以使熟知技藝者實施在此所述 之系統和方法的特定實施例。其它實施例可包含結構、邏 輯、製程和其他改變。範例僅代表可能的變異。 下面描述執行本結構和方法之各實施例的元件。可用 熟知結構來配置許多元件。也應了解本結構和方法的技術 可運用多種技巧來執行。 本發明大體而言係有關於一種改善的内連結構,其使 用含有比例相當低的錄之焊料合金。該改善的結構通常提 供’例如,用來生產晶圓 曰日圓級晶片尺寸封裝(chip-scale package, CSP)或覆晶内;击么丄^ ^連結構之無鉛焊料改善的接合點 機械強度而擁有長效機絲-Pi 碼蛾可靠度。在一實施例中,使用重 量百分比(wt°/〇)0.01至Λ υ·2〇的鎳輔助無鉛焊料合金。例 如,無鉛焊料合金較佳妯 干圧地實質上由錫一銀一銅和〇.〇1至 6 200828548 0.20 wt%的鎳組成。一般可以習知比例使用錫、銀、和鋼。 該焊料合金可以,例如,回流並連接至球下金屬層 (under bump metal) *其可,例如,形成為真空沉積薄膜或 電鍍膜。可用其他習知製造技術來製造如下所述之内連結 構。 咸信鎳輔助無鉛合金與球下金屬層 (under-bump-metallurgy, UBM)的組合一般會提供改善的 接合點機械強度,藉由控制焊料塊材内焊料/ U B Μ介面以 及錫晶粒邊界(内部樹枝狀結構)之介金屬形成。這由發明 人在改善的南速剪力狀態中觀察到並透過掉落測試結果得 到證實’與使用無鎳輔助之無鉛合金的相同結構比較。此 接合點強度的改善對於使用晶圓級CSP或覆晶内連結構的 電子7G件來說是有益的,其中該元件易於掉落,特別是行 動物件,例如行動電話、個人數位助理、ΜΡ3播放器、遊 戲機等。 現在將在後方更詳細討論可執行該鎳辅助焊料合金内 。在第一實施例中,焊料係One of the existing interconnected structures was observed. M asked Jing Yu from the early, long-term surnames of individual, series of mechanical damage events, such as drop shock, vibration, and shear. The first attempt to solve the mechanical strength of this door joint includes the use of ^tong and ~modulus and low-hardness lead-free solder to help reduce the fragile interior by 'Y〇Mg s The connection structure is broken and the solder is more chopped (for example, indium-based bismuth-welding, rough tin-copper-free lead-free solder, or less silver content), Yu Ping, W镊一银~Steel, the previous skill attempt It is not satisfactorily removed from this & early ancient interconnect failure. It is therefore expected to have improved joints when using solder to fabricate wafer-level round-turn, and tantalum-size packages or flip-chip components. Mechanical Strength [Invention] 5 200828548 The structure described herein includes an interconnect structure disposed between spaced electrical contacts. The interconnect structure comprises substantially nickel (Ni), tin (Sn), silver ( Lead-free (Pb) solder alloy consisting of Ag) and copper (Cu). The nickel (Ni) in the lead-free (pb) solder alloy is in the range of weight percent (wt%) 〇.〇i to 〇·2〇. An embodiment of the structure described herein is an element comprising a substrate disposed on a first metal layer on the substrate, a solder block body disposed on the metal layer, and a wafer element coupled to the metal layer through the solder block body. The main system of the solder block is recorded by (Ni), Tin (Sn), silver (Ag) and copper (Cu). Nickel (Ni) is in the range of weight percent (wt%) 〇.〇i to 〇·2〇. [Embodiment] The following description and drawings Specific embodiments are sufficient to enable those skilled in the art to implement the systems and methods described herein. Other embodiments may include structures, logic, processes, and other variations. The examples merely represent possible variations. The following describes the implementation of the present structures and methods. The elements of the embodiments. Many of the elements can be configured with well-known structures. It should also be understood that the techniques of the structures and methods can be performed using a variety of techniques. The present invention generally relates to an improved interconnect structure having a relatively low percentage of use. Recorded solder alloy. The improved structure usually provides 'for example, to produce wafer-scale chip-scale package (CSP) or flip chip; lead-free structure The solder has improved joint mechanical strength and possesses long-lasting wire-Pi code moth reliability. In one embodiment, a weight-accepting (wt°/〇) 0.01 to Λ υ 2〇 nickel-assisted lead-free solder alloy is used. The lead-free solder alloy preferably consists essentially of tin-silver-copper and bismuth 〇1 to 6 200828548 0.20 wt% nickel. Generally, tin, silver, and steel can be used in a conventional ratio. For example, it is reflowed and attached to an under bump metal * which may, for example, be formed as a vacuum deposited film or a plated film. Other conventional manufacturing techniques may be used to fabricate the interconnect structure as described below. The combination of a salt-free nickel-assisted lead-free alloy and an under-bump-metallurgy (UBM) generally provides improved joint mechanical strength by controlling the solder/UB Μ interface and tin grain boundaries in the solder block ( The intermetallic formation of the internal dendritic structure. This was observed by the inventors in the improved south speed shear state and confirmed by the drop test results as compared to the same structure using a nickel-free auxiliary lead-free alloy. This improvement in joint strength is beneficial for electronic 7G pieces using wafer level CSP or flip chip interconnect structures, where the elements are prone to drop, especially for moving objects such as mobile phones, personal digital assistants, ΜΡ3 playback , game consoles, etc. The nickel-assisted solder alloy can be implemented in more detail later in the discussion. In the first embodiment, the solder system

Q 連結構之結構的更具體實施例。在第一 該UBM之間。A more specific embodiment of the structure of the Q-connected structure. In between the first UBM.

7 200828548 用電鑛形成。適合的UBM結 之鋁一鎳(飢)一銅。其他可能 下合金:鈦/鎳釩/銅、鈦/ 鎳/銅、鈦鎢/鎳釩/銅、鉻 適合的厚膜U B Μ之範例可使 /金、鎳構/鎳把/金、把填 /鎳/金。 構之範例是以鋼接觸該焊料 的選擇包含,但不限於,如 鎳/鋼、銥鶴/鋼、鈦鎢/ /鎳/鋼或絡/鎳飢/銅。 用如下合金形成:銅、鎳磷 /金、把磷、鎳/金、或銅 Ο7 200828548 Formed with electricity. A suitable UBM junction is aluminum-nickel (hungry)-copper. Other possible alloys: titanium/nickel vanadium/copper, titanium/nickel/copper, titanium tungsten/nickel vanadium/copper, chromium suitable for thick film UB Μ examples can be / gold, nickel structure / nickel handle / gold, fill / Nickel / Gold. An example of a structure is the choice of steel to contact the solder, but is not limited to, for example, nickel/steel, shovel/steel, titanium tungsten//nickel/steel or lanthanum/nickel/copper. Formed with the following alloys: copper, nickel phosphorus/gold, phosphorus, nickel/gold, or copper

料塊材的延展性 接合點機械強度。 内連結構之接合點強度取決於該焊 (撓性)以及IMC在焊料/ UBM界面處的 雖然預期内連結構有增強的可靠性,但介面imc本身被視 為是相當脆弱的。 咸信無錯焊料内連結構之改善的接合點機械效能可由 如下幾點之一或組合來輔助:改善焊料塊材微結構性質、 改善UBM、结構的相容性(例如,UBM膜應力水準或可溶 性)、以及藉由改善對於介面IMC成長和發展之控制。 藉由使用已知的鬲速剪力和高速冷拉球試驗The ductility of the material block is the mechanical strength of the joint. The joint strength of the interconnect structure depends on the weld (flexibility) and the IMC's reliability at the solder/UBM interface, although the expected interconnect structure is enhanced, but the interface imc itself is considered to be quite fragile. The improved joint mechanical performance of the solder-free solder interconnect structure can be assisted by one or a combination of: improving the microstructure of the solder block, improving UBM, structural compatibility (eg, UBM film stress level or Soluble), and by improving control over the growth and development of interface IMC. By using known idle shear and high speed cold drawn ball tests

Pull test)來_擬機械掉落衝擊事件觀察到利用在晶圓級 C/P和t晶内連結構上使用擁有上述焊料纟金内連結構之 、θ料鬼材所#到的改善。該試驗包含使用大範圍的測試條 件參數(例如,衝整前六 ^ 衝擎剪力拉速、和衝擊剪力高度),以估 量使用錄輔助焊料所得到的改善。使用已知掉落試驗設備 八式驗測試以鎳輔助焊料製成之結構的掉落測試可靠 度’其表現比可得的其他選擇顯著好許多。測試也包含擁 強的〜、薄膜應力水準和可溶金屬厚度之各種Μ選 8 200828548 擇的相容性測試。 第1圖示出組裝至基材前的晶圓級晶片尺寸或覆晶封 裝100之一部分的剖面圖。提供一晶圓元件1〇2(例如,威 型的積體電路(IC)晶粒)以進行隨後至基材的連接(見第2 圖)。一刪108,形成在晶圓元件102上,在介面IMC114 處與焊料塊材106(例如,焊料凸塊或錫球)接觸。在實際 的封裝中,通常會使用大量的焊料凸塊或錫球。The pull test was observed to utilize the improvement of the use of the above-mentioned solder-tantalum interconnect structure on the wafer-level C/P and t-crystal interconnect structures. This test involves the use of a wide range of test condition parameters (for example, the first six strokes of the punching force and the impact shear height) to estimate the improvement achieved with the use of the auxiliary solder. The drop test reliability of a structure made of nickel-assisted solder using a known drop test device is much better than other options available. The test also included a selection of strong ~, film stress levels and soluble metal thicknesses. Figure 1 shows a cross-sectional view of a wafer level wafer size or a portion of a flip chip package 100 prior to assembly to a substrate. A wafer component 1 〇 2 (e.g., a shaped integrated circuit (IC) die) is provided for subsequent attachment to the substrate (see Figure 2). A 108 is formed on the wafer component 102 to contact the solder bumps 106 (e.g., solder bumps or solder balls) at the interface IMC 114. In practical packages, a large number of solder bumps or solder balls are typically used.

υ 第2圖示出組裝後的焊料内連結構2〇〇之一部分的剖 面圖。利用焊料塊材106將晶圓元件1〇2與基材ι〇4(例 如,印刷電路板)連接。 在基材104上形成習知金屬表面處理或層ιι〇,其對 於焊料附著具傳導性,並在介面IMC 112處與焊料塊材ι〇6 接觸。焊料塊# 106擁有在此所述之焊料合金成分。金屬 表面處理 1 1 〇可,例如 擁有與UBM類似的銅上層。但 並非總疋如此。若金屬表面處理11〇擁有鋼表面處理,其 厚度通常顯著大於晶圓側上的UBM者。基材1〇4上的銅 表面處理範圍可在,例如,約2至5微米(|Lims)。 可使用各種基材1 04表面處理。例如,一種普遍的基 材表面處理是位於表面上之連同有機層的鋼,以保護銅不 欠氧化’稱為’’銅Ο S P ’’。其它範例是鎳磷/金,或銀(有時 稱為浸鍍銀)。 介面IMC 114的厚度可以是,例如,低於約2 〇微米 (pms)。UBM 108的厚度可以是,例如,低於約2.0微米 (μηι〇。這些厚度在其他實施例中可大幅度改變。 200828548 在此所述之内連結構和方法可在,例如,又其他類型 的晶片尺寸或晶圓級封裝中實施(例如,板上連接式晶片封 裝(chip-on-board,COB)組件應用或用於覆晶封裝應用之 標準覆晶封裝)此類實施之範例在美國專利第6,441,487號 (2 0 02年8月27號核准予Elenius等,標題為使用高延展 錫球之晶片尺寸封裝)和美國專利第5,844,304號(1998年 12月1號核准予Kata等,標題為製造半導體元件和半導 體晶圓之製程)、以及美國專利第5,547,740號(1 996年8 Γ》 k 月20號核准予犯8(1〇11等,標題為覆晶積體電路元件之可 焊接觸)和美國專利第6,251,501號(2001年6月26號核准 予Higdon等,標題為表面黏著電路元件和其焊料凸塊方法) 中描述,每一者皆在此藉由引用其至少關於封裝應用、結 構和製造方法之教不的方式併入本文中。 現在在具體範例中更詳細討論該内連結構本身。在一 實施例令,一無鉛焊料合金實質上由錫一銀一銅和〇 〇l至 0.20 wt%的鎳組成。該無鉛焊料合金之一範例是98 4%錫 〇 一 K〇%銀—〇·5%銅一 〇.1%鎳。做為該錫一銀一銅組成之範 例,銀成分可以是約〇·25至4·〇 wt%,而銅約〇至2 〇 wt〇/〇。 錫成分可以是,例如,約99· 75至94.5 wt%,或提供任何 上列成分的平衡。如在任何焊料組成中者,通常有微量元 素存在,其係不重要的並且當保持在習知標準内時預期不 會影響到該内連結構的性質。該焊料合金可以是,例如, . 不連續焊料球體(即,錫球)或踢膏型態。該焊料可以,例 如回",l至利用真空沉積薄骐或電鍍膜形成的UBM處。 10 200828548 咸上述焊料合金組成連同UBM的應用 料回流後於該UBM /焊料介面處提供較平滑、 屬厚度,其最小化此脆弱介面的異質成長。在 " 例中’該UBM的上層是鋼,其與該焊料塊材 . 確地說,在一較佳實施例中,該U B Μ上表面 銅在該回流製程期間形成為介金屬(IMC)層, UBM中之邊界錄層。相反地,若該UBM僅是 ^ 銅層’則其絕不會在製程中任何時點或介面處^ 此外,咸信上述結構的使用可在焊料回流 塊材内圍繞該锡晶粒邊界處的内部樹枝狀焊接 低程度的介金屬。這協助使該焊料塊材比無鎳 更具撓性。在一實施例中,該UBM結構擁有肩 因為某些封裝產業所需要之薄膜需求。這與僅 的電鑛銅相悖,其無法適切符合UBM製造封 該較佳實施例中的UBM擁有其他薄膜金屬層 應在UBM上層中使用足夠的銅以將imc形成 滑度。例如,該UBM中銅層的最小厚度應該是 在該較佳實施例中,該UBM内的鋼與焊料中 形成該平滑的IMC層。該UBM内的鎳也可在 對IMC形成產生貢獻。 在其他實施例中,該UBM中之不同金屬 與該焊料反應並對該IMC的形成及其性質產 如,在一鎳磷基UBM中,該UBM内的鎳可與 錫而非銅反應而形成該平滑的IMC層。 可輔助在焊 較薄的介金 一較佳實施 反應。更明 内大部分的 這暴露出該 一相當厚的 波完全消耗。 後在該焊料 區内提供較 摻雜的合金 限量的銅, 使用一薄層 襞的要求。 ’例如鎳釩。 至預期的平 約7,000埃。 的鎳反應而 某些程度上 結構組合會 生貝獻。例 該焊料中的 11 200828548 在此間描述之預期的鎳摻雜範圍内,觀察到該介面 IMC厚度比相同的無鎳摻雜合金厚。進一步觀察到該介面 IMC之較平滑的微結構比沒有鎳的無鉛合金中普遍存在之 鋸齒狀、扇形邊的微結構更令人滿意。該較平滑的微結構 使該IMC内可以有平均的應力。該鋸齒狀、荷葉邊的微結 構擁有較高應力狀態的區域,因為該結構並不如較平滑的 微結構般同質。 例如,第3圖示出無鎳摻雜之介面IMC構形300。構 形3 00顯示出不樂見的突波302。相反地,第4圖示出擁 有如上所述之鎳摻雜的介面IMC 114之構形。介面IMC 114的表面400在與無鎳摻雜之IMC相比較下實質上是平 滑的。 關於該内連結構的製造本身,可使用習知晶圓級晶片 尺寸和覆晶製程。例如,可施加焊料至該UBM,並以達到 熔點的焊料回流以在焊料和UBM之間形成實體焊接。 在另一實施例中,可使用厚膜銅UBM。焊料内的鎳會 在回流製程期間與銅反應而形成平滑的介面 IMC 1 1 4層 (見第2圖)。、 藉由前面揭示,改善的内連結構和方法已經描述。上 述之結構及方法通常提供如下優勢。透過摻雜鎳之錫一銀 一銅合金焊料的使用,機械完整性在該焊料塊材的撓性和 該介面IMC厚度的異質成長及成形的最小化,其係該内連 結構中最脆弱的結構,兩者上獲得改善。整體結構比其他 可得選擇顯著地更具延展性,增加該結構吸收來自例如掉 12 200828548 落衝擊、震動和剪力之除此之外具破壞性之機械能量的能 力。 前面對於特定實施例的描述充分揭露本揭示之通則, 而使他人可,藉由應用本知識,輕易地將其修飾及/或改 變,並在不背離基本概念下用於各種應用。因此,此類改 變或修飾係落在所揭示實施例之等效物的涵義和範圍内。 在此所使用的措詞和術語係為了描述而非限制的目的。 【圖式簡單說明】 為了更完整了解本揭示,現在參考如下圖式,其中在 該等圖式中相似的元件符號表示相仿的物件: 第1圖示出根據本揭示之一例示實施例之組裝至基材 前的晶圓級晶片尺寸或覆晶封裝之一部分的剖面圖。 第2圖示出根據本揭示之一例示實施例之組裝後的焊 料内連結構。 第3圖示出無鎳摻雜之介面IMC(金屬互化物)構形。 第4圖示出根據本揭示之一例示實施例之含鎳摻雜之 介面IMC構形。 在此所提出的範例示出特定實施例,並且此範例不應 被視為以任何方式限制本發明。 【主要元件符號說明】 100 封裝 102 晶圓元件 104 基材 106 焊料塊材 13 200828548 108 UBM 110 金屬表面處理 112、 114 介面IMC 200 焊料内連結構 300 構形 302 突波 400 表面 14υ Fig. 2 is a cross-sectional view showing a part of the assembled solder interconnect structure 2〇〇. The wafer component 1〇2 is connected to the substrate ι4 (e.g., a printed circuit board) by the solder bulk material 106. A conventional metal finish or layer is formed on the substrate 104 that is conductive to the solder attachment and is in contact with the solder block ι6 at the interface IMC 112. Solder block #106 has the solder alloy composition described herein. Metal Finishing 1 1 〇 可, for example, has a copper upper layer similar to UBM. But this is not always the case. If the metal surface treatment has a steel surface treatment, the thickness is usually significantly larger than the UBM on the wafer side. The copper surface treatment on substrate 1〇4 can range, for example, from about 2 to 5 microns (|Lims). A variety of substrates can be used for surface treatment. For example, a common substrate surface treatment is steel with an organic layer on the surface to protect the copper from oxidizing 'called ''copper Ο S P ''. Other examples are nickel phosphorus/gold, or silver (sometimes referred to as immersion silver plating). The thickness of the interface IMC 114 can be, for example, less than about 2 〇 microns (pms). The thickness of the UBM 108 can be, for example, less than about 2.0 microns (μηι〇. These thicknesses can vary widely in other embodiments. 200828548 The interconnect structures and methods described herein can be, for example, other types Example implementations in wafer size or wafer level packaging (eg, chip-on-board (COB) component applications or standard flip chip packages for flip chip packaging applications) No. 6,441,487 (Approved to Elenius et al., August 27, 2002, entitled Wafer Size Package Using Highly Expanded Tin Balls) and US Patent No. 5,844,304 (Approved to Kata et al., December 1, 1998, Title) Process for manufacturing semiconductor components and semiconductor wafers, and U.S. Patent No. 5,547,740 (1 996 Γ k k k 20 20) approved for 8 (1〇11, etc., titled Solderable Circuit Components Contact) and U.S. Patent No. 6,251,501 (issued to Higdon et al., entitled "Surface Adhesive Circuit Element and Its Solder Bump Method", June 26, 2001, each of which is hereby incorporated by reference herein Package application The teachings of the structure and method of fabrication are incorporated herein. The interconnect structure itself is now discussed in more detail in the specific examples. In one embodiment, a lead-free solder alloy consists essentially of tin-silver-copper and tantalum To 0.20 wt% nickel composition. An example of the lead-free solder alloy is 98 4% tin antimony-K〇% silver-rhenium 5% copper-niobium. 1% nickel. As an example of the tin-silver-copper composition The silver component may be about 至25 to 4·〇wt%, and the copper may be about 2 〇wt〇/〇. The tin component may be, for example, about 99·75 to 94.5 wt%, or any of the above listed components may be provided. The balance, as in any solder composition, is usually trace element present, which is not critical and is not expected to affect the properties of the interconnect structure when maintained within conventional standards. The solder alloy can be, for example, . Discontinuous solder sphere (ie, solder ball) or kick paste type. The solder can, for example, back to the UBM formed by vacuum deposition of a thin crucible or a plated film. 10 200828548 Salted above solder alloy composition together UBM application material is supplied at the UBM/solder interface after reflow Smooth, thickness, which minimizes heterogeneous growth of the fragile interface. In the " example, the upper layer of the UBM is steel, and the solder block. Indeed, in a preferred embodiment, the UB Μ The upper surface copper is formed as a via metal (IMC) layer during the reflow process, and a boundary layer in the UBM. Conversely, if the UBM is only a copper layer, it will never be at any point or interface in the process ^ In addition, it is believed that the use of the above structure can weld a low degree of intermetallic metal within the solder reflow block around the inner dendrites at the boundaries of the tin grain. This assists in making the solder block more flexible than nickel free. In one embodiment, the UBM structure has a shoulder because of the film requirements required by certain packaging industries. This is contrary to the only copper ore, which does not conform to the UBM manufacturing seal. The UBM in the preferred embodiment possesses other thin film metal layers. Sufficient copper should be used in the upper layer of the UBM to form the slip of the imc. For example, the minimum thickness of the copper layer in the UBM should be such that in the preferred embodiment, the smooth IMC layer is formed in the steel and solder within the UBM. Nickel in the UBM can also contribute to the formation of IMC. In other embodiments, different metals in the UBM react with the solder and form the IMC and its properties. In a nickel-phosphorus-based UBM, nickel in the UBM can react with tin rather than copper. The smoothed IMC layer. It can assist in the better implementation of the reaction of thinner metal. It is clear that most of this reveals that this rather thick wave is completely consumed. A limited amount of copper is then provided in the solder zone to limit the amount of copper used, using a thin layer of germanium. ' For example, nickel vanadium. Up to the expected level of 7,000 angstroms. The nickel reacts to some extent. Example 11 200828548 In this solder, the expected IMC thickness is observed to be the same thickness as the nickel-free doped alloy in the expected nickel doping range described herein. It is further observed that the smoother microstructure of the interface IMC is more satisfactory than the zigzag, scalloped microstructures prevalent in lead-free alloys without nickel. This smoother microstructure allows for an average stress within the IMC. The jagged, ruffled microstructure has a region of higher stress because the structure is not as homogeneous as a smoother microstructure. For example, Figure 3 shows a nickel-free doped interface IMC configuration 300. Configuration 300 shows a glitch 302 that is unpleasant. Conversely, Fig. 4 shows the configuration of the interface IMC 114 having the nickel doping as described above. The surface 400 of the interface IMC 114 is substantially smooth compared to a nickel-doped IMC. Regarding the fabrication of the interconnect structure itself, conventional wafer level wafer size and flip chip process can be used. For example, solder can be applied to the UBM and solder reflow to a melting point to form a physical weld between the solder and the UBM. In another embodiment, a thick film copper UBM can be used. Nickel in the solder reacts with copper during the reflow process to form a smooth interface IMC 1 1 4 layers (see Figure 2). The improved interconnect structure and method have been described by the foregoing disclosure. The above structures and methods generally provide the following advantages. Through the use of nickel-doped tin-silver-copper alloy solder, mechanical integrity is the most fragile in the interconnect structure due to the flexibility of the solder block and the heterogeneous growth and formation of the interface IMC thickness. Structure, both improved. The overall structure is significantly more ductile than other available options, increasing the ability of the structure to absorb destructive mechanical energy from, for example, the impact, shock and shear forces of 200828548. The above description of the specific embodiments fully discloses the general principles of the disclosure, and others can be easily modified and/or changed by applying the present knowledge and used in various applications without departing from the basic concepts. Therefore, such changes or modifications are within the meaning and range of equivalents of the disclosed embodiments. The words and terms used herein are for the purpose of description and not limitation. BRIEF DESCRIPTION OF THE DRAWINGS For a more complete understanding of the present disclosure, reference is now made to the drawings in which like referenced FIGS. A cross-sectional view of a wafer level wafer size or a portion of a flip chip package to the front of the substrate. Figure 2 illustrates an assembled solder interconnect structure in accordance with an illustrative embodiment of the present disclosure. Figure 3 shows the interface of the nickel-free doped interface IMC (intermetallic compound). Figure 4 illustrates a nickel-doped interface IMC configuration in accordance with an illustrative embodiment of the present disclosure. The examples presented herein are illustrative of specific embodiments and are not to be considered as limiting the invention in any way. [Main component symbol description] 100 Package 102 Wafer component 104 Substrate 106 Solder block 13 200828548 108 UBM 110 Metal surface treatment 112, 114 Interface IMC 200 Solder interconnect structure 300 Configuration 302 Surge 400 Surface 14

Claims (1)

200828548 十、申請專利範圍: 1 · 一種内連結構’設置在隔開之電氣接觸之間,該内連結 構至少包含: 一無鉛(Pb)焊料合金,其實質上由鎳(Ni)、錫(Sn)、銀 • (Ag)和銅(Cu)組成; 其中錄(Ni)係在重量百分比(wt%)〇 〇1至〇 2〇範圍内。 〇 2·如申請專利範圍第1項所述之内連結構,其中上述之内 連結構係包含在一覆晶封裝中。 3 · —種元件,其至少包含: 一基材; 一第一金屬層,設置在該基材上; 一焊料塊材主體,設置在該金屬層上; 一晶圓元件,透過該焊料塊材主體與該金屬層連結;以 〇 及 其中該焊料塊材主體係由鎳(Ni)、錫(Sn)、銀(Ag)、和 銅(Cu)組成;其中鎳(Ni)係在重量百分比(wt%)0.01至0.20 範圍内。 4.如申請專利範圍第3項所述之元件,其中上述之焊料塊 材主體包含: 9 8 · 4 % 錫(S η)、1 · 0 % 銀(A g)、0 · 5 % 銅(C u)、以及 0.1% 15 200828548 鎳(Ni) 〇 5 ·如申請專利範圍第3項所述之元件,其中上述之焊料塊 ' 材主體包含: . 重量百分比(wt%)約0·25至4.0的銀(Ag); 重量百分比(wt%)約0至2.0的銅(Cu);以及 重量百分比(wt%)約99.75至94.5的錫(Sn)。 f' 16200828548 X. Patent application scope: 1 · An interconnect structure is disposed between spaced electrical contacts, the interconnect structure comprising at least: a lead-free (Pb) solder alloy substantially consisting of nickel (Ni) and tin ( Sn), silver • (Ag) and copper (Cu); wherein (Ni) is in the range of weight percent (wt%) 〇〇1 to 〇2〇. The interconnect structure of claim 1, wherein the interconnect structure is included in a flip chip package. a component comprising at least: a substrate; a first metal layer disposed on the substrate; a solder bulk body disposed on the metal layer; and a wafer component through the solder block The main body is coupled to the metal layer; the crucible and the main system of the solder block are composed of nickel (Ni), tin (Sn), silver (Ag), and copper (Cu); wherein nickel (Ni) is in weight percent (wt %) in the range of 0.01 to 0.20. 4. The component of claim 3, wherein the solder block body comprises: 9 8 · 4 % tin (S η), 1 · 0 % silver (A g), 0 · 5 % copper ( C u), and 0.1% 15 200828548 Nickel (Ni) 〇5. The component of claim 3, wherein the above-mentioned solder block material comprises: . Weight percent (wt%) of about 0·25 to Silver (Ag) of 4.0; copper (Cu) in a weight percentage (wt%) of about 0 to 2.0; and tin (Sn) in a weight percentage (wt%) of about 99.75 to 94.5. f' 16
TW096137172A 2006-10-05 2007-10-03 Wafer-level interconnect for high mechanical relia TWI360211B (en)

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US8610270B2 (en) 2010-02-09 2013-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and semiconductor assembly with lead-free solder

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CN103165472A (en) * 2011-12-15 2013-06-19 北京大学深圳研究生院 Fiber channel (FC)-ball grid array (BGA) packaging bump distributed heat dissipation novel method
KR101514529B1 (en) * 2013-07-09 2015-04-22 삼성전기주식회사 Printed circuit board and manufacturing method thereof

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GB2346380B (en) * 1999-01-28 2001-07-11 Murata Manufacturing Co Lead-free solder and soldered article
US6413851B1 (en) * 2001-06-12 2002-07-02 Advanced Interconnect Technology, Ltd. Method of fabrication of barrier cap for under bump metal
JP3796181B2 (en) * 2002-02-14 2006-07-12 新日本製鐵株式会社 Electronic member having lead-free solder alloy, solder ball and solder bump
TW578217B (en) * 2002-10-25 2004-03-01 Advanced Semiconductor Eng Under-bump-metallurgy layer

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TWI414049B (en) * 2009-07-16 2013-11-01 瑞薩電子股份有限公司 Semiconductor device manufacturing method
US8633103B2 (en) 2009-07-16 2014-01-21 Renesas Electronics Corporation Semiconductor device and manufacturing method of the same
US8610270B2 (en) 2010-02-09 2013-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and semiconductor assembly with lead-free solder

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