TW200824128A - Pixel structure and fabricating method thereof - Google Patents

Abstract

A pixel structure including a scan line, a data line, an active device, a shielding electrode, and a pixel electrode is provided on a substrate. The data line includes an upper and a bottom conductive wire. The upper conductive wire is disposed on the scan line and crosses over the scan line. The bottom conductive wire is electrically connected to the upper conductive wire. The active device is electrically connected to the scan line and the upper conductive wire. The shielding electrode is disposed on the bottom conductive wire. The pixel electrode is electrically connected to the active device. Furthermore, part of the pixel electrode and part of the shielding electrode form a storage capacitor.

Description

。 。 。 。 。 。 。 。 。 The structure of the halogen and its manufacturing method. [Prior Art] Thin Film Transistor Liquid

Crystal Display (TFT LCD) is mainly composed of a thin film transistor substrate, a color filter substrate, and a liquid crystal layer. Among them, the thin film transistor is usually used as a driving switch, which is composed of a gate, an active layer, a source and a drain. The film pen day and day body can be divided into amorphous dream (ajjjQrphous silicon, a-Si) thin film transistor and polycrystalline germanium (1 > 〇 17_ 〇 〇 11) thin film transistor according to the material of the active layer, due to polycrystalline Compared with the amorphous Aussie thin film transistor, the Shixi thin film transistor has a small power consumption and a large electron mobility, and the liquid crystal display using the low temperature polycrystalline germanium film transistor as a driving element has a thin thickness, a light weight, and a resolution. It is especially suitable for mobile terminal products that require light and power saving. The structure of the conventional polycrystalline germanium thin film transistor liquid crystal display includes a scanning line, a data line, a polycrystalline thin film transistor and a halogen electrode. Among them, the _) size factor between the halogen electrode and the data line, the utilization of the light source of the opening i of the (IV) element structure, and thus the liquid crystal display at the pixel age, when The electrode and the (4) wire are too stalked 'the element of the electrode and the data line _ stray capacitance Cpd nce 200824128 AUU6Uyi28 22451twf.doc/e between pixel and data line) will become larger, resulting in the voltage of the halogen electrode in the polycrystalline film During the period when the transistor is turned off, it is affected by the signal transmitted by the data line, and a so-called cross talk is generated, thereby affecting the display quality of the liquid crystal display panel. In order to reduce the crosstalk effect of the above-mentioned halogen structure, and at the same time maintain the aperture ratio of the halogen structure to a certain extent, many elemental structures have been proposed. Figure 1 is a schematic cross-sectional view of a conventional halogen structure. Referring to FIG. 1, the pixel structure 100 is disposed on a substrate 110. The pixel structure 1 is composed of a scan line (not shown), a data line 130, an active device 140, and a pixel electrode. 150 and a planarization layer 160 are formed. The scan line and the feed line 130 are all disposed on the substrate 110. The active component 14 is disposed on the substrate 11A of the target line and the data line 130, and is electrically connected to the sweeping cat line and the data line 130. The halogen electrode 15 is electrically connected to the active element 140. The planarization layer 160 is disposed over the data line 13A to extend the edge of the pixel electrode 150 above the data line 130 to increase the aperture ratio. Since the thickness of the planarization layer (10) is thick and is often a material with a low dielectric constant, the variation of the stray capacitance Cpd on the halogen electrode 150 can be reduced. However, in the current flattening layer _ process, the dissimilar organic material, such as acrylic vinegar, has the disadvantage of easily absorbing moisture and causing poor adhesion. In the process, the material itself cannot be completely bleached. The disadvantage of reducing the overall penetration of alizarin. In the pixel structure 100, the storage capacitor is composed of a plurality of layers 142 (lower electrodes), and the effect of storing electricity and the conduction of the upper and lower electrodes are related. In the 200824128 AU0609128 22451twf.doc/e part process of the germanium structure, since part of the polysilicon layer 142 is covered by the upper first metal layer, !44, the ion doping process of the poly germanium layer 142 is not easily performed. The conductivity of the polysilicon layer 142 is lowered. In order to achieve a certain level of performance in the storage valley, the drive voltage is increased. SUMMARY OF THE INVENTION The present invention is directed to a halogen structure having a shielding electrode. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display panel having the present invention described in the present invention, which is compatible with existing processes. The present invention relates to an optoelectronic device having the display panel of the present invention. In order to specifically describe the content of the present invention, a picture j is disposed on a substrate, and the pixel structure includes a scan line, a data line, a moving electrode, and a halogen electrode. The scan lines are placed on the substrate. The data line is disposed on the substrate, and the data line includes an upper layer conductor* above the scan line and spans the scan line: the lower layer ¥ line is electrically connected to the upper layer line. The active component is coupled to the substrate and electrically connected to the scan line and the upper layer. Shading electrode configuration: g v line above. The pixel electrode is located above the shielding electrode and is connected to the active ns and the hetero-pixel electrode and the hybrid electrode are formed by the present invention. The present invention further provides a detailed display panel, which comprises an embodiment of the invention arranged on the substrate. The structure of the morpheme. , 7 200824128

Auuouyi28 22451twf.d〇c/e This is a method for manufacturing a species of a halogen structure, including the following steps. First, an active component, a scan line, and an I are formed on a substrate, wherein the active component is electrically connected to the scan line. Next, a g-shielding electrode is formed in which the shielding electrode is on the lower layer conductor and the upper layer is electrically connected to the active element. Thereafter, a halogen electrode electrically connected to the main element is formed, wherein the cover electrode is located at the shield electrode to the square and the portion of the halogen electrode and the partial shield electrode form a volume of 0, which is in the present invention. The data line in the pixel structure and the pixel electrode are arranged to shield the electrode, which can reduce the influence of the data line on the voltage of the input pixel electrode when transmitting the signal. In addition, since the shielding electrode shields the data line to generate an electric field generated by different voltages, the influence of the data line on the halogen electrode is greatly reduced, so the design of the pixel electrode can be extended above the data line to increase the aperture ratio of the halogen structure. , thereby improving the display brightness of the liquid crystal display. [Embodiment] FIG. 2A is a schematic diagram of a display panel composed of a matrix structure array arranged on a substrate according to an embodiment of the present invention, and FIG. 2B is a view corresponding to AA in FIG. 2A. Schematic diagram of the B-B' and C-C' section lines. Referring to the figure, the display panel is composed of a plurality of halogen structure 2 arrays arranged on the substrate 21A. For convenience of explanation, only two halogen structures 2 are represented in the figure. Referring to FIG. 2A and FIG. 2B, the pixel structure 200 200824128 AUU6〇yi28 22451 tw/doc/e of the present embodiment is disposed on a substrate 210, and the pixel structure 200 includes a scan line 220, a data line 230, and a The active component 240, a shielding electrode 250 and a halogen electrode 260. The scan line 220 is disposed on the substrate 210. The data line 230 is disposed on the substrate 210' and the data line 230 includes an upper layer conductor 230a and a lower layer conductor 230b. The upper layer conductor 230a is disposed above the scan line 220 and spans the scan line 220. The lower layer conductor 230b is electrically connected to the upper layer conductor 230a. In order to reduce the contact resistance between the data wires 230a and 230b to reduce the obstruction of the lean material transmission, in the present embodiment, the partial regions of the lower layer wires 23〇b overlap the upper layer wires 230a and directly meet at the overlap. However, in other embodiments, the lower layer conductors 230b and the upper layer conductors 23a may not overlap each other and may be electrically connected by a third conductive material. The third conductive material comprises a light transmissive material (eg, indium tin oxide, indium zinc oxide, aluminum zinc oxide, zinc oxide or the like), and a reflective material (eg, gold, silver, copper, iron, wrong, entangled, Niobium, titanium, titanium, group, or alloy, or a nitride thereof, or an oxide thereof, or other, or a combination thereof, or a combination thereof. The active device is disposed on the substrate 210 and the active device is electrically connected to the scan line 22A and the upper layer 230a. The shielding electrode 250 is disposed above the lower layer conductor 23, and blocks the electric field of the lower layer conductor. The halogen electrode is located above the shielding pole 250 and electrically connected to the active component 24, and a portion of the pixel electrode 260 and a portion of the shielding electrode 250 form a storage capacity. In the implementation of t], the moving element is, for example, a thin-film germanium crystal, and the thin-film transistor contains a single-single-electron crystal; the vermiculite U-shaped film or other transistor, Example of Lai Crystal 200824128

Auuouy ι28 2245 Itwf.doc/e is exemplified by a polycrystalline slab film transistor and is manufactured using a low temperature process, but is not limited thereto. In other embodiments, the active device may also be an amorphous thin film transistor, a single crystal thin film transistor, a microcrystalline thin film transistor, or a combination thereof. In the present embodiment, the active device 240 is composed of a semiconductor layer 242 and a gate 246. The semiconductor layer 242 has a source region 242a electrically connected to the upper layer conductor 2 and a drain region 242b electrically connected to the pixel electrode 260 (shown in FIG. 2B). However, in order to lower the halogen electrode 26 The contact impedance when the germanium is in direct contact with the active device 240 further includes forming the drain electrode 27〇b while forming the shield electrode 250 and the upper layer conductor 230a, so that the pixel electrode 260 is electrically connected to the drain region 242b via the drain 270b. In addition, the semiconductor layer 242 also has a turning portion 242c connected between the source region 242 & and the drain region 242b. The semiconductor layer 242 located under the scan line 220 is not replaced by an intrinsic semiconductor (such as, for example, $emic〇n, such as gamma), and the semiconductor layer 242 not covered by the scan line 220 is doped. In the extrinsic semiconductor E (Extrinsic Semiconductor), the inflection portion 242c Φ includes the intrinsic semiconductor 1 and the extrinsic semiconductor E. In addition, in the embodiment, the turning portion 242c is substantially 90 degrees, so that the source region 242a, the drain region 242b, and the turning portion 242c are arranged in a substantially L shape, but is not limited thereto. In the example, the turning portion 242c may be a so-called turning or other non-90 degree turning, that is, the shape of the semiconductor layer 242 is substantially U-shaped, substantially S-shaped, or other shapes. In this embodiment, the width of the shielding electrode 250 is substantially greater than or equal to the width of the lower layer conductor 230b, and the shielding electrode 250 has an extension portion 200824128 AUU6U^128 22451 tw doc/e 252 extending along the scanning line 22 资料 and the data line 23 The direction of at least one of the crucibles is connected to the shielding electrodes 250 on the left and right sides of the halogen. In other words, the extension 252 extends below the halogen electrode 26〇. In the embodiment of the present invention, the extension portion 252 extends the direction of the scanning line 22〇, but is not limited thereto, and the left and right electrodes 25〇= at least one of the extension portions 252 may extend the scanning line. Extending in the direction of 220, but not electric! 1 connection, the extension length depends on the aperture ratio required by the present invention, that is, the extension portion 252 of at least one of the shielding electrodes 250 on the left and right sides and any shielding electrode There is a spacing between 25 、, or the extension is extended in the direction of the data line 230, and then the scanning line 22 is extended.

St extension 'and electrical connection or non-electrical connection of the other - shielding electrode 250 can be seen, the aperture ratio requirement design, or the direction of the scanning line 22 先 first, and then extend in the direction of the data line 230 Depending on the design of the scanning line 22〇2 and the electrical connection or non-electrical connection of the other shielding electrode 25〇/U ratio, or other feasible methods. In the display panel of the preferred embodiment, each of the shielding electrodes 250 of each pixel structure is connected to each other by the extension portions 252, and is electrically connected with the f-voltage 'to shield the lower layer wires 23%. The main electric field generated when the (four) voltage is transmitted is such that the voltage input to the elemental electrode 26A is not affected by the image quality, and the voltage may include the common electrode voltage or other fabrications of the present invention. The implementation of the financial, the structure of the vegetarian system is not painful. Referring to FIGS. 3A to 3C, an element 240, a scan line 220, and a lower layer conductor 23b are formed on the substrate 21, wherein the material of the substrate 11 200824128 AUU6〇yi28 22451twf.doc/e 200 includes a transparent material (eg, glass) , quartz, or other materials are not f first material (such as · Shi Xi material, pottery, or other materials), or can be around the raw material (such as · plastic, polypropylene shaft polymer, polyester polymer, polyene The polymer of the present invention, or other polymers, the embodiment of the present invention uses glass for each example. The active device 240 is, for example, composed of a gate 246 and a semiconductor | 242 having source and drain regions 242a, 242b. Semiconductor thin film transistor. First, referring to FIG. 3A, a semiconductor reed 242 is first formed on a substrate. The method for forming the semiconductor layer 242 is, for example, low pressure chemical vapor deposition (LPCVD), followed by a recrystallization process, and then The patterning is performed to form the semiconductor layer 242, or vice versa. Next, as shown in FIG. 3B, a first dielectric layer 244 covering the semiconductor layer is formed on the substrate 21A. Thereafter, in the first dielectric Forming a first layer 244 The photoresist layer 248 is formed, wherein the first patterned photoresist layer 248 has an opening H1, H2 respectively above the two ends of the semiconductor layer 242, and the two openings H1, H2 are used to define the first doping The position of the impurity regions 242ai, 242bl. Next, the first doping process D1 is performed by using the first patterned photoresist layer 248 as a mask. In the embodiment, the first dielectric layer 244 is formed on the substrate 21A. The method is, for example, chemical vapor deposition (CVD), and the material of the first dielectric layer 244 is, for example, hafnium oxide, tantalum nitride, hafnium oxynitride, niobium carbide, organic niobium or a combination thereof. In the present embodiment, the first doping process Di belongs to a high concentration holding process. Then, referring to FIG. 3C, after performing the first doping process D1, the first patterned photoresist layer 248 is illustrated. 3B). Next, 12 200824128 AUU〇uyi28 2245Itwf.doc/e forms a gate 246, a scan line 220 and a lower layer 230b on the dielectric layer 244. The gate 246 is located above the semiconductor layer 242. The scan line 220 is electrically connected to the active device 24A. Embodiment, the gate 246 is formed in, further comprising forming a second doped region 242 VII 2421) 2 on the semiconductor layer 242. As shown in FIG. 3C, the second doped regions 242a2, 242b2 are simultaneously formed and the second doped regions 242a2, 242b2 are located adjacent to the first doped regions 242ai, 242b of one end of the semiconductor layer 24: 2 [in In other embodiments, the second doping regions 242a2, 2423b may be selected to be doped only on one side of the first doping regions 242ai, 242b!. The method of forming the second doping regions 242a2, 242t > 2 includes performing a second doping process D2' with the gate 246 as a mask such that the semiconductor layer 242 on both sides of the gate 246 is formed by the first doping region 242ai, 242b! and a source region 242a and a drain region 242b formed by the second doping regions 242a2, 2421 > In the present embodiment, the gate 246 is formed by, for example, first forming a first metal layer on the substrate 21, and then patterning a metal layer ' to form the gate 246. In this embodiment, the first doping process D2 belongs to a low concentration doping process. Then, as shown in FIG. 3D, a second dielectric layer 249 covering the active device 240, the scan line 220 and the lower layer conductor 230b is formed on the substrate 210, and then patterned by a lithography/button engraving process. An opening H3, an opening H4, and an opening: H5 are formed in the dielectric layer 44 and the second dielectric layer 249. ^3, it can be seen that the opening H3 and the opening H4 are respectively located above the first doping regions Μ%! and 242b!, and the opening H5 is located above the partial lower layer wires 23〇1), wherein the two openings DH3, H4 will be used Defining the position where the active component is connected to the upper conductor 230a and the halogen electrode 260, and the opening H5 will be used 13 200824128

Auwuyi28 22451twf.doc/e to connect the lower f-wire 23〇b to the upper layer 2 ground. In addition, "=' this first, the material f of the electric layer 249 is, for example, nitrogen cut, yttria, her St. phlegm, organic bismuth, organic material, or other materials, or a first: electroacoustic: two in the patterning After the second dielectric layer 249 and the first layer of the erbium cladding layer 244, the second dielectric layer; = a mask, 250, wherein the upper layer of the conductor 2 is electrically connected to the main reed by the opening Η3 The wire is 23 sen. The heart t is electrically connected to the lower I. The value is, in this embodiment, the upper layer is formed.

The line 230a and the shield electrode 25 are simultaneously included to form a source (not labeled) and a gate 270b on the opening H4. In other words, the source (not labeled), and the pole 270b, the shielding electrode 25A and the upper layer conductor are formed by patterning the same material layer, such as 绍(A1), 钿(Mo), titanium(五), 敛( Nd), gold, copper, chromium, silver, group, tin, iron, or a nitride thereof, an oxide, or an alloy thereof, or other materials, or the above, please continue to refer to FIG. 3F on the substrate 21〇 Forming a protective layer 280 thereon, forming an opening H6 in the protective layer 280 by a patterning process such as lithography/remaining, wherein the opening H6 is located above the drain 27〇b to expose at least one portion, the pole 270b . In the present embodiment, the material of the protective layer 28 is, for example, tantalum nitride, tantalum oxide, tantalum oxynitride, tantalum carbide, organic tantalum, organic material, or other materials, or a combination thereof. Then, as shown in FIG. 3G, after the patterned protective layer 280, the connection of 200824128 22451twf.d〇c/e AUU〇uyi28 = formation of Gan - through the opening H6 and the non-extremely charged connection of the main Sutong The halogen electrode 26G is electrically connected by the secret semiconductor layer 242. The material of the splicing electrode 260 of the splicing element 240 is determined to include transparency negative ^ ^ ^ tin oxide, indium zinc oxide, aluminum zinc oxide, zinc her, indium secret, or other) , reflective conductive material (such as: Shao (10), = (10) ', (9), 铉 _, gold, copper, complex, silver, tin, iron, or the above nitride, or the above oxide, or the above alloy,

The material of the element electrode 26G of the present embodiment is a material of the dielectric material f as an example. It is to be noted that the 'bungee 270b can reduce the contact resistance of the halogen electrode 26 〇 in direct contact with the active element 24 ,, which is advantageous for the pixel electrode 260 to receive the voltage input from the active element 240. In addition, the halogen electrode 26 is located above the shielding electrode 250, and a part of the halogen electrode 26 and a portion of the 250 constitute a storage capacitor, since the main storage capacitance of the structure is a part of the halogen electrode 260 and the portion The shielding electrode 25〇 is formed, and the first metal layer 144 and the semiconductor layer M2 are used as the main storage capacitor electrodes in the conventional process, so the storage capacitor of the halogen structure 200 is less effective in the performance than the conventional technology. The semiconductor layer 242 cannot smoothly perform ion doping and causes a problem that the driving voltage is large. Upon completion of this step, a unitary structure 200 is formed. In the present embodiment, the design of the shielding electrode 250 in the halogen structure 200 greatly reduces the influence of the tributary wire 230 on the halogen electrode 260, and the difference between the pixel electrode 260 and the tributary wire 230 is reduced due to the electric field screen effect. The bulk capacitance Cpd affects, so in the technical field of high aperture ratio, regardless of the design of the crosstalk effect 15 200824128 Αυυ _ 28 22451 twf.dOC / e or the storage capacitor design, not I. , the system can further obtain higher penetration "2 [Second embodiment] 尺I soil edge is not time quality. Production; second embodiment of the second embodiment of the 'milk structure is similar, but the two The difference lies in the method of forming the source region 242a and the drain region 242b in the body 240, and the method of forming the source region 242a and the gate region 242b. The ai + board plus the formation-covering semiconductor/24=forming, and then forming a second patterned light on the base layer 244 of the 孤 〃 〃 244 layer 244 The resist layer 29〇 is used to form the gate 246, the scan line 220 and the lower layer 230b. Then, through the ^-money engraving process (such as: isotropic etching process or other engraving process), at the first = patterning The gate 246, the scan line 22〇 and the lower layer $2301 below the photoresist layer 290 generate an undercut (un (jercut). In other words, the width of the second patterned photoresist layer 290 is larger than that of the gate, and then, The second photoresist layer 290 is used as a mask of the third doping D3 to form first doping regions 242a!, 242b!. In this embodiment, the second The patterned photoresist layer 290 has a dual function, one is a mask patterned as the gate 246, and the other is a mask as the third doping process D3. In this embodiment, the etching process is, for example, wet etching or In addition, the third doping process D3 belongs to a high concentration doping process. Next, as shown in FIG. 4C, after the second patterned photoresist layer 29 is removed, the gate 246 is directly used as a mask. The doping process D4 is such that the second doping region 242a2, 16200824128 AU0609128 22451twf.doc/e 2421?2 is formed adjacent to the first doping region 2423^2421^, so that the two sides of the semiconductor layer 242 become one The source region 242a and the first doping region 242b are formed at the same time, and the second doping regions 242a, 242b2 are simultaneously formed and the second doping regions 242a, 2422a are located at the first doping region 242a adjacent to the two ends of the semiconductor layer 242. !, 242b, in other embodiments, the second doping regions 242az, 242b2 may be selected to be doped only on one side of the first doping regions 242%, 242b!. In this embodiment, the fourth The doping process D4 belongs to a low concentration doping process. Subsequent FIGS. 4D to 4G are similar to FIGS. 3D to 3G, here. In the above embodiment, in addition to the FIGS. 3A to 3C and FIGS. 4A to 4C, the present invention further provides a method for forming the active device 240 including the following. The steps are sequentially shown in FIGS. 5A to 5D. First, as shown in FIG. 5A, a semiconductor layer 242 is formed on the substrate 210, and a first dielectric layer 244 is formed to cover the semiconductor layer 242. The first dielectric layer 244 is patterned by forming a stepped photoresist layer 291. As shown in FIG. 5A, a substantially stepped dielectric layer 244 is formed on the semiconductor layer 242. The method of forming the stepped photoresist layer 291 includes, for example, using a half-tone photo-mask, a gray-tone photomask (gray_tone photo.sk), a slit-pattern photomask, and a winding pattern. A reticle (diffracti〇I1 ph〇t〇-inask) is used to perform a lithography process. Next, a fifth doping process D5 is performed. Since the dielectric layer 244 as a mask has a stepped shape, the semiconductor layer 242 under the uncovered dielectric layer 244 is after the fifth doping process D5. The two ends of the semiconductor layer 242 form first doped regions 242%, 242bi. After the semiconductor layer 242 covered by the thin dielectric layer 244 region is subjected to the fifth doping process D5, the second doping region 2, 2働2 is formed in the semiconductor layer 242. 5C, the first doped regions 242 & 2, 2 pseudo 2 are first doped regions 242a2, 242b2 formed at the same time and located at the opposite ends of the adjacent half & In other embodiments, the second doped regions 242%, 242b2 may alternatively form only one of them. Thereafter, as shown in FIG. 5D, a dielectric layer 244 is formed over the semiconductor layer 242 on which the doped regions have been formed. Next, a gate 246 is formed over the dielectric layer 242, and the gate 246 is located above the semiconductor layer. In this embodiment, after the step-like dielectric layer is removed, the dielectric layer 244 is formed on the semiconductor layer on which the doped regions have been formed. However, preferably, the stepped dielectric layer is directly formed on the semiconductor layer 242 and the stepped dielectric layer where the doped region is formed without removing, and the etching process can be omitted, and the dielectric process can be omitted. Cost of production. The present invention further proposes a method of forming the active device 24A including the following steps' sequentially shown in Figs. 6A to 6D. First, as shown in Fig. 6A, a semiconductor layer 242 is formed on the substrate 21A. Next, a substantially oblique-shaped photoresist layer 292 is formed to pattern the first dielectric layer 244, as shown in FIG. 6B, to form a substantially oblique ladder-shaped dielectric layer 244 on the semiconductor layer 242. Then, the sixth doping process D6 is performed. Since the dielectric layer 244 as a mask has a tapered shape, after the sixth doping process D6, the semiconductor@242 is used as a mask. The dielectric layer 244_, the semiconductor layer 242 is doped at a higher concentration. As shown in FIG. 6C, the lower semiconductor layer not covered by the inclined ladder dielectric layer 244 is formed, and after the sixth holding process D6, the first doping region is formed at the two ends of the semiconductor layer 242, 2421^, The semiconductor layer 242 covered by the thin dielectric layer 244 region is formed into a second doped region 242a2, 242t > 2 in the semiconductor layer 242 via the second doping process D6 of 200824128 Αυυουνι 28 22451 twf.doc/e. The concentration distribution of the two doped regions 242, 242b2 is distributed in a diagonal ladder shape. As shown in FIG. 6C, the second doped regions 242a2, 2421) 2 are first doped regions 242a2, 242b2 which are simultaneously formed and located at both ends of the adjacent semiconductor layer 242. In other embodiments, the second doped regions 242, 2421 can be selected to form only one of them. Thereafter, as shown in FIG. 6D, a dielectric layer 244 is formed over the semiconductor layer 242 on which the doped regions have been formed. Next, a gate 246 is formed over the dielectric layer 242, and the gate 246 is over the semiconductor layer 242. In this embodiment, after the oblique ladder dielectric layer is removed by an etching process, a dielectric layer 244 is formed on the semiconductor layer 242 on which the doped regions have been formed. Preferably, the oblique ladder-shaped dielectric layer is not removed, and the dielectric layer 244 is directly formed on the semiconductor layer 242 and the oblique-shaped dielectric layer on which the doped region has been formed, and the etching may be omitted. Process, while reducing production costs. The present invention further provides a method for forming the active device 240, which includes the following steps 2 and is sequentially shown in FIGS. 7A to 7D. First, as shown in Fig. 7A, a semiconductor layer 242 is formed on the substrate 210, and then a dielectric layer 244 is formed on the semiconductor layer 242. Thereafter, as shown in FIG. 7B, a photoresist layer 293 is formed on the dielectric layer 244, and the photoresist layer 293 has a thick region 293a and a thin region 293b. The method for forming the photoresist layer 293 is, for example, a half-tone photo-mask, a gray t-light photo-mask, and a grid pattern mask (slit_pattem ph〇t〇_ Mask), diffraction mask (diffraction photomask) - lithography process. Next, a seventh doping process is performed with the photoresist layer 293 as a mask. As shown, a first doping region, 200824128 AU0609128 22451 twf.doc/e 2421^ is formed at both ends of the semiconductor layer 242, and adjacent thereto The first doped regions 242ai, 242b at the two ends of the semiconductor layer 242 simultaneously form the second doped regions 242a2, 242b2. In other embodiments, the second doped regions 242az, 242bz may alternatively form only one of them. Thereafter, as shown in FIG. 7D, a gate 246 is formed over the dielectric layer 244, and the idle electrode 246 is over the semiconductor layer 242. It should be noted that, in the above embodiments of the present invention, there is no semiconductor layer under the lower layer electrode 230b, however, if necessary, it may be under

A semiconductor is present in the dielectric layer 244 under the layer electrode 230b for use as an auxiliary capacitor. Further, as shown in Fig. 8, the display panel 3A composed of the array arrangement of the halogen structures 2A described in the above embodiment can be combined with the electronic component 4 to form a photovoltaic device 500. The electronic component 4 includes, for example, a control component, an operation component, a processing component, an input component, a memory component, a driving component, a light emitting component, a sensing component, a sensor component, or other functions, a component, or the like combination. And optical devices such as mobile phones, cameras, cameras, notebook computers, game consoles, watches, music playback n, e-mail transceivers, map navigators or similar products =, audio and video products (such as Audio and video projectors or similar products), Rong screen, t, Kanban, panels in the projector, etc. In addition, the display panel includes a positive display panel and an organic electroluminescent display panel, depending on at least the material in the panel, such as: liquid crystal two; = light layer (eg, small molecule) , or a combination of the above, or the above-described composition of the present invention, the present invention has the following advantages: 1. One embodiment of the present invention is less than 20 200824128 AUU〇uyi28 22451twf.doc/e The shielding electrode of the halogen structure can reduce the influence of the data line on the voltage of the display halogen electrode when transmitting the signal, reduce the crosstalk effect, and improve the display quality. 2. In an embodiment of the present invention, since the shielding electrode greatly reduces the influence of the data line on the halogen electrode, the stray capacitance Cpd between the halogen electrode and the data line is negligibly small, so it is familiar with the technical field. In the design of the halogen structure, the technician can extend the element electrode above the data line without the limitation of the stray capacitance Cpd, so as to increase the aperture ratio of the pixel, thereby improving the display brightness of the liquid crystal display. 3. In one embodiment of the present invention, since the main storage capacitor is composed of a gold!=shading electrode, the first metal pattern is not used in the conventional process; and the +-body is stored in a capacitor, and the layer is doped at a high concentration. In the process of the process, the second structure of the pixel = map: and led to the drive of the domain. (10) 饤 掺杂 掺杂 脱离 脱离 脱离 脱离 掺杂 掺杂 掺杂 掺杂 掺杂 掺杂 掺杂 掺杂 掺杂 掺杂 掺杂 掺杂 掺杂 掺杂 掺杂 掺杂 掺杂 掺杂 掺杂 掺杂 掺杂 掺杂 掺杂 掺杂 掺杂 掺杂 掺杂 掺杂 掺杂 掺杂 掺杂 掺杂 掺杂 掺杂 掺杂 掺杂 掺杂 掺杂 掺杂 掺杂 掺杂 掺杂 掺杂 掺杂The present invention is in the form of a schematic diagram of the structure of the elementary structure of the embodiment. 200824128 AU0609128 22451twf.doc/e Figure 2B shows the cross-sectional view corresponding to the line of Fig. 2 in Fig. 2C. FIG. 3A to FIG. 3G are schematic diagrams showing the manufacturing method of the present invention. FIG. 4A to FIG. 4G are diagrams showing the method for manufacturing the stem-apricot structure of the present invention. Fig. 5D shows the other active components of the present invention: - shows the LTM meeting of another active component manufacturing method of the present invention. It is shown as a further method for fabricating an active device according to the present invention. The figure is a schematic representation of a photovoltaic device composed of a halogen structure of the present invention. [Main component symbol description] 100, 200: Alizarin structure 110, 210: Substrate 130, 230 : data line 140, 240 · active elements 142, 242: polysilicon layer 144: first gold Layers 150, 260: Alizardin electrode 160 · Flattening layer 22 200824128 AU0609128 22451twf.doc/e 220 : Scanning line 230a: Upper layer conductor 230b: Lower layer conductor 240: Active element 242: Semiconductor layer 242a · Source region 242b · No Polar regions 242ai, 242b: first doped regions 242a2, 242b2 · second doped region 242c: turn portion 244: first dielectric layer 246: gate 248: first patterned photoresist layer 249: second Dielectric layer 250: shielding electrode 252: extension portion 260: halogen electrode 270b: drain 280: protective layer 290: second patterned photoresist layer 291: stepped photoresist layer 292: oblique ladder photoresist layer 293: Photoresist layer 300 : display panel 23 200824128 AUUOUy 128 2245 ltwf.doc / e 400 : electronic component 500 : optoelectronic device m, H2, H3, H4, H5, H6: opening D1: first doping process D2: second doping Miscellaneous Process D3 · Third Doping Process D4: Fourth Doping Process D5: Fifth Doping Process D6: Sixth Doping Process D7: Seventh Doping Process I: Intrinsic Semiconductor E: Exotic Semiconductor 24

Claims (1)

200824128 Αϋ060912δ 2245Itwf.d〇c/e X. Application for patents: L A halogen structure is disposed on a substrate, including a scanning line disposed on the substrate; a data line disposed on the substrate The data line includes: an upper layer conductor disposed above the scan line and spanning the scan line, the lower layer conductor is electrically connected to the upper layer conductor; an active component disposed on the substrate, and the active component is electrically Connected to the scan line and the upper layer conductor; a shielding electrode disposed on the lower layer conductor; and a halogen electrode electrically connected to the active component, the pole being located on the shielding electrode, and a portion of the pixel level The shield electrode constitutes a - capacitor. ,, the crystal of the cover 2. As claimed in the scope of patents! In the halogen structure described in the item, the layer conductor overlaps with a portion of the upper layer conductor. /, ^ 3·If the towel please patent scope! The halogen structure described in the item, the dynamic element comprises a top gate type thin film transistor. , Ding to soil = the source region of the electrical connection and - with the painting 5. As described in the fourth paragraph of the patent application scope, the guide "has - connected to the source region and the" two 6 A halogen structure as described in claim 5, wherein the source 25 200824128 AU0609128 22451 twf.doc/e polar region, the shape of the transition portion and the drain region, including substantially L-shaped, substantial The U-shaped or substantially s-shaped. The magnetic structure as described in claim 5, wherein the turning portion comprises an intrinsic semiconductor and an extrinsic semiconductor. The pixel structure of the present invention, wherein the shielding electrode has a width greater than a width of the lower layer conductor. The pixel structure of claim 2, wherein the shielding electrode has a scan line and the data An extension extending in at least one of the directions of the line. 〇 — — 显示 显示 显示 显示 显示 显示 显示 显示 显示 显示 ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ Each of the shielding electrodes in the prime structure The electrical connection is connected to Φ 12. The display panel of claim 1 , wherein the active component comprises a top gate type thin film transistor, and the valley 13 is as claimed in claim 12 a display panel, the top gate type thin film transistor has a semiconductor layer, and the source region of the semiconductor thick connection and the pixel element are as described in claim 14 The halogen array, wherein each 26 200824128 Αϋϋ6ϋ9ΐ28 22451twf.doc/e, the source region, the shape of the turning portion and the drain region, including substantially L-shaped, substantially u-shaped or substantially s-shaped. The display panel of claim 6, wherein the width of each of the shielding electrodes is greater than or equal to the width of the lower layer of the conductor. The display panel of claim 16, wherein each of the shielding electrodes has An extension extending in at least one of the scan line and the data line. A method for manufacturing a pixel structure, comprising: forming an active component, a scan line, and a lower layer of conductor on a substrate to facilitate electrical connection of the active component to the scan line; forming an upper layer conductor and a shield An electrode, wherein the shielding electrode is located above the lower layer conductor, and the upper layer conductor is electrically connected to the active component; and a halogen electrode is electrically connected to the active component, wherein the pixel electrode is located above the shielding electrode And the halogen electrode and a portion of the concealing electrode form a storage capacitor. 19. The method of manufacturing a halogen structure as described in claim 18 of the patent scope further comprises forming a drain, wherein the halogen electrode is connected to the active element by the drain. 2. The method of fabricating a halogen structure according to claim 18, wherein the drain electrode, the shield electrode and the upper layer conductor are patterned by the same barrier layer. 21) The method for manufacturing a halogen structure according to the method of claim 18, wherein the method for forming the elemental structure of the active element comprises: 27 200824128 AU_y i28 22451twtdoc/e forming a semiconductor layer on the substrate; forming a dielectric layer On the substrate, and covering the semiconductor layer; the upper square is free on the dielectric layer' and the interpole is located at the semiconductor layer to form a first doped region at both ends of the semiconductor layer. The method of claim 21, wherein the method of forming the first doped region comprises: ### forming a patterned photoresist layer on the dielectric layer, and the patterned photoresist The layer exposes the semiconductor layer < _ # > /, row a first doping ^ Xinhai patterned photoresist layer for the mask method, m special, the manufacturing method of the halogen structure described in Item 22 a doped region in the semiconductor layer, the first doping 24 adjacent to the two ends of the semiconductor layer, such as the 23rd method of the 5th patent, the +, _ method, forming the second doping The method of the zone = the manufacturing equation of the 昼 昼 结构 structure. After the formation of the interpole, a second doping method is performed by using the idle mask, and the fabrication of the halogen structure described in Item 21 forms the doped region in the semiconductor sound. The photoresist layer of the gate is a mask 'row: the first doping is in the + conductor layer, and the second 28 200824128 Auuouy ι28 2245 ltwf.doc / e (10) in the semiconductor layer The method of forming the second doped region by the method of forming the second doped region of the first doped region is as follows: after the gate is formed, The method of forming the magnetic element as described in claim 18, wherein the method for forming the active element comprises: forming a semiconductor layer on the substrate; Forming a substantially stepped dielectric layer on the semiconductor layer; forming a doped region at both ends of the semiconductor layer; 9; and forming a second doped region in the semiconductor layer, and the Two of the first doped regions located adjacent to the two ends of the semiconductor layer And forming a gate on the dielectric layer, and the gate is located in the semiconductor layer. The method for forming the active device is as follows: a semiconductor layer on the substrate; forming a substantially oblique ladder-shaped dielectric layer on the semiconductor layer; forming a first doped region at both ends of the semiconductor layer; and forming a second doped region In the semiconductor layer, and the second portion of the first doped region adjacent to the two ends of the semiconductor layer is formed over 29 22451 twf.doc/e 200824128 iTLV^WV^X-28 a method of fabricating a semiconductor structure according to claim 18, wherein the method of forming the active device comprises: forming a semiconductor layer on the substrate Forming a dielectric layer on the semiconductor layer; forming a first doped region at both ends of the semiconductor layer; and forming a second doped region in the semiconductor layer, and the second doped region is adjacent The first of the two ends of the semiconductor layer One of the doped regions; formed on the upper side - difficult to be on the electrical layer, located in the semiconductor reed 3L, such as the cap patent Gu Di%, the method of forming the first doped seam of the second doped region The second light S' is on the dielectric layer, and the photoresist layer has a thickness-to-doping process using the photoresist layer as a mask. =· As in the case of the halogen structure described in item i of the patent scope, the material composition of the center V line is the same as that of the scanning line. β The board includes a plurality of the photoelectric device of the 32nd item of the patent scope, and the photoelectric device is included in the patent application.