200824117 〜005 19510twf.doc/006 九、發明說明： 【發明所屬之技術領域】 且特別是有關於一 本發明是有關於一種半導體元件 種防止閂鎖現象的半導體元件。 【先前技術】 半導體it件的設計，必須隨著日趨提高的積集度 jintegration)及日益複雜的需求而不斷改進。舉例而言， 高壓元件的設計必須使元件能夠容忍高電壓操作，而且不 會影響其他元件的操作。以下利用圖i來說明一種高壓元 件的問題及限制。 圖1是習知的一種高壓元件的剖面示帛圖。此高壓元 件疋一互補式金氧半場效電晶體（complementa^ metal o^xide semiconductor ’ CMOS ) ’其是由兩個橫向雙擴散金 氧半場效電晶體（lateral double-diffused metal oxide semiconductor，LDMOS)所構成。 Φ 請參照圖1，此高壓元件包括P型基底（p-sub) loo、 閘極102及104、閘介電層1〇6及ι〇8、p井（p_WELL) 112p、P 槽（P-TUB) 114p、摻雜區 ιΐ6ρ、ιΐ8ρ 及 I20p、 N 槽（N-TUB) 122η 及 124η、摻雜區 126η、128η 及 130η、 隔離結構134、介電層136、内連線（intereonnect) 138及 介電層140。其中，P型基底1〇〇可分為區域11¥1^]^〇8及 HVPMOS，分別包含高壓N型金氧半場效電晶體及高壓p 型金氧半場效電晶體。摻雜區126η、128η及閘極102分別 200824117 01-2005-005 19510twf.doc/006 是高壓N型金氧半場效電晶體源極、汲極及閘極，摻雜區 120p、118p及閘極104分別是高壓P型金氧半場效電晶體 的源極、汲極及閘極。摻雜區116p、ii8p及i20p是p+ 的傳導類型（conductivity type)，且摻雜區 126η、128η 及130η是η+的傳導類型。 圖1的高壓元件會有以下缺點： 1.此高壓元件會有閂鎖現象（latch_up)。更詳細而言，摻 雜區120P、N槽124η及P型基底100構成一個寄生的 雙載子電晶體的射極、基極及集極，摻雜區126η、ρ型 基底100及Ν槽124η構成另一個寄生的雙载子電晶體 的射極、基極及集極。當兩個雙載子電晶體的電流增益 乘積大於1時，此高壓元件將無法正常操作。 2·上述之高壓Ρ型金氧半場效電晶體及高壓ν型金氧半場 效電晶體是配置在Ρ型基底議上。由於施加在摻雜區 120Ρ，上的輸入電壓會直接施加於ρ型基底1〇〇，因此輪 =電壓將受雜大的關’進而減縮此高壓元件的 範圍。 ’、 3·、般而δ ’Ρ型基底1〇〇上更配置有其他的半導體元件。 然而此高壓元件兩侧沒有足夠的隔離結構 ,(lsolatlon),因此高壓元件會與這些半導體元件互 干擾。 今日 麻jfT知’由於任—半導體元件的操作均可能影響基 & 他半導體元件的操作，因此必須提供改善的方案。 7 200824117 υι-ζυυ3-ΰ〇5 19510twf.doc/006 【發明内容】 有鑑於此，本發明之目的是提供一種半導體元件，以 改善輸入電壓受限的問題，並避免與其他的半導體元件互 相干擾。 本發明之另一目的是提供一種互補式金氧半場效電 晶體’以改善問鎖現象。 為達上述或是其他目的，本發明提出一種半導體元 件’包括第一傳導類型（conductivity type )的基底、第一 磊晶層、第一下沈層（sinker)、第一埋入層（buriedlayer) 以及第二傳導類型的第二磊晶層、第二下沈層、第二埋入 層。第一磊晶層配置於基底上，且第二磊晶層配置於第一 磊晶層上。第一下沈層配置於第一磊晶層中及第二磊晶層 中’且自基底延伸至第二磊晶層上表面，並將第一磊晶層 及弟一蠢晶層分隔出第一區域。第二下沈層配置於第二遙 晶層中，且自第一磊晶層延伸至第二磊晶層上表面，並將 第一區域的第二磊晶層分隔出第二區域。主動元件配置於 第二區域内。第一埋入層配置於第一區域及基底之間，且 連接第一下沈層。第二埋入層配置於第二區域及第一磊晶 層之間，且連接第二下沈層。 在本發明之一實施例中，上述之第一埋入層的摻質濃 度例如是大於基底的摻質濃度。 ' 在本發明之一實施例中，上述之第二埋入層的摻質濃 度例如是大於第二磊晶層的摻質濃度。 在本發明之一實施例中，上述之主動元件例如是高壓 8 200824117 vi-^.w^-005 19510twf.doc/006 金氧半場效電晶體（high voltage metal oxide semiconductor，HVMOS )。 在本發明之一實施例中，上述之第一傳導類型是P 型，且第二傳導類型是N型。在本發明另一實施例中，上 述之第一傳導類型是N型，且第二傳導類型是P型。 為達上述或是其他目的，本發明再提供一種互補式金 氧半場效電晶體，包括基底、第一磊晶層、第二磊晶層、 第一下沈層、第二下沈層、第三下沈層、第四下沈層、井 區、第一電晶體、第二電晶體、第一埋入層、第二埋入層、 第三埋入層及第四埋入層。基底具有第一傳導類型。第一 磊晶層具有第一傳導類型，且配置於基底上。第二磊晶層 具有第二傳導類型，且配置於第一磊晶層上。第一下沈層 具有第一傳導類型，且配置於第一磊晶層中及第二磊晶層 中。第一下沈層自基底延伸至第二磊晶層上表面，且將第 一遙晶層及第二蠢晶層分隔出第一區域。第二下沈層具有 第二傳導類型，且配置於第二磊晶層中。第二下沈層自第 一磊晶層延伸至第二磊晶層上表面，且將第一區域的第二 磊晶層分隔出第二區域。第三下沈層具有第一傳導類型， 且配置於第一區域以外的第一磊晶層中及第二磊晶層中。 第三下沈層自基底延伸至第二磊晶層上表面，且將第一磊 晶層及第二磊晶層分隔出第三區域。第四下沈層具有第二 傳導類型，且配置於第二磊晶層中。第四下沈層自第一磊 晶層延伸至第二磊晶層上表面，且將第三區域的第二磊晶 層分隔出第四區域。井區具有第一傳導類型，且配置於第 9 19510twf.doc/006 200824117 —vw 005 二區域内。第一電晶體配置於井區内，且第二電晶體配置 於第四區域内。第一埋入層具有第一傳導類型，且配置於 弟一區域及基底之間。第一埋入層連接第一下沈層。第二 埋入層具有第二傳導類型，且配置於第二區域及第一磊晶 層之間。第二埋入層連接第二下沈層。第三埋入層具有第 一傳導類型，且配置於第三區域及基底之間。第三埋入層 連接第三下沈層。第四埋入層具有第二傳導類型，且配置200824117 〜005 19510twf.doc/006 IX. Description of the Invention: [Technical Field of the Invention] In particular, the present invention relates to a semiconductor element for preventing a latch-up phenomenon of a semiconductor element. [Prior Art] The design of semiconductor components must be continuously improved with increasing integration and increasingly complex requirements. For example, high voltage components must be designed so that they can tolerate high voltage operation without affecting the operation of other components. The problem and limitations of a high voltage component will be described below using Figure i. 1 is a cross-sectional view of a conventional high voltage component. The high voltage component is a complementary double-diffused metal oxide semiconductor (LDMOS). Composition. Φ Referring to Figure 1, the high-voltage component includes a P-substrate (p-sub) loo, gates 102 and 104, a gate dielectric layer 1〇6 and ι〇8, a p-well (p_WELL) 112p, and a P-groove (P- TUB) 114p, doped regions ιΐ6ρ, ιΐ8ρ and I20p, N-grooves (N-TUB) 122η and 124η, doped regions 126η, 128η and 130η, isolation structure 134, dielectric layer 136, intereonnect 138 and Dielectric layer 140. Among them, the P-type substrate 1〇〇 can be divided into regions 11¥1^^^8 and HVPMOS, which respectively comprise a high-voltage N-type gold-oxygen half-field effect transistor and a high-voltage p-type gold-oxygen half-field effect transistor. The doped regions 126η, 128η and the gate 102 are respectively 200824117 01-2005-005 19510twf.doc/006 are high-voltage N-type gold-oxygen half-field transistor source, drain and gate, doped regions 120p, 118p and gate 104 is the source, drain and gate of a high-voltage P-type gold-oxygen half-field effect transistor, respectively. The doped regions 116p, ii8p, and i20p are the conductivity type of p+, and the doped regions 126n, 128n, and 130n are the conductivity type of η+. The high voltage component of Figure 1 has the following disadvantages: 1. This high voltage component has a latching phenomenon (latch_up). In more detail, the doped region 120P, the N-well 124n, and the P-type substrate 100 constitute an emitter, a base, and a collector of a parasitic bipolar transistor, a doped region 126n, a p-type substrate 100, and a trench 124n The emitter, base and collector of another parasitic bipolar transistor are formed. When the current gain product of the two bipolar transistors is greater than 1, the high voltage component will not operate properly. 2. The above-mentioned high-pressure Ρ-type gold-oxygen half-field effect transistor and high-voltage ν-type gold-oxygen half-field effect transistor are arranged on the 基底 type substrate. Since the input voltage applied to the doped region 120 会 is directly applied to the p-type substrate 1 〇〇, the wheel = voltage will be subjected to a large off - and thus the range of the high voltage element is reduced. Further semiconductor elements are disposed on the Δ, λ, δ Ρ type substrate 1 。. However, there is not enough isolation structure on both sides of the high voltage component, so the high voltage component interferes with these semiconductor components. Today, the operation of semiconductor components may affect the operation of the semiconductor components, so an improved solution must be provided. 7 200824117 υι-ζυυ3-ΰ〇5 19510twf.doc/006 SUMMARY OF THE INVENTION In view of the above, it is an object of the present invention to provide a semiconductor device for improving the problem of limited input voltage and avoiding interference with other semiconductor elements. . Another object of the present invention is to provide a complementary MOS field effect transistor to improve the problem of the lock. To achieve the above or other objects, the present invention provides a semiconductor device 'including a first conductivity type substrate, a first epitaxial layer, a first sinker layer, and a first buried layer. And a second epitaxial layer, a second sinking layer, and a second buried layer of the second conductivity type. The first epitaxial layer is disposed on the substrate, and the second epitaxial layer is disposed on the first epitaxial layer. The first sinking layer is disposed in the first epitaxial layer and the second epitaxial layer and extends from the substrate to the upper surface of the second epitaxial layer, and separates the first epitaxial layer and the second staggered layer An area. The second sink layer is disposed in the second remote layer and extends from the first epitaxial layer to the upper surface of the second epitaxial layer and separates the second epitaxial layer of the first region from the second region. The active component is disposed in the second area. The first buried layer is disposed between the first region and the substrate and is connected to the first sink layer. The second buried layer is disposed between the second region and the first epitaxial layer and is connected to the second sink layer. In one embodiment of the invention, the dopant concentration of the first buried layer is, for example, greater than the dopant concentration of the substrate. In one embodiment of the invention, the dopant concentration of the second buried layer is, for example, greater than the dopant concentration of the second epitaxial layer. In an embodiment of the invention, the active component is, for example, a high voltage metal oxide semiconductor (HVMOS). In an embodiment of the invention, the first conductivity type is a P type and the second conductivity type is an N type. In another embodiment of the invention, the first conductivity type is N-type and the second conductivity type is P-type. To achieve the above or other objects, the present invention further provides a complementary MOS field effect transistor, comprising a substrate, a first epitaxial layer, a second epitaxial layer, a first sinking layer, a second sinking layer, a third sinking layer, a fourth sinking layer, a well region, a first transistor, a second transistor, a first buried layer, a second buried layer, a third buried layer, and a fourth buried layer. The substrate has a first conductivity type. The first epitaxial layer has a first conductivity type and is disposed on the substrate. The second epitaxial layer has a second conductivity type and is disposed on the first epitaxial layer. The first sinking layer has a first conductivity type and is disposed in the first epitaxial layer and in the second epitaxial layer. The first sinking layer extends from the substrate to the upper surface of the second epitaxial layer, and separates the first and second stray layers from the first region. The second sink layer has a second conductivity type and is disposed in the second epitaxial layer. The second sinking layer extends from the first epitaxial layer to the upper surface of the second epitaxial layer, and separates the second epitaxial layer of the first region from the second region. The third sink layer has a first conductivity type and is disposed in the first epitaxial layer and the second epitaxial layer outside the first region. The third sinking layer extends from the substrate to the upper surface of the second epitaxial layer, and separates the first epitaxial layer and the second epitaxial layer from the third region. The fourth sink layer has a second conductivity type and is disposed in the second epitaxial layer. The fourth sink layer extends from the first epitaxial layer to the upper surface of the second epitaxial layer, and separates the second epitaxial layer of the third region from the fourth region. The well zone has a first conductivity type and is disposed in the second region of 919010wf.doc/006 200824117-vw 005. The first transistor is disposed within the well region and the second transistor is disposed within the fourth region. The first buried layer has a first conductivity type and is disposed between the first region and the substrate. The first buried layer connects the first sinking layer. The second buried layer has a second conductivity type and is disposed between the second region and the first epitaxial layer. The second buried layer is connected to the second sinking layer. The third buried layer has a first conductivity type and is disposed between the third region and the substrate. The third buried layer is connected to the third sinking layer. The fourth buried layer has a second conductivity type and is configured
於第四區域及第一磊晶層之間。第四埋入層連接第四下沈 層0 在本發明之一實施例中，上述之第一埋入層及第三埋 入層的摻質濃度例如是大於基底的摻質濃度。 在本發明之一實施例中，上述之第二埋入層及第四埋 入層的摻質濃度例如是大於第二磊晶層的摻質濃度。 在本發明之-實施例中，上述之第一電晶體及第二電 晶體例如是高壓金氧半場效電晶體。 在本發明之一實施例中，上述之第一傳導類型是p 型，且第二傳導類型是_。在本發明另一實施例中，上 逑之第-傳導型，且第二傳導_是？型。 的本發料㈣免互補式金財場效電晶體 、、見象、增加半導體元件的輸入電壓的容，筘^。# 與基底上其他的半導體元件被有效地隔離的4乾圍。並 易懂之上述和其他目的、特徵和優點能更明顯 日L下 實施例，並配合所附圖式，作詳細說 200824117Between the fourth region and the first epitaxial layer. The fourth buried layer is connected to the fourth sinking layer 0. In one embodiment of the invention, the doping concentration of the first buried layer and the third buried layer is, for example, greater than the dopant concentration of the substrate. In an embodiment of the invention, the dopant concentration of the second buried layer and the fourth buried layer is greater than the dopant concentration of the second epitaxial layer, for example. In an embodiment of the invention, the first transistor and the second transistor are, for example, high voltage gold oxide half field effect transistors. In an embodiment of the invention, the first conductivity type is p-type and the second conductivity type is _. In another embodiment of the invention, the first conduction type of the upper jaw and the second conduction _ are? type. The present issue (4) is free of complementary gold field effect transistor, seeing, increasing the input voltage of the semiconductor component, 筘 ^. # 4 dry perimeters that are effectively isolated from other semiconductor components on the substrate. And the above-mentioned and other objects, features and advantages can be more clearly understood. The embodiment of the day and the accompanying drawings are described in detail. 200824117
Ul-2UU>-005 19510twfd〇c/〇〇6 【實施方式】 為了改善習知半導體元件的缺點，本發明是將半導體 元件置於基底上的磊晶層中。更詳細而言，磊晶層自美底 而上可以分為第一磊晶層及第二磊晶層。第一磊晶層：有 與基底相_料_ ’且第二蟲晶層具有與基底相反的 傳類型。第-蟲晶層及第二蠢晶層可以提供二極體的整 流功能’以防止载子注人基底。再者，由於基底的摻雜濃 度可以大於第-蟲晶層，且基底例如是接地（g_ded)， 因此基底提供了一個低阻抗的路徑’以將多餘的载子導 出如此，可以避免多餘的載子影響基底上其他的半導體 元件。 此外，在第二蠢晶層與第一蟲晶層之間，以及第一蠢 晶層與基底之間分麻置—層埋人層，且可以經由兩下沈 層來分別將兩層埋人層與外界電性連接。由於調整埋入層 ^電位可以避免轉體元件的輸人電壓全部施加於基底， ^匕可以增加半導體元件的操作範圍。此外，藉由埋入層 =置，可以改變寄生二極體或寄生電晶體的結構，所以 結構不會發生問鎖現象。以下湘第-及第二實施 例來詳細說明上述的結構。 【第一實施例】 圖2疋本發明帛一實施例的一種半導體元件的剖面示 I圖。 明麥照圖2 ’本發明的半導體元件包括基底2〇〇、第 200824117 01-2005-005 19510twf.doc/006 一蠢晶層201p、弟二层晶層2〇2n、第一下沈層204p、第 一埋入層206p、第二下沈層207n、第二埋入層2〇8n及主 動元件A1。在本實施例中，此半導體元件還包括隔離結構 210、介電層 212、井區 214p、内連線 234、236、238、239 及240,然而本發明並不限定於此。主動元件A1可以是任 何一種主動元件。主動元件A1例如是高壓金氧半場效電 晶體，包括橫向雙擴散金氧半場效電晶體。在本實施例中， _ 主動元件A1是以另一種高壓金氧半場效電晶體為例，主 動元件A1包括閘極220、閘介電層222、摻雜區226p、 228η、230η及232η。此外，如圖2所示，上述各構件的傳 導類型是以 P-sub、P-epi、N_epi、Ν、PBL、NBL、P_WELL、 η+ ρ+、N-drift專名稱來表示，以使於本領域具有通常知 識者易於瞭解，然而並非用以限定本發明。換言之，在另 一實施例中，上述各構件例如具有相反的傳導類型。另外， 在本實施例中，第一傳導類型是P型，而第二傳導類型是 N型。然而在另一實施例中，第一傳導類型是，而第 _ 二傳導類型是P型。 基底200具有第一傳導類型。第一磊晶層2〇lp具有 第一傳導類型，且配置於基底200上。基底2〇〇的摻質濃 度例如是大於第一磊晶層201P。若將基底200接地，則基 底200提供了一個低阻抗的路徑，使操作主動元件A1所 產生的多餘的载子得以被導出。如此，可以避免這些多餘 的载子影響基底200上其他的半導體元件。 第二磊晶層202η具有第二傳導類型，且配置於第一 12 200824117 Ul-^UUD-005 19510twf.doc/006 磊晶層201p上。第二磊晶層202n及第一遙晶層201p構成 一個二極體。在操作主動元件A1時，此二極體的整流功 能可以防止載子注入第一磊晶層201p及基底200。 第一下沈層204p具有第一傳導類型，且配置於第一 蠢晶層201p中及第二蠢晶層202η中。第一下沈層204p 自基底200延伸至第二磊晶層202η上表面，且將第一磊晶 層20 Ip及弟二蟲晶層202η分隔出第一區域pi。另外，内 連線239配置於介電層212中，且電性連接第一下沈層 204ρ。在本實施例中，第一下沈層204ρ例如是由埋入層 216ρ及井區218ρ所構成。埋入層216ρ自基底200延伸至 弟^一遙晶層202η ’而井區218ρ自埋入層216ρ延伸至第二 遙晶層202η上表面。 第二下沈層207η具有第二傳導類型，且配置於第二 磊晶層202η中。第二下沈層207η自第一磊晶層201ρ延伸 至第二磊晶層202η上表面，且將第一區域？丨的第二磊晶 層202η分隔出第二區域R1。另外，内連線240配置於介 電層212中，且電性連接第二下沈層207η。井區214ρ具 有第一傳導類型，且配置於第二區域R1内。主動元件Α1 配置於井區214ρ内。在此半導體元件的製程中，井區2ΐ4ρ 例如是與井區218ρ同時形成。主動元件A1的摻雜區226ρ 具有第一傳導類型，且摻雜區228η、230η及232η具有第 二傳導類型。其中，摻雜區228η、230η及232η分別是主 動元件Α1的源極、汲極及漂移區（把丘regi〇n)。摻雜區 228η及230η分別配置於閘極220兩侧的井區214p中，且 13 200824117 005 19510twf.doc/006 掺雜區230n配置於摻雜區232η中。另外，内連線234、 238及236配置於介電層212中，且分別電性連接摻雜區 230η、閘極220、摻雜區228η及226ρ。 第一埋入層206ρ具有第一傳導類型，且配置於第一 區域Ρ1及基底200之間。第一埋入層2〇6ρ連接第一下沈 層204ρ。第二埋入層208η具有第二傳導類型，且配置於 第二區域R1及第一蠢晶層201ρ之間。第二埋入層208η 連接第二下沈層207η。第一埋入層206ρ及第二埋入層208η 例如是重摻雜（heavily doped)的摻雜區。其中第一埋入 層206p的摻質濃度例如是大於基底200的摻質濃度，且第 二埋入層208η的摻質濃度例如大於第二磊晶層202η的摻 質濃度。由於設置有第一埋入層206ρ及第二埋入層208η， 主動元件Α1的輸入電壓不會全部施加於基底200,因此可 以增加此輸入電壓的容許範圍。舉例而言，若在内連線234 上施加高電壓，則第二埋入層208η可以避免第二磊晶層 202η及第一蠢晶層201ρ的介面發生電崩潰（breakdown)。 再者，當在内連線234上施加高電壓時，内連線240的電 位例如低於内連線234的電位，且高於内連線236的電位。 因此，上述的南電壓得以直接施加於内連線240，以進一 步避免第二蠢晶層202η及第一遙晶層201p的介面發生電 崩潰。另一方面，也可以調整内連線239的電位，以避免 上述的高電壓施加於基底200。因此，施加於内連線234 的電壓可以有更大的容許範圍。顯而易見的是，施加於内 連線236的電壓也可以有更大的容許範圍。因此，第一下 200824117 υι-ζυυ>〇〇5 I95l〇twf.d〇c/o〇6 沈層204ρ、第二下沈層207η、第一埋入層2〇όρ及第二埋 入層208η可以吸收多餘的載子，以避免施加於主動元件 Α1的電壓干擾基底200上其他的半導體元件。因此，主動 元件土 1的操作不會造成其他半導體元件的閂鎖現象。在 另一實施例中，經由調整内連線239及24〇的電位，更可 以避免其他的半導體元件的輸入電壓干擾主動元件A1的 運作。 上述的半導體元件可以避免發生閂鎖現象，以下利用 本發明的一種互補式金氧半場效電晶體來詳細說明。 【第二實施例】 圖3疋本發明第二實施例的一種互補式金氧半場效電 曰曰體的剖面示意圖。為簡化說明内容，以下僅說明與第一 實施例的不同處。 μ 睛參照圖3，此互補式金氧半場效電晶體包括第一電 晶體及第二電晶體Α2。在本實施例中，第一電晶體即是上 述之主動兀件Α1，其例如是高壓金氧半場效電晶體。第二 電晶體Α2例如也是高壓金氧半場效電晶體。然而本發明 ，不限於此，換言之，第一電晶體及第二電晶體Α2可以 疋任何一種金氧半場效電晶體。在本實施例中，此互補式 金氧半場效電晶體還包括内連線318、320、322、324、326 及328’配置於介電層212内。然而本發明並不限定於此。 此互補式金氧半場效電晶體更包括第三下沈層 301ρ、第三埋入層307ρ、第四下沈層3〇2η及第四埋入層 304η。第二下沈層3〇lp具有第一傳導類型，且配置於第一 15 200824117 ϋ1-2ϋυ^-005 19510twf.doc/006 區域Ρ1以外的第一磊晶層201ρ中及第二磊晶層202η中。 第三下沈層301ρ自基底200延伸至第二磊晶層202η上表 面，且將第一磊晶層201ρ及第二磊晶層202η分隔出第三 區域Ρ2。另外，内連線326電性連接第三下沈層301ρ。 在本實施例中，第三下沈層301ρ例如是由埋入層303ρ及 井區305ρ所構成。埋入層303ρ自基底200延伸至第二磊 晶層202η ’而井區305ρ自埋入層303ρ延伸至第二蠢晶層 202η上表面。 第四下沈層302η具有第二傳導類型，且配置於第二 遙晶層202η中。第四下沈層302η自第轰晶層201ρ延伸 至弟一蠢晶層202η上表面’且將第三區域Ρ2的第二蠢晶 層202η分隔出弟四區域R2。另外，内連線324電性連接 第四下沈層302η。第二電晶體Α2配置於第四區域R2内。 苐二電晶體Α2包括閘極306、閘介電層308、摻雜區310η、 312ρ、314ρ及316ρ。其中摻雜區312ρ、314ρ及316ρ分別 是苐二電晶體Α2的源極、汲極及漂移區。摻雜區3ι〇η具 有第二傳導類型，且摻雜區312p、314p及316p具有第一 傳導類型。摻雜區312p及摻雜區314p位於閘極3〇6兩側 的第二磊晶層202η内，且摻雜區314p位於摻雜區316p 内。在本實施例中，摻雜區316p更以P-drift來表示。此 外，内連線318、322及320分別電性連接摻雜區314p、 閘極306、摻雜區310η及312p。 第三埋入層307p具有第一傳導類型，且配置於第三 區域P1及基底200之間。第三埋入層3〇7p連接第三下沈 200824117 01-2005-005 19510twf.doc/006 層301p。此外，第四埋入層3〇4n具有第二傳導類型，且 配置於第四區域R2及第一磊晶層201ρ之間。第四埋入層 304η連接第四下沈層302η。因為設置了第一埋入層206ρ、 第一下沈層204ρ、第二埋入層20811、第二下沈層20711、 弟二埋入層307ρ、第三下沈層301ρ、第四埋入層30411及 第四下沈層302η，所以改變了由摻雜區312ρ、第二磊晶層 202η、第一磊晶層201ρ、基底200及摻雜區228η所構成 φ 的寄生二極體的結構，從而防止閂鎖現象。 另一方面，在此互補式金氧半場效電晶體的製程中， 第三埋入層307ρ例如是與第一埋入層206ρ同時形成，且 第四埋入層304η例如是與第二埋入層207η同時形成。由 上述可知，第一埋入層206ρ例如是重摻雜的摻雜區，且其 摻質濃度例如是大於基底200的摻質濃度。因此，在本實 施例中，第三埋入層307Ρ的摻質濃度大於基底2〇〇的摻質 濃度。同理，因為第二埋入層207η的摻質濃度例如是大於 第二磊晶層202η的摻質濃度，所以第四埋入層3〇4η的摻 _ 質濃度可以大於第二磊晶層202η的摻質濃度。此外，摻雜 區312ρ、第二區域Ρ2的第二遙晶層2〇2η及基底200分別 構成一個寄生的雙載子電晶體的射極、基極及集極，且摻 雜區228η、基底200及第三區域Ρ2的第二磊晶層2〇211分 別構成另一個寄生的雙載子電晶體的射極、基極及集極。 由於弟二埋入層307ρ及弟四埋入層3〇4η可以是重摻雜的 摻雜區，因此增加了上述基極的摻雜濃度，從而降低上述 的雙載子電晶體的電流增益。再者，經由調整内連線239、 17 200824117 υ iwv/j-005 19510twf.doc/006 324及326的電位，可以改變上述的電流增益，以進一步 避免閂鎖現象。 另一方面，施加於第二電晶體A2的電壓可以具有更 大的範圍。舉例而言，若在内連線320上施加高輸入電壓， 由於可以調整内連線324及326的電位，因此上述的輸入 電壓得以直接施加於内連線324及326，能夠避免此輸入 電壓直接施加於基底200，以進一步避免第二磊晶層202η 及第一蟲晶層201ρ的介面發生電崩潰。因此，施加於内連 線320上的電壓可以有更大的容許範圍。顯而易見的是， 施加於内連線318的電壓也可以有更大的容許範圍。除此 之外，因為設置了第三埋入層307ρ、第三下沈層301ρ、第 四埋入層304η及第四下沈層302η，第二電晶體Α2與基底 200上其他的半導體元件得以被有效地隔離。 另一方面，在本實施例中，此互補式金氧半場效電晶 體更包括一載子收集區（collector region) 330η。載子收集 區330η具有第二傳導類型。載子收集區330η例如是由埋 入層332η及隔離區334η所構成。其中埋入層332η例如是 配置於第一磊晶層201ρ及第二磊晶層202η之間，且隔離 區334η例如是自埋入層332η延伸至第二磊晶層202η上表 面。此外，在此互補式金氧半場效電晶體的製程中，埋入 層332η例如是與第四埋入層304η同時形成，且隔離區 334η例如是與第四下沈層3〇2η同時形成。另外，内連線 328電性連接隔離區334η。由於配置有載子收集區33〇η， 因此第一電晶體及第二電晶體Α2之間的多餘載子會被吸 18 200824117Ul-2UU>-005 19510twfd〇c/〇〇6 [Embodiment] In order to improve the disadvantages of the conventional semiconductor device, the present invention places the semiconductor element in an epitaxial layer on a substrate. In more detail, the epitaxial layer can be divided into a first epitaxial layer and a second epitaxial layer from the bottom. The first epitaxial layer has a type opposite to the substrate and the second layer has a type opposite to the substrate. The first-worm layer and the second stray layer can provide a rectifying function of the diode to prevent the carrier from being implanted into the substrate. Furthermore, since the doping concentration of the substrate can be greater than that of the first-crystal layer, and the substrate is, for example, grounded (g_ded), the substrate provides a low-impedance path to derive excess carriers so that excess loading can be avoided. The sub-effects affect other semiconductor components on the substrate. In addition, between the second stray layer and the first crystal layer, and between the first stray layer and the substrate, the layer is buried, and the two layers can be buried respectively through the two sink layers. The layer is electrically connected to the outside. Since adjusting the buried layer potential can prevent the input voltage of the rotating element from being entirely applied to the substrate, the operating range of the semiconductor element can be increased. In addition, by embedding the layer = set, the structure of the parasitic diode or the parasitic transistor can be changed, so that the structure does not suffer from the problem of the lock. The above structure will be described in detail below with reference to the second embodiment and the second embodiment. [First Embodiment] Fig. 2 is a cross-sectional view showing a semiconductor device of an embodiment of the present invention. Fig. 2 'The semiconductor device of the present invention comprises a substrate 2 〇〇, 200824117 01-2005-005 19510 twf. doc / 006 a stray layer 201p, a second layer 2 〇 2n, a first sink layer 204p The first buried layer 206p, the second sinker layer 207n, the second buried layer 2〇8n, and the active device A1. In the present embodiment, the semiconductor device further includes an isolation structure 210, a dielectric layer 212, a well region 214p, interconnect lines 234, 236, 238, 239, and 240, but the present invention is not limited thereto. The active component A1 can be any active component. The active device A1 is, for example, a high voltage MOS half field effect transistor including a lateral double diffused MOS field effect transistor. In the present embodiment, the active element A1 is exemplified by another high voltage MOSFET, and the active element A1 includes a gate 220, a gate dielectric layer 222, doped regions 226p, 228n, 230n and 232n. In addition, as shown in FIG. 2, the conductivity types of the above components are represented by P-sub, P-epi, N_epi, Ν, PBL, NBL, P_WELL, η+ ρ+, N-drift, etc., so that It is readily understood by those skilled in the art, but is not intended to limit the invention. In other words, in another embodiment, each of the above-described members has, for example, an opposite conductivity type. Further, in the present embodiment, the first conductivity type is a P type, and the second conductivity type is an N type. In yet another embodiment, the first conductivity type is, and the second conductivity type is P-type. Substrate 200 has a first conductivity type. The first epitaxial layer 2 〇 lp has a first conductivity type and is disposed on the substrate 200. The dopant concentration of the substrate 2 turns is, for example, greater than that of the first epitaxial layer 201P. If the substrate 200 is grounded, the substrate 200 provides a low impedance path for the excess carrier generated by the active device A1 to be derived. As such, these extra carriers can be prevented from affecting other semiconductor components on the substrate 200. The second epitaxial layer 202n has a second conductivity type and is disposed on the first 12 200824117 Ul-^UUD-005 19510 twf.doc/006 epitaxial layer 201p. The second epitaxial layer 202n and the first tele晶 layer 201p form a diode. When the active device A1 is operated, the rectifying function of the diode prevents the carrier from being injected into the first epitaxial layer 201p and the substrate 200. The first sinker layer 204p has a first conductivity type and is disposed in the first doped layer 201p and in the second doped layer 202n. The first sink layer 204p extends from the substrate 200 to the upper surface of the second epitaxial layer 202n, and separates the first epitaxial layer 20p and the second episode 202n from the first region pi. In addition, the interconnect 239 is disposed in the dielectric layer 212 and electrically connected to the first sink layer 204ρ. In the present embodiment, the first sinker layer 204p is composed of, for example, the buried layer 216p and the well region 218p. The buried layer 216p extends from the substrate 200 to the remote layer 202n' and the well region 218p extends from the buried layer 216p to the upper surface of the second remote layer 202n. The second sink layer 207n has a second conductivity type and is disposed in the second epitaxial layer 202n. The second sink layer 207η extends from the first epitaxial layer 201p to the upper surface of the second epitaxial layer 202n, and the first region is? The second epitaxial layer 202n of germanium separates the second region R1. In addition, the interconnect 240 is disposed in the dielectric layer 212 and electrically connected to the second sink layer 207n. The well region 214p has a first conductivity type and is disposed in the second region R1. The active component Α1 is disposed within the well region 214p. In the process of the semiconductor device, the well region 2ΐ4ρ is formed, for example, simultaneously with the well region 218p. The doped region 226p of the active device A1 has a first conductivity type, and the doped regions 228n, 230n, and 232n have a second conductivity type. The doped regions 228η, 230n, and 232n are the source, drain, and drift regions of the active device Α1, respectively. Doped regions 228n and 230n are respectively disposed in well regions 214p on both sides of gate 220, and 13 200824117 005 19510 twf.doc/006 doped regions 230n are disposed in doped regions 232n. In addition, the interconnects 234, 238, and 236 are disposed in the dielectric layer 212, and are electrically connected to the doped region 230n, the gate 220, and the doped regions 228n and 226p, respectively. The first buried layer 206p has a first conductivity type and is disposed between the first region Ρ1 and the substrate 200. The first buried layer 2〇6ρ connects the first sinker layer 204ρ. The second buried layer 208n has a second conductivity type and is disposed between the second region R1 and the first doped layer 201p. The second buried layer 208n connects the second sinker layer 207n. The first buried layer 206p and the second buried layer 208n are, for example, heavily doped doped regions. The dopant concentration of the first buried layer 206p is, for example, greater than the dopant concentration of the substrate 200, and the dopant concentration of the second buried layer 208n is, for example, greater than the dopant concentration of the second epitaxial layer 202n. Since the first buried layer 206p and the second buried layer 208n are provided, the input voltage of the active device Α1 is not all applied to the substrate 200, so the allowable range of the input voltage can be increased. For example, if a high voltage is applied to the interconnect 234, the second buried layer 208n can prevent electrical breakdown of the interface between the second epitaxial layer 202n and the first doped layer 201p. Moreover, when a high voltage is applied across the interconnect 234, the potential of the interconnect 240 is, for example, lower than the potential of the interconnect 234 and higher than the potential of the interconnect 236. Therefore, the above-mentioned south voltage can be directly applied to the interconnect 240 to further prevent electrical breakdown of the interface between the second doped layer 202n and the first crystal layer 201p. Alternatively, the potential of the interconnect 239 can be adjusted to prevent the above-described high voltage from being applied to the substrate 200. Therefore, the voltage applied to the interconnect 234 can have a larger allowable range. It will be apparent that the voltage applied to the interconnect 236 can also have a greater tolerance. Therefore, the first lower 200824117 υι-ζυυ>〇〇5 I95l〇twf.d〇c/o〇6 sinking layer 204ρ, the second sinking layer 207η, the first buried layer 2〇όρ and the second buried layer 208η Excess carriers can be absorbed to prevent voltages applied to the active device Α1 from interfering with other semiconductor components on the substrate 200. Therefore, the operation of the active component 1 does not cause latching of other semiconductor components. In another embodiment, by adjusting the potentials of the interconnects 239 and 24, it is possible to prevent the input voltage of other semiconductor components from interfering with the operation of the active device A1. The above-described semiconductor element can avoid the latch-up phenomenon, and will be described in detail below using a complementary MOS field effect transistor of the present invention. [Second Embodiment] Fig. 3 is a cross-sectional view showing a complementary metal oxide half field effect electric discharge body according to a second embodiment of the present invention. In order to simplify the description, only differences from the first embodiment will be described below. Referring to Fig. 3, the complementary MOS field effect transistor includes a first transistor and a second transistor Α2. In the present embodiment, the first transistor is the above-described active element Α 1, which is, for example, a high voltage MOS field effect transistor. The second transistor Α2 is, for example, also a high voltage MOS field effect transistor. However, the present invention is not limited thereto, in other words, the first transistor and the second transistor Α2 may be any type of MOS field effect transistor. In this embodiment, the complementary MOS field effect transistor further includes interconnect lines 318, 320, 322, 324, 326 and 328' disposed in the dielectric layer 212. However, the invention is not limited thereto. The complementary MOS field effect transistor further includes a third sink layer 301p, a third buried layer 307p, a fourth sink layer 3〇2η, and a fourth buried layer 304n. The second sinking layer 3 〇 lp has a first conductivity type, and is disposed in the first epitaxial layer 201ρ and the second epitaxial layer 202n except the region Ρ1ϋυ^-005 19510 twf.doc/006 in. The third sink layer 301p extends from the substrate 200 to the upper surface of the second epitaxial layer 202n, and separates the first epitaxial layer 201p and the second epitaxial layer 202n from the third region Ρ2. In addition, the interconnect 326 is electrically connected to the third sink layer 301ρ. In the present embodiment, the third sinker layer 301p is composed of, for example, a buried layer 303p and a well region 305p. The buried layer 303p extends from the substrate 200 to the second epitaxial layer 202n' and the well region 305p extends from the buried layer 303p to the upper surface of the second doped layer 202n. The fourth sink layer 302n has a second conductivity type and is disposed in the second spin layer 202n. The fourth sink layer 302n extends from the first crystal layer 201p to the upper surface of the second stella layer 202n and separates the second stray layer 202n of the third region Ρ2 from the fourth region R2. In addition, the interconnect 324 is electrically connected to the fourth sink layer 302n. The second transistor Α2 is disposed in the fourth region R2. The second transistor Α2 includes a gate 306, a gate dielectric layer 308, and doped regions 310n, 312ρ, 314ρ, and 316ρ. The doped regions 312ρ, 314ρ and 316ρ are the source, drain and drift regions of the second transistor Α2, respectively. The doped region 3m has a second conductivity type, and the doped regions 312p, 314p, and 316p have a first conductivity type. The doped region 312p and the doped region 314p are located in the second epitaxial layer 202n on both sides of the gate 3?6, and the doped region 314p is located in the doped region 316p. In the present embodiment, the doping region 316p is further represented by P-drift. In addition, the interconnects 318, 322, and 320 are electrically connected to the doped region 314p, the gate 306, and the doped regions 310n and 312p, respectively. The third buried layer 307p has a first conductivity type and is disposed between the third region P1 and the substrate 200. The third buried layer 3〇7p is connected to the third sinking. 200824117 01-2005-005 19510twf.doc/006 Layer 301p. Further, the fourth buried layer 3〇4n has a second conductivity type and is disposed between the fourth region R2 and the first epitaxial layer 201ρ. The fourth buried layer 304n connects the fourth sink layer 302n. Because the first buried layer 206p, the first sinker layer 204p, the second buried layer 20811, the second sinker layer 20711, the second buried layer 307p, the third sinker layer 301p, and the fourth buried layer are provided 30411 and the fourth sink layer 302n, so that the structure of the parasitic diode composed of the doped region 312p, the second epitaxial layer 202n, the first epitaxial layer 201p, the substrate 200, and the doped region 228n is changed. Thereby preventing latch-up. On the other hand, in the process of the complementary MOS field effect transistor, the third buried layer 307p is formed simultaneously with the first buried layer 206p, for example, and the fourth buried layer 304n is, for example, and the second buried layer. Layer 207η is formed simultaneously. As apparent from the above, the first buried layer 206p is, for example, a heavily doped doped region, and its dopant concentration is, for example, greater than the dopant concentration of the substrate 200. Therefore, in the present embodiment, the dopant concentration of the third buried layer 307 is greater than the dopant concentration of the substrate 2〇〇. Similarly, since the doping concentration of the second buried layer 207n is, for example, greater than the dopant concentration of the second epitaxial layer 202n, the doping concentration of the fourth buried layer 3〇4η may be greater than that of the second epitaxial layer 202n. The concentration of the dopant. In addition, the doped region 312ρ, the second remote layer 2〇2n of the second region Ρ2, and the substrate 200 respectively constitute an emitter, a base and a collector of a parasitic bipolar transistor, and the doped region 228η, the substrate The second epitaxial layer 2 211 of 200 and the third region Ρ2 respectively constitute an emitter, a base and a collector of another parasitic bipolar transistor. Since the second buried layer 307ρ and the fourth buried layer 3〇4η may be heavily doped doped regions, the doping concentration of the above-mentioned base is increased, thereby reducing the current gain of the above-described bipolar transistor. Furthermore, by adjusting the potentials of the interconnects 239, 17 200824117 υ iwv/j-005 19510twf.doc/006 324 and 326, the current gain described above can be varied to further avoid latch-up. On the other hand, the voltage applied to the second transistor A2 can have a larger range. For example, if a high input voltage is applied to the interconnect 320, since the potentials of the interconnects 324 and 326 can be adjusted, the above input voltage can be directly applied to the interconnects 324 and 326, thereby avoiding direct input voltage. It is applied to the substrate 200 to further prevent electrical collapse of the interface between the second epitaxial layer 202n and the first crystal layer 201p. Therefore, the voltage applied to the interconnect 320 can have a larger tolerance. It will be apparent that the voltage applied to interconnect 318 may also have a greater tolerance. In addition, since the third buried layer 307p, the third sinker layer 301p, the fourth buried layer 304n, and the fourth sinker layer 302n are disposed, the second transistor Α2 and other semiconductor elements on the substrate 200 can be Is effectively isolated. On the other hand, in the present embodiment, the complementary MOS field effect crystal further includes a carrier region 330n. The carrier collection region 330n has a second conductivity type. The carrier collection region 330n is composed of, for example, an buried layer 332n and an isolation region 334n. The buried layer 332n is disposed between the first epitaxial layer 201p and the second epitaxial layer 202n, for example, and the isolation region 334n extends from the buried layer 332n to the upper surface of the second epitaxial layer 202n, for example. Further, in the process of the complementary MOS field effect transistor, the buried layer 332n is formed, for example, simultaneously with the fourth buried layer 304n, and the isolation region 334n is formed, for example, simultaneously with the fourth sink layer 3?2?. In addition, the interconnect 328 is electrically connected to the isolation region 334n. Since the carrier collection region 33〇η is disposed, the excess carrier between the first transistor and the second transistor Α2 is sucked 18 200824117
Ol-2UU>-005 19510twf.doc/006 收’ l確保此互補式金氧半場效電晶體可以正常運作。 综上所述，本發明可以避免互補式金氧半場效電晶體 的問鎖現象、增加半導體元件的輸入電壓的容許範圍。並 /、基底上其他的半導體元件被有效地隔離。此外，因為下 沈層佔用基底的可用面積的極小部分，且埋入層是位於主 動元件之下，所以能夠符合高積集度的要求。 —雖然本發明已以較佳實施例揭露如上，然其並非用以 φ 限^本發明，任何熟習此技藝者，在不脫離本發明之精神 ^範圍内，當可作些許之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1是習知的一種高壓元件的剖面示意圖。 圖2是本發明第一實施例的一種半導體元件的剖面示 意圖。 圖3是本發明第二實施例的一種互補式金氧半場效電 # 晶體的剖面示意圖。 【主要元件符號說明】 100 ·· P型基底 102、104、220、306 :閘極 106、108、222、308 :閘介電層 112p : P 井 114p : p槽 !16ρ、ΐΐ8ρ、Ι20ρ、126η、128η、130η、226ρ、228η、 19 200824117Ol-2UU>-005 19510twf.doc/006 Accepts l to ensure that this complementary metal oxide half field effect transistor can operate normally. In summary, the present invention can avoid the problem of the lock-up of the complementary MOS field-effect transistor and increase the allowable range of the input voltage of the semiconductor device. And /, other semiconductor components on the substrate are effectively isolated. In addition, since the sinking layer occupies a very small portion of the usable area of the substrate, and the buried layer is located under the active element, it is possible to meet the requirement of high integration. </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; Therefore, the scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view of a conventional high voltage component. Fig. 2 is a cross-sectional view showing a semiconductor device of a first embodiment of the present invention. 3 is a schematic cross-sectional view showing a complementary MOS field FET # crystal according to a second embodiment of the present invention. [Description of main component symbols] 100 · P-type substrate 102, 104, 220, 306: gate 106, 108, 222, 308: gate dielectric layer 112p: P well 114p: p-groove! 16ρ, ΐΐ8ρ, Ι20ρ, 126η , 128η, 130η, 226ρ, 228η, 19 200824117
Ul-2UU^-005 19510twf.doc/006 322 > 230η、232η、310η、312ρ、314ρ、316ρ :摻雜區 122η、124η : Ν 槽 134、210 :隔離結構 136、140、212 :介電層 138、234、236、238、239、240、318、320 324、326、328 :内連線 200 :基底 201ρ :第一磊晶層 胃 202η :第二磊晶層 ( 204ρ:第一下沈層 206ρ :第一埋入層 207η :第二下沈層 208η :第二埋入層 214ρ、218ρ、305ρ :井區 216ρ、303ρ、332η :埋入層 301ρ :第三下沈層 _ 302η :第四下沈層 304η :第四埋入層 307ρ :第三埋入層 330η :載子收集區 3 3 4n ·隔離區 A1 :主動元件 A2 :第二電晶體 HVNMOS、HVPMOS :區域 20 200824117Ul-2UU^-005 19510twf.doc/006 322 > 230η, 232η, 310η, 312ρ, 314ρ, 316ρ: doped regions 122n, 124n: Ν grooves 134, 210: isolation structures 136, 140, 212: dielectric layer 138, 234, 236, 238, 239, 240, 318, 320 324, 326, 328: interconnect 200: substrate 201ρ: first epitaxial layer stomach 202n: second epitaxial layer (204p: first sinking layer 206ρ: first buried layer 207n: second sinking layer 208n: second buried layer 214ρ, 218ρ, 305ρ: well region 216ρ, 303ρ, 332η: buried layer 301ρ: third sinking layer _ 302η: fourth Sinking layer 304η: fourth buried layer 307ρ: third buried layer 330n: carrier collection region 3 3 4n · isolation region A1: active device A2: second transistor HVNMOS, HVPMOS: region 20 200824117
Ul-2UU^-005 19510twf.doc/006 PI :第一區域 R1 :第二區域 P2 :第三區域 R2 :第四區域Ul-2UU^-005 19510twf.doc/006 PI: first area R1: second area P2: third area R2: fourth area