200810089 九、發明說明: 【發明所屬之技術領域】 本發明係關於一種垂直電晶體製作方法，尤其是指一 種關於汲極深度較閘極凹槽深度深，源極深度又較閘極凹 槽深度淺的垂直電晶體之製作方法。 【先前技術】 9 隨著電子產品日益朝向輕、薄、短、小發展.，動態隨機 存取記憶體(Dynamic Random Access Memory, DRAM)元件 的設計也必須符合高積集度、高密度之要求朝小型化發展 之趨勢發展。由於傳統水平式(planar)溝渠電容(trench capacitor)動態隨機存取記憶體之電晶體之源極(s〇urce)、閘 極(gate)與汲極(drain)係呈水平式地置放製作於基底表面 上，使得傳統水平式溝渠電容動態隨機存取記憶體之電晶 _ 體較佔晶片面積，在提昇半導體元件之積集度時會有所限 制。因此目前業界多使用垂直電晶體(verticd transist〇r)結 構應用於溝渠電容動態隨機存取記憶體中。 一般來說，垂直電晶體溝渠電容動態隨機存取記憶體結 構的製作方式，通常是先在半導體基材巾㈣出深溝渠 (deep trench)，並在深溝渠内形成電容結構，接著再於溝渠 •電容旁製作垂直電晶體，將及極、閑極與源極垂直置放， 以大巾田降低電晶體的橫向單位面積，增加半導體元件的積集度。 5 200810089 然而，在垂直電晶體溝渠電容動態隨機存取記憶體中， 閘極通道(channel)的長度(length)和寬度(width)係為影響該 垂直電晶體效能的重要因素’閘極通道的長度決定了由源 極通往祕之電子路徑長短，閘極通道的寬制關係到由 源極通往祕之電子數量，因此如果㈣縮短垂直電晶體 溝渠電容動態賴麵記憶體切極料的長度，則能夠 =降低電晶體漏電的情況’進而有效提升垂直電晶^溝 渠電容動態隨機存取記憶體的效能。所以如何製作 2晶體溝渠電容動態隨機存取記憶體具有降低電晶體漏 電的功能者，實為目前業界的課題。 ' 【發明内容】 解決上述習 本發明係提供-種垂直電晶體製作方法， 知技術之問題。 本發明之一較佳實施例係提供一種垂 構，其包含有閘極堆疊結槿 日日體的、、-口 佈植區位於閘極堆疊結構 /基底中’―個第一離子 於間極堆疊結構不同於第m ――離子佈植區位 離子佈植區位㈣基底之深的另―側’且第一 底之深度深。 乂弟—離子佈植區位於石夕基 種垂直電晶體的製 本發明之另-擁實_係提供_ 200810089 作方法，其製程是先形成閘極堆疊結構於矽基底中，再利 用遮罩進行弟一離子佈植形成没極於閘極堆疊結構之一 側，並使汲極位於矽基底之深度較閘極堆疊結構位於矽基 底之沬度沬，接著再利用遮罩進行第二離子佈植形成源極 於閘極堆疊結構不同於汲極之—侧，並使源極位於石夕基底 之深度較閘極堆疊結構位於石夕基底之深度淺。 由於本發明垂直電晶體之汲極的深度較閘極凹槽深， 且源極深度又較閘極凹槽淺，相較於寳知技術中汲極和源 極的深度都較閘極凹槽短的情況，本發明的閘極通道長度 車乂驾知技術短，而較長的閘極通道可有效防止動態隨機存 取記憶體之電晶體發生漏電的情況。而且，在習知技術中， 因為汲極和源極皆比閘極凹槽淺，所以由源極通往汲極的 電子流通路徑是水平的，但是，本發明之汲極較閘極凹槽 冰’源極又較閘極凹槽淺，所以本發明中由源極通往汲極 的電子流通路徑是垂直的。 【實施方式】 睛參考第1至4圖，第1至4圖係為本發明之垂直電 曰曰體製程不意圖。請參考第1圖，本發明之方法可應用在 動悲隨機存取記憶體之記憶單胞(mem〇ry cell)之電晶體製 私中而動態隨機存取記憶體之記憶陣列（memory array) 區域ίο係设置於一石夕基底，例如一半導體晶圓（wafer) 7 200810089 二絕緣剛基底。本發明之方法絲於記憶陣列區 5 *成所需之溝渠電容(treneheapadt。!·）（未顯示）， 此為通常知識者所熟知，故在此不多加贅述。接著利用一 硬遮罩（未顯不）^；義出閘極凹槽㈣e π⑽⑽的位置並 以敍刻製_成閘細槽16，接著去除硬鮮（未顯示）， 並進仃-凊洗製程以及—起始電壓㈤調整製程，狹後再 =熱氧化製程於祕凹槽16㈣基底12上形成閑極絕 、、曰14。隨後於閘極凹槽16中填入多晶矽（未顯示），並 於：基底12上方沈積-層多晶矽層（未顯示)，接著在利 囷案化遮罩疋義出閘極堆疊（gate stack)結構22位置之 ，’㈣去除多餘的多⑽層（未顯示），以使_剩餘的 夕晶石夕層和閘極凹槽16中的多晶㈣成閘極堆疊結構 22，如第2圖所示。 、、晴參考第3圖’ 遮罩32定義出 >及極34的位置， 並進行―離〜子佈植以形纽極34。請繼續參考第4圖，利 用遮罩42定義出源極44的位置並進行離子佈植，以形成 \ 4即疋成動態隨機存取記憶體之記憶陣列區域1〇 ^電"體值得注意的是，本發明所製作汲極34的深 = 和閘極凹槽16的深度深，其係利用不同的離 ^佈植犯里來分別形成汲極34和源極44，使得汲極34的 J ]極凹槽16的深度深，但是源極44的深度卻較閘 °凹槽16的味度淺的結構。又，由於汲極34深度較閘極 8 200810089 凹槽16深，源極44深度較閘極凹槽16淺，所以本發明中 電晶體的電流導通路徑是垂直的，不同於習知技術中水平 的電流導通路徑。再者，由於本發明之没極34和源極44 係利用兩不同之離子佈植步驟加以形成，因此没極34和源 極44的製程順序、離子劑量或掺質叩㈣種類等，皆可 視產品需求及功能考量來適當地進行調整。 如上所述，本發明之方法係應用在記憶單胞(mem〇ry celi)之電晶體製程中’此外，本發明之方法也可以應用在 内嵌式記憶體(embedded DRAM)製程中，以有效整合邏輯 區域和記憶陣列區域之電晶體製程。請參考第5至9圖， 第5至9圖係為本發明製作垂直電晶體於動態隨機存取記 憶體之製程示意圖。如第5圖所示，動態隨機存取記憶體 的記憶陣列區域50係設置於一矽基底52，例如一半導體 晶圓（waf^r)或一矽覆絕緣(s〇I)基底。首先，於記憶陣列區 域5〇中形成所需之溝渠電容(trench capacitor)(未顯示）， 此亦為習知相關技藝者所熟知，故在此不多加贅述。接著 利用一個圖案化遮罩層，例如一已經圖案化的氧化層54， 於圮憶陣列區域50中定義出閘極凹槽57，並以氧化層54 作為蝕刻製程的硬遮罩來蝕刻矽基底52，形成閘極凹槽 57。然後進行一清洗製程以及一起始電壓(Vth)調整製程， 並進行一熱氧化製程形成閘極絕緣層56於閘極凹槽57 中，接著再於閘極凹槽57中填入多晶矽（未顯示），並經 9 200810089 過化學機械研磨（Chemical Machine Polishing，CMP)和回餘 刻製程形成多晶矽層58。隨後再沈積一氧化矽層或氮化石夕 層（未顯示）於多晶矽層58、閘極凹槽57和氧化層54上， 並回钱刻（etch back)該氧化矽層或氮化矽層（未顯示）形成 侧壁子（spacer)62，最後再沈積多晶矽（未顯示）並施以化 本機械研磨製程以形成多晶砍層64，如第6圖所示。值得 注意的是，侧壁子62對於後續製作閘極導線(gate conductor) ❿ 的自對準(alignment)製程有幫助，可有效增加製程範疇 (process window) 〇 接著’在矽基底52之邏輯(logic)區域（未顯示）表面 形成閘極絕緣層（未顯示），並在邏輯區域（未顯示）和記 憶陣列區域50上沈積一層多晶矽層72，如第7圖所示。 之後再利用一圖案化遮罩（未顯示）分別定義出邏輯區域 Φ (未顯不）之閘極（未顯示）和記憶陣列區域50之多晶矽 層81的位置並加以餘刻，形成邏輯區域的閘極（未顯示） 和記憶陣列區域50的多晶矽層81，而多晶矽層58、64、 81則形成閘極堆疊結構82，如第8圖所示。然後再以遮罩 84疋義出§己憶陣列區域5〇中之垂直電晶體之汲極％的位 置’並進行離子佈植以形成汲極86。請繼續參考第9圖， 最後利用遮罩92同時定義出記憶陣列區域50中之垂直電 -晶體之源極94與邏輯區域（未顯示）中之電晶體之源極/ •汲極（未顯不）的位置並進行離子佈植，以形成源極94(以 200810089 及邏輯區域中之電晶體的雜級極），即完成動紐機存取 記憶體之垂直電晶體。當然，在本較佳實施例中亦利用不 同的離子佈植能量來形成汲極86和源極94，使得汲極86 的深度亦較閘極凹槽57的深度深，而源極94的深度較閘 極凹槽57的深度淺。此外，由於本發明之垂直電晶體的汲 極86和源極94係利用兩次不同之離子佈植步驟加以形 成，因此汲極86和源極94的製程順序、離子劑量或掺質 種&員專’皆可視產品需求及功能考量來適當地進行調整， 而且邏輯區域中之電晶體的源極/汲極亦可再利用另一單 獨之遮罩與離子佈植加以形成。 值得一提的是此較佳實施例亦可應用於棋盤式深溝渠 電容動態隨機存取記憶體(checkerboard trench DRAM)中， 請參考第10圖，第10圖係為棋盤式深溝渠電容動態隨機 存取記憶體之結構示意圖。深溝渠電容動態隨機存取記憶 體100即是各個深溝渠電容102和電晶體108呈現如西洋 棋棋盤狀的交錯排列，一個電晶體108配一個深溝渠電容 102，而主動區域(active area，A A) 104和閘極導線(gate conductor，GC) 106則是相互垂直且交錯於深溝渠電容 和電晶體108的位置。因此只要適當地修改光罩的佈局 (layout)圖案，本發明第5圖至第9圖所述之最佳實施例之 垂直電晶體結構，即可應用在第10圖之棋盤式深溝渠電容 動態隨機存取記憶體1〇〇之電晶體108結構中。 200810089 由於在本發明之垂直電晶體中，汲極的深度較閘極凹 样深，日、店 曰 線極深度又較閘極凹槽淺，故相較於習知技術中 汲極和源極的深度都較閘極凹槽短，而且，在習知技術中， 因為汲極和源極皆比閘極凹槽淺，所以由源極通往汲極的 電子机通路徑是水平的，但是本發明之汲極較閘極凹槽 罙源極又#父閘極凹槽淺，所以本發明中由源極通往汲極 的電子流通路徑是垂直的。又，本發明可藉由垂直電晶體 中侧壁子的製作，幫助閘極導線自對準製程的進行，增加 製程範疇。另外，本發明更可同時製作邏輯區域和記憶陣 列區域的閘極，簡化並整合製程步驟。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範 圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。200810089 IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD The present invention relates to a method for fabricating a vertical transistor, and more particularly to a method in which the depth of the drain is deeper than the depth of the gate, and the depth of the source is deeper than the depth of the gate. A method of making a shallow vertical transistor. [Prior Art] 9 As electronic products become increasingly light, thin, short, and small, the design of dynamic random access memory (DRAM) components must meet the requirements of high integration and high density. Development towards miniaturization. The source (s〇urce), gate (gate) and drain of the transistor of the conventional planar capacitor dynamic random access memory are horizontally placed. On the surface of the substrate, the crystal cell of the conventional horizontal trench capacitor dynamic random access memory is more limited than the wafer area, which is limited when the semiconductor element is increased. Therefore, in the industry, the vertical transistor (verticd transist〇r) structure is often used in the trench capacitor dynamic random access memory. In general, the vertical transistor trench capacitor dynamic random access memory structure is usually fabricated by first making a deep trench in the semiconductor substrate (4) and forming a capacitor structure in the deep trench, followed by a trench. • A vertical transistor is fabricated next to the capacitor, and the pole and the idle pole are placed perpendicular to the source, and the lateral unit area of the transistor is reduced by the large towel field to increase the integration of the semiconductor components. 5 200810089 However, in vertical transistor trench dynamic memory random access memory, the length and width of the gate channel are important factors affecting the performance of the vertical transistor. The length determines the length of the electronic path from the source to the secret. The width of the gate channel is related to the number of electrons from the source to the secret, so if (4) shorten the vertical transistor trench capacitance dynamic surface memory body cutting material The length can reduce the leakage of the transistor', which effectively improves the performance of the vertical galvanic capacitor dynamic random access memory. Therefore, how to make a 2-crystal trench capacitor dynamic random access memory has the function of reducing the leakage of the transistor, which is a problem in the industry. SUMMARY OF THE INVENTION The above conventional invention is provided to provide a method for fabricating a vertical transistor, which is a problem of the prior art. A preferred embodiment of the present invention provides a vertical structure comprising a gate stacking crucible, and the -port implanting region is located in the gate stack structure/substrate 'a first ion to the interpole The stacking structure is different from the m-th ion implantation site ion implantation site (4) the other side of the base depth and the depth of the first bottom is deep. The younger brother-ion implanting area is located in the Shihji-type vertical transistor. The invention is based on the method of 200810089. The process is to first form a gate stack structure in the germanium substrate, and then use a mask. The ion-ion implant forms no side on one side of the gate stack structure, and the depth of the drain is located at the base of the crucible is greater than the thickness of the gate stack structure at the base of the crucible, and then the second ion implant is performed by using the mask. The source is formed on the side of the gate stack structure different from the drain side, and the depth of the source is located at the base of the Shixia base is shallower than the depth of the gate stack structure at the base of the Shixi base. Since the depth of the drain of the vertical transistor of the present invention is deeper than that of the gate trench, and the source depth is shallower than that of the gate trench, the depth of the drain and the source is lower than that of the gate trench in the Baozhi technology. In the short case, the gate channel length of the present invention is short, and the longer gate channel can effectively prevent the leakage of the transistor of the dynamic random access memory. Moreover, in the prior art, since both the drain and the source are shallower than the gate recess, the electron flow path from the source to the drain is horizontal, but the buckle of the present invention is more than the gate recess The 'source' of the ice is shallower than the gate groove, so the electron flow path from the source to the drain in the present invention is vertical. [Embodiment] The drawings refer to Figs. 1 to 4, and Figs. 1 to 4 are schematic diagrams of the vertical electromechanical system of the present invention. Referring to FIG. 1, the method of the present invention can be applied to a memory array of a memory cell of a memory cell of a singular random access memory (memory) and a memory array of a dynamic random access memory. The area ίο is disposed on a stone base, such as a semiconductor wafer (wafer) 7 200810089 two insulated rigid substrates. The method of the present invention is applied to the memory array region 5* into the desired trench capacitance (treneheapadt.!) (not shown), which is well known to those skilled in the art and will not be described here. Then use a hard mask (not shown) ^; the position of the gate groove (four) e π (10) (10) and the etched sluice 16 , then remove the hard fresh (not shown), and enter the 仃 - wash process And - the starting voltage (five) adjustment process, and then the = thermal oxidation process on the secret groove 16 (four) substrate 12 to form a free pole, 曰 14. Then, a polysilicon (not shown) is filled in the gate recess 16 and a polysilicon layer (not shown) is deposited on the substrate 12, and then the gate stack is formed in the mask. At the location of structure 22, '(iv) removes excess (10) layers (not shown) such that the remaining polycrystalline (tetra) in the etched layer and the gate recess 16 form a gate stack structure 22, as shown in FIG. Shown. Referring to Figure 3, the mask 32 defines the position of the > and the pole 34, and performs a "off-to-sub-plant" to form the button 34. Please continue to refer to FIG. 4, using the mask 42 to define the position of the source 44 and performing ion implantation to form a memory array region of the dynamic random access memory (1). The depth of the drain 34 and the depth of the gate recess 16 made by the present invention are deep, and the drains 34 and the source 44 are respectively formed by different implants, so that the drain 34 is J] The depth of the pole groove 16 is deep, but the depth of the source 44 is shallower than that of the gate groove 16. Moreover, since the depth of the drain 34 is deeper than the recess 16 of the gate 8 200810089, and the depth of the source 44 is shallower than that of the gate recess 16 , the current conduction path of the transistor in the present invention is vertical, which is different from the level of the prior art. Current conduction path. Furthermore, since the dipole 34 and the source 44 of the present invention are formed by two different ion implantation steps, the process sequence, the ion dose or the dopant type (four) of the dipole 34 and the source 44 are all visible. Product requirements and functional considerations are adjusted appropriately. As described above, the method of the present invention is applied to a memory cell process of memory cells (in addition, the method of the present invention can also be applied to an embedded DRAM process to be effective. A transistor process that integrates logic regions and memory array regions. Please refer to Figures 5 to 9, and Figures 5 to 9 are schematic views showing the process of fabricating a vertical transistor in a dynamic random access memory. As shown in Fig. 5, the memory array region 50 of the DRAM is disposed on a substrate 52, such as a semiconductor wafer or a silicon-on-insulator (s?I) substrate. First, the required trench capacitors (not shown) are formed in the memory array region 5, which are well known to those skilled in the art and will not be described here. A gate mask 57 is then defined in the memory array region 50 by a patterned mask layer, such as an patterned oxide layer 54, and the germanium substrate is etched with the oxide layer 54 as a hard mask for the etch process. 52, forming a gate recess 57. Then, a cleaning process and a starting voltage (Vth) adjustment process are performed, and a thermal oxidation process is performed to form the gate insulating layer 56 in the gate recess 57, and then the gate recess 57 is filled with polysilicon (not shown). The polycrystalline germanium layer 58 is formed by a chemical mechanical polishing (CMP) and a back-cut process by 9 200810089. Subsequently, a hafnium oxide layer or a nitride layer (not shown) is deposited on the polysilicon layer 58, the gate recess 57 and the oxide layer 54, and the tantalum oxide layer or the tantalum nitride layer is etched back ( Not shown) a spacer 62 is formed, and finally polycrystalline germanium (not shown) is deposited and subjected to a mechanical polishing process to form a polycrystalline chopped layer 64, as shown in FIG. It is worth noting that the sidewalls 62 are useful for the subsequent fabrication of the gate conductor ❿ alignment process, which effectively increases the process window and then the logic at the 矽 substrate 52 ( A logic region (not shown) surface is formed with a gate insulating layer (not shown), and a polysilicon layer 72 is deposited on the logic regions (not shown) and the memory array region 50, as shown in FIG. Then, a patterned mask (not shown) is used to define the positions of the gates (not shown) of the logic region Φ (not shown) and the polysilicon layer 81 of the memory array region 50, respectively, and to form a logic region. A gate (not shown) and a polysilicon layer 81 of the memory array region 50, and a polysilicon layer 58, 64, 81 form a gate stack 82, as shown in FIG. Then, the position of the drain % of the vertical transistor in the array region 5 ’ is rewritten by the mask 84 and ion implantation is performed to form the drain electrode 86. Please continue to refer to Figure 9, and finally use the mask 92 to simultaneously define the source of the vertical electro-crystal in the memory array region 50 and the source of the transistor in the logic region (not shown) / The position is not and ion implantation is performed to form the source 94 (to 200810089 and the heteropolar pole of the transistor in the logic region), that is, to complete the vertical transistor of the memory access memory. Of course, different ion implantation energy is also used in the preferred embodiment to form the drain 86 and the source 94 such that the depth of the drain 86 is also deeper than the depth of the gate recess 57, while the depth of the source 94 is deep. It is shallower than the depth of the gate groove 57. In addition, since the drain 86 and source 94 of the vertical transistor of the present invention are formed using two different ion implantation steps, the process sequence, ion dose or dopant species & The “specialist” can be appropriately adjusted according to product requirements and functional considerations, and the source/drain of the transistor in the logic region can be formed by using another separate mask and ion implant. It is worth mentioning that the preferred embodiment can also be applied to a checkerboard trench DRAM. Please refer to FIG. 10, which is a checkerboard deep trench capacitor dynamic random. A schematic diagram of the structure of the access memory. The deep trench capacitor dynamic random access memory 100 means that each deep trench capacitor 102 and the transistor 108 are arranged in a staggered arrangement like a chessboard, a transistor 108 is provided with a deep trench capacitor 102, and an active area (AA) 104 and a gate conductor (GC) 106 are perpendicular to each other and staggered to the location of the deep trench capacitor and transistor 108. Therefore, as long as the layout pattern of the reticle is appropriately modified, the vertical transistor structure of the preferred embodiment described in the fifth to ninth embodiments of the present invention can be applied to the dynamic dynamics of the checkerboard deep trench in FIG. The random access memory is in the structure of the transistor 108. 200810089 In the vertical transistor of the present invention, the depth of the drain is deeper than that of the gate, and the depth of the day and the shop line is shallower than that of the gate, so compared with the bungee and source in the prior art. The depth of the gate is shorter than that of the gate recess. Moreover, in the prior art, since the drain and the source are shallower than the gate recess, the electronic path from the source to the drain is horizontal, but The buckoo of the present invention is shallower than the source of the gate trench and the source of the gate of the gate. Therefore, the electron flow path from the source to the drain is vertical in the present invention. Moreover, the present invention can facilitate the self-aligned process of the gate wire by the fabrication of the sidewalls in the vertical transistor, and increase the process range. In addition, the present invention can simultaneously fabricate the gates of the logic region and the memory array region, simplifying and integrating the process steps. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should fall within the scope of the present invention.
【圖式簡單說明】 第1至4圖係為本發明之垂直電晶體製程示意圖。 第5至9圖係為本發明製作+ + 憶體之製程示意圖。垂直電晶體於動態隨機存取記 苐10圖係為棋盤式深丨冓準 構示意圖。 電容動態隨機存取記憶體之結 12、52矽基底 【主要元件符號說明】 10、50 記憶陣列區域 200810089 14、 56 閘極絕緣層 16、57 閘極凹槽 22、 82 閘極堆疊結構 32、42、84、92 遮罩 34、 86 汲極 44、94 源極 54 氧化層 58、64、72、81多晶矽層 62 侧壁子 100深溝渠電容DRAM 102 深溝渠電容 104 主動區域 106 閘極導線 108電晶體 13BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 to 4 are schematic views of a vertical transistor process of the present invention. Figures 5 through 9 are schematic views of the process of making + + memory in the present invention. The vertical transistor in the dynamic random access memory 苐 10 is a checkerboard squat schematic diagram. Capacitor dynamic random access memory junction 12, 52 矽 base [main component symbol description] 10, 50 memory array area 200810089 14, 56 gate insulation layer 16, 57 gate groove 22, 82 gate stack structure 32, 42, 84, 92 Mask 34, 86 Dippole 44, 94 Source 54 Oxide layer 58, 64, 72, 81 Polysilicon layer 62 Sidewall 100 Deep trench capacitor DRAM 102 Deep trench capacitor 104 Active region 106 Gate conductor 108 Transistor 13