200819005 t 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種嵌埋半導體晶片之電路板社 構，尤指一種在電路板中嵌埋有半導體晶片之結構。 【先前技術】 k 隨著半導體封裝技術的演進，半導體裝置 (Semiconductor device)已開發出不同的封裝型態，其主要 係在一封裝基板（package substrate)先接置一半導體晶 ®片，再將該半導體晶片電性連接該封裝基板，並以膠體進 行封裝·，其中球柵陣列式（Ball grid array，BGA)係為一種先 進的半導體封裝技術，其特點在於採用一封裝基板來安置 半導體晶片，並於該封裝基板背面植設複數陣列排列之凸 塊（bump)，使相同單位面積之半導體晶片承載件上可以容 納更多輸入/輸出連接端（I/O connection)以符合高度集積 - 化（Integration)之半導體晶片所需，以藉由此些錫球將整個 -春封裝單元焊結並電性連接至外部裝置。 惟傳統半導體封裝結構是將半導體晶片黏貼於基板 頂面’接者進4亍打線接合（wire bonding)或覆晶接合（Flip chip)封裝，再於基板之背面植以錫球以進行電性連接，如 此，雖可達到高腳數的目的，但是在更高頻使用時或高速 操作時，其將因導線連接路徑過長導致阻抗增加，使電氣 特性之效能無法提昇，而有所限制。 有鑑於此，為了能有效地提昇電性品質以符合下世代 產品之應用，業界紛紛研究採用將半導體晶片埋入電路板 5 19675 200819005 , 内作直接的電性連接，藉以縮短電性傳導路徑，並減少訊 號損失、訊號失真及提昇高速操作之能力。 習知嵌埋半導體晶片之電路板之製法流程圖如第ia 至ID圖所不，首先提供一承載板10,該承載板1〇具有第 表面10a及與该弟一表面相對之第二表面1仙，且於該 t承載板10中形成至少一貫穿該第一表面1(^及第二表面 r〇b之開口 1⑽（如第1A圖所示）；接著將一半導體晶片 籲11容置於該承載板1〇之開口 1〇〇中，而該半導體晶片U 具有一主動面11a及與其相對應之非主動面llb，且該主 動面11a具複數電極墊112，於該主動面lla具有一鈍化 層113並露出該電極墊〗丨2，又於該電極墊丨！ 2表面具有 金屬墊114 (如第1B圖所示）；之後於該承載板之第一 表面10a及半導體晶片11之主動面ila形成一介電層 且该介電層12具有複數開孔12〇以露出該半導體晶片j! 之金屬墊114 (如第1C圖所示）；最後於該介電層12之表 -_面形成一線路層13，且在該介電層開孔丨2〇中形成有導電 結構131以電性連接該半導體晶片金屬墊114(如第 1D圖所示）。 依上習知述製程所製成之嵌埋半導體晶片之電路板 雖可縮短電性傳導路徑，並減少訊號損失、訊號失真及提 昇在高頻運作之能力以克服習知半導體晶片接置於電路板 表面之種種缺失。 惟由於該半導體晶片11與介電層12之間的熱膨脹係 數（CTE)差異大，該半導體晶片約為3 ppm/°c，而該介 19675 6 4 200819005 分層的情況(二。 晶片之品質，甚至使得該電路 二 使用。 人卞夺版日日片失效而不堪 *以避免羽去i何提出一種敗埋半導體晶片之電路板結構， •片斑介：：3t導體晶片於電路板中’導致該半導體晶 •:進間的接合面產生分層的問題，實已成為亟需 【發明内容】 導缺失’本發明之目的即在提供-種嵌埋半 片之電路板結構，得改進習„埋半導體晶片之電 反中、，料導體晶片與介電層之間的分層問題。 為2上述及其他目的，本發明係提供—㈣埋半導體 日日之电路板結構，係包括：承載板，係具一第一表面及 •與f相對之第二表面m載板具有至少-貫穿該第一 =二表面之開σ;半導體晶片，係容置於該開口中，該 、導體晶片具有—主動面及與其相對之非主動面，且該主 * 衩數书極墊，於該主動面具有一鈍化層並露出該電 二ί、二：该電極墊表面具有金屬墊；緩衝層，係形成於 °’導體晶片之鈍化層表面，並包覆在該金屬墊周圍，僅 i4·出該金屬攀夕μ主 ^ 上表面；至少一介電層，係形成於該承載 反之第一表面、半導體晶片之金屬塾及緩衝層表面；以及 泉路層係、形成於該介電層表面，且該線路層藉由形成於 7 19675 200819005 5亥介電層中之導電結構以電性連接該金屬墊。 相較於習知技術，本發明之嵌埋半導體晶片之電路板 結構，係於半導體晶片之主動面及介電層間加入一緩衝 層，藉由該缓衝層以包覆該半導體晶片之金屬墊，且露出 該金屬墊之上表面，而可藉由該緩衝層以降低該介電層與 a半導體晶片之間接合面的應力，以避免產生分層的情況。 【實施方式】 _ 以下係藉由特定的具體實施例說明本發明之實施方 式，热悉此技藝之人士可由本說明書所揭示之内容輕易地 暸解本發明之其他優點與功效。 [第一實施例] 凊苓閱第2A至2G圖，係為本發明之嵌埋半導體晶片 之電路板結構之製法剖視流程圖。 如第2A圖所示，提供一承載板21，該承載板21具有 —一第一表面21a及與其相對之第二表面21b，且該承載板 ·21具有至少一貫穿該第一表面21a及第二表面2ib之開口 21〇 ’而該承載板21係為絕緣板、金屬板或具有線路之電 路板。 如第2B圖所示，於該承載板21之第二表面21b形成 有一離型膜22，以封住該承載板21之開口 21〇的一端。 如第2C圖所示，接著於該承載板21之開口 210中接 置一半導體晶片23，該半導體晶片23具有一主動面23a 及與其相對之非主動面23b，且該主動面23a具複數電極 塾231 ’於該主動面23a具有一鈍化層232並露出該電極 8 19675 200819005 墊231’又於該電極墊231表面具有金屬墊233丨又於該半 導體晶片U之主動面23a以網印或注入方式形成一缓衝層 24’且該缓衝層24並包覆該金屬塾233之周圍而露出該金 屬塾2 3 3之外表面，該缓衝層2 4係為低熱膨服係數（例如 約3〜2〇PpmrC)或低楊氏係數（例如約 有機聚合物；其中該緩衝層24之熱膨服係數最佳係可 •介於半導體晶片23及介電層25之間。 如第2D圖所示，然後於該承载板2ι之第一表面…、 Π體晶片23之金屬塾233及緩衝層24表面形成-介電 二二介電層25可視製程需要而不填入該承載板 一人半$體晶片23之間隙。 醒胺：：電層/5料例如為環氧樹脂(Ερ-、聚乙 fib、°Ilmi e)、亂脂❿⑽攸ester)、玻璃纖維（Giass t)、雙順丁烯二酸酿亞胺/三氮拼（BT，Bismaleimide ABF或混合環氧樹脂與玻璃纖維等材質所構成。 層二該介電層25表面形成-線路 961 " 了猎由形成於該介電層25中之導雷 〜構=以電性連接該半導體晶片23之金屬塾加。“ 形成咬所不’復可於該介電層25及線路層26上 電声271 \曰、、、°構27,其中該線路增層結構27係包括介 介上之線路層27™成於該 接該線路芦26 且該導電結構273可供電性連 電性連接^ 274亚於该線路增層結構27表面形成有複數 ，又於該線路增層結構27上覆蓋有一防焊 19675 9 200819005 蠢 層28，且該防焊層28具有複數個開孔，俾以顯露線路 增層結構27之電性連接墊274，該電性連接墊274若為焊 墊（Pad)則可供植置凸塊（bump)或接腳(pin)。 如第2G圖所示，移除該離型膜22，並於該承載板21 ^開口 21G與半導體晶片23之間的間隙中形成—例如為樹 脂材料之黏著材料29，俾以將該半導體晶片23固定於該 開口 210中。 φ 由於该半導體晶片23與介電層25之間於製程中所產 生的熱應力與熱膨脹係數差異（CTE difference)和揚氏係 數（Young’s Modulus)之乘積為正比，因此可藉由該緩衝 層24之低熱％脹係數或低揚氏係數之物性，以釋放半導體 曰曰片23與介電層25之間熱膨脹係數差異所產生之應力， 以避免產生分層的情況，俾可提升該半導體晶片23嵌埋於 承載板21中之可靠度。 [弟二貫施例] • 請麥閱第3 A至3D圖，係為本發明之嵌埋半導體晶片 之電路板結構之製法剖視流程圖。 如第3A圖所示，提供一係如前一實施例所述之承载 板21、離型膜22及半導體晶片23,該承載板21具有至少 一貫穿該第一表面21a及第二表面21b之開口 210;並於 該承載板21之第二表面21b形成有一離型膜22，以封住 該承載板21之開口 210的一端；又於該承載板21之開口 210中接置有一半導體晶片23,該半導體晶片23具有一主 動面23a及與其相對之非主動面23b，且該主動面23a具 10 19675 200819005 * 複數電極墊231，於該主動面23a具有一鈍化層232並露 出該電極墊231，又於該電極墊231表面具有金屬墊233， 方、忒半$體晶片23之鈍化層232表面形成有一緩衝層 24且该緩衝層24包覆該金屬墊233之周圍而露出該金屬 墊233之外表面。 如第3B圖所示，然後於該承載板21之第一表面21心 半導體晶片23之金屬墊233及缓衝層24表面形成一介電 ^5,且該介電層25係填入該承載板21之開口 210與半 導體晶片23之間的間隙中，俾以將該半導體晶片23固定 於該開π 21 〇中。 如第3C：圖所示，之後於該介電層乃表面形成一線路 層26’且該線路層26可藉由形成於該介電層乃中之導電 結構而電性連接該半導體晶片23之金屬墊233。 ,、如第3D圖所不，復可於該介電層25及線路層26上 二成、泉路立曰層結構27 ’其中該線路增層結構η係包括至 ’丨毛層27卜璺置於該介電層上之線路層272，以及形 =該介電層中之導電結構奶，且該導電結構π可供 該線路層26,並於該線路增層結構27表面形成 一：Ϊ電性連接墊274 ’又於該線路增層結構27上覆蓋有 以^ t 28且遠防焊層28表面具有複數個開孔280，俾 择頁路線路增層結構27之電性連接墊274。 半導本發明之敌埋半導體晶片之電路板結構’係於 該半；I曰：主動面形成有―缓衝層，藉由該缓衝層包覆 以千与Τ月豆日日片之令厪轨，；# 、’ 而可糟由該緩衝層以降低嵌埋於 19675 11 200819005 承載板内之半導體晶片與介電層之間的接合面於製程中 產生的熱應力，以避免該接合面產生分層的現象。 所 上述實施例僅為例示性說明本發明之原理及其功 效，而非用於限制本發明。任何熟習此項技藝之人士均可 在不堤背本發明之精神及範疇下，對上述實施例進行修飾 與變化。因此，本發明之權利保護範圍，應如後述之 專利範圍所列。 月BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit board structure in which a semiconductor wafer is embedded, and more particularly to a structure in which a semiconductor wafer is embedded in a circuit board. [Prior Art] k With the evolution of semiconductor packaging technology, semiconductor devices have developed different package types, which are mainly connected to a semiconductor substrate in a package substrate. The semiconductor wafer is electrically connected to the package substrate and encapsulated by a gel. The ball grid array (BGA) is an advanced semiconductor packaging technology, and is characterized in that a package substrate is used to place the semiconductor wafer. And stacking a plurality of arrays of bumps on the back surface of the package substrate, so that the semiconductor wafer carrier of the same unit area can accommodate more I/O connections to conform to the height accumulation-integration ( The semiconductor wafer of Integration) is required to solder and electrically connect the entire-spring package unit to the external device by means of the solder balls. However, in the conventional semiconductor package structure, the semiconductor wafer is adhered to the top surface of the substrate, and the wire bonding or Flip chip package is attached, and then the solder ball is implanted on the back surface of the substrate for electrical connection. In this way, although the purpose of the high number of feet can be achieved, in the case of higher frequency use or high speed operation, the impedance will increase due to the long connection path of the wire, and the performance of the electrical characteristics cannot be improved, and there is a limit. In view of this, in order to effectively improve the electrical quality to meet the application of the next generation of products, the industry has studied the use of semiconductor wafers buried in the circuit board 5 19675 200819005, for direct electrical connection, thereby shortening the electrical conduction path, It also reduces signal loss, signal distortion and the ability to improve high-speed operation. A method for manufacturing a circuit board embedding a semiconductor wafer is as shown in the first to the id chart. First, a carrier board 10 having a first surface 10a and a second surface 1 opposite to the surface of the younger one is provided. And forming at least one opening 1 (10) penetrating the first surface 1 (the second surface r〇b) (as shown in FIG. 1A); and then placing a semiconductor wafer 11 The semiconductor wafer U has an active surface 11a and an inactive surface 11b corresponding thereto, and the active surface 11a has a plurality of electrode pads 112, and the active surface 11a has a The passivation layer 113 exposes the electrode pad 丨2, and the surface of the electrode pad 丨! 2 has a metal pad 114 (as shown in FIG. 1B); then the first surface 10a of the carrier plate and the semiconductor wafer 11 are actively activated. The surface ila forms a dielectric layer and the dielectric layer 12 has a plurality of openings 12 to expose the metal pad 114 of the semiconductor wafer j (as shown in FIG. 1C); finally, the surface of the dielectric layer 12 Forming a wiring layer 13 and forming a conductive structure 131 in the dielectric layer opening 〇2〇 to electrically The semiconductor wafer metal pad 114 is connected (as shown in FIG. 1D). The circuit board embedded with the semiconductor chip fabricated according to the conventional process can shorten the electrical conduction path and reduce signal loss, signal distortion and enhancement. The ability to operate at high frequencies overcomes the deficiencies of conventional semiconductor wafers placed on the surface of the board. However, due to the large difference in thermal expansion coefficient (CTE) between the semiconductor wafer 11 and the dielectric layer 12, the semiconductor wafer is approximately 3 ppm. / °c, and the introduction of the 19675 6 4 200819005 layered case (two. The quality of the chip, and even the use of the circuit two. People usurped version of the Japanese film failure is unbearable * to avoid the feathers to ask for a failure to bury The circuit board structure of the semiconductor chip, • Chip spot:: 3t conductor chip in the circuit board 'causes the semiconductor crystal: the problem of delamination of the joint surface between the electrodes has become an urgent need. The object of the present invention is to provide a circuit board structure with embedded half-pieces, which can improve the delamination problem between the semiconductor wafer and the dielectric layer. And the other object of the present invention is to provide a circuit board structure for a semiconductor chip, comprising: a carrier plate having a first surface and a second surface opposite to f, wherein the carrier plate has at least - through the first The opening σ of the two surfaces; the semiconductor wafer is disposed in the opening, the conductive wafer has an active surface and an inactive surface opposite thereto, and the main * 书 book pad has a active mask The passivation layer exposes the electricity, and the surface of the electrode pad has a metal pad; the buffer layer is formed on the surface of the passivation layer of the 'the conductor wafer, and is wrapped around the metal pad, only the metal plate The upper surface of the upper surface; at least one dielectric layer formed on the opposite surface of the carrier, the metal germanium and the buffer layer surface of the semiconductor wafer; and the spring layer layer formed on the surface of the dielectric layer, and the line The layer is electrically connected to the metal pad by a conductive structure formed in the 7 19675 200819005 5 dielectric layer. Compared with the prior art, the circuit board structure of the embedded semiconductor wafer of the present invention is characterized in that a buffer layer is added between the active surface and the dielectric layer of the semiconductor wafer, and the buffer layer is used to cover the metal pad of the semiconductor wafer. And exposing the upper surface of the metal pad, and the buffer layer can be used to reduce the stress on the bonding surface between the dielectric layer and the a semiconductor wafer to avoid delamination. [Embodiment] The following describes the embodiments of the present invention by way of specific embodiments, and those skilled in the art can readily understand the other advantages and advantages of the present invention from the disclosure herein. [First Embodiment] Referring to Figs. 2A to 2G, there is shown a flow chart of a circuit board structure of a buried semiconductor wafer of the present invention. As shown in FIG. 2A, a carrier board 21 is provided. The carrier board 21 has a first surface 21a and a second surface 21b opposite thereto, and the carrier board 21 has at least one through the first surface 21a and The opening 21 二 of the surface 2 ii is the insulating plate, the metal plate or the circuit board having the wiring. As shown in Fig. 2B, a release film 22 is formed on the second surface 21b of the carrier plate 21 to seal one end of the opening 21 of the carrier plate 21. As shown in FIG. 2C, a semiconductor wafer 23 is further disposed in the opening 210 of the carrier board 21. The semiconductor wafer 23 has an active surface 23a and an inactive surface 23b opposite thereto, and the active surface 23a has a plurality of electrodes.塾 231 ' has a passivation layer 232 on the active surface 23a and exposes the electrode 8 19675 200819005. The pad 231 ′ has a metal pad 233 on the surface of the electrode pad 231 and is screen printed or injected on the active surface 23 a of the semiconductor wafer U. The buffer layer 24 is formed and the buffer layer 24 covers the periphery of the metal crucible 233 to expose the outer surface of the metal crucible 23 3 . The buffer layer 24 is a low thermal expansion coefficient (for example, 3~2〇PpmrC) or a low Young's modulus (for example, about an organic polymer; wherein the thermal expansion coefficient of the buffer layer 24 is optimally between the semiconductor wafer 23 and the dielectric layer 25. As shown in FIG. 2D As shown, the first surface of the carrier substrate 2, the metal germanium 233 of the body wafer 23, and the surface of the buffer layer 24 are formed to form a dielectric dielectric layer 25, which is required for the process without filling the carrier board. $The gap between the body wafers 23. The amine:: the electrical layer / 5 material is for example a ring Resin (Ερ-, polyethyl fib, °Ilmi e), sputum (10) 攸ester), glass fiber (Giass t), bis-maleic acid-imide/triazine (BT, Bismaleimide ABF or mixed epoxy) A resin is formed of a material such as glass fiber. Layer 2 is formed on the surface of the dielectric layer 25 - a line 961 is used to steer the metal formed in the dielectric layer 25 to electrically connect the metal of the semiconductor wafer 23 。 “ “ “ “ “ “ “ “ “ “ “ “ “ “ “ “ “ “ “ 该 该 该 该 271 271 271 271 271 271 271 271 271 271 271 271 271 271 271 271 271 271 271 271 271 271 271 271 271 271 271 The TM is connected to the line 26 and the conductive structure 273 is electrically connected. The 274 is formed on the surface of the line build-up structure 27, and the line build-up structure 27 is covered with a solder-proof 19765. 9 200819005 The stupid layer 28, and the solder resist layer 28 has a plurality of openings for exposing the electrical connection pads 274 of the line build-up structure 27, and the electrical connection pads 274 can be implanted if they are pads (Pad) A bump or a pin is placed. As shown in FIG. 2G, the release film 22 is removed, and the carrier plate 21 is opened. An adhesive material 29 such as a resin material is formed in a gap between the 21G and the semiconductor wafer 23 to fix the semiconductor wafer 23 in the opening 210. φ Since the semiconductor wafer 23 and the dielectric layer 25 are in the process The thermal stress generated in the product is proportional to the product of the difference between the CW difference and the Young's Modulus, and therefore can be released by the low thermal % expansion coefficient or the low Young's coefficient of the buffer layer 24 The stress generated by the difference in thermal expansion coefficient between the semiconductor wafer 23 and the dielectric layer 25 avoids the occurrence of delamination, and the reliability of the semiconductor wafer 23 embedded in the carrier 21 can be improved. [Different Example] • Please refer to Figures 3A to 3D for a schematic cross-sectional view of the circuit board structure of the embedded semiconductor wafer of the present invention. As shown in FIG. 3A, a carrier board 21, a release film 22, and a semiconductor wafer 23 according to the previous embodiment are provided. The carrier board 21 has at least one through the first surface 21a and the second surface 21b. An opening 210 is formed on the second surface 21b of the carrier 21 to seal one end of the opening 210 of the carrier 21; and a semiconductor wafer 23 is disposed in the opening 210 of the carrier 21. The semiconductor wafer 23 has an active surface 23a and an inactive surface 23b opposite thereto, and the active surface 23a has 10 19675 200819005 * a plurality of electrode pads 231 having a passivation layer 232 on the active surface 23a and exposing the electrode pads 231 Further, a surface of the electrode pad 231 has a metal pad 233, and a buffer layer 24 is formed on the surface of the passivation layer 232 of the square and half body wafer 23, and the buffer layer 24 covers the periphery of the metal pad 233 to expose the metal pad 233. Outside surface. As shown in FIG. 3B, a dielectric layer 5 is formed on the surface of the metal pad 233 and the buffer layer 24 of the semiconductor wafer 23 on the first surface 21 of the carrier 21, and the dielectric layer 25 is filled in the carrier. In the gap between the opening 210 of the board 21 and the semiconductor wafer 23, the semiconductor wafer 23 is fixed in the opening π 21 。. As shown in FIG. 3C: a wiring layer 26' is formed on the surface of the dielectric layer, and the wiring layer 26 is electrically connected to the semiconductor wafer 23 by a conductive structure formed in the dielectric layer. Metal pad 233. , as shown in FIG. 3D, may be applied to the dielectric layer 25 and the circuit layer 26, and the spring road layer structure 27 ' wherein the line build-up structure η includes to the 'bristle layer 27 divination a circuit layer 272 disposed on the dielectric layer, and a conductive structure milk in the dielectric layer, and the conductive structure π is available for the circuit layer 26, and a surface is formed on the surface of the circuit build-up structure 27: The electrical connection pad 274 ′ is further covered on the line build-up structure 27 with a plurality of openings 280 on the surface of the remote solder mask 28, and the electrical connection pads 274 of the page line build-up structure 27 are selected. . The semi-conductive circuit board structure of the embedded semiconductor wafer of the present invention is attached to the half; I曰: the active surface is formed with a “buffer layer”, and the buffer layer is coated with the order of the thousand and the moon beans.厪 rail,;#,' can be used to reduce the thermal stress generated in the process by the buffer layer to reduce the bonding surface between the semiconductor wafer and the dielectric layer embedded in the 19695 11 200819005 carrier board to avoid the bonding surface Produce a layered phenomenon. The above-described embodiments are merely illustrative of the principles of the invention and its advantages, and are not intended to limit the invention. Modifications and variations of the above-described embodiments can be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the following patent scope. month
圖式簡單說明】 第1A至1D圖係為習知嵌埋半導體晶片 之製法流程 弟2A至2G圖係為本發明 結構之第一實施製法流程圖； 第3 A至3 D圖係為本發明 結構之第二實施製法流程圖。 之嵌埋半導體晶片之電路板 以及 之歲埋半導體晶片之電路板 【主要元件符號說明】 _ 10、21 100 、 210 l〇a、21a l〇b 、 21b 11、23 112 ^ 231 113 、 232 114 、 233 274 承載板 開口 弟一表面 弟一表面 半導體晶片 電極墊 ~ 純化層 金屬墊 電性連接墊 19675 12 200819005 . lla、23a 主動面 11b 、 23b 非主動面 12 、 25 、 271 介電層 120 、 280 開孔 13 、 26 > 272 線路層 131 、 261 、 273 導電結構 22 離型膜 24 缓衝層 •29 黏著材料 27 線路增層結構 28 防焊層BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A to FIG. 1D are diagrams showing a conventional process for embedding a semiconductor wafer. 2A to 2G are flowcharts of the first embodiment of the structure of the present invention; FIGS. 3A to 3D are diagrams of the present invention. The second implementation method flow chart of the structure. A circuit board in which a semiconductor chip is embedded and a circuit board in which a semiconductor chip is buried [Main component symbol description] _ 10, 21 100 , 210 l〇a, 21a l〇b, 21b 11, 23 112 ^ 231 113 , 232 114 233 274 carrier plate opening one surface of a surface semiconductor wafer electrode pad ~ purification layer metal pad electrical connection pad 19675 12 200819005 . lla, 23a active surface 11b, 23b inactive surface 12, 25, 271 dielectric layer 120, 280 opening 13 , 26 & gt 272 circuit layer 131 , 261 , 273 conductive structure 22 release film 24 buffer layer • 29 adhesive material 27 line build-up structure 28 solder mask
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