200818514 21558twf.doc/n 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種半導體結構及其製造方法，且特 別是有關於-種具有隔離結構的非揮發性記憶體及其 方法。 【先前技術】 記憶體，顧名思義便是用以儲存資料或數據的半 元件。當電腦微處理器之功能越來越強，軟體所進行之程 式與運异越來越龐大時，記憶體之需求也就越來越高 了製造容量大且便宜的記憶體以滿足這種需求_勢，^ =體：件之技術與製程’已成為半導體科技持續往： 積集度挑喊之驅動力。 以非揮發性記憶體為例，當元件的尺寸越來越小，度 於微影製程的複雜度也會提高。不論是光罩的製作 前的對準(alignment)、光阻圖案的顯影等等 ::時往會造成製造成本的大幅提高，並且拉:整個製 為了避免上述問題的發生’採用自行對準的 少光罩的使用，就成為製作記憶體的另一種選擇。/ 然而’-㈣應記«元件的設計，在記憶胞 便會較密集。而為了使自行對準的钱刻製 私中具有較大的|虫刻裕度，隔離結構又必須具備一定的古 f °如此—來，會使得後續卿成之橫跨_結構的字= 線，因為隔離結構與基底的高度落差，而產生均勻戶 5 200818514 21558twf.doc/n (uniformity)不佳的情形。尤其是在記憶胞陣列的周邊，字 元線的線寬甚至會與陣列中央之字元線的線寬相差至12% 左右。此外，隔離結構的側壁還可能會產生字元線之導體材 料的殘留物，導致相鄰字元線之間會有短路的現象。這些情 形都會造成元件的電性表現不穩定，影響產品的良率。 【發明内容】 有鑑於此，依照本發明提供實施例之目的就是在提供 二種具f隔離結構的非揮發性記憶體，其源極線外側的隔 離結構高度較低，且字元線的圖案均勻度較佳。 依照本發明提供實施例之另一目的是提供一種非 ==製造方法’可以增加字元編刻裕度與钕刻 後的均勻度，進而改善元件的電性表現。 洋置閘極的頂部低於凸出部頂面。源極 本發明提出-種具有隔離結構的非揮發性記憶體 括基底、隔離結構、開口、浮置閘極、源極線*字元線。 _結構平行設置於基底中，並且相鄰二隔離結構定^出 立主動區1其中，隔離結構具有凸出部與凹陷部，且 :的頂面高於凹陷部的頂面，凹陷部的頂面約高於 底的頂面。開㈣置於主動區之基底中，開π為相鄰二 離結構之凸出部所包夾。浮置閘極設置於開口 :隔 之其ιέ u 線設置於開口底邱 之基底上，並且橫跨隔離結構之凸出部。 之凹陷部 上述具有隔離結構的非揮發性記憶體中，凸出部與 之基底上，約略平行於源極線並 凹 21558twf.doc/n 200818514 陷部分別具有一平坦的表面。 上述具有隔離結構的非揮發性 頂部而浮置f_T二=的 I、有隔騎構的非揮發 以自行對準的方式所形成的。=體中e置間極是 上述具有隔離結構的非揮發性記憶 材質包括摻雜多晶矽。隔離a α '甲’極的 線的材質包括摻雜多晶Γ、，、。構的材質包括叫 序垂非揮發性記憶體中，開口側壁依 :金直層宜有牙隨介電層、浮置間極、層間介電層與源極 供-= = 記憶體的製造方法，包括提 t 些隔離結構的頂面高於基底頂面。 之側辟區之基底中形成多個開口。繼而於各開口 線，源極綠抑社二 、、開口底部之基底上形成源極 除源極❹Μ ι *置閘極並且橫跨這些隔離結構。繼而移 基底上形財元線。#射來’於雜線外側之 構而發性記憶體的製造方法中，移除部分隔離結 ΐ匕:阻=;外側之部分隔離結構。而後以圖 案化先阻層絲幕，移除部分_結構，㈣ 200818514 21558twf.doc/n 之後再移除圖案化光阻層。 上述非揮發性記憶體的製造方法中，移除部分隔離結 構的方法包括乾式敍刻法。 上述非揮發性記憶體的製造方法中，更包括以自行對 準的方式形成浮置閘極。 上述非揮發性記憶體的製造方法中，凹陷部的頂面約 高於等於基底之頂面。 、 上述非揮發性記憶體的製造方法中，開口的形成方法 包括於基底上形成罩幕層，覆蓋住隔離結構。移除主動區 上以及隔離結構上之部分罩幕層，而後以罩幕層為 移除部分基底，而形成開口。 上述非揮發性記憶體的製造方法中，這些隔離結構的 形成方法包括高密度電漿化學氣相沈積法。 上述非揮發性記憶體的製造方法中，更包括於形成這 =口=後於開π内依序形成一魏介電層、浮置閉極以 ^ ^電層；於開口底部之基底中形成，極區；移除 ^述非揮發性記憶體的製造方法中，源極線電性連接 二其^卩之層間介電層以及穿遂介電層，以露出開口底部 “，以及於開口底部之基底上形成源極線 源極區 這些隔離結構的 雜多晶矽。源極 字元線約略平行 上述非揮發性記憶體的製造方法中 雜i:r_括. 上述非揮發性記憶體的製造方法中 200818514 21558twf.doc/n 源極線，並且橫跨隔離結構之凹陷部。 上述非揮發性記憶體，移除了源極線外側的部分隔離 結構，降低隔離結構與基底的高度差，使得後續形成的字 元線，蝕刻裕度大增，進而得以形成均勻度較佳的字元線。 不但能夠改善元件的電性穩定性，也有助於提高製程良率。 【實施方式】 圖1是繪示本發明一實施例之一種具有隔離結構的非 揮發性記憶體的立體結構剖面圖。 請參照圖1，本實施例提出的具有隔離結構的非揮發 性記憶體，至少含有基底1〇〇、隔離結構11〇、浮置閘極 120、源極線130與字元線140。 基底100例如是矽基底。隔離結構110呈條狀設置於 基底100中，往X方向延伸，並且定義出主動區1〇5。隔 離結構110具有交替配置的凸出部113與凹陷部115。凸 出部113與凹陷部115具有平坦的頂面，且凸出部113的 頂面高於凹陷部115的頂面，凹陷部115的頂面約高於等 於基底100的頂面。隔離結構11〇的材質例如是氧化矽 絕緣材料。 主動區105之基底1〇〇中設置有開口 1〇8，開口⑺8 為前後二隔離結構110之凸出部113所包夹。浮置問極12〇 設置於開π 108的側壁。浮置閘極12〇的頂部具有角狀於 構，且其頂部低於隔離結構11〇之凸出部ιΐ3頂面，而： 隔離結構110所分隔，呈塊狀分佈於開口 1⑽之中。广置 閘極120的材質例如是摻雜多晶石夕。浮置閘極12〇與^口 200818514 21558t\vf.doc/n 108侧壁例如是設置有一層穿隧介電層118。穿隧介電芦 118的材質例如是氧化矽。 i曰 開口 108底部之基底1〇〇中設置有源極區125。源極 區125例如是含有磷、砷等N型摻質之摻雜區。 源極線130呈條狀設置基底刚上，橫跨隔離結構ιι〇 之凸出部113，往Y方向延伸，並且與源極區125電性連 接。源極線130的材質例如是摻雜多晶矽。源極線13〇與 #置閘極12G之間設置有—層層間介電層128。層間介^ I 128的材質例如氧化;^ ’或;^氧化♦氮化⑪/氧化秒等 複合介電材料。源極線13〇上方還可以設置有一層保護層 ，其材質例如是氧化矽。 S 曰 字元線140設置於源極線13〇外側之基底丨⑻上，約 略平行於源極線130 ,並且橫跨隔離結構11〇而設置。字 元線140係對稱地設置於源極線丨3〇之二 說明，圖i省略其中一侧字元線14〇未緣示。字元線14〇 ，基底100之間例如是設置有介電層m，其材質例如是 〔 氧化石夕專絕緣材料，用來隔絕字元線140與基底1⑻。 +由於隔離結構U0的凹陷部115與基底100之間的高 度落差小，因此，橫跨設置於其上方的字元線14〇，不會 產生均勻度不佳的問題。也就是說，即使是在記憶胞陣列 的周邊，字元線140的線寬仍可約略維持與記憶胞陣列中 央之子元線140相同的線寬。從而，可以保持記憶體元件 的電性％、定，並增加產品的良率。 以下說明本發明一實施例之非揮發性記憶體的製造方 200818514 21558twf.doc/n 法，圖2A至圖2D是繪示此非揮發性記憶體的製造流程立 體剖面圖。 請參照圖2A，此方法係先提供基底2〇〇，基底2〇〇例 如疋石夕基底。基底200上已形成有多數個隔離結構21〇， 這些隔離結構210定義出主動區205，往X方向延伸。隔 離結構210例如是淺溝渠隔離結構或是場氧化層，其材質 例如是氧化矽，其形成方法例如是高密度電漿化學氣相沈 積法。這些隔離結構210的頂面高於主動區2〇5之基底2〇〇 Γ 頂面。在一實施例中，隔離結構210的頂面例如是高於主 動區205之基底200頂面約11〇〇埃。基底2〇〇上還可以是 設置有一層墊層211，此墊層例如是在隔離結構21〇的製 造過程中所形成的。墊層211的材質例如是氧化石夕，其形 成方法例如是化學氣相沈積法。 然後，請繼續參照圖2A，於基底200上形成一層罩幕 層213,覆蓋住這些隔離結構210。罩幕層213的材質例如 是氮化矽、碳化矽或碳氮化矽，其形成方法例如是化學氣 I 相沈積法。在一實施例中，罩幕層213的厚度例如是3600 i 埃。之後再移除主動區205上之部分罩幕層213與部分基 底200而形成開口 208。此時，隔離結構210上方的部分 罩幕層213也會一併被移除。在一實施例中，所形成的開 口 2〇8深度（開口 208底部與基底200頂面的距離）例如 是2000埃。 然後，請參照圖2A、圖2B與圖2C，於開口 208内 壁形成一層穿隧介電層218。穿隧介電層218的材質例如 11 200818514 r —r - 21558twf.doc/n 疋氧化石夕其形成方法例如是南溫熱氧化法，當然，後續 可以再進行快速熱回火以改善氧化石夕的品質。 接著，於開口 208的侧壁形成浮置閘極220，浮置閘 極220的頂部低於隔離結構210頂面並且高於基底200頂 面，浮置閘極220的頂部例如是具有一角狀結構。 浮置閘極220的形成方法例如是先於開口 208中填入 一層導體層（未繪示），導體層的頂面具有凹陷並且低於 ( 隔離結構210頂面、高於基底200頂面。導體層的材質例 ' 如疋摻雜多晶矽，其形成方法例如是採用臨場植入摻質的 方式以化學氣相沈積法形成之。然後於開口 208側壁形成 間隙壁223 ’利用自行對準的方式，以間隙壁223為罩幕， 移除部分導體層，即形成浮置閘極22〇。移除部分導體層 的方法包括乾式飿刻法。 由於導體層的頂面低於隔離結構215，因此，後續形 成的浮置閘極220可以藉由隔離結構215的分隔來形成區 塊狀的浮置閘極220，而無須透過微影技術來形成之。 I 繼而’请參照圖2B ’於基底200上形成一層層間介電 層228,覆蓋住浮置閘極220。層間介電層228的材質例如 是氧化石夕’其形成方法例如是先進行高溫熱氧化沈積法， 再進行快速熱回火。當然，層間介電層228也可以是由多 層介電材料所形成的複合介電層，如氧化矽-氮化秒_氧化 石夕。 然後，於開口 208底部之基底200中形成源極區235。 源極區235例如是具有磷、砷等N型摻質之摻雜區，其妒 12 2l558twf.doc/n 200818514 成方法例如是離子植入法。之後，移除開口 208底部之層 間介電層228與穿隧介電層218，而裸露出開口 208底部 之基底200。移除層間介電層228與穿隧介電層218的方 法例如疋濕式敍刻法，其例如是以氫氟酸為韻刻劑。 爾後，於開口 208中形成源極線240，源極線240橫 ，隔離結構210，往γ方向延伸。源極線24〇的材質例如 是摻雜多晶矽、金屬、金屬矽化物等導體材料，其形成方 法例如化學氣相沈積法。而後於源極線24〇上形成一層保 護層245 ’保護層245的材質為氧化石夕等介電材料，其形 成方法例如是辨氣相沈積法或絲化法。之後，移除罩 幕層213，裸露出隔離結構21〇與主動區2〇5之基底2⑽。 當然’若基底200上形成有塾層211，即係裸露出整層211。 接著，請參照圖2C’移除源極線外側之部分隔離 結構210 ’而於隔離結構21〇中形成凹陷部217，凹陷部 217的底部約高於等於基底2〇〇頂面。在一實施例中，凹 陷部217底部例如是高於基底2〇〇頂面約2〇〇〜埃。 移除部分隔離結構200而形成凹陷部217的方法例如 是先於基底200上形成—層圖案化光阻未繪示），裸 露出源極線240兩外側之部分隔離結構21〇。然後以圖案 ^且層，幕’利用乾纽刻法移除部分隔 210 ’而形成凹陷部217。繼而再移除圖案化光阻層。 接下來’清參照圖2D，於源極線24〇夕卜側之基底· 上形i Γ。字元線250約略平行於源極線240，並 且橫跨隔離結構2H)’特別是橫跨過隔離結構=之凹陷 13 200818514 21558twf.doc/n 部217。字元線250的形成方法例如是先於基底2〇〇上形 成一層導體層（未繪示），覆蓋住保護層245與隔離結構 210。然後，移除保護層245上之導體層。之後再於源極線 240側壁形成絕緣間隙壁253,並以此絕緣間隙壁253為罩 幕，移除裸露之導體層，而形成字元線250。200818514 21558twf.doc/n IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor structure and a method of fabricating the same, and more particularly to a non-volatile memory having an isolated structure and method thereof . [Prior Art] Memory, as the name implies, is a semi-component for storing data or data. As the functions of computer microprocessors become stronger and stronger, and the programs and operations carried out by software become larger and larger, the demand for memory becomes higher and higher. The memory with large capacity and cheap capacity is met to meet this demand. _ potential, ^ = body: the technology and process of the 'has become the semiconductor technology continues to: the driving force of the accumulation of screaming. Taking non-volatile memory as an example, as the size of the component becomes smaller and smaller, the complexity of the lithography process increases. Whether it is the alignment of the mask before the development of the photoresist, the development of the photoresist pattern, etc.:: the time will cause a substantial increase in manufacturing costs, and pull: the whole system in order to avoid the above problems, 'self-aligned The use of less reticle is another option for making memory. / However, '-(4) should remember that the design of the components is denser in memory. In order to make the self-aligned money engraved privately with a large | insect margin, the isolation structure must have a certain ancient f ° so - will make the follow-up _ structure of the word = line Because of the height difference between the isolation structure and the substrate, a situation in which the uniform household 5 200818514 21558twf.doc/n (uniformity) is not good is generated. Especially at the periphery of the memory cell array, the line width of the word line may even differ from the line width of the word line in the center of the array by about 12%. In addition, the sidewalls of the isolation structure may also create residues of conductor material of the word lines, resulting in short circuits between adjacent word lines. These conditions can cause the electrical performance of the component to be unstable, affecting the yield of the product. SUMMARY OF THE INVENTION In view of the above, the object of the embodiments of the present invention is to provide two non-volatile memory structures with f isolation structure, the isolation structure outside the source line has a low height, and the pattern of the word lines. The uniformity is better. Another object of an embodiment in accordance with the present invention is to provide a non-== manufacturing method' which can increase the wording margin and the uniformity after engraving, thereby improving the electrical performance of the component. The top of the oceanic gate is lower than the top of the projection. Source The present invention proposes a non-volatile memory substrate having an isolation structure, a spacer structure, an opening, a floating gate, and a source line* word line. The structure is disposed in parallel in the substrate, and the adjacent two isolation structures define the active area 1 wherein the isolation structure has a protrusion and a recess, and the top surface is higher than the top surface of the recess, the top of the recess The surface is about the top surface above the bottom. The opening (4) is placed in the base of the active area, and the opening π is sandwiched by the protruding portion of the adjacent two-way structure. The floating gate is disposed at the opening: the ιέ u line is disposed on the base of the open bottom and spans the protrusion of the isolation structure. The recessed portion of the non-volatile memory having the isolated structure, the projections and the substrate are approximately parallel to the source line and recessed. The recesses respectively have a flat surface. The non-volatile top having the isolated structure is floated with f_T==, and the non-volatile, non-volatile structure is formed by self-alignment. = The inter-electrode interpole is a non-volatile memory material having an isolated structure including doped polysilicon. The material of the line separating the α 'A' pole includes doped polysilicon, . The material of the structure includes the non-volatile memory, and the sidewall of the opening is: the gold straight layer should have a tooth with dielectric layer, the floating interpole, the interlayer dielectric layer and the source supply -= = memory manufacturing method The top surface of the isolation structure is higher than the top surface of the substrate. A plurality of openings are formed in the base of the sill region. Then, on each of the open lines, the source is green, and the source is formed on the substrate at the bottom of the opening. The source is separated from the source and the gate is crossed. Then move the base line on the base. In the method of manufacturing the structured memory, the partial isolation barrier is removed: the resistance is a partial isolation structure on the outer side. Then, the patterned photoresist layer is removed, and the portion of the structure is removed. (4) 200818514 21558twf.doc/n The patterned photoresist layer is removed. In the above method of manufacturing a non-volatile memory, a method of removing a part of the isolation structure includes a dry scribe method. In the above method for manufacturing a non-volatile memory, it is further included that the floating gate is formed in a self-aligned manner. In the above method for producing a non-volatile memory, the top surface of the depressed portion is higher than or equal to the top surface of the substrate. In the above method for manufacturing a non-volatile memory, the method of forming the opening includes forming a mask layer on the substrate to cover the isolation structure. A portion of the mask layer on the active area and on the isolation structure is removed, and then the mask layer is used to remove a portion of the substrate to form an opening. In the above non-volatile memory manufacturing method, the formation method of these isolation structures includes a high-density plasma chemical vapor deposition method. In the method for fabricating the non-volatile memory, the method further includes forming a Wei dielectric layer and a floating closed electrode in the opening π to form a Wei dielectric layer, and forming the dielectric layer in the substrate at the bottom of the opening. In the manufacturing method of removing the non-volatile memory, the source line is electrically connected to the interlayer dielectric layer and the dielectric layer through the dielectric layer to expose the bottom of the opening, and at the bottom of the opening a heteropolysilicon of the isolation structure of the source line source region is formed on the substrate. The source word line is approximately parallel to the manufacturing method of the non-volatile memory, and the method of manufacturing the non-volatile memory Medium 200818514 21558twf.doc/n source line, and across the recess of the isolation structure. The above non-volatile memory removes part of the isolation structure outside the source line, reducing the height difference between the isolation structure and the substrate, so that In the formed word line, the etching margin is greatly increased, thereby forming a word line with better uniformity. Not only can the electrical stability of the device be improved, but also the process yield can be improved. [Embodiment] FIG. Show the invention A perspective view of a three-dimensional structure of a non-volatile memory having an isolated structure. Referring to FIG. 1, a non-volatile memory having an isolated structure according to the embodiment includes at least a substrate 1 and an isolation structure 11 The floating gate 120, the source line 130 and the word line 140. The substrate 100 is, for example, a germanium substrate. The isolation structure 110 is disposed in a strip shape in the substrate 100, extends in the X direction, and defines an active region 1〇5. The isolation structure 110 has the protrusions 113 and the recesses 115 arranged alternately. The protrusions 113 and the recesses 115 have a flat top surface, and the top surface of the protrusions 113 is higher than the top surface of the recesses 115, and the recesses 115 The top surface of the substrate is approximately equal to or greater than the top surface of the substrate 100. The material of the isolation structure 11 is, for example, a yttria insulating material. The substrate 1 of the active region 105 is provided with an opening 1 〇 8 , and the opening ( 7 ) 8 is a front and rear isolation structure 110 . The protruding portion 113 is sandwiched. The floating questioner 12 is disposed on the side wall of the opening π 108. The top of the floating gate 12 is angularly formed, and the top portion thereof is lower than the protruding portion of the isolation structure 11 Ϊ́3 top surface, and: isolation structure 110 points , the block is distributed in the opening 1 (10). The material of the wide gate 120 is, for example, doped polysilicon. The floating gate 12 〇 and ^ 200818514 21558t\vf.doc / n 108 side wall is for example set There is a tunneling dielectric layer 118. The material of the tunneling dielectric reed 118 is, for example, hafnium oxide. The source region 125 is disposed in the substrate 1 at the bottom of the opening 108. The source region 125 is, for example, containing phosphorus and arsenic. The doped region of the N-type dopant. The source line 130 is disposed on the substrate just in the strip, extends across the protrusion 113 of the isolation structure, extends in the Y direction, and is electrically connected to the source region 125. The material of the epipolar line 130 is, for example, doped polysilicon. An interlayer dielectric layer 128 is disposed between the source line 13A and the # gate 1G. The material of the interlayer I 128 is, for example, oxidized; ^ 或 or ^ oxidized ♦ nitride 11 / oxidized second composite dielectric material. A protective layer may also be disposed above the source line 13A, and the material thereof is, for example, yttrium oxide. The S 字 word line 140 is disposed on the substrate 丨 (8) outside the source line 13 ,, approximately parallel to the source line 130, and disposed across the isolation structure 11 。. The word line 140 is symmetrically disposed on the source line 丨3〇, and the i-shaped one of the word lines 14 is omitted. The word line 14A, for example, is provided with a dielectric layer m between the substrate 100, and the material thereof is, for example, [a oxidized stone dielectric material for isolating the word line 140 from the substrate 1 (8). + Since the height difference between the depressed portion 115 of the isolation structure U0 and the substrate 100 is small, there is no problem that the uniformity is not good across the word line 14〇 disposed above it. That is, even at the periphery of the memory cell array, the line width of the word line 140 can approximately maintain the same line width as the sub-line 140 of the center of the memory cell array. Thereby, it is possible to maintain the power % of the memory element, and to increase the yield of the product. The following describes a manufacturing method of a non-volatile memory according to an embodiment of the present invention. The method of manufacturing a non-volatile memory is shown in the following figure. FIG. 2A to FIG. 2D are schematic cross-sectional views showing the manufacturing process of the non-volatile memory. Referring to Figure 2A, the method first provides a substrate 2, such as a ruthenium substrate. A plurality of isolation structures 21A have been formed on the substrate 200, and the isolation structures 210 define an active region 205 extending in the X direction. The isolation structure 210 is, for example, a shallow trench isolation structure or a field oxide layer made of, for example, hafnium oxide, and is formed by, for example, a high density plasma chemical vapor deposition method. The top surface of these isolation structures 210 is higher than the top surface of the active area 2〇5. In one embodiment, the top surface of the isolation structure 210 is, for example, about 11 angstroms above the top surface of the substrate 200 of the active region 205. The substrate 2 may also be provided with a pad 211 which is formed, for example, during the fabrication of the isolation structure 21A. The material of the underlayer 211 is, for example, oxidized stone, and the forming method is, for example, a chemical vapor deposition method. Then, referring to FIG. 2A, a mask layer 213 is formed on the substrate 200 to cover the isolation structures 210. The material of the mask layer 213 is, for example, tantalum nitride, tantalum carbide or tantalum carbonitride, and the formation method thereof is, for example, a chemical gas phase deposition method. In an embodiment, the thickness of the mask layer 213 is, for example, 3600 i angstroms. A portion of the mask layer 213 on the active region 205 and a portion of the substrate 200 are then removed to form an opening 208. At this time, part of the mask layer 213 above the isolation structure 210 is also removed. In one embodiment, the depth of the opening 2〇8 (the distance between the bottom of the opening 208 and the top surface of the substrate 200) is, for example, 2000 angstroms. Then, referring to FIG. 2A, FIG. 2B and FIG. 2C, a tunneling dielectric layer 218 is formed on the inner wall of the opening 208. The material of the tunneling dielectric layer 218 is, for example, 11 200818514 r -r - 21558 twf.doc / n 疋 疋 其 其 其 其 其 其 南 南 南 南 南 南 南 南 南 南 南 南 南 南 南 南 南 南 南 南 南 南 南 南 南 南 南 南 南 南 南 南Quality. Next, a floating gate 220 is formed on the sidewall of the opening 208. The top of the floating gate 220 is lower than the top surface of the isolation structure 210 and higher than the top surface of the substrate 200. The top of the floating gate 220 has an angular structure, for example. . The floating gate 220 is formed by, for example, filling a layer of a conductor (not shown) in the opening 208. The top surface of the conductor layer has a recess and is lower (the top surface of the isolation structure 210 is higher than the top surface of the substrate 200). The material of the conductor layer is exemplified as a ruthenium-doped polysilicon, which is formed by, for example, chemical vapor deposition using a field implant dopant. Then a spacer 223 is formed on the sidewall of the opening 208. With the spacer 223 as a mask, a part of the conductor layer is removed, that is, the floating gate 22 is formed. The method of removing a part of the conductor layer includes a dry engraving method. Since the top surface of the conductor layer is lower than the isolation structure 215, The subsequently formed floating gate 220 can be formed by the separation of the isolation structure 215 to form the block-shaped floating gate 220 without forming through lithography. I then 'see FIG. 2B' on the substrate 200. An interlayer dielectric layer 228 is formed thereon to cover the floating gate 220. The material of the interlayer dielectric layer 228 is, for example, oxidized oxide, which is formed by, for example, high-temperature thermal oxidation deposition followed by rapid thermal tempering. . The interlayer dielectric layer 228 may also be a composite dielectric layer formed of a plurality of dielectric materials, such as yttrium oxide-nitriding seconds-oxidized oxide. Then, a source region 235 is formed in the substrate 200 at the bottom of the opening 208. The source region 235 is, for example, a doped region having an N-type dopant such as phosphorus or arsenic, and the germanium 12 2 558 twf.doc/n 200818514 is, for example, an ion implantation method. Thereafter, the interlayer dielectric at the bottom of the opening 208 is removed. The layer 228 and the tunnel dielectric layer 218 expose the substrate 200 at the bottom of the opening 208. The method of removing the interlayer dielectric layer 228 and tunneling the dielectric layer 218 is, for example, a wet-drying method, which is, for example, hydrofluoric. The acid is a rhyme. Then, a source line 240 is formed in the opening 208, the source line 240 is horizontal, and the isolation structure 210 extends in the γ direction. The material of the source line 24 is, for example, doped polysilicon, metal, metal deuteration. A conductive material such as a material is formed by a chemical vapor deposition method, and then a protective layer 245 is formed on the source line 24'. The protective layer 245 is made of a dielectric material such as oxidized oxidized stone, and the forming method is, for example, gas discrimination. Phase deposition or silking. After that, remove the cover The curtain layer 213 exposes the substrate 2 (10) of the isolation structure 21A and the active region 2〇5. Of course, if the germanium layer 211 is formed on the substrate 200, the entire layer 211 is exposed. Next, please refer to FIG. 2C for the removal source. A portion of the isolation structure 210' outside the polar line forms a recess 217 in the isolation structure 21, and the bottom of the recess 217 is approximately equal to or higher than the top surface of the substrate 2. In an embodiment, the bottom of the recess 217 is, for example, high. The top surface of the substrate 2 is about 2 Å to Å. The method of removing the partial isolation structure 200 to form the recess 217 is, for example, forming a layer patterned photoresist on the substrate 200, and exposing the source. A portion of the isolation structure 21 两 on both outer sides of the line 240. Then, the depressed portion 217 is formed by patterning the layer and the screen' by removing the partial spacer 210' by dry etching. The patterned photoresist layer is then removed. Next, referring to Fig. 2D, the base of the source line 24 is on the upper side and the upper surface is i Γ. The word line 250 is approximately parallel to the source line 240 and extends across the isolation structure 2H)', particularly across the isolation structure of the isolation structure = 200818514 21558twf.doc/n portion 217. The word line 250 is formed by, for example, forming a conductor layer (not shown) on the substrate 2 to cover the protective layer 245 and the isolation structure 210. Then, the conductor layer on the protective layer 245 is removed. Then, an insulating spacer 253 is formed on the sidewall of the source line 240, and the insulating spacer 253 is used as a mask to remove the exposed conductor layer to form the word line 250.
由於源極線240外側之隔離結構21〇已經被移除了一 部份，凹陷部217與基底200之間的高度落差縮小，因此， 在形成字元線250的過程中，能夠改善蝕刻速率不均的問 題，進而得以提高字元線250的均勻度。即使是在記憶胞 陣列周邊的字元線250,其與陣列中央的字元線25〇相比， 兩者線寬相差小於2%。字元線250的均勻度提高，連帶 地會增加元件的電性表現。 此外，因為源極線240外側之隔離結構21〇的高度降 低，所以，在蝕刻導體層形成字元線250之時，不會二隔 離結構21G的側壁留下導體層的殘留物，而免除相i字元 線25^產生短路的機會，有助於提昇產品的良率。Since the isolation structure 21〇 on the outer side of the source line 240 has been removed, the height difference between the recess 217 and the substrate 200 is reduced, so that the etching rate can be improved during the formation of the word line 250. The problem of uniformity, in turn, improves the uniformity of the word line 250. Even in the word line 250 around the memory cell array, the line width differs by less than 2% from the word line 25A in the center of the array. The uniformity of the word line 250 is increased, which in turn increases the electrical performance of the component. In addition, since the height of the isolation structure 21A outside the source line 240 is lowered, when the word line 250 is formed by etching the conductor layer, the sidewall of the second isolation structure 21G does not leave a residue of the conductor layer, and the phase is eliminated. The i-character line 25^ has the opportunity to create a short circuit, which helps to improve the yield of the product.
伯叮、^所述’本發明制厚度高低交替的隔離結構，不 -可以稭此形成自行對準式的浮置雜 線的圖案均勻度，增進元件的電性表現。0叫同子凡 ί之保相㈣倾社巾料__界定者為 14 200818514 21558twf.doc/n 【圖式簡單說明】 圖1是繪示本發明一實施例之一種非揮發性記憶體的 立體結構剖面圖。 圖2A至圖2D是繪示本發明一實施例之一種非揮發性 記憶體的製造流程立體剖面圖。 【主要元件符號說明】 100、200 :基底 105、205 ··主動區 110、210 :隔離結構 108、208 :開口 111 :介電層 113 :凸出部 115 :凹陷部 118、218 :穿隧介電層 120、220 :浮置閘極 128、228 :層間介電層 125、235 :源極區 130、240 :源極線 135、245 :保護層 140、250 :字元線 211 :墊層 217 :凹陷部 223 :間隙壁 253 :絕緣間隙壁 15According to the invention, the isolation structure of the thickness of the invention is not uniform, and the pattern uniformity of the self-aligned floating noise can be formed to improve the electrical performance of the component. 0 is the same as the child of the ί 保 ( 四 四 四 四 四 四 四 四 四 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 A three-dimensional structure sectional view. 2A to 2D are perspective cross-sectional views showing a manufacturing process of a non-volatile memory according to an embodiment of the present invention. [Main component symbol description] 100, 200: substrate 105, 205 · active region 110, 210: isolation structure 108, 208: opening 111: dielectric layer 113: protrusion 115: recess 118, 218: tunneling Electrical layers 120, 220: floating gates 128, 228: interlayer dielectric layers 125, 235: source regions 130, 240: source lines 135, 245: protective layers 140, 250: word lines 211: pads 217 : recessed portion 223 : spacer 253 : insulating spacer 15