TW200818501A - Metal layer inducing strain in silicon - Google Patents

Abstract

A metal layer (62), especially a metal compound, induces strain into a gate channel (16) of a MOS transistor (60). Compressive strain of over 4GPa is available from sputter deposited TiN. The amount of strain can be controlled at least up to 11GPa, for example, by wafer biasing. The compressive strain may induce compressive strain in a PMOS channel when deposited around the channel and induce tensile strain in an NMOS channel when deposited over the channel.

Description

200818501 IX. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to semiconductor elements and their formation. More specifically, the present invention relates to a semiconductor element having strained silicon and a metal layer deposited by sputtering to strain the crucible. [Prior Art] Continued progress can be described by Moore's Law, and Moore's Law also points out that the number of components in the most advanced integrated circuit chips will double every 18 months. Today, an advanced integrated circuit contains billions of transistors. The continued progress of the integration is mainly accomplished by reducing the size of the individual active components of the integrated circuit. Advances in photolithography have partially contributed to this progress, but other aspects, such as shallower and more highly doped junctions, and low dielectric constants are also required. At this time, 65 nanometer (nm) components have entered mass production, while 45 nanometer components are still in development. One advantage of the reduction in size is that the operating speed of the switching transistor increases as the size decreases. It is necessary to continue this trend in the integration. However, such progress will be increasingly difficult and may require more fundamental changes. Recently, the use of components with strain enthalpy has been introduced. This strain promotes the manufacture of faster transistors without the need to achieve an equivalent reduction in actual size. It is known to have a higher hole mobility than unstrained strained silicon (C(). On the other hand, the tensile strain 矽 (tensile strained 5 200818501) compared to the unstrained treatment

Silicon) has a higher electron mobility. Part of the conventional technique for introducing strain involves a layer of germanium and an epitaxial growth of a layer of germanium (SiGe). Due to the different lattice constants of the two materials, the layer grown thereafter will grow with built-in stress as long as its thickness is not too large. In one technique, the crucible re-grows in the source and the drain region of the recess, and transmits the strain to the middle gate channel. Recently developed technologies include chemical vapor deposition (CVD) of a dielectric layer (such as tantalum nitride or hafnium oxide) deposited under conditions in which nitrides or oxides are strained.矽 Above. The stress in the dielectric layer can be at least partially transferred to the crucible to affect the mobility of the Shi Xizhong. Figure 1 is a cross-sectional view showing an example of a metal-oxide-semiconductor transistor, which may also be called a metal oxide half field effect transistor (M0SFET; MOS field). Effect transistor). Since the first embodiment of the present invention is implemented in a p-type metal oxide semiconductor (PMOS) transistor, the doping type suitable for pm 〇 S will be described. However, this description can also be applied to an n-type MOS transistor, as long as the doping type is simply reversed. A PM0S transistor 10 is formed on the surface of a stone substrate 12 having a lightly doped «-type well formed by ion implantation on its surface. The PM0S transistor 10 is surrounded by a shallow trench isolation (STI) 14 which is an oxide stone accumulated in a trench of the stone substrate 1 2 by the light yellow trench isolation. Formed in the evening. Shallow trench isolation 14 surrounds one or a particular number of transistors to electrically isolate them from other transistors. The gate of the transistor is formed by a gate, a first (G) 16 formed in the surface of the substrate 1? I Z · well 200818501. A thin gate oxide 18 is deposited on the channel 16 or formed after the channel 16 is oxidized, and a heavily doped polysilicon gate electrode 20 is deposited and defined in the gate oxide. Above the object 8. The sides of the polysilicon gate electrode 20 can be oxidized to form a liner 22. A nitride spacer 24 and its extension legs are formed around the gate electrode 2''. The structure can be adjusted to a flash memory formed by including an oxide-nitride oxide (〇N〇) tunneling memory cell in the gate electrode 20. f' Before the lining 22 and the spacer 24 are formed, the gate electrode can function as an implant mask, which is doped and implanted at a mid-degree angle to the deeper The shallow extensions 30, 3 2 of the source and drain electrodes (s and D) 34, 36, wherein the gate spacers 24 are used as a mask, and by a higher dose of P-type dopant Ion implantation and later forming a source of ice and no pole. Nickel ohmic contacts 40, 42, 44 are formed on the polysilicon gate electrode 2 and the germanium source and drain electrodes 34, 36 by depositing a nickel layer and annealing the nickel layer. To form a germanide (underneath), to provide an ohmic contact between the stone and the later formed metallizations. An etch stop layer 50 and a front metal dielectric layer 52 are deposited conformally (typically by chemical vapor deposition) over the gate electrode 20 and the planar region of the substrate 12. Generally, the residual termination layer is composed of tantalum nitride having a composition of SisN4, and the front metal dielectric layer 52 is composed of cerium oxide (Si〇2, commonly referred to as oxidized oxide eve). In advanced components, a dielectric of low dielectric constant is formed by doped yttrium oxide. During the etching of the holes, the front metal dielectric layer 52 is first passed through, and then through the etch stop layer 50, and then, a gold 7

200818501 The genus method (for example, tungsten) is used to fill the holes to form a source of no (uη 1 an ded) contact with the immersive contact 5 4, 5 6 , and a gate contact, with some techniques The strain is introduced as shown in Figure 1. In one technique, the source 34 and the drain 3 6 may be formed in the region of the crucible, wherein the niobium alloy is epitaxially re-grown in the engraved region of the crucible substrate. The compressive strain introduced by the crucible can be transmitted to the channel 16, and the strain is also generated by the channel 16, wherein the crucible is separated from the smaller lattice spacing (pseudomorphic). In another technique described in U.S. Patent No. 2005/025 5 667 to Arghavani et al., the shallow trench isolation 14 oxide is grown in a tensile strain pattern and the tensile strain is introduced into the MO S body 10. In another technique described in U.S. Patent Publication No. 2006/0 1 603 1 4, the disclosure of which is incorporated herein by reference. Under the condition, the nitride etch stop layer 5 grows and generates strain. The oxide liner 22 or the precursor metal dielectric layer 52 induces the strained oxime ohmic contact layer 4〇, 42, 44 to grow to induce strain, although the technique for inducing strain can be effectively increased] Mobility, and the speed of the integrated circuit is cut, but today's technology 4 produces a maximum of about 3GPa stress furnace, χ ^ stress of this force, however, when stress 1 is adjacent to the layer, bee sting Transfer to the bottom... Force: The second level will usually be greatly reduced: the product, and the structure: a few payments: „This stress induces, what is the 4th. For the reduction of the distance between the advanced gates, prepare a few t ^ The body circuit and θ are sufficient. The future oxide-induced strain layer change) is enough for the future generation of the circuit generation system to be the stress and strain point 5 8 〇 shows the alloy and passes the pseudo-crystal Li Gongzhong The special opening strip can be self-contained, and the sub-segment has a surface that is sent to 0 with a shortage of |. 8 200818501 [Invention] The strain can be induced by a metal layer of a metal compound deposited adjacent to the transistor. Into a 0 S transistor or other The metal compound may be a metal nitride. The titanium nitride grown by plasma reactive sputtering has a compressive strain of 4 GPa and greater. For example, a compressive strain metal layer of titanium nitride is When deposited around the channel rather than deposited over the channel, it induces compressive strain into a MOS gate channel, which is advantageous for a PMOS transistor. f. Alternatively, when nitriding When titanium is deposited on the channel, it induces tensile strain into a MOS gate, which is advantageous for an NMOS electro-crystalline system. [Embodiment] According to an embodiment of the present invention, the metal layer is deposited. Adjacent to a channel, a high and controllable level of strain is transmitted to the channel. The strain can be selected to increase carrier mobility in the semiconductor channel. An example of a metal layer can be titanium nitride (TiN), The titanium nitride is deposited by reactive bonds, also known as physical vapor deposition (PVD). The clock conditions can be controlled to deliver a desired strain level to the channel. The strain level can be up to -12 GPa. Reactive It is repeatedly observed in the sputtered titanium nitride, and the strain level is far beyond the currently available -3 GP a of the strain-inducing layer of yttrium oxide and tantalum nitride formed by chemical vapor deposition. An embodiment of the strained MOS transistor 60, as shown in the cross-sectional view of Fig. 2, a metal compression layer 62 is formed around the gate electrode 20 to provide compressive strain. By virtue of this geometric configuration, the metal compression layer The compressive strain of 62 will cause the underlying helium to produce tensile strain, which in turn will push against the imperfections around the gate channel 16, thereby inducing the desired 9 200818501 compressive strain in the channel. The compressive strain will increase in the semiconductor channel. The mobility of the holes in l6, and thus the speed of the p-type MOS transistor. The compression layer 62 is formed, for example, of titanium nitride, and the titanium nitride is reactively sputtered to have a desired compression ratio t. The initial results show that titanium nitride can grow and have a stress of up to 10 GPa, which far exceeds the strain-inducing layer @ 3GPa currently available from oxidized stone and gasification. ^化钦 is a well-known village material. It can also be used to form a barrier layer (-Η) in the through-hole, and the through-hole passes through the inteMevei dielectric layers of the upper metal layer in the integrated circuit. When formed by reactive plating, the titanium nitride has a strain characteristic of known #, and usually the strain is regarded as a negative effect because it lowers reliability.

f K

In the illustrated embodiment, a metal compression layer 62 is deposited over the nitride etch stop layer 50. Other structures are also possible. For example, the etch stop layer 50 may be replaced by a oxidized stone layer, and the oxygen... has little or no strain, but may have a conductive feature underneath: - an insulating layer. However, the embodiment of ' has the advantage of having a suitable amount of tensile strain for growth and extending adjacent to the two sides of the electromagnet to provide the desired tensile strain iJ body. The metal compression layer 62 is then grown in the region of the nitride layer 5 on the nitride PMOS transistor, and this growth is produced by the tensile stress that is greater than the nitride that is overcompensated on the PMOS transistor: force Go on. Thus, as desired, the PM〇s transistor is under compressive strain: and the NMOS transistor is under tensile strain. Alternatively, the metal layer 52 can be deposited with a suitable amount of variation, and the tensile strain can be compensated by the high compression of the metal magic layer 62, and by 10 200818501 degrees. Unlike tantalum oxide or tantalum nitride, titanium nitride has a suitably high conductivity' and is therefore considered a metal and is not considered a dielectric. Therefore, the titanium nitride compression layer 62 must be patterned to avoid The metal contacts 54, 56, 58 do not short the contact of the filler metal. The strain-inducing layer of the germanide contact of the prior art avoids this short circuit problem because it is located on the expected conductive path' and has been Contact isolation. Patterned etching of titanium nitride can be performed by techniques developed for the name of the name, for example, using a chlorine-based plasma. In US Patent Publication No. 2004/0074869, Wang et al. A further embodiment of the present invention is described in the cross-sectional view of Fig. 3, which is based on U.S. Patent Publication No. 2005/0282329 to Li et al. and Kudo et al. U.S. Patent Publication No. 2004/0 1 42546 The shape of the alternative replacement gate is described. The geometric effect causes the compressed titanium nitride to induce tensile strain in the underlying gate channel, which is particularly valuable for NM0S transistors, while NM0S transistors It can be paired with a PMOS transistor in a conventional CMOS integrated circuit that is widely used in advanced logic circuits as described above. An alternative gate Μ 电 S transistor can be similar to the polysilicon gate electrode used in FIG. The initial step of the crystal is fabricated. However, the polysilicon gate electrode 20 is one of the sacrificial electrodes to be removed. A cross-sectional view of the alternative gate transistor 7A as shown in Fig. 3 The spacers 24 are formed around the polycrystalline silicon gate electrode, the source and drain electrodes have been implanted, and the source and drain ohmic contacts 4, 4 4 are deuterated, and a dielectric layer 7 2 is deposited. Above the surface, and planarizing the spacer 24 and the top end of the sacrificial polycrystalline silicon gate 11 200818501 pole, for example by chemical mechanical polishing. The dielectric layer 72 may comprise an etch stop layer, but main Consisting of a low dielectric constant dielectric as a front metal dielectric. The polysilicon is then removed from between the spacers 24. Before the formation of the sacrificial gate electrode or after its removal, a thin A high dielectric constant gate dielectric layer 74 is formed on the bottom surface of the hole. Exemplary high dielectric constant dielectrics may be hafnium oxide (HfO), zirconium oxide (ZrO), and aluminum oxide (Al203). The gate electrode layer 76 is deposited over the gate dielectric layer 74. The gate electrode layer 76 can be formed of a metal or metal alloy selected to be ζ-, for the doping pattern of the gate channel 16. It has an appropriate work function, for example, titanium hydride (TiSi) for NMOS transistors or titanium aluminide (TiAl) for PMOS transistors. In accordance with this embodiment of the invention, a compressively strained metal layer 78 is formed over the gate electrode layer 76. As described above, titanium nitride is a preferred material for the compression inducing metal layer 78. One or more of the layers 74, 76, 78 may be preserved in a conformal manner on the sidewall of the aperture and possibly on the outside of the spacer 24, depending on the deposition procedure and the point in time at which the procedure is performed. For example, a metallized metal of aluminum is deposited via physical vapor deposition (PVD) to fill and overfill the remainder of the hole. The chemical mechanical polishing method i (CMP) removes the metallized metal outside the hole leaving a gate contact with the metal 80. Further processing procedures will be formed in the source and anode contacts 54, 56 in Figure 2. However, in other procedures, the dielectric layer 72 will be removed and replaced by another one. The compressive strain layer 78 of titanium nitride is located above the gate channel 16 and causes the gate channel 16 to have tensile strain in the reaction, which is desirable for NM0S transistors. Thus, the strain-inducing layer of the same composition and the strain of the same type are dependent on the geometry of the strain-inducing layer and the channel to induce a tensile 丄 或 knife or compressive force in the 矽 channel. The transistors 60, 7 〇 π, and J in FIGS. 2 and 3 are respectively applied to the PMOS and NMOS transistors of the integrated circuit, or the NMOS and NMOS gate transistors 70 can be used for the NMOS transistor. And other ways to see, 丨

~ Used to provide the desired compressive strain in a PMOS transistor. Furthermore, the inducing metal layer can be combined with other methods of providing the same or opposite strain as well as station, Q, such as those mentioned in the prior art section. Strain-induced nitride and yttrium oxide layer of conventional techniques, typically

Deposited by chemical vapor deposition. The inductive metal layer of the present invention is deposited economically and ingeniously by sputtering from a metal target. A plasma sputtering reaction chamber 90 is schematically illustrated in the cross-sectional view of Fig. 4.

Vacuum reaction: t 92 contains a pedestal electrode 94 a fulcrum of a crystal, and a material relative to the target 98 of the wafer 96 is sputtered onto the wafer %. For the Tibetan mineralized nitrite, at least the surface of the dry material 98 is composed of titanium. The vacuum reaction chamber 92 is typically electrically grounded and supports the dry material 98 via a separator. The <il power supply 1 2 is electrically biased under the target of 98 to a negative voltage at about 6 Torr to 8 VDC to support a plasma in the vacuum reaction chamber 92. A vacuum pumping system 104 draws the vacuum reaction chamber to a base pressure in the microTorr range or lower. An argon gas source 106 supplies argon gas to the vacuum reaction chamber 92 via the mass flow controller 108 to act as a sputtering working gas. When the argon pressure in the vacuum reaction chamber 92 is in the low milliTorr range, a negative voltage is applied to the target relative to the grounded reaction chamber or the shielded shield chambers (not shown). 98 can excite argon gas into a plasma. The positively charged argon ions are attracted to the negatively biased target 9 8 and the titanium atoms are sputtered from the target 9 8 13 200818501. Some of the titanium atoms sputtered will strike the wafer and plate the Wafer. The magnetic control 110 is disposed on the back surface of the target 98 and typically includes an inner magnetic pole 1 12 of magnetic polarity and a strong outer pole 114 around a relative polarity to generate a magnetic field adjacent to the sputtering surface of the target 98. In order to increase the male and the degree of the plasma, and thereby increase the sputtering rate. A relatively small magnetron 110 will rotate along the central axis of the reaction chamber to provide more uniform target erosion and wafer plating. For a high target power and a small, strong magnetron, a substantial amount of sputtered atoms will be ionized. A primary power source 161 aurically biases the pedestal electrode 94 via a capacitive coupling circuit 丨丨8 to generate a negative direct current self-bias on the wafer 96 to accelerate argon gas and The target ions move toward the wafer 96. The nitriding of the nitriding can be achieved by a nitrogen gas source 12 其 which supplies nitrogen gas to the vacuum chamber 92 via another mass flow controller 1 2 2 . In a process known as reactive money plating, nitrogen will react with the trapped titanium atoms to form a titanium nitride layer on the surface of the wafer 96. A series of titanium nitride films were grown under six different sets of sputtering conditions by sputtering the reaction chamber as shown in Figure 4. The stress of the films and their sheet resistance rs are then measured. The results depicted in Figure 5 show that the stress generated in the titanium nitride can be adjusted between -1 GPa and -12 GPa by appropriate control of the sputtering conditions. Therefore, the stress and the magnitude of 4PGa and more or even 7 GPa or more can be easily and controllably determined in comparison with the limitation of 3 GPa. The impedance of the titanium nitride film is as large as possible. However, the experiment pointed out that there is a major exception. The sheet resistance varies inversely with the compressive force between the range of 18 to 75 ohms per square. More systematic experiments were carried out by means of a bare-metal wafer, and the voltage-voltage plating of the magnetically-coated tube was supposed to be approximately or 14 200818501 = 300 thermally oxidized on the wafer. On the nanometer thick yttrium oxide, a high strain titanium nitride film is grown. As shown in the graph shown in Fig. 6, on a substrate having a thickness of between 20 and 100 nm, the substrate has two thicknesses but small but measurable compressive stress changes and both The equivalent stress is thinner than the thin geometric layout expected for the next 10 generations. The film can also be grown on two substrates applied to the pedestal electrode at different RF bias powers. > Figure 7, compressive stress Ο

The maximum value is generated ☆ without the condition T of wafer/pressure power, and the compressive stress decreases as the bias power increases. The difference observed between the substrate materials is very small. The titanium nitride of the present invention does not need to be a purely stoichiometric titanium oxide compound, however, it may have varying amounts of titanium and nitrogen as long as the final material = electrically conductive and can be viewed For a metal. Titanium nitride can contain other elements in S as long as titanium and nitrogen are the two largest atomic components. In particular, some oxygen can replace nitrogen. K, the invention is not limited to titanium nitride. Other layers containing strain-inducing metals may also be used, such as a metal nitride such as tantalum nitride or tungsten nitride. Other examples of metals include other refractory metals such as strontium (Sr), hafnium (Hf), vanadium (V), niobium (Nb), button (Ta), chromium (Cr), and molybdenum (ruthenium). For the purposes of the present invention, "Shi Xi is not considered to be a metal component in the strain inducing layer because neither tantalum nitride nor ruthenium oxide is electrically conductive. Although the strain inducing metal layer is advantageously applied to a MO S electric body to increase the mobility in the channel, it can also be applied to a semiconductor device that is advantageous for variation. It will be appreciated that niobium may be doped or alloyed, for example, by adding niobium as long as the final material exhibits a pure tantalum band structure and general mobility characteristics. 15 200818501 The strained layer of the present invention can be deposited in other sputtering reaction chambers, such as a sputtering reaction chamber containing a radio frequency coil for the plasma source region. CVD grown films may also provide the required strain under suitable growth conditions. The present invention thus makes it possible to utilize a material that is conventionally deposited and can be deposited from a more economical source to allow a greater and controllable amount of strain to enter the day. The above are only the preferred embodiments of the present invention, and are not intended to limit the scope of the present invention; all other equivalent changes or modifications which are not departing from the spirit of the present invention should be included in the following patents. Within the scope. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view of a conventional metal oxide semiconductor (MOS) transistor; FIG. 2 is a cross-sectional view of a first embodiment of the MOS transistor of the present invention having a surrounding gate channel a metal strain inducing layer; Fig. 3 is a second embodiment of the MOS transistor of the present invention having a metal strain inducing layer over the gate channel; and Fig. 4 is a schematic cross-sectional view of a sputtering reaction chamber It can be used in combination with the present invention; Fig. 5 is a graph showing the relationship between the compressive stress and the sheet resistance for showing the relationship between the compressive stress and the sheet resistance of the titanium nitride film under the sputtering condition; The relationship between compressive stress and thickness is used to show the relationship between compressive stress and thickness produced by different thicknesses of titanium nitride film deposited on different substrates; and Figure 7 is the compressive stress and different wafer bias The power relationship diagram is used to show the relationship between the compressive stress generated by the titanium nitride film deposited on different substrates and the different wafer bias powers. 16 200818501

[Main component symbol description] 10 transistor 12 chopping substrate 14 shallow trench isolation 16 channel 18 gate oxide 20 gate electrode 22 pad 24 spacer 30, 32 extension portion 34 source 36 drain 40, 42, 44 ohm contact (layer) 50 etch stop layer/nitride 52 front metal dielectric layer 54 (source) contact 56 (drain) contact 58 (gate) contact 60 transistor 62 compression layer 70 transistor 72 dielectric layer 74 Gate dielectric layer 76 Gate electrode layer 78 Metal layer/strain layer 80 Contact metal 90 Reaction chamber 92 Vacuum reaction chamber 94 Base electrode 96 Wafer 98 Target 100 Isolation body 102 Power supply 104 Vacuum extraction system 106 Argon Gas source 108 mass flow controller 110 magnetron 112 inner magnetic pole 114 outer magnetic pole 116 RF power 118 capacitive coupling circuit 120 nitrogen gas source 122 mass flow controller 17

Claims (1)

200818501 X. Patent application scope: 1. A metal-oxide-semiconductor (MOS) transistor comprising: a substrate comprising a channel region of a semiconductor germanium; and a strain inducing layer, the strain induction The layer is a metal compound formed on the substrate and located in a region of the channel region with strain and induced strain in the channel region. C 2 The transistor of claim 1, wherein the metal compound is a nitride. 3. The transistor of claim 2, wherein the metal compound comprises gasified ruthenium. 4. The transistor according to any one of claims 1 to 3, wherein the substrate further comprises: a p-type (p -1 ype) source and a non-polar region, the One side of the channel region, wherein the strain inducing layer is formed on a side of the channel region. The transistor according to any one of claims 1 to 3, wherein the substrate further comprises: an n-type (η -1 ype) source and a drain region, respectively One side of the channel region, and wherein the strain inducing layer is formed directly on the center of one of the channel regions. 6. The electro-crystal 18 200818501 according to any one of claims 1 to 3, wherein the strain is one of compressive strain having an intensity value of at least 4 GPa (4 billion Pascals). 7. The transistor of claim 6, wherein the compressive strain has an intensity of at least 7 GPa. 8. The transistor of any one of claims 1 to 3, wherein the substrate further comprises: an fx η source source and a drain region, each of which is located on one side of the channel region Wherein the strain is a compressive strain, and wherein the strain inducing layer is formed directly on a center of the channel region. 9. A strained MOS transistor comprising: a substrate comprising a channel region of a semiconductor germanium; and a strain inducing layer, the strain inducing layer being titanium nitride, the strain inducing layer being formed on the substrate And located in a region of the channel region 'and induces strain in the channel region. (V1 0. The transistor of claim 9, further comprising: a p-type source and a drain region, respectively formed on one side of the channel region, and wherein the strain inducing layer is Formed on the side of the channel region and not directly on a center. 1 1. The transistor according to claim 9 or 10, further comprising: an n-type source and a drain region And the system is formed on one side of the channel region 19 200818501, and wherein the strain inducing layer is directly formed on the center of one of the channel regions. 12. A method for inducing strain in a crucible, the method comprising: Sputter deposition deposits a strain inducing layer comprising a metal compound on a substrate to form a region adjacent to a channel region of one of the MOS transistors formed in the germanium substrate and inducing strain therein. The method of claim 12, wherein the metal compound comprises a metal nitride. The method of claim 13, wherein the metal nitride comprises titanium nitride. 1 5 . If you apply for a patent The method of any one of clauses 1 to 4, wherein the metal compound is deposited in a plasma sputtering chamber having a pedestal electrode to support the chopping substrate And the substrate is in a relative position of a dry material, the material comprising a metal of the metal compound. The method of claim 15, wherein the target comprises a titanium sputtering a surface, and additionally comprising introducing nitrogen into the plasma sputtering chamber. The method of claim 15, wherein the bias power applied to the one of the susceptor electrodes is selected such that The strain in the metal compound reaches a predetermined level. 20 200818501 1 8 The method of claim 15, wherein the metal compound comprises titanium nitride, and the predetermined level of strain has a strength of at least 4 GPa 〇 19 The method of claim 18, wherein the MOS transistor is a PMOS transistor, and the strain inducing layer is deposited on a side of the channel region rather than directly above it. For example, the 18th item of patent application The method, wherein the MOS transistor is an NMOS transistor, and the strain inducing layer is directly deposited on the channel region. 21. The method according to any one of claims 12 to 14 The method wherein the strain is a compressive strain.