200818414 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種陶瓷基板結構及其製法，尤指一 種在陶兗板中敢埋半導體晶片之陶曼基板結構及其製法。 【先前技術】 ，隨現代各式電子產品輕薄短小化之發展趨勢，業界係 將半導體晶片埋人封裝基板中以因應此—趨勢。另一方 面陶究材料亦由於其揚氏係數（Y〇ung’s驗灿奶）較一 般有機材料大’具有較佳剛性，而被應用於基板之製作。 目前業界大多數之陶㈣料製作，係採用諸如鈦酸鎖、氧 化銘等之粉末，先調製成膏狀之陶兗生胚，再經高溫燒結 而成再者，運用陶瓷基板以嵌埋半導體晶片之製程，係 將半V體曰a片等肷埋於陶瓷基板中，復於該陶瓷基板上進 行增層製程以形成與該半導體晶片電性連接之線路，藉以 形成嵌埋半導體晶片之電路板結構。 馨 由於陶兗基板具有較佳剛性，可以承受一定程度以下 之應力而不變形，因此可應用於一些核心板兩表面具有不 對稱增層結構的基板，而不會產生翹曲（wa卬age);然而， 由於陶瓷基板亦具有脆性，承受一定程度以上之應力即發 生龜裂（crack) ’其抗彎曲強度較差，一般以陶瓷材料製作 之核心板板材（panel)兩表面若形成不對稱的增層結構，由 於其產生不對稱之總應力可能超過該陶瓷板材所能承受應 力之限度，遂發生板材龜裂，因而無法進行後續之製程。 因此，目前習知技術難以適用大尺寸薄型基板板材之 19640 5 200818414 ,· 製作，而僅適用於小型模組或封裝。 、、匕如何提出一種後埋半導體晶片之陶兗基板技 β ’以避免習知採用陶£基板作爲半導體晶片承載件所引 =的，路板結構抗-曲強度差以使陶板無法適合大尺 r的缚型基板之缺失，實爲目前業界亟待克服之課題。 【發明内容】 ％ θ鑑於上述習知技術之種種缺點，本發明之主要目的在 :提仏種瓜埋半導體晶片之陶瓷基板結構及其製法，得 以增加該電路板結構之抗彎曲強度。 —本毛月之又一目的在於提供一種嵌埋半導體晶片之 嘉板、口構及其製法，以避免不對稱的增層製程中結構 產生遇曲，也減少發生板材龜裂的可能性，以適合大尺寸 薄型基板嵌埋晶片之製作。 、口大尺寸 n - =明之再一目的在於提供一種嵌埋半導體晶片之. =基板結構及其製法，其不需以調製陶究生胚，再經高 4結來製造陶兗基板，得以簡化製程與節省成本。 為達上述及其他目的，本發明揭露一種嵌埋半導體晶 1之陶兗基板結構之製法，主要係包括··提供—承載板， 5亥承载板具有一結合層，並且右 I/、有兩虱化金屬層分別形成於 二層之兩表面上’於該承载板之至少—氧化金屬層中 少一開口，以露出部分之結合層；於該開口中容置 一 +導體晶片’該半導體晶片係具有__主動表面及對應之 主主動表面’該主動表面具有複數個電極塾，且該非主動 表面係位於該結合層上；於該具有容置半導體晶片之開口 19640 6 200818414 的氧化金屬層之表面及該半導體晶片之主動表面上形— 介電層；以及於該介電層内形成複數個導電盲孔，^於士 介電層上形成-線路層，該導電盲孔係電性連 = 與該半導體晶片主動表面之電極墊。 線路層 、上述結構之製法，復包括於該介電層與該線路層 成一增層結構，以形成一多層電路板。 ^ 么:結構之製法’復包括於該承载板之兩 載=承載板中形成至少-導電通孔，以電： 遷接孩承载板兩侧之增層結構。 括製法，其中，該承载板之製造方法係包 兩孟屬板’並於該兩金屬板之—表面分別 金屬層丄提供—結合層於該兩金屬板之兩氧化金屬 “二槿Γ進行壓合’以形成一五層結構板；以及去除該 五層、、口構板兩表面之金屬層， — 其間之結合層所構成之承載板/以乳化至屬層及 ’構，復=:種嵌埋半導體晶片之陶变基板結 兩气、^ 7载板’ δ亥承载板具有一結合層，並具有 二；氡：ϋ分別形成於該結合層之兩表面上，且於至少 屬層中具有至少—開口，以露出部分之結合 體晶片係’係容置於該開口中，該半導 面具有複數Γ電 ρ Α 亥非主動表面係位於該結合層 氡^2層，係形成於該具有容置半導體W之開口的 孔化金屬層之表面及該半導體晶片之主動表面；以及一線 19640 7 200818414 路層’係形成於該介電層上， 於該介電層内，該導電盲孔係 體晶片主動表面之電極墊。 與複數個導電盲孔，係形成 电性連接該線路層與該半導 ，上述之結構，復包括至少_增層結構，係形成 η層與該線路層上，以形成—多層電路板。 … ”結構’復包括該承载板之兩侧 f，且至少一導電通孔’係形成於該承載板内，以電』：200818414 IX. Description of the Invention: [Technical Field] The present invention relates to a ceramic substrate structure and a method of manufacturing the same, and more particularly to a Tauman substrate structure in which a semiconductor wafer is buried in a ceramic plate and a method of manufacturing the same. [Prior Art] With the development trend of light and thin modern electronic products, the industry has buried semiconductor wafers in package substrates to cope with this trend. The other ceramic material is also used in the fabrication of substrates because its Young's coefficient (Y〇ung's milk) is more rigid than conventional organic materials. At present, most of the pottery (four) materials in the industry are made of powders such as titanate lock and oxidized ingot, which are first prepared into a paste-like pottery embryo, and then sintered at a high temperature, and a ceramic substrate is used to embed the semiconductor. The process of the wafer is to embed a semi-V body 曰 a piece or the like in a ceramic substrate, and perform a build-up process on the ceramic substrate to form a circuit electrically connected to the semiconductor chip, thereby forming a circuit for embedding the semiconductor chip. Board structure. Because the ceramic substrate has better rigidity, it can withstand a certain degree of stress without deformation, so it can be applied to some substrates with asymmetric augmentation structure on both surfaces of the core plate without warping. However, since the ceramic substrate is also brittle, it is cracked when subjected to a certain degree of stress, and its bending strength is poor. Generally, the surface of the core plate made of ceramic material is asymmetrically increased. The layer structure, because the total stress generated by the asymmetry may exceed the limit of the stress that the ceramic plate can withstand, and the plate crack occurs, so that the subsequent process cannot be performed. Therefore, the conventional technology is difficult to apply to the large-sized thin substrate sheet 19640 5 200818414, and is only suitable for small modules or packages. How to propose a ceramic substrate technology for semiconductor chip embedded in the semiconductor technology to avoid the conventional use of the ceramic substrate as a semiconductor wafer carrier, the resistance of the road plate structure is not strong enough to make the ceramic plate suitable for large-scale The lack of r-type substrate is an urgent problem to be overcome in the industry. SUMMARY OF THE INVENTION In view of the above disadvantages of the prior art, the main object of the present invention is to improve the ceramic substrate structure of the semiconductor wafer and the method of manufacturing the same, thereby increasing the bending strength of the circuit board structure. - Another objective of this month is to provide a slab, a mouth structure and a method for fabricating the same, in order to avoid the occurrence of curvature in the asymmetric build-up process and to reduce the possibility of cracking of the sheet. It is suitable for the fabrication of large-size thin substrate embedded wafers. The large size of the mouth n - = Ming is to provide a buried semiconductor wafer. = Substrate structure and its preparation method, which does not need to modulate the green embryo, and then manufacture the ceramic substrate through the high junction, which is simplified Process and cost savings. To achieve the above and other objects, the present invention discloses a method for fabricating a ceramic substrate structure in which a semiconductor crystal 1 is embedded, mainly comprising: providing a carrier plate, the 5 sea carrier plate having a bonding layer, and the right I/, having two The deuterated metal layers are respectively formed on two surfaces of the two layers: at least one opening in the metal oxide layer of the carrier plate to expose a portion of the bonding layer; and a + conductor wafer is accommodated in the opening The active surface has a plurality of electrode electrodes, and the active surface is located on the bonding layer; and the metal oxide layer having the opening 19640 6 200818414 for accommodating the semiconductor wafer Forming a dielectric layer on the surface and the active surface of the semiconductor wafer; and forming a plurality of conductive blind vias in the dielectric layer, forming a circuit layer on the dielectric layer, the conductive blind via electrical connection = An electrode pad with an active surface of the semiconductor wafer. The circuit layer, the method for fabricating the above structure, is further included in the dielectric layer and the circuit layer to form a layered structure to form a multilayer circuit board. ^: The structure of the structure is included in the load-bearing plate of the load-bearing plate to form at least - conductive through-holes to electrically: migrating the build-up structure on both sides of the load-bearing plate. The method for manufacturing the carrier plate comprises: applying a two-layered plate and providing a metal layer on the surface of the two metal plates - bonding the two metal oxide plates to the two metal plates Combining 'to form a five-layer structural board; and removing the metal layer of the five layers, the two surfaces of the mouth plate, the carrier layer formed by the bonding layer therebetween / emulsified to the genus layer and the structure, complex =: species The ceramic substrate embedded with the semiconductor wafer has two gas, and the seventh carrier plate has a bonding layer and has two layers; 氡: ϋ are respectively formed on both surfaces of the bonding layer, and are in at least a layer Having at least an opening, the exposed portion of the bonded wafer system is disposed in the opening, the semi-conductive surface having a plurality of ρ Γ 非 非 非 非 非 非 位于 位于 位于 位于 位于 位于 , a surface having a perforated metal layer accommodating the opening of the semiconductor W and an active surface of the semiconductor wafer; and a line 19640 7 200818414 being formed on the dielectric layer, the conductive via hole in the dielectric layer Electrode wafer active surface electrode And the plurality of conductive blind vias are electrically connected to the circuit layer and the semiconductor. The above structure comprises at least a build-up structure, and the η layer and the circuit layer are formed to form a multilayer circuit board. The "structure" includes both sides f of the carrier board, and at least one conductive via hole ' is formed in the carrier board to electrically:
接該承載板兩側之增層結構。 丈 本發明之後埋半導體晶片之陶莞基板結構及其製 法，主要係由承餘之兩氧化金屬層與其間之結合層 =之豐合結構，以增㈣承餘之結構強度。該兩氧化金 萄層之剛性可以抵抗後續不對稱增層製程中產生之不平 應力’以避免產生龜曲，且該結合層之純能夠吸收部份 該不平衡應力，以減少板材發生龜裂的可能性。The layered structure on both sides of the carrier plate is connected. The structure of the ceramic substrate and the method for manufacturing the semiconductor wafer after the invention are mainly based on the rich structure of the bonded metal oxide layer and the bonding layer between them to increase the structural strength of the bearing. The rigidity of the gold oxide layer can resist the uneven stress generated in the subsequent asymmetric layer-growth process to avoid the occurrence of tortuosity, and the pureness of the bonding layer can absorb part of the unbalanced stress to reduce cracking of the sheet. possibility.
本發明之嵌埋半導體晶片之陶瓷基板結構及其製 法’其中該承載板之製造方法，係以氧化製程來生成_ 基板’而不需以習知技術之調製陶竟生胚’再經高溫燒結 來製造陶瓷基板，得以簡化製程與節省成本。 【實施方式】 ，以下係藉由特定的具體實施例說明本發明之實施方 式，熟悉此技藝之人士可由本說明書所揭示之内容輕易地 瞭解本發明之其他優點與功效。 (製法實施例） 本叙明之肷埋半導體晶片之陶瓷基板結構及其製 8 19640 200818414 法，主要係提供_ 形成於該結合該承載板具有一結合層及分別 ^ 3兩相對表面之兩氧化金屬層，後續復可於 =1氧化金屬層形成至少一開口以露出部分之結合 於所形成的開σ中放置半導體晶片，之後復可於該 载線路製程以形成本發明之陶曼基板結構。 :i閱第1Α至1Ε圖，係為本發明之喪埋半導體晶片 之陶究，板結構之製法第一實施例之剖面示意圖。 •〜如第1A圖所示，首先，提供一第一金屬板100及一 弟一孟屬板102,該第一及第二金屬板1〇〇，1〇2係為銘板； 於該第一金屬板100之一表面形成-第-氧化金屬層 101’並於該第二金屬才反1〇2之一表面形成一第二氧化金屬 s 103 "亥兩金屬板之一表面係進行氧化製程以形成氧化 紹之第-及第二氧化金屬層1〇1，1〇3，且該氧化製程係在 電解槽中進行。 如第1B圖所示，提供一結合層1〇4於該兩金屬板 鲁100，102之兩氧化金屬層1〇1，1〇3之間，並進行壓合，以形 成一五層結構板1〇,該結合層1〇4之材料可選自熱固性樹 脂或膠體。 ^ 如弟1C圖所示，利用例如餞刻（以心匕幻製程移除該第 一及第一金屬板1〇〇, 1〇2(即未氧化之部分），以形成一由第 一氧化金屬層101、結合層104及第二氧化金屬層1〇3所 構成之承載板10’。 如第1D圖所示，於該第一氧化金屬層1〇1中運用例 如蝕刻或挖槽（routing)製程以形成至少一第一開口 1〇1&以 9 19640 200818414 j該結合層m之-部份，並於該第―開口⑼ 一弟一半導體晶片11，該第一丰 曰 今 動表面1U及對應之非主動表面Ub，：該-主 具有複數電極墊110，且該非主動表面m係接置於= 一開口购中露出之結合層104之表面 第该弟 化金屬層ΠΠ之表面及該第一半導體元件弟一乳 11a上形成-介電層且使該介電層謂填充第一 開口難與第一半導體元件η飞間的間隙中，以 一半導體兀件11固定於該第一開口 1〇13中。如第，圖 所示，亦可於形成該介電層170前，於該第一開口 101: 與該第一半導體晶片11之間的間隙中填充一黏著材料 u，以將該第一半導體晶片11固定於該第一開口 101a中。 如第1E圖所示，復於該介電層17〇上形成一線路層 171a，並於該介電層170中形成複數個導電盲孔i7ib 導電盲孔171b係電性連接該線路層171&與該半導體晶片 11之主動表面11a。接著於該介電層17〇表面及該線路層 171a表面上進行增層製程以形成一增層結構19，該增層結 構19係包括有至少一介電層19〇、至少一疊置於該介電層 190上之線路層191 a，以及複數形成於該介電層1中之 導電盲孔191b，且該導電盲孔191b電性連接至該第一半 導體晶片11之電極墊Π 0，並於該增層結構19外表面形 成複數電性連接墊191c。又於該增層結構19上形成一防 焊層20，且該防焊層2〇中具有複數開孔200以露出該增 層結構19之電性連接墊i91c。 10 19640 200818414 . 另請參閱第2圖，本發明亦可於該第二氧化金屬層103 上形成另-增層結構19,，並於承載板1()，内形成有至少一 導電通孔18以電性連接該增層結構19，19,，該增層结構 19,外表面形成複數電性連接墊19U，，又於該增層結構19, 上形成-防焊層20，，且該防焊層2〇，中具有複數開孔2〇〇· 以露出該增層結構19,之電性連接墊191c,。 ^復請參閱第3圖，本發明亦可於該第二氧化金屬層103 馨形成有一第二開口 103a，並於該第二開口 l〇3a中容置一 第二半導體晶片12，其後續之製程係形成一介電層17〇，、 一線路層171a，、導電盲孔171b’，與一增層結構19，，可參 考前面相關說明而得知，故於此不再贅述。 〆 (結構實施例） 本叙明亦提供一種後埋半導體晶片之陶瓷基板結 構，如第1D圖所示，係包括：一承載板丨〇，，該承載°板1 〇， 具有一結合層104,該結合層1〇4之兩表面分別具有一第 氧化金屬層101及第二氧化金屬層1〇3，且該第一氧化 金屬層101中具有至少一第一開口 1〇la以露出部分之結合 層104;至少一第一半導體晶片U係容置於該第一開口。 101a中，該半導體晶片u係具有一主動表面iu及對應 之非主動表面11b，其中，該半導體晶片之非主動表面ub 係位於該結合層104上；一介電層17〇，係形成於該第一 氣化金屬層101之表面及該半導體晶片11之主動表面 11a ’且該介電層no可填充於該第一開口 i〇la與第—半 導體元件11之間的間隙中，以將該第一半導體元件u固 19640 11 200818414 定於該第一開口 10〗a _。如第I〇t圖所 :電㈣前，以一黏著材料13填充於該第二： +導體晶片”之間的間隙中，以將該 日日片11固定於該第一開口 1〇u中。 蛉體 …如第1E圖所示’本發明之結構復包括一線路層 係形成於該介電層170上，與複數個導電盲孔⑺: 成於該介電層m中，該導電f孔171b 線路 層171a與該半導體晶片η之主動表面lla。 線路 另外，本發明之結構復包括一增層結構19， 該介電層no*面及該線路層心表面上 層二 19係包括有至少一介電層跡至少一疊置於該介電=90 上之線路層191a，以及形成於該介電層19〇中之導子 191b，且該導電盲孔191b電性連接至該第一半導體晶目片 11之電極塾110,並於該增層結構19外表面形成複數曰曰電性 連接墊19U，又包括一防層2〇,係形成於該增層結構Μ 上，且該防焊層20中具有複數開孔2〇〇以露出該增層結 19之電性連接墊191c。 另請參閱第2圖，本發明之結構復可包括另一增層結 構19’，係形成於該第二氧化金屬層1〇3上，並具有至少一 V電通孔18形成於該承載板10内，以電性連接該增層結 構19，19，且該增層結構〗9,外表面具有複數電性連接塾 191c’ ’又包括一防焊層20,，係形成於該增層結構19，上， 且該防焊層20’中具有複數開孔200’以露出該增層結構} 之電性連接墊19U，。 12 19640 200818414 m 復請參閱第3® ’本發明之結龍可包括於該第 化金屬層103形成有一第二開口 l〇3a，並於該第二開口 103a中容置_第二半導體晶片12，其後續之結構係包括— ;丨私層17〇、一線路層171a,、導電盲孔171b，，與一增層 結構19，可翏考前面相關說明而得知，故於此不再贅述。 相車乂於習知技術，本發明之嵌埋半導體晶片之陶 板結構及其製法，主要係由承載板之兩氧化金屬層與其『二 之t合層所構成之疊合結構，明強該承載板之結構強 度。該兩氧化金屬層之剛性可以抵抗後續不對稱增層製程 中產生之不平衡應力’以避免產生翹曲，且該結合層之 性則能夠吸收部份料平衡應力，以減少板 ^ ^ 可能性。 霉衣的 本發明之嵌埋半導體晶片之陶瓷基板結構及其製 法，其中該承载板之製造方法’係以氧化製程來：成陶变 基板’而不需以習知技術之調製陶瓷生胚’再經高溫燒结 籲來製造陶瓷基板，得以簡化製程與節省成本。 、° 上述實施例僅為例示性說明本發明之原理及其功 效，而非用於限制本發明。任何熟習此項技藝之人士均可 在不違背本發明之精神及範訂，對上述實^例進行修飾 與變化。因此，本發明之權利保護範圍，應如後述之申許 專利範圍所列。 月 【圖式簡單說明】 第1Α至1Ε圖係為本發明之喪埋半導體晶片之電路板 之實施例之流程圖； 19640 13 200818414 制二圖係為本發明之實施例對應於第⑴圖之另一 表》ίτ，具中，—与 的間隙中填充；屬層之開口與半導體晶片之間 口中· 4者材料，以將該半導體晶片固定於該開 例，=圖f月之嵌埋半導體晶片之電路板之實施 — /一氧化金屬層表面形成另一增層結構；以及 2圖係為本發明之嵌埋半導體晶片之電路板之 =中，第二氧化金屬層嵌埋半導體晶片並形成另1 【主要元件符號說明】 10 五層結構板 10， 承載板 100 第一金屬板 101 第一氧化金屬層 101a 第一開口 102 第二金屬板 103 弟二氧化金屬層 103a 第二開口 104 結合層 11 第一半導體晶片 lla，12a 主動表面 llb，12b 非主動表面 110,120 電極墊 12 第二半導體晶片 19640 14 200818414 13,131 黏著材料 18 導電通孔 19,191 增層結構 190,170,1701 介電層 191a,171a，171af 線路層 19 lb, 191b’，171b，171b，導電盲孔 191c,191c1 電性連接墊 20,20， 防焊層 ⑩ 200,20(^ 開孔 15 19640The ceramic substrate structure of the embedded semiconductor wafer of the present invention and the method for manufacturing the same, wherein the method for manufacturing the carrier plate is to form an _substrate by an oxidation process without using a conventional technique to prepare a ceramic preform and then to be sintered by high temperature. The ceramic substrate simplifies the process and saves costs. The embodiments of the present invention are described below by way of specific embodiments, and those skilled in the art can readily appreciate the other advantages and advantages of the present invention from the disclosure. (Production Example) The ceramic substrate structure of the buried semiconductor wafer of the present invention and the method thereof are generally provided as a metal oxide formed on the carrier sheet having a bonding layer and two opposite surfaces respectively. The layer is subsequently formed by forming at least one opening in the =1 oxidized metal layer to deposit the semiconductor wafer in the exposed σ formed by the exposed portion, and then multiplexed in the carrier circuit process to form the terrarium substrate structure of the present invention. Fig. 1 is a cross-sectional view showing a first embodiment of a method for manufacturing a buried structure of a semiconductor wafer of the present invention. • As shown in FIG. 1A, firstly, a first metal plate 100 and a first and a second plate 102 are provided, and the first and second metal plates 1 and 2 are used as name plates; One surface of the metal plate 100 is formed with a first-oxidized metal layer 101' and a surface of one of the two metal plates is formed on one surface of the second metal surface to be oxidized. The first and second oxidized metal layers 1 〇 1, 1 〇 3 are formed, and the oxidation process is carried out in an electrolytic cell. As shown in FIG. 1B, a bonding layer 1〇4 is provided between the two metal oxide layers 1〇1, 1〇3 of the two metal plates 100, 102, and is pressed to form a five-layer structural board. 1〇, the material of the bonding layer 1〇4 may be selected from a thermosetting resin or a colloid. ^ As shown in FIG. 1C, the first and first metal plates 1 〇〇, 1 〇 2 (ie, unoxidized portions) are removed by, for example, engraving to form a first oxidation. The carrier layer 10' composed of the metal layer 101, the bonding layer 104 and the second metal oxide layer 1〇3. As shown in FIG. 1D, for example, etching or trenching is applied to the first metal oxide layer 1〇1. a process for forming at least a first opening 1〇1 & 9 19640 200818414 j the portion of the bonding layer m, and at the first opening (9) a young semiconductor wafer 11, the first Feng Wei current surface 1U And corresponding non-active surface Ub, the main body has a plurality of electrode pads 110, and the non-active surface m is connected to the surface of the bonding layer 104 exposed in an opening, and the surface of the deuterated metal layer Forming a dielectric layer on the first semiconductor device 11a and exposing the dielectric layer to a gap between the first opening and the first semiconductor element η, and fixing the semiconductor device 11 to the first opening 1〇13. As shown in the figure, before the formation of the dielectric layer 170, the first opening 101: filling a gap between the first semiconductor wafer 11 and an adhesive material u to fix the first semiconductor wafer 11 in the first opening 101a. As shown in FIG. 1E, the dielectric layer is overlying the dielectric layer A circuit layer 171a is formed on the substrate, and a plurality of conductive vias i7ib are formed in the dielectric layer 170. The conductive vias 171b are electrically connected to the circuit layer 171& and the active surface 11a of the semiconductor wafer 11. The surface of the dielectric layer 17 and the surface of the circuit layer 171a are subjected to a build-up process to form a build-up structure 19, the build-up structure 19 includes at least one dielectric layer 19, at least one of which is stacked on the dielectric layer. a circuit layer 191a on the 190, and a plurality of conductive vias 191b formed in the dielectric layer 1, and the conductive vias 191b are electrically connected to the electrode pads 0 of the first semiconductor wafer 11, and A plurality of electrical connection pads 191c are formed on the outer surface of the layer structure 19. A solder resist layer 20 is formed on the build-up structure 19, and the plurality of openings 200 are formed in the solder resist layer 2 to expose the electricity of the build-up structure 19. Sex connection pad i91c. 10 19640 200818414 . See also Figure 2, this issue An additional build-up structure 19 may be formed on the second oxidized metal layer 103, and at least one conductive via 18 is formed in the carrier 1 (1) to electrically connect the build-up structure 19, 19, The build-up structure 19 has a plurality of electrical connection pads 19U formed on the outer surface, and a solder resist layer 20 is formed on the build-up structure 19, and the solder resist layer 2 has a plurality of openings 2 The second connection opening 103a is formed in the second oxidized metal layer 103, and the second opening 103a is formed in the second oxidized metal layer 103, and the second opening 103a is formed in the second oxidized metal layer 103. A second semiconductor wafer 12 is received in the opening 10a, and a subsequent process is formed by forming a dielectric layer 17A, a wiring layer 171a, a conductive blind via 171b', and a build-up structure 19, which can be referred to It is known from the previous description, so it will not be described here.结构 (Structural Embodiment) The present invention also provides a ceramic substrate structure of a buried semiconductor wafer, as shown in FIG. 1D, comprising: a carrier plate, the carrier plate 1 〇 having a bonding layer 104 The two surfaces of the bonding layer 1 〇 4 respectively have a second oxidized metal layer 101 and a second oxidized metal layer 1 〇 3, and the first oxidized metal layer 101 has at least one first opening 1 〇 1a to expose a portion thereof. The bonding layer 104; at least one first semiconductor wafer U is received in the first opening. In 101a, the semiconductor wafer u has an active surface iu and a corresponding inactive surface 11b, wherein the inactive surface ub of the semiconductor wafer is located on the bonding layer 104; a dielectric layer 17 is formed in the semiconductor layer a surface of the first vaporized metal layer 101 and an active surface 11a' of the semiconductor wafer 11 and the dielectric layer no may be filled in a gap between the first opening i〇1a and the first semiconductor element 11 to The first semiconductor element u solid 19640 11 200818414 is fixed to the first opening 10 _a _. As shown in the first figure: before the electric (four), an adhesive material 13 is filled in the gap between the second: + conductor wafers to fix the sunday piece 11 in the first opening 1〇u The body of the present invention is as shown in FIG. 1E. The structure of the present invention includes a wiring layer formed on the dielectric layer 170, and a plurality of conductive via holes (7): in the dielectric layer m, the conductive f The hole 171b is provided with the circuit layer 171a and the active surface 11a of the semiconductor wafer η. In addition, the structure of the present invention further includes a build-up structure 19, the dielectric layer no* surface and the upper layer of the circuit layer upper layer 19 includes at least a dielectric layer trace is disposed at least on the wiring layer 191a on the dielectric = 90, and a derivation 191b formed in the dielectric layer 19?, and the conductive via 191b is electrically connected to the first semiconductor An electrode 塾110 of the crystal substrate 11 and a plurality of electrical connection pads 19U formed on the outer surface of the layered structure 19, further comprising a protective layer 2〇 formed on the build-up structure ,, and the solder resist The layer 20 has a plurality of openings 2 〇〇 to expose the electrical connection pads 191c of the build-up junctions 19. See also Figure 2, the present invention The structure may include another build-up structure 19' formed on the second oxidized metal layer 1 〇 3 and having at least one V via hole 18 formed in the carrier 10 to electrically connect the build-up structure 19, 19, and the build-up structure -9, the outer surface has a plurality of electrical connections 塾 191c ′′ and further includes a solder resist layer 20 formed on the build-up structure 19, and the solder resist layer 20 ′ The electrical connection pad 19U having a plurality of openings 200' to expose the buildup structure}. 12 19640 200818414 m Please refer to the 3® 'The knot of the present invention may be included in the first metal layer 103 to form a first a second opening 103a, and accommodating the second semiconductor wafer 12 in the second opening 103a, the subsequent structure comprising - a private layer 17?, a wiring layer 171a, a conductive blind hole 171b, and A build-up structure 19 can be referred to in the foregoing description, and thus will not be described herein. The conventional technology, the ceramic plate embedded semiconductor wafer of the present invention and the method for manufacturing the same are mainly carried by a carrier plate. The combination of the two metal oxide layers and the combination of the two layers of T, Mingqiang The structural strength of the plate. The rigidity of the two metal oxide layers can resist the unbalanced stress generated in the subsequent asymmetric build-up process to avoid warping, and the properties of the bond layer can absorb the balance stress of the partial material to reduce [^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ The modulating ceramic green embryo' is then subjected to high temperature sintering to manufacture a ceramic substrate, which simplifies the process and saves cost. The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person skilled in the art can modify and change the above embodiments without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the scope of the claims as described later. BRIEF DESCRIPTION OF THE DRAWINGS [Fig. 1 to 1] is a flow chart of an embodiment of a circuit board for a buried semiconductor wafer of the present invention; 19640 13 200818414 The second embodiment of the present invention corresponds to the (1) figure of the embodiment of the present invention. Another table, ίτ, is filled with a gap in the gap between the opening and the opening of the layer and the semiconductor wafer, to fix the semiconductor wafer to the opening example, and the embedded semiconductor of FIG. The implementation of the circuit board of the wafer - the surface of the metal oxide layer forms another build-up structure; and the second figure is the circuit board of the embedded semiconductor wafer of the present invention, wherein the second metal oxide layer embeds the semiconductor wafer and forms 1 [Major component symbol description] 10 Five-layer structure board 10, carrier board 100 First metal board 101 First oxide metal layer 101a First opening 102 Second metal board 103 Young metal dioxide layer 103a Second opening 104 Bonding layer 11 first semiconductor wafer 11a, 12a active surface 11b, 12b inactive surface 110, 120 electrode pad 12 second semiconductor wafer 19640 14 200818414 13,131 adhesive material 18 conductive via 1 9,191 build-up structure 190, 170, 1701 dielectric layer 191a, 171a, 171af circuit layer 19 lb, 191b', 171b, 171b, conductive blind holes 191c, 191c1 electrical connection pads 20, 20, solder resist layer 10 200, 20 (^ Opening 15 19640