TW200818204A - Mixed-use memory array with different data states and method for use therewith - Google Patents

Abstract

A mixed-use memory array with different data states and a method for use therewith are disclosed. In one preferred embodiment, a memory array is provided comprising a plurality of memory cells, each memory cell comprising a memory element comprising a switchable resistance material configurable to one of at least three resistivity states. A first set of memory cells uses X resistivity states to represent X respective data states, and a second set of memory cells uses Y resistivity states to represent Y respective data states, wherein X ≠ Y.

Description

200818204 IX. Description of the invention: [Prior Art] When the memory unit is still shaped to be converted into a certain characteristic of a memory element system that can be erased and achieved, or the memory memory The unit's electricity, such as a data non-volatile memory array, even when the device power is turned off. In a single-programmable memory array, each record is in an initial unprogrammed state and can be stylized. This change is permanent and cannot be erased. In other types of memory, the memory is single and can be rewritten multiple times. The δ-hexene unit can also be changed in the memory form I and medium of each memory unit. The data state can be stored by changing the detectable memory bank, such as flowing through the current under a threshold voltage of a transistor within a predetermined applied voltage. A data state is one of the memory cells with a different value of π 〇 π or a data "1." Some: The scheme for achieving an erasable or multi-state memory cell is complicated. For example, & The SQ memory cell operates by storing a charge in which the stored charge of the μ is present, does not exist, or the amount of charge changes by a threshold voltage of the transistor. The memory cells are three-terminal devices, in the case of a modern integrated circuit Under the very small size of f force, their memory is relatively difficult to manufacture and operate. Other memory cells operate by changing the electrical potential of relatively exotic materials (such as chalcogen). In most semiconductor production (4) Among them, chalcogen is difficult to use and can be challenging. The depletion is provided by a two-column erasable or multi-state memory formed by a structure that is easy to scale to a small size using a semiconductor material 121890.doc 200818204. Advantages. Swinging memory array [Invention] The present invention is made by the following claims, / ^ ^ bh rfe ,, and (4) in this paragraph should not be regarded as Limitation of the claim. By way of introduction, the preferred embodiment described below provides a mixed use of the right and different states of the material, and a method of using the same. item

In the specific embodiment of the car master, the invention provides a plurality of arrays, including a plurality of ^^^, which includes a component, the memory component including configurable to small Two cats + ^ A switchable resistive material of at least two of the resistivity states. A first group - ... a ° ° 匕 兀 兀 兀 兀 兀 兀 兀 兀 兀 兀 兀 兀 兀 兀 兀 兀 兀 兀 兀 兀 兀 兀 兀 兀 兀 兀 兀 兀 兀 兀 兀 兀 兀 兀 兀 兀 兀 兀 兀 电阻 电阻 电阻 电阻Wherein X ... reveals other specific embodiments, and each of the conjugates can be used alone or in combination. Preferred embodiments will now be described with reference to the drawings. [Embodiment] It is known that by applying an electric pulse, the resistance of a resistor formed by doped polysilicon can be trimmed and adjusted between stable resistance states. These trimmable resistors have been used as components in an integrated circuit. However, it is not customary to use a trimtable polysilicon resistor in a non-volatile memory cell to store data. It is difficult to fabricate a memory array of a polysilicon resistor. If a resistor is used as a memory cell in a large cross-point memory array, then when a voltage is applied to 121890.doc 200818204 a selected memory cell, there will be an unwanted leakage across the memory array. More than half of the selected and unselected memory units. For example, please refer to FIG. 1 ' assuming that a voltage is applied between the bit line B and the word line A to set, reset or sense the selected memory cell S. The current is intended to flow through the selected memory unit S. However, a leakage current can flow through the alternate memory cells υι, U2, and U3 over an alternate path (for example, between bit line B and word line A). There are many such alternative paths that can exist. By forming the mother-memory unit as a two-terminal device including a diode, the leakage current can be greatly reduced. The diode has a nonlinear p V (current-voltage) characteristic that allows a very small amount of current flow below the turn-on voltage and a higher current flow to the turn-on voltage. In general, diodes are also used as check valves to make it easier to travel in one direction than in the other. Therefore, as long as the selected biasing scheme ensures that only the selected memory cell is subjected to a forward current higher than the turn-on voltage, the non-predetermined routing can be greatly reduced (such as U1-U2-U3 in Figure 1 Leakage current for normal path). U.S. Patent Application Serial No. 10/955,549, filed on Sep. 29, 2004, to s.

Dielectric Antifuse Having High-and Low-Impedance States" (hereinafter referred to as the '549 application and incorporated herein by reference) describes a single-chip three-dimensional memory array in which a semiconductor junction-polar crystal semiconductor The resistivity state of the material stores the data of the memory cell. This memory unit is a single-programmed memory unit with two types of data. The diode is formed in a high resistivity state; the application of a stylized voltage causes the diode to be permanently transformed into a low resistivity. 121890.doc 200818204 In a particular embodiment of the invention, three types of memory elements (such as the fifth half of the pleading: body diode) formed by the doped semiconductor material can be achieved by applying appropriate electrical pulses. Four or more stable resistivity values. In other embodiments of the present invention, the semiconductor material can be converted from an initial high resistivity state to a lower resistivity state; then, under application of an appropriate electrical pulse, Return to the higher resistivity state. The specific embodiments may be used individually or in combination to form a memory unit that can have two or more states and can be single-programmed or rewritable. As described above, the inclusion of _ diodes between the conductors of the memory unit allows for > in the array of intersections and memory. In the preferred embodiment of the present invention, the 'subsequent' polycrystalline, amorphous or microcrystalline semiconductor memory device is formed to be connected in series to the diode, or more preferably, to form the diode itself. % In this discussion, the escaping from the higher resistivity state to the lower resistivity state will be referred to as the set "transition, which is affected by the set current, the set voltage, or the set T-shoot; from the lower resistivity state The inverse of the higher resistivity state will be referred to as a "reset" transition, which is affected by reset current, reset voltage, or reset pulses. In a preferred single-programmed embodiment, A polycrystalline semiconductor diode disk - octagonal /, electrical rupture anti-fuse pairing, however, in other embodiments 'an anti-fuse can be omitted. Figure 2 Green does not form a memory according to a preferred embodiment of the present invention The bottom conductor 12 is formed of a conductive material (for example, tungsten) and extends toward a first direction. The barrier layer and the adhesive layer may be included in the bottom conductor 12. 121890.doc 200818204

The compound 6, the semiconductor diode 2 has an intended undoped; and a bottom heavily doped n-type region 4; an intrinsic region top heavily doped region 8, however the orientation of the diode can be reversed. Regardless of the orientation of the diode, it will be referred to as a diode. In some embodiments, a dielectric rupture antifuse 14 is included. The top conductor 16 can be formed in the same manner and material as the bottom conductor 12 and < different from the first direction in one of the second directions. The polycrystalline semiconductor diode 2 is vertically disposed between the bottom conductor 12 and the top conductor 16. Qiu Fu: The semiconductor diode 2 is formed to be in a high resistivity state. The memory cell can be formed on top of a suitable substrate. For example, a single crystal wafer is overlaid on the wafer. Figure 3 illustrates a portion of the memory level of the device formed in the parent fork memory array, the body 12 and Between the top conductors 16 (in this figure, the memory is stacked on a substrate and the memory array is stacked. The middle diode 2 is arranged in the bottom lead to omit the anti-refining wire 14). A plurality of layers can be formed to form a high density monolithic film. A region of the semiconductor material that is intended to be undoped is described as an _essential region. However, those skilled in the art will appreciate that, in practice, the essence may include - low concentration p-type or n-type dopants. The dopant may extend from adjacent regions into the intrinsic region' or may be due to deposition from earlier deposition during deposition; dyeing is present in the deposition chamber. It should be further understood that the deposited semi-inorganic material (such as % may include defects, causing it to be slightly η-doped, using the term "essence" to describe 矽, 锗, 矽 gold or some other half The ## material is not intended to imply that this region does not contain any dopants' and is not intended to imply this: it is completely electrically neutral. The doped polycrystalline or microcrystalline semiconductor can be made by applying appropriate electrical pulses. 121890.doc 200818204 Material The resistivity of (e.g., 矽) changes between steady states. It has been found that, in a preferred embodiment, it is advantageous to cooperate with the diode to bias forward only under a forward bias, while the diode is It is easier to achieve and control the reset transition under reverse bias. However, in some cases, the diode can be reverse biased to achieve a set transition, and the diode is forward biased to achieve a reset transition. The switching behavior of the semiconductor is complicated. For the diode, the diode has achieved both set transition and reset transition under forward bias. Generally, the reset pulse applied by the one body under forward bias is applied. (its foot The amplitude of the polycrystalline semiconductor material constituting the diode from a predetermined resistivity state to a higher resistivity state is lower than a corresponding set pulse (which switches the same polycrystalline semiconductor material from the same resistivity state) To a lower resistivity state) and have a longer pulse width. Switching under reverse bias exhibits a different behavior. Assume a polycrystalline indiode (like the diode shown in Figure 2) A relatively long switching pulse is applied under reverse bias. After the switching pulse is applied, a smaller read pulse (e.g., 2 volts) is applied, and the measurement flows through a current at the read voltage (referred to as a read current). As the voltage of the switching pulse under reverse bias increases in the post-signal, the subsequent read current is changed by two volts, as shown in Figure 4. It will be understood that initially with the reverse voltage and the switching pulse The electric grab is large, § the read current increases when the read voltage is applied after the mother-switching pulse, that is, the initial turn of the semiconductor material (in this case, the semiconductor material system) in the set direction The variable line is oriented towards a lower resistivity. Once the switching pulse reaches a certain reverse bias voltage (the point in Figure 4, in this example is 121890.doc 200818204 about -14.6 volts), the read current suddenly begins to drop, the reason is achieved Reset and increase the resistivity of the Shishi. When the reverse bias switching pulse is applied, the switching voltage (at this switching voltage, the set trend is reversed and the diode is reset) depends on (for example) The resistivity state of the bismuth of the diode changes. Next, it will be understood that by setting the appropriate voltage, the diode can be set to reverse the bias voltage to achieve the setting or resetting of the semiconductor material constituting the diode. The distinct data state of the memory cell of the present invention corresponds to the resistivity state of the polycrystalline or microcrystalline semiconductor material constituting the diode, which is detected by flowing through the memory cell when a read voltage is applied ( The current between the top conductor 16 and the bottom conductor 12 is discerned. Preferably, the current flowing between any of the distinct data states and any of the different data states is at least 2 factors to allow for differences between states to be easily detectable. The memory unit can be used as a single-programmable memory unit or a rewritable β-single unit, and can have two, three, four or more kinds of sorrows. Under forward bias and reverse bias, the memory cells can be converted from any data state to any other data state in any order. • Several examples of preferred embodiments will be provided. However, it should be understood that they have no limit intent. Those skilled in the art will appreciate that other methods for programming a two-terminal device, including a diode and a polycrystalline or microcrystalline semiconductor material, are within the scope of the present invention. A single-programmed multi-level memory cell 121890.doc -12-200818204 / In the preferred embodiment of the invention - a diode formed by a polycrystalline semiconductor material and a dielectric rupture anti-fuse Arranged in series and arranged between the top and bottom conductors. The two-terminal device is used as a single-programmable multi-bit memory, which is preferably implemented in three or four data states. Figure 2 illustrates a preferred memory unit. The diode 2 is preferably formed of a polycrystalline or micro-conductor material, for example, a stone, a wrong, or a stalk and/or a faulty port. More preferably, the diode 2 is a multi-layered germanium. In this example, the bottom heavily doped region 4 is of the type 11 and the top heavily doped region 8 is shaped, however the polarity of the diode can be reversed. The memory unit includes a portion of the top conductor, a portion of the bottom V body, and a diode disposed between the conductors. When formed, the double crystal body 2 of the polycrystalline silicon is in a high resistivity state, and the 'I electrical cracking reversely soluble filament 14 is intact. Figure 5 is a graph showing the probability of current flow in a memory cell in various states. Referring to FIG. 5, when a read voltage (for example, 2 volts) is applied between the top conductor 16 and the bottom conductor 12 (with the one body 2 under forward bias), the top conductor -6 and the bottom conductor The read current flowing between i 2 is preferably in the range of naamper, for example, less than about 5 nanoamperes. The area v on the graph of Fig. 5 corresponds to the first data state of the memory unit. For some memory cells in the memory array, this memory cell will not be pulsed or reset, and this state will be taken as a data state for one of the memory cells. This first data state will be referred to as the V state. A first electrical pulse is applied (preferably with diode 2 under forward bias) between 121890.doc 13 200818204 between top conductor 16 and bottom conductor 丨2. This pulse is, for example, between about 8 volts and about 12 volts, for example, about 10 volts. The current system is, for example, between about 8 〇 microamperes and about 200 microamperes. The pulse width is preferably between about 1 nanosecond and about 500 nanoseconds. The first electrical pulse causes the dielectric rupture anti-fuse bucket to rupture and switches the semiconductor material of the diode 2 from a first resistivity state to a second resistivity state, the second resistivity state being lower than the first resistance Rate status. This second data state will be referred to as the P state, and this transition is indicated in Figure 5 as "V-P". The current flowing between the top conductor "and the bottom conductor 12 at a read voltage of 2 volts is about 10 microamperes or more. The resistivity of the semiconductor material constituting the diode 2 is reduced by a factor of about 1000 to about 2000. In an embodiment, the change in resistivity is small, but will be at least 2 factor between any data state and any other data state, preferably a factor of at least 3 or 5' and more typically a factor of 100 or more. Some of the memory cells in the memory array will be read by this data state and will not be pulsed or reset by an additional set. This second data state will be referred to as the p state. A second electrical pulse is applied ( Preferably, the diode 2 is placed under reverse bias between the top conductor 16 and the bottom conductor 12. This pulse is, for example, between about _8 volts and about _14 volts, preferably between about -1 The stagnation is between about -12 volts, preferably about -11 volts. The current system is, for example, between about 8 angstroms microamperes and about 2 angstrom microamperes. The pulse width is, for example, between about 100 angstroms. Between nanoseconds and about 10 microseconds, preferably between about 100 nanoseconds and about 1 Between microseconds, more preferably between about 2 nanoseconds and about 800 nanoseconds. This second electrical pulse causes the semiconductor material of the diode 2 to switch from the second resistivity state to a third resistivity. State, third electric 121890.doc -14- 200818204 state is higher than the second resistivity state. The current flowing between the body 16 and the bottom conductor 12 under the 2 volt read electric dust is about H) Amperes and about 5.00 nanoamperes are preferably between about (10) nanoamperes and about 5G0 nanoamperes. The memory cells will be taken from this data state and will not be affected. Additional setting pulse or reset pulse. This third data state will be referred to as R state, and this transition is labeled as "p-R in Figure 5," 'In order to reach the fourth data state, a third electrical pulse is applied ( Preferably, the diode 2 is forward biased between the top conductor 16 and the bottom conductor η. The rush system is, for example, between about 8 volts and about 12 volts (e.g., about a dog). The current system is between about 5 microamperes and about amps. This third electrical pulse causes the bipolar semiconductor material to be from the third resistivity. State transition to - fourth resistivity state 'the first resistivity state is lower than the second resistivity state, and the preferred resistivity is the same as the _th resistivity state. 纟 2 volts read voltage flows to the top conductor 16 and The current between the bottom conductors 12 is between about 5 microamperes and about 4.5 microamps. Some of the memory cells in the memory array will be read by this data state (which will be % s state) and The transition is labeled "R4S" in 5. The difference in current between any two adjacent data states at the read voltage (eg, 2 volts) is preferably at least a factor of 2. For example, it is in the data state. The read current of any memory cell is preferably at least twice the read current of any memory cell in the data state v; the read current of any memory cell in the data state s is preferably at least twice as large as the data. The read current of any memory cell of the state ruler; and the read current of any memory cell in the data state p is preferably at least twice the read current of any memory cell in the data state §. For example, the read current of 12I890.doc -15· 200818204 in the data state ruler can be twice the read current in the data state v; the read current in the data state S can be twice as much as The read current in the data state R; and the read current in the data state P can be twice the read current in the data state S. If the ranges are defined as being small, the difference may be quite large; for example, if the memory cell of the highest current V state can have a read current of 5 nanoamperes, and the memory cell of the lowest current R state can have If the current is read by 1 ampere, the current difference will be a factor of 20. By selecting other limits, it is ensured that the difference in read current between adjacent memory states will be at least a factor of three. This will be described below. A repetitive read-verify-write process can be applied to ensure that the memory cells are in one of the defined data states after a set pulse or reset pulse and are not in the state of their data. So far, the difference between the highest current in a data state and the lowest current in the second highest adjacent data state has been discussed. The difference in read current of most memory cells in the adjacent data state is still large; for example, the memory cell in the V state can have a read current of 1 nanoamperes; the memory cell in the R state can be It has a read current of 100 nanoamperes; a memory cell in the S state can have a read current of 2 microamperes (2000 nanoamperes); and a memory cell in the P state can have a read current of 20 microamperes. The currents in each of their adjacent states may differ by a factor of 10 or more. Memory cells having four distinct data states have been described. In order to assist in identifying the status of the data, it is preferable to select three data states (instead of the four data states). For example, a three-state memory cell can be tied to I2I890.doc -16-200818204 to be in data state v, set to data state p, and then reset to data state R. This memory unit does not have a fourth data state s. In this case, the difference between adjacent data states (for example, between Han and 卩 data states) may be significantly larger. As programmed, a single stylized memory array containing memory cells as described, each memory unit being programmed to one of three distinct data replies (in a particular embodiment) Or one of four distinct data states (in an alternate embodiment). These are merely examples; obviously, there may be three or more identical resistivity states and corresponding data states. However, in a memory array containing a single-programmable memory cell, the memory cells can be programmed in a variety of ways. For example, referring to FIG. 6, the memory cell of FIG. 2 can be formed to be in a first state (v-shaped sadness). A first electrical pulse (preferably under forward bias) causes the rupture antifuse 14 to break and switch the monolayer of the polar body from a first resistivity state to a first resistivity state (second The resistivity state is lower than the first resistivity state; the 5th memory cell 70 is in the p state, in this example, the p state is the lowest resistivity state. A second electrical pulse (preferably under reverse bias) switches the polysilicon of the diode from a second resistivity state to a third resistivity state (the third resistivity state is higher than the second resistivity state) , so that the memory unit is in the s state. A second electrical pulse (preferably under reverse bias) switches the polysilicon of the diode from a second resistivity state to a fourth resistivity state (the third resistivity state is in a second resistivity state) , so that the memory unit is in the R state. Any data state (V state, R state, S state 121890.doc -17-200818204 and P-like complaints) can be read as one of the data states of the memory unit. Each transition is labeled in Figure 6. The four different states are shown in the figure; there may be three or more states as needed. In other embodiments, each successive electrical pulse can switch the semiconductor material of the diode to a successive lower resistivity state. As shown in FIG. 7, for example, the memory cell can progress from the initial V state to the R state, from the R-shaped cancer to the S state, and from the S state to the p state, for each state, the current system is read. At least twice the read current of the previous state, each corresponding to a different data state. This scheme is more advantageous when the memory unit does not contain any antifuse. In this example, a pulse is applied under forward bias or reverse bias. In alternative embodiments, there may be three data states or more than four data states. In a specific embodiment, the memory cell includes a polycrystalline germanium or microcrystalline diode 2 as shown in FIG. 8, and the diode includes a bottom heavily doped p-type region 4, an intermediate or lightly doped region. 6 and top heavily doped n-type region 8. As in the previous specific embodiment, the diode 2 can be arranged in series with a dielectric rupture antifuse and disposed between the top and bottom conductors. The bottom heavily doped p-type region 4 may be doped in situ, that is, by doping the dopant atoms by flowing a gas (such as boron) that supplies a p-type dopant during deposition of the germanium. Incorporate into the film that is formed. Referring to Figure 9, it has been found that the memory cell is formed in a v state wherein the current between the top conductor 16 and the bottom conductor 12 is less than about 8 nanoamperes at a read voltage of 2 volts. A first electrical pulse (preferably applied under a forward bias) causes the dielectric rupture antifuse 14 (if present) to break. 121890.doc 200818204

!: and switch the helium-first-resistivity state of the diode 2 to the dipole-resistivity state (the second resistivity state is lower than the first resistivity state); leaving the memory cell in the data state P . In the status of the data? The current between the top conductor 16 and the bottom conductor 12 at a voltage is between about 1 microamperes and about 4 microamperes. - a second electrical pulse (preferably applied under reverse bias) causes the double crystal of the diode 2 to switch from the second resistivity state = a three resistivity state, the third resistivity state being lower than the first resistivity Sad. The third resistivity state corresponds to the data state M. In the data state, the current between the top conductor 16 and the bottom conductor is about 10 microamperes at the read voltage. As in the previous embodiment, between any memory cells of adjacent data (between the highest current memory cell in the V state and the lowest current memory cell in the Ρ state, or between? The difference in current between the highest current memory cell and the lowest current memory cell in the erbium state is preferably at least 2, preferably 3 or more. Any data status (V, Ρ or Μ) can be detected as one of the data status of the memory unit. Figure 4 shows that when the semiconductor diode is subjected to a reverse bias, generally the 'semiconductor material initially undergoes a set transition to a lower resistivity, and then, as the voltage increases, the reset to a higher resistivity is experienced. change. For this particular diode, the top heavily doped n-type region 8 is used, and the bottom heavily doped region 4 formed by in-situ doping with a germanium dopant is preferably used, with an increase in the reverse direction. Switching from a set transition to a reset transition with a bias voltage does not occur suddenly or abruptly like the diodes of other embodiments. This means that it is easier to control the set transition under reverse bias using this diode. 121890.doc -19- 200818204 Rewritable Memory Unit In a second embodiment, the memory unit acts as a rewritable memory 70, and can be repeatedly switched between two or three data states. FIG. 10 illustrates a memory unit that can function as a rewritable memory unit. The memory unit is the same as the one shown in Figure 2, and the body is early, except for dielectric breaks. A majority of the rewritable embodiments do not include in the memory unit: an anti-fuse, but if desired, an anti-fuse. ::: Figure u, in the first preferred embodiment, the memory cell is in the two resistivity state V' and the current at 2 volts is about 5 nanoamperes. In the embodiment, the initial V state is not used as the data state of the memory unit. An -first electrical pulse (preferably with a body 2 under forward bias) is applied between the top conductor 16 and the bottom conductor η. This pulse is, for example, between about 8 volts and about 12 volts, preferably (10) volts. The first electrical pulse causes the semiconductor material of the diode 2 to switch from a first resistivity state to a second resistivity state, the second resistivity state being lower than the first: resistivity state. In a preferred embodiment, the ρ state is also not used as one of the data states of the 5' k' body. In other embodiments, the ρ state will be used as a data state for one of the memory cells. ^ A second electrical pulse is applied (preferably with the diode 2 under reverse bias) between the top conductor (four) and the bottom conductor 12. The pulse is, for example, between about _8 gangs and about -14 volts, preferably between about _9 volts and about _13 volts, more preferably about 0 volts. The required voltage will be diversified with the thickness of the intrinsic zone. The second electrical pulse causes the semiconductor material of the diode 2 to switch from the second resistivity state to the third resistivity state R, the third resistivity state being higher than the resistivity state of the 121890.doc -20-200818204. In a preferred embodiment, the R state corresponds to a data state of the memory early element. ▲ A third electrical pulse can be applied between the top conductor 16 and the bottom conductor 12, Preferably, under forward bias, the pulse is, for example, between about 90 volts and about 9 volts = about 6.5 volts and the current is between about ampere and about ruthenium: Preferably, it is between about 5 〇 micro ampere and about ι 〇〇 micro ampere. The third electricity: the semiconductor of the diode 2 is switched from the third resistivity state (4) to the fourth resistivity state S, The fourth resistivity state is lower than the third resistivity state. In a preferred embodiment, the s state pairs (4) one of the memory cells is in a data state. In this rewritable, two-state embodiment, sensing or reading The r state and the S state are taken as the data state. The memory cell can be repeatedly switched between the two states. For example, Shih, silver _ ^ bovine case and θ, one brother four electric pulse (better with diode 2 Under reverse bias, the semiconductor material of the diode is from a fourth resistivity state s (four) to a fifth resistivity state R (its substantially phase Same as the fifth electric pulse of the third resistor town (preferably with the diode 2 under forward bias), the semiconductor material of the diode is switched from the fifth resistivity state R to the sixth resistivity state S (the essence thereof) The same as the fourth resistivity 8), and so on. It may be more difficult to return the memory cell to the initial V state and the second P state; therefore, in the rewritable memory cell, the hopeful industry can 1 + τ 4 sorrow may not be used as a data state. It may be preferable to perform a first-electric pulse (which causes the memory unit to self-initial before the memory array reaches the user (for example, in a manufacturing waste or test facility) V-response switches to the "state" and the second electrical pulse (which causes the memory cell to switch from the I state to the R state). In other embodiments, it may be more than 121890.doc -21-200818204 To perform only the first electrical pulse (which causes the memory cell to switch from the initial v state to the p state) before the memory array reaches the user. As shown in Figure 11, in the example provided, Data status

Any of the 5 memory cells are in a state of adjacent data (in this case, the R tributary state (between about 10 nanoamperes and 500 nanoamperes) and the R data state (between about 1 · 5 micro The difference between the current between the top conductor 16 and the bottom conductor 12 between the readout voltage (eg, 2 volts) between any of the memory cells between amps and 4.5 microamperes)) is at least The factor of 3. Depending on the range selected for the state of the data, the difference may be a factor of 2, 3, 5 or more. In an alternate embodiment, a rewritable memory unit can be switched between three or more data states in any order. The set transition or reset transition can be implemented with the diode in forward bias or reverse bias. In both the single fire programmable embodiment and the rewritable embodiment described, the data state is indicated to correspond to the resistivity state of the polycrystalline or microcrystalline semiconductor material constituting the diode. The data state does not correspond to the resistivity switching metal oxide or nitride resistivity state, as described in Herner et al., US Patent Application No. - nN_〇latile Memorym C〇mprising a Di〇de and a

The description of ReSiStanCe-Switching M攸rial, which is owned by the assignee of the present invention and incorporated herein by reference in its entirety herein. In the memory cell array, the memory cell is subjected to a large voltage in the reverse bias voltage. 121890.doc -22-200818204 has reduced the leakage current compared to the reverse bias step. Referring to FIG. It is assumed that 10 volts of forward bias is applied across the selected memory cell 8. (The actual voltage to be used will depend on a number of factors, including the configuration of the memory cell, the amount of dopant, the height of the nature region, etc.; Just an example). Bit line B0 is set to 1 〇' and the word line is set to ground. To ensure half-selected memory unit 1 (which is the same as the selected memory unit, S shares bit line B0) Maintaining a lower turn-on voltage than the diode, the word line is further reduced to 5 but below the voltage of the bit line B〇; for example, the word line 10 W1 can be set to 9·3 volts. Applying cross-memory unit F to 7 volts (only one memory cell F is shown in the figure, but there may be hundreds, thousands or more. Similarly, in order to ensure a half-selected memory cell H (which shares the word line W0 with the selected memory cell S) Maintaining a turn-on voltage lower than the diode, the bit line 扪 is again σ to the same voltage but quite close to the word line w〇; for example, the bit line Β1 can be set to 〇·7 volts, so that Applying volts across the memory (reciprocal fire can have thousands of seven memory elements Η). Unselected memory unit U (which does not share the 纟 line W0, Φ + common bit line with the selected memory unit 8 Β0) is subjected to -8.6 volts. Since there are millions of unselected memory cell ports, significant line leakage currents in the § memory array are caused. ' Figure 13 shows a large reverse bias across the memory cells. A favorable biasing scheme for voltage (for example, as a heavy (four) rush). Bit line B0 is set to _5 volts, and word line W0 is set to 5 volts' such that it is applied across the selected memory cell s, volts, two The pole system is in reverse bias, so as not to deliberately set or reset the low reverse bias of the selected memory cell. The word lines and bit line B1 are grounded to subject the half-selected memory cell to _5 volts. 121890.doc -23- 200818204 Generally speaking, setting or resetting with reverse bias seems to occur at or near two The polar body transforms into a reverse breakdown voltage (which is generally higher than _5 volts). Using this scheme, the voltage across the unselected memory cell u is caused, causing ..., reverse leakage. The result, for example, for example U.S. Patent Application Serial No. 11/461,352, entitled "Dual Data-Dependent Busses for Coupling Read/Write Circuits to a Memory Array", filed by the same application in the present application. Further description in the number No. 023-0051 can significantly increase the bandwidth. The biasing scheme of Figure 13 is merely an example; obviously, many of its schemes can be used. For example, bit line B0 can be set to ramp, word line |〇 can be set to -10 volts, and bit line B1 and word line W1 can be set to volts. In the scheme of Fig. 13, the voltage across the selected memory cell s, the half-selected memory cells το Η and F, and the unselected memory cell u will be the same. In another example, the bit line Β〇 can be set to ground, the word line w 〇 can be set to 10 volts, and the bit line B1 and the word line W1 can be set to 5 volts. Repetitive setting and resetting to the point, this discussion has described the application of an appropriate electrical pulse to switch the semiconductor material of the diode from a resistivity state to a different resistivity state ' thus switching the memory cell to two Between different data states. In practice, the setting steps and resetting steps can be repeated procedures. As mentioned, the difference between the currents flowing during the reading in the adjacent data state is preferably a factor of at least 2; in many embodiments, it may be preferred to set each data state. The current range, and the phase 12I890.doc -24- 200818204 is a factor of 3, 5, 1 or more. Referring to FIG. 14, as described, the voltage is read at 2 volts, and the data state V can be defined as a read current of 5 nanoamperes or less. The data state R can be defined as about 1 nanoamperes and about 500 nanoamperes. Between the data states S can be defined as between about 1.5 microamperes and about 4.5 microamps, and the data state P can be defined as greater than about 10 microamperes. Those skilled in the art should understand that they are merely examples. In another embodiment, for example, the data state V can be defined in a smaller range, wherein the voltage is read at 2 volts and the read current is 5 nanoamperes or less. The actual read current will vary with the characteristics of the memory cell, the configuration of the memory array, the selected read voltage, and many other factors. It is assumed that the single-programmed memory cell is in the data state P. A reverse biased electrical pulse is applied to the memory cell to switch the memory cell to the data state S. However, in some cases, the read current may not be in the desired range after the application of the electrical pulse; that is, the resistivity state of the semiconductor material of the diode is above or below the desired state. For example, assume that after applying an electrical pulse, the read current of the memory cell is at the Q point shown on the graph, between the S state and the P state current range. After an electrical pulse is applied to switch the memory cell to the desired data state, the memory cell can be read to determine if the desired data state is reached. If the desired data status is reached, an additional pulse is applied. For example, when current Q is sensed, an additional reset pulse is applied to increase the resistivity of the semiconductor material, reducing the read current into a range corresponding to the s data state. This set pulse can be applied under forward or reverse bias as described above. The pulse width of the amplitude (voltage or current) of the extra pulse can be longer or shorter than the original I21890.doc -25- 200818204 start pulse. After the additional set pulse, the memory cell is read again, and then the set pulse or reset pulse is applied as appropriate until the read current is in the desired range. In a two-terminal device, such as a memory unit including the described diodes, this would be particularly advantageous for reading to verify settings or resets and adjustments if needed. Applying a large reverse bias across the diode can damage the diode; therefore, it is advantageous to minimize the reverse bias voltage when the mating diode is set or reset in reverse bias. Manufacturing considerations

U.S. Patent Application Serial No. 11/148,530, the entire disclosure of which is hereby incorporated by reference in its entirety, the entire entire entire entire entire entire entire entire entire entire content Application Nos. 10/954, 5 10 "Memory Cell Comprising a Semiconductor Junction Diode Crystallized Adjacent to a Silicide" (all of which are owned by the assignee of the present invention and are hereby incorporated by reference) The crystallization of the polycrystalline germanium adjacent to the appropriate telluride affects the properties of the polycrystalline germanium. The lattice structure of certain metal halides (such as cobalt telluride and titanium telluride) is very close to the lattice structure of germanium. When the microcrystalline germanium is crystallized to contact one of the tellurides, during the crystallization, the lattice structure of the telluride provides a template for the germanium. The resulting germanium will be highly ordered and the defects are rather low. When doped with a conductivity-enhancing dopant, the high-quality polysilicon is relatively highly conductive when formed. In contrast, when amorphous or microcrystalline The material is crystallized to be in contact with 121890.doc -26- 200818204 with a telluride (the crystal lattice of this telluride is well matched to ruthenium), for example, 'only in contact with such as ruthenium dioxide and titanium nitride (two The yttrium oxide and the crystal lattice of titanium do not significantly match 矽), then the resulting ruthenium ruthenium will have many defects of a greater degree, and J; B: έ士曰/μ λ- 卫1 The doped polysilicon in the daytime will have very low conductivity when formed. In the aspect of the invention, the semiconductor material forming the diode is switched between two or more resistivity states. Change flow at a given reading voltage

The current through the diode 'different' (corresponding to the resistivity state) corresponds to a different data state. It has been found that a diode formed by a highly defective germanium (or other suitable semiconductor material such as a tantalum-bismuth alloy) that is not crystallized adjacent to a compound or a similar material that provides a crystallized tantalum plate exhibits a greater Favorable switching behavior. Without wishing to be bound by any particular theory, it is believed that the mechanism that supports the observed resistivity variability is that a set pulse above the threshold amplitude causes the dopant atoms to move out of the grain boundary (where the dopant atoms are Inactive) enters the crystal body (where dopant atoms will increase conductivity and reduce the resistance of the semiconductor material). In contrast, resetting the pulses can cause the dopant atoms to move back to the grain boundaries to reduce conductivity and increase electrical resistance. However, there may be other mechanisms to operate or as an alternative, such as increasing or decreasing the degree of sequencing of the polycrystalline material. It has been found that the state of resistivity of the crystallized very low defect 相邻 adjacent to the appropriate telluride is not as easy to switch as when the semiconductor material has a higher degree of defects. The presence of defects or the presence of a large number of grain boundaries may allow for easier cutting. In a preferred embodiment <column H, the polycrystalline or micro-ruthenium material forming the dipole is not crystallized adjacent to the material having a small lattice mismatch with it. 121890.doc -27 - 200818204. The twins do not match, for example, about 3 percent or less of the wafers do not match. Evidence has suggested that switching behavior can focus on changes in the essential area. The switching behavior has been observed in the resistor and the p-i-n diode, and is not limited to p_i_n diode 胄' but the use of the Bub 11 diode may be particularly advantageous. The specific embodiment described so far includes the p_i_n diode. However, in other embodiments, the 'diode' may alternatively be a P-n diode and have negligible or no intrinsic regions. The detailed description of the preferred embodiments of the invention is set forth.

U.S. Patent Application Serial No. 10/320,470 ft "An Improved Method for Making High Density Nonvolatile Memory" (and is hereby incorporated by reference). The manufacturing details will help to form the diodes of their specific embodiments with information from the $shirt application. U.S. Patent Application No. φ 11/〇15,824, "N〇nV〇latile Mem〇ry Cell Comprising a Reduced Height Vertical Diode", filed by Hemer et al., December 17, 2004. The usefulness of the information is derived from the assignee of the present invention and is hereby incorporated by reference. In order to avoid obscuring the present invention, all details from their application are not included, but it should be understood that they are not intended to exclude information from their applications. Example The single-memory level will be fabricated in detail. Additional memory levels can be stacked, each formed in a monolithic manner above the memory level below it. In this embodiment, the polycrystalline semiconductor diode will be used as a switchable element. Referring to Figure 15a, the formation of the memory begins at the substrate (10). The substrate 100 can be any semi-conductive substrate known in the art, such as a single crystal stone IV-IV compound (such as Shiguangyu or Shishiwu carbon), a cucurbit compound, a & VII compound, Here, the epitaxial layer on the temple substrate or any other semiconductive material. The substrate may include an integrated circuit fabricated therein. An insulating layer 102 is formed on the substrate 100. The insulating layer 102 can be a ruthenium oxide, a I fossil, a high dielectric film, a Si-C-O-H film, or any other suitable insulating material. On the substrate and the insulator on the ancient tour > » _ ^ above the formation of a conductor 2 〇〇. A barrier layer 1〇4 may be interposed between the insulating layer 1〇2 and the conductive layer 106 to assist the conductive layer 1〇6 to adhere to the insulating layer 102. If it is desired that the conductive layer is tungsten, it is preferable to use titanium nitride as the adhesive layer 104. Next, the exhibition to be deposited is in the #措g•, 曰 system V layer 106. Conductive layer 106 can comprise any of the conductive layer materials known in the art, such as (4) or other materials, including buttons, titanium, copper, cobalt, or any alloy thereof. - All layers that will form conductor tracks will be used with any suitable: ", and etching processes to pattern and etch their layers to form substantially parallel: coplanar conductors 2", such as The cross-sectional view of the figure is shown: in one embodiment, the sinking, the first resistance, and the lithography and their etched layers are used to pattern the photoresist, and * photoresist. The standard process technology is used to remove the germanium. The conductor 200 is formed by a damascene method. Next, the dielectric material (10) on the conductor track 2 can be made of a p4 L-dielectric material 108. Any known electrically insulating material, for example, oxidized 121890.doc -29- 200818204 yttrium nitride and/or yttrium oxynitride. In a preferred embodiment, ruthenium oxide can be used as the dielectric material 1 . The subsequent 'removal of excess dielectric material 108' on the very top of the conductor track 200 exposes the topmost portion of the conductor track 200 separated by the dielectric material 108 and leaves a substantially flat surface 109. Figure 15a shows the result Structure. Any process known to the art (such as chemistry) Mechanical polishing (CMP) or etch back) to perform overfill dielectric removal to form a flat surface 10 109. An advantageous etchback technique is described by Raghuram et al. on June 30, 2004. U.S. Patent Application Serial No. 1/883,417, the disclosure of which is incorporated herein by reference. A plurality of substantially parallel first conductors are formed on the substrate at a first height. Next, referring to Figure 15b, a vertical column will be formed over the finished conductor. (In order to save space, the substrate 1 is not shown in Fig. 15b; _ is confirmed to have a substrate present). Preferably, a barrier layer 110 is deposited as the first layer following the planarization conductor. Any suitable material can be used in the barrier layer, including tungsten nitride, nitride buttons, titanium nitride, or a combination of these materials. In a preferred embodiment, titanium nitride is used as the barrier layer. If the P early layer is titanium nitride, the barrier layer can be deposited in the same manner as described above for depositing the adhesion layer. Next, a semiconductor material that will be patterned into a pillar is deposited. The semiconductor material can be a tantalum, niobium, tantalum-niobium alloy or other suitable semiconductor or semi-conducting alloy. For the sake of brevity, this sub-paragraph refers to the semiconductor material as 121890.doc -30- 200818204 矽, but those skilled in the art should clarify the material as an alternative. White may select any other suitable for the preferred embodiment, and the column includes a semiconductor junction diode. As used herein, a six-junction diode is used to refer to a non-ohmic conduction property having a terminal electrode and a semiconductor material (the p-type at one electrode: the n-type at the other electrode). Semiconductor device. Examples include "diode and η-ρ diode (which has contact 1) type semiconductor material and n-type semiconductor

Materials such as Zener diodes and ρ]_η diodes (wherein the intrinsic (unsubstituted) semiconductor material is interposed between the p-type semiconductor material and the type 11 semiconductor material. It is well known by the art. Any deposition doping method to form the bottom heavily doped region 112. The deposition can be followed by doping with germanium, but preferably by flowing a donor gas that provides n-type dopant atoms (eg, phosphorus) during deposition of germanium. In-situ doping. The thickness of heavily doped region 112 is preferably between about 1 Å and about 800 Å. The layer 14 can be formed by any method known in the art. An alloy of stone, enamel or any stone or enamel, and having a thickness of between about 1100 angstroms and about 3300 angstroms, preferably about 2 angstroms. Please refer back to Figure 15b, the just deposited semiconductor layer. 114 and 112 will be patterned and etched along with the underlying barrier layer 110 to form pillars 3. The pillars 300 should have approximately the same distance and width from the conductors 200 below, such that each pillar 300 is formed on the conductor 2〇〇 The top of the line. Some misplaced positions can be tolerated. The mask and etch process are combined to form pillars 300. For example, photoresist can be deposited, patterned using standard lithography techniques, and etched with the light 121890.doc -31 - 200818204, followed by removal of the photoresist. To form a hard mask of some other material (eg, cerium oxide) on the top of the semiconductor layer stack (with a bottom anti-reflective coating (B ARC) on top), followed by patterning and etching. A dielectric anti-reflective coating (DARC) can be used as a hard mask. 'US Patent Application No. 10/728436, "Photomask Features with Interior Nonprinting, filed on December 5, 2003

US Patent Application No. 10/815312 "Photomask, filed by Chen, Alternating Phase Shifting; or Chen, April 1, 2004

The lithography techniques described in the Features of Chromeless Nonprinting Phase Shifting Window's (both of which are owned by the assignee of the present invention and incorporated herein by reference) are herein Any lithography step used in the volume array. A dielectric material 108' is deposited over and between the semiconductor pillars 300 to fill the gaps between the pillars. Dielectric material 108 can be any known electrically insulating material ' _ for example, hafnium oxide, tantalum nitride, and/or hafnium oxynitride. In a preferred embodiment, cerium oxide is used as the insulating material. Next, the dielectric material removed on the topmost portion of the pillar 300 is exposed, the topmost portion of the pillar 300 separated by the dielectric material 108, and leaving a substantially flat surface. Overfill dielectric removal is performed by any process well known in the art, such as CMP or etch back. Ion implantation is performed after CMP or etch back to form a top heavily doped p-type region 116. The p-plastic dopant is preferably a shed or BC13. This implantation step completes the formation of the diode 111. Figure 15b shows the resulting structure. In the diode just formed, the bottom heavily doped region 112 121890.doc -32 - 200818204 is n-type, and the top heavily doped region 116 is p-type; obviously, the polarity can be reversed. Referring to Figure 15c, next, a dielectric rupture antifuse layer 11 8 is formed on top of each heavily doped p-type region ι16. The antifuse 11 8 is preferably a layer of ruthenium dioxide formed by oxidizing underlying ruthenium in a rapid thermal annealing (e.g., about 600 degrees). The counter-solvent 118 can have a thickness of about 20 angstroms. Alternatively, an anti-fuse 117 can be deposited.

The top conductor 4 can be formed in the same manner as the bottom conductor 200, for example, by depositing an adhesive layer 12 (preferably made of titanium nitride) and a conductive layer 122 (preferably made of tungsten). ). Next, the conductive layer 122 and the adhesion layer 12A are patterned and etched using any suitable masking and etching process to form substantially parallel, substantially coplanar conductors, as shown in the left to right spread of FIG. 15e. . In a preferred embodiment, the photoresist is deposited and removed by lithography and their layers, and then the photoresist is removed using standard process techniques. Next, a dielectric material (shown in the figure) is deposited over and between the conductor tracks 400. The dielectric material may be (iv) known as an electrically insulating material, for example, yttrium oxide, tantalum nitride, and/or 童f servants are also cut. In a preferred embodiment, silica dioxide can be used as the dielectric material. It has been described that a first memory layer is formed, and an additional memory level is formed on this memory level to form an early two-dimensional memory array. In some embodiments, the conductor may be shared between the levels of the body, i.e., the top conductor 400 will serve as the bottom conductor of the next level, body level. In the 匕/, body embodiment, a layer of dielectric (not shown) is formed above the layer of the layer of FIG. 15 〇 C C C , , , , , , , , , , , , , , 121 121 121 121 121 121 121 121 121 121 121 121 121 121 121 121 121 121 121 The configuration of the first memory level begins with this planarized interlayer dielectric and has no shared conductor. A monolithic two-dimensional memory array is a memory array in which multiple memory levels are formed over a single substrate (such as a wafer) and there is no interposer. The layers forming a memory level are deposited or grown directly over an existing layer or layers of multiple levels. In contrast, stacked memory has been constructed by forming memory levels on a substrate that is unique and bonding the memory levels to each other on top, as in Leedy's U.S. Patent No. 5,915,167 "Three As proposed in the "dimensional structure memory", the substrates can be thinned or removed from the memory levels before bonding, but when the memory layers are initially formed on separate substrates, the memories are not truly single. a three-dimensional memory array. The monolithic three-dimensional memory array formed over the substrate includes at least a first memory level (which is formed at a higher level than the first height of the substrate) and a first memory level (which is A second height different from the first height is formed. In this multi-level memory array, three, four, eight or even any number of memory levels can be formed above the substrate. In Radigan et al., May 2006 US Patent Application Serial No. 11/444,936 "Conductive Hard Mask to Protect Patterned

An alternative method for forming a similar array of memory elements is described in the Feature During Trench Etch&quot;, wherein a mosaic is used to form the conductor, which is owned by the assignee of the present invention and is hereby incorporated by reference. The method of Radigan et al. may alternatively be used to form the sequel array according to the invention 121890.doc 34. 200818204. Alternative Embodiments In addition to the specific embodiments that have been described, many alternative embodiments of memory cells that store their data states in the resistivity state of a polycrystalline or microcrystalline semiconductor material are also possible and within the scope of the present invention. . A few other possible specific embodiments will be mentioned, but this list is not intended to be exhaustive. Figure 16 illustrates a switchable memory element 117 formed in series with a diode U1. Switchable memory component 117 is formed from a semiconductor material that is switched between resistive states using electrical pulses as described. As described above, a monopolar body is preferably crystallized adjacent to a lithiated compound (such as a crystallization template provided by Shi Xihua), resulting in a semiconductor material defect of the diode being extremely low and exhibiting negligible or absent. Switch behavior. Preferably, the switchable memory element 117 is doped and should be doped to the same conductivity type as the top heavily doped region 116. The method of manufacture of this device is described in the '167 application. Detailed manufacturing methods have been described herein, but any other method of forming the same structure may be used, with the results falling within the scope of the present invention. Exemplary Applications The foregoing specific embodiments describe how memory cells can be used as two data state type memory cells, two or more data state memory cells, a single stylized memory cell, or a rewritable memory. unit. This versatility allows the use of a common memory cell architecture to provide multiple types of memory products. The versatile nature of memory cells and their potential to provide versatile memory arrays are discussed below. The memory cell retrofit described above has a memory component that includes a switchable resistive material, such as a semiconductor material configurable to one of at least three resistive densities L. The memory element can be 'configured' during the formation of the memory element to a resistivity state (eg, the initial, unprogrammed state of the memory element has an initial resistivity state) or by subsequent The memory element is subjected to a set pulse or a reset pulse to &quot;μ" the memory element to a resistivity state. Because of this characteristic, a single 1 A flat can be used as a two-way method. Action: It is possible to program a single memory unit or a rewritable 5 unit. In addition, because of this characteristic, the memory unit can use two data states or two or more data states. Accordingly, any predetermined memory cell has the potential to operate as a single-programmed memory cell or rewritable memory cell having two or more data states. As shown and as above Said that when the memory unit operates as a single-programmable memory unit, the resistivity state is used to represent a data state of the memory unit; but when the memory unit operates as a rewritable Memory early disease, do not use the resistivity state to represent a data structure of the memory unit. In other words, when the memory single (9) is used as a single-programmed memory unit, it can be used in the memory unit. In the early morning, there may be a _, extra &quot; state. For example, regarding the memory described above and in conjunction with FIG. 5 and FIG. u, the memory unit is manufactured to be in the initial state. Resistivity (4) (V state), and when the memory unit operates as a single-programmed memory unit, this initial power state is used; but when the memory unit operates as 121890.doc -36·200818204 'The initial resistivity state is not used. When the memory unit operates as a rewritable memory unit, two other data states (R state and S state) are used to represent the data state of the memory cell. (As described below, they can also be used in a single-programmed memory unit). By changing the resistance of the switchable Wu Leiri 1 L, and Λ resistance materials to achieve their data for a long time, their other state of education does not include only when the memory unit operates as a single. The material L used to represent the data state can use an extra lean state (for example, R2 sorrow between the r state and the § state) to allow the rewritable memory cell to achieve three or achieve Three or more different data states. It should be noted that in the preferred embodiment, the memory element comprises a switched resistive material (eg, a semiconductor material) connected in series with the antifuse, and the V state is only singularly tangible when the domain material transports The resistivity state used when the memory cell is used. The reason is that once the antifuse is blown, the memory component cannot be returned. However, even when the anti-solvent wire is not used, the state of the resistivity state is specified as the state that is used only when the memory cell operates as a single-programmable memory cell. It should also be noted that the Ρ state can also be used when the memory unit operates as a single-programmable memory unit, but it is a resistivity state that is not used when the memory unit operates as a rewritable memory unit. However, in some embodiments, instead of or in addition to the Ρ state, one or both of the R state and the S state are used to represent a data state of the memory cell that cannot be monolithically programmed, such as A single-time weighted memory unit stores three or four data states. In this case, the single-programmable and rewritable memory units of the memory unit will have a resistivity state in common. For example, instead of a single-programmed memory cell and a rewritable memory cell having a unique state state (eg, V-state and P-state are used for a single-programmed memory cell, and R-state and S The state is for a rewritable memory unit), and the single-programmed memory unit and the rewritable memory unit can have a state together (for example, there is no difference between the S state and the P state). However, when the memory unit operates as a single-programmable memory unit, at least one resistivity state (eg, V-state) will still be used to represent a data state of the memory cell; however, when the memory cell operates as This is not the case when overwriting the memory unit. An advantage of this versatility is that a single integrated circuit having such memory cells can be designated as a single-programmable memory array or as a rewritable memory array. This provides manufacturing flexibility and yield improvement. To determine if a memory array is to be used as a single-programmable memory array or as a rewritable memory array, a set of test memory cells in the memory array can be tested during (or after) manufacturing. For example, the test memory cells can be utilized by reprogramming, resetting, and setting their test memory cells. </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; Based on the test results, it is predicted whether the memory array will be normalized as a rewritable memory array. For example, if the test exhibits an indistinct state and an S state (these states are used when the memory array operates as a rewritable note (4) (4)), the (4) component will most likely not be properly programmed to be rewritable. Memory Array ^ However, the stylized memory array is discarded because the memory cells in the memory array of 121890.doc -38 - 200818204 can be arrayed or as a rewritable result expected by the rewritable memory array. As a result, co-manufacturing flexibility and yield improvement. Operates as a single-programmed memory, so instead of providing this component, you can specify that the component is available as a single-associated memory unit architecture.

At this point, there may be manufacturing differences. The tested memory array can be used for further formatting (for example, staging all memory cells from the V state ^ state) and then applying between the verification state and the s state as the most, and the Berg test 4) 'Affinity is a rewritable memory array (for example, a memory card with a reading camera) that is shipped to a warehouse or user. Memory samples that fail the test can be packaged and sent to the same part of the manufacturer to program a single stylized content. Alternatively, the part can be sent to the warehouse by the library staff or the user to programmatically program the content in a single program (for example, using kiosk) » Unprogrammed parts can also be sold to the user for use as an archive memory body. Preferably, a flag is used to send a signal to a device for reading and writing to the memory array (for example, a controller on a memory device including a memory array or a hardware/software in the host device). The memory array is told to be a single-programmed memory array or a rewritable memory array. A "flag" may be one or more bits stored in a memory array. For example, a flag can be set in a special address location (e.g., address 〇〇〇〇) in the imaginary array. When the host device detects the flag, it can be adapted to the single-programmable nature of the memory array by not attempting to reprogram the memory array. Instead of using the entire memory array as a single-programmable memory array 121890.doc -39- 200818204 or as a rewritable memory array, the °-hidden array can be a "multi-purpose" but body array. In a specific embodiment, all of the memory cells in the memory cell array can be used as a single-programmable memory cell or as: a rewritable memory cell, so a first-display, and 5 The single-single-single-single unit operates as a single-programmed memory unit, and a group of _ _ 圮 兀 兀 兀 兀 兀 兀 兀 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 A single-programmed memory unit and a rewritable memory can be programmed on the integrated circuit. As mentioned above,

The test can be performed to determine whether a given set of memory cells should be designated as a single-person private memory cell or a rewritable memory cell. FIG. 17 is a diagram showing a hybrid memory array 200 of a preferred embodiment. A first set of memory cells 210 operates as a single-programmable memory cell, and a second set of memory cells 220 operates as a rewritable memory cell. In this embodiment, the memory cells in the two sets 210, 220 all contain the same number of memory cell data states, however, the number of memory cell data states is feasible, as described below. In a specific embodiment, the first set of memory cells stores data that is considered permanent and can be related to the operation of the memory array. Examples of this information include, but are not limited to, one or more of the following: content management bits, trim bits, manufacturer data, and formatted material. ‘’Content Management Bit&quot; refers to information related to the management of stylized content. The "trimming bit" is a custom message that sets various options in the circuit on the wafer. In operation, the on-wafer circuit reads the trim bits in the first set of memory cells 210 and the read trim bit control circuitry further operates. For example, the trim bit can include a write for the memory device / 121890.doc -40- 200818204 B: the circuit of the car "guy write &quot; read like current or voltage) exemption $.&quot; The manufacturer's bedding material may include the manufacturer's name and serial number. "Formatted data" indicates that the memory array is not self-contained. a μ &amp; ^ file, specifically s, one of the memory arrays And/or poor and redundant columns and/or row locations. For more information on redundancy, see U.S. Patent Application Nos. 10/402,385 and '646, and their patent applications have been It is to be noted that the assignee of the present invention is hereby incorporated by reference.

Af. For example, the 记忆-group memory unit 2 process may include in-game valley data (ie, the computer code of the game), and the second group of memory units 220 may include game state data (ie, when the user requests to save An indication of the position of the user in the game during the game). Further, the data in the first set of memory cells 2 or the second set of memory cells 220 can be programmed at the manufacturing facility or by subsequent users. In Fig. 17, there is only one section of a single-programmed memory unit and only one section of a rewritable s-resonance unit. In another embodiment, at least one additional set of memory cells operates as a single-programmable memory cell or a rewritable memory cell. Figure 18 illustrates this embodiment in which two pre-programmed sections 230, 250 are interleaved with two rewritable sections 240, 260 (i.e., two adjacent sets of memory cells are not available) Single stylized or both are rewritable). As described above, any data can be stored in any section. For example, the game content data may be stored in the single-programmable sections 230, 250, and the game state data may be stored in the rewritable sections 240, 260. 121890.doc -41 - 200818204 It should be noted that although 17 and 18 illustrate that the sets of memory cells are oriented in a horizontal manner, but in an alternative embodiment, one or more sets of memory cells can be oriented in a vertical manner. For example, instead of having formatted data in a horizontal column of memory cells (as shown in Figure 17), the formatted material can be tied to a vertical column of memory cells. In this way, redundant data will span many pages. Mixed horizontal orientation and vertical orientation information can also be used. For example, manufacturing materials can be oriented horizontally, while formatted data can be oriented vertically. As shown in FIG. 18, each page of data may include one or more flag bits "❹" indicating whether a page is single-programmable or rewritable. In Figure 18, the πι" flag indicates It can be single-programmed, and the "0" flag indicates rewritable. Preferably, the flag is stored in a single-programmable memory unit (even if the memory unit is in a rewritable section). Furthermore, a preferred method is to optimize the preset read conditions for the single-programmed data (so that the single-programizable flag bits stored in the single-programizable section can be successfully read and Trimming the bits, manufacturing materials, etc.), and modifying the reading conditions if the flag indicates a rewritable lean. One advantage of using flag bits is that it is virtually impossible to use a single-programmed memory cell as a rewritable memory cell, and vice versa, because the on-wafer write circuit interprets the flag. The write-once circuit on the wafer is programmed to prevent more than a second write to the memory cell if the flag indicates that a memory cell is single-programmable. As an alternative to using a flag bit, the address space calculation and write control can be moved to the chip, e.g., to the hardware/software in the host device. 121890.doc -42- 200818204 For example, if a memory device is used as the game device, the software in the host device can use a pre-specified address space for storing game state data (the host device knows the address space) , but the memory does not know the address space). An alternative would be to use a single stylized portion of the memory array that can be stored in the game content data in the memory array (eg, a special address location in the memory array (eg, address 〇) 〇〇〇)) or information in the device controller in the memory device that is separate from the memory array to inform the host device of the address space for the game state data. In the specific embodiment shown in FIG. 17 and FIG. 18, in the sense that some memory cells can be single-programmed memory cells and others are rewritable memory cells, the memory array is mixed. Use &quot;. In other embodiments, instead of or in addition to a single stylized/rewritable feature, the mixed-use &quot;memory array includes other &quot;hybrid&quot; features. As described above, flag cells or Other mechanisms are used to determine the properties of a given set of memory cells. For example, a first set of memory cells in the same memory array can be more reliable than a second set of memory cells and have a wider temperature and voltage range. For example, using the preferred memory cell structure described above, a given memory cell can be programmed (1) with a forward bias (eg, the same single-programmed memory cell or can be heavy) Write memory unit); or (ii) program with reverse bias (for example, the same rewritable memory unit, but different from the two-state single-programmed memory unit). In other words, it can be single The stylized memory unit can only accept forward bias programming, while the rewritable memory unit can accept forward bias programming and 121890.doc -43-200818204 reverse bias programming. See the circuit diagrams of Figures 19 and 20. For a detailed description of forward bias writes, see U.S. Patent No. 6,618,295; and for a detailed description of reverse bias writes, see U.S. Patent Application No. 11/461,339 (Attorney Docket No. 023-0048) entitled "'Passive Element Memory Array Incorporating Reversible Polarity Word Line and Bit Line Decoders" and US Patent Application No. 11/461,364 (Attorney Archives) No. 023-0054) entitled "'Method for Using a Passive Element Memory Array Incorporating Reversible Polarity Word Line and Bit Line Decoders", each of which has been assigned to the assignee of the present invention and is hereby incorporated by reference. Accordingly, "a hybrid n memory array can include: a first set of memory cells that are programmed with forward bias; and a second set of memory cells that are reverse biased Stylized. A memory cell that is programmed with a reverse bias can also be erased with a forward bias. In an erase operation (compared to a write operation), individual data bits in a page are not variables because all bits are erased during the erase operation. For a detailed description of the erasing operation, see U.S. Patent Application Serial No. 11/461,339 (Attorney Docket No. 023-0048) entitled "Passive Element Memory Array Incorporating Reversible Polarity Word Line and Bit Line Decoders&quot; And U.S. Patent Application Serial No. 11/461,364 (Attorney Docket No. 023-0054) entitled &quot;Method for Using a Passive Element Memory Array Incorporating Reversible Polarity Word Line and Bit Line Decoders&quot; It has been assigned to the assignee of the present invention and is hereby incorporated by reference. 121890.doc -44- 200818204, until the end of the discussion about the use of memory cells as a single-program fossil memory unit or as a rewritable memory unit, and memory array = with early stylization A combination of a memory unit and a rewritable memory unit, as described above, another preferred form of memory is that the memory unit (whether it can be single-programmed) The memory unit or the rewritable memory unit can store two data states or two or more data states. The test can be tested for each _ possible data state. How much data can be stored in the memory array. The burdock is 〗. The test memory t-element can be tested in the v, p, s, and R data states to infer whether the memory cell desirably operates as a four-state, single-programmed memory cell. If the memory array fails the test, it can be used as a two-state memory array in which the appropriate flags are stored. This port uses an inverse c memory array that can be used in conjunction with a set of memory cells using x resistivity states to represent the X data states, and together with the Y resistivity states - a second set of memory cells - It is used to represent Y species of beriberi, where X矣γ. In this manner, the number of data states stored in a memory cell in the memory array can vary between groups of memory cells. The various versatile and mixed versatility described above can be combined. For example, S, the first set of memory cells and the second set of memory cells in the memory array can use different numbers of data states, and both can be single-programmed and both can be rewritten. Or a single stylized and rewritable mix. In other words, portions of the memory array can be any combination of a single-programmed memory unit and a rewritable memory unit, some of which store I2890.doc -45-200818204 data status (eg, + description) The second, the two negative states) and the other part stores the gamma data state (for example, two Germans vu _ two or more tributary states). For example, the memory array can have a first or a group of brothers, which can be single-programmed and have more than two types of caution (for example, for stylized data); And a set of two memory cells, which are rewritable and have two or more kinds of data for use as scratch pad memory. There can be more than two parts.

As described above, the choice of how many data states to use in any group of memory cells can be determined by testing. For example, if the circuit is read, what is the difference between V and ? With the R state, the four-state single-programmed memory failed the test 70 times earlier. The memory array segment containing their test memory cells can then be used as a two-state rewritable portion. In this case, the write circuit can be verified using a repetitive write stylization (as described above) and then re-privatized to push the R state &quot;push&quot; to the v state and the $state&quot; "Y-sorrowful. In other words, the repeated feedback mechanism, open" space between the R state and the S state, the multi-purpose memory array with different data states is determined: in fact, although ^ The memory unit has the potential to store more than two data states. The most efficient use of the memory cells in the memory array occurs in the memory array. Not all memory cells store more than two states. For example, In a preferred embodiment, a first set of memory cells is for a single-human autumn memory cell, and a second set of memory cells 2 is a rewritable memory cell. This embodiment is shown. In this embodiment, the optimal configuration for reading the four-state memory unit is stored in the two state memory cells. For example As shown in the figure, the configuration bit in the page indicates the page read by the two-state read circuit operation per memory unit with respect to the operation of the four-state read circuit per memory unit. The state bit also determines that each The limitation of the available bits in the two-bit sad page of the memory unit. When writing to the page, the part of the wafer for the two-state data and the four-state data is configured. For the single-programmed memory unit In this way, the page can be written several times to include additional configuration bits indicating the extra portion for the two-state data, since the configuration bits are all set to logic "&quot;, indicating the page division. In addition, all pages are read as four-state data (ie, the default configuration is only read page 〇 for two-dimensional data retention)

) Native early = person privateized memory unit state (V-shaped sadness) is logic 1 &quot;. The default configuration and interpretation of the configuration bits is performed by logic coding on the memory chip. The number of columns is not necessarily equal to the number of pages, but is preferably a simple multiple (for example, four pages to one column). Tian Ran's other configuration systems are feasible. For example, another application may have the third part of the data as a single-state and two-state data, which is based on the system, and the test refers to the second-order best memory in the third part of the memory.兀 (10) In yet another application, the memory array has a single-person &-memory memory unit in the first portion and two or more state-of-the-art re-memory units (eg, you η μ, 』 R, S and R1 states). The optimal circuit configuration is stored in a two-state single-programmed memory unit. In addition, the memory array can be two of the right/network/partial part. The state-of-the-art rewritable memory unit and the two or more state-of-the-art rewritable memory units in the second omnibus &quot; knife. Dry 121890.doc •47- 200818204 Please refer to the figure again, Figure 22 shows A specific implementation diagram, the towel is represented by the flag bit on the field of the body matrix of each entity i.. 3⁄4 body array refers to the two states of the body unit and the four-character flag of each memory unit: Good system two state data per memory unit. Even number is associated with each column Read as &quot;" shows that the page is not available. It is not available. The page flag of the page can not be used. It is also stored in the control logic or software, and can be used by the body outside the day. The system is re-delegated by known redundant/bad block mechanisms. Alternatively, the flag can be associated with multiple pages, with the flag number 兀 'unit status number and two The number of even columns per memory column for the column is available. Preferably, each square is used for a number of adjacent columns, and the &amp; block used for the bad block table is preferably defined as a binary of the column. FIG. 23 is a diagram showing the memory array of the preferred embodiment of the memory array stored in the memory array, and the T memory can be stored in the memory array. The portion of the four-state of the body unit. The translation table has a correspondence between the logical page/the body column in the body array, and the translation, =L1—the flag bit of the number of bits stored in the entity column. 2. The translation table also has instructions indicating that certain pages can be single-programmed = 糸 two rewritten materials. The flag, the flag bit, preferably controls the read and write circuits for the optimal setting of the type of data used for the indication. Figure is a diagram showing a memory array of a preferred embodiment, wherein: The upper flag bit indicates the two states of each memory unit. The early humanized αΡ points, the two states of each memory unit can be weighted, and the memory unit states can be single-cut material. 121890.doc -48- 200818204 The 'flag bit is stored as two state data per memory unit. An even number of pages are associated with each column. The off-chip controller scans the flag information to create a bad block table. A flag bit for some pages indicates that the page is not available. The flag bit also preferably controls the read and write circuits on the wafer to provide two state operations and rewritable relative to each memory cell. The best configuration for single-programming operations. In this case, the flag bit indicated in FIG. 24 includes at least one bit for indicating the number of states per memory unit and a bit for indicating that it can be single-programmed or rewritable. In some embodiments, more than two bits can be used. A preset setting of the two states of the memory unit reads the flag bit located at the preliminary physical address (step 320). If you want to be in the company -

Or write the page data (step 35〇:). Figure 25 depicts a flow diagram of a preferred embodiment using a wafer flag and an off-chip bad block mechanism. Provide a logical page address (step 3〇〇). A bad block table in the controller-memory controller wafer is associated with the translation logic to determine a preliminary physical address associated with the logical page address (step 31). Then, with each

A TL1Dlnary) metal oxide, other switchable resistive material includes, but is not limited to, a compound, a phase change material (e.g., U.S. Patent No. I21890.doc-49-200818204 5,751,012 and U.S. Patent No. 4,646,266 And an organic material resistor 'for example' includes a plurality of memory cells of an organic material layer comprising at least one layer having a conductivity-like conductivity and at least one organic material applying an electric field to change the conductivity. U.S. Patent No. 0,055,180 describes an array of organic passive τ. Another varistor material is an amorphous ruthenium doped with v, Co Ni, Pd, Fe or Mn, as described more fully in U.S. Patent No. 5,541,869. U.S. Patent No. 6,473,332 teaches another-category material. These materials are _ titanium ore materials, such as PmCaxMn〇3 (PCM0), Lai xCaxMn〇3 (LCM〇),

LaSrMn03 (LSMO) or GdBaCox〇Y (GBCO). Another option for this variable resistance material is a carbon polymer film comprising, for example, carbon black particles or graphite mixed in a plastic polymer, as taught in U.S. Patent No.. Another switchable resistive material is taught in U.S. Patent Application Serial No. 9/943, 190, and U.S. Patent Application Serial No. 09/941,544. This material is a chalcogenide glass doped with the molecular formula AXBY, wherein A contains at least one of the following elements of the periodic table: Group (1) Group 8 (B, A, Ga, In, Ti), Group IVA (C, Si, Ge, Sn, Pb), Group VA (N, P, As, Sb, Bi) or Group VIIA (F, Cl, Br, I, At); wherein the B is selected from the group consisting of s, with Te and mixtures thereof. The dopant is selected from the group consisting of noble metals (n〇Me met卟 and transition metals, including Ag, An, Pt, Cu, Cd, Ir, Ru, c〇, Cr, Mn or Ni. This chalcogenide glass (amorphous sulfur) The family, rather than the crystalline state, is preferably formed in a memory cell adjacent to the mobile metal ion reservoir. Some other solid electrolyte material may be substituted for the chalcogenide glass. In a preferred embodiment, the component comprises The antifuse is connected in series to the semiconductor material 121890.doc • 50-200818204. In another preferred embodiment, the memory component comprises an antifuse, a binary metal oxide, and a polysilicon germanium isolation device. In addition, although the memory unit can be a component of the two-dimensional memory array, in a more conventional manner, the memory unit is a component of a single-chip three-dimensional memory array, wherein the memory unit is arranged in a plurality of layers of memory, Each memory level is formed over a single substrate and without any interposer. It is presently preferred that the memory elements are non-volatile. However, in an alternate embodiment, the memory elements operate. In the data state used when the memory cell can be rewritten, the memory component can be volatile. For example, the 'memory component can allow the chirp state and the p state to be permanent, but can allow the R state and the s state to slowly fade. Using this-memory component, the R state and the S state will be refreshed over time. As described in detail, only a few of the many forms of the present invention can be used, and for many reasons, for this reason, The syllabus of the syllabus is to explain the invention, not to limit the invention. Only the following requests (including all equivalents) are intended to define the scope of the invention. Description] Figure 1 shows the circuit diagram required for electrical isolation between the memory cells in the memory array. Figure 2纟 shows a better and better mode according to the present invention. A cross-sectional view of a multi-state or rewritable memory cell formed by the example of a basket. Figure 3 is a cross-sectional view of a portion of the memory level of the memory device shown in Figure 2. 4 depicts the record of the present invention Recall that the current of the body is changed as the reverse bias voltage across the diodes 121890.doc -51- 200818204 increases. Figure 5 shows that the memory cell changes from the v state to the p state, Figure 6 shows the memory cell transition from V state to P state, P state to S state, and S state transition to R. Figure 7 illustrates the probability plot of the memory unit transitioning from the V state to the r state, the transition from the r state to the S state, and the transition from the s state to the p state. Figure 8 illustrates that the present invention can be embodied in the present invention. A cross-sectional view of a vertically oriented p-i_n diode used in the embodiment. Figure 9 illustrates a probability plot of a memory cell transitioning from a v state to a p state and from a p state to a chirp state. 10 is a cross-sectional view of a multi-state or rewritable memory cell formed in accordance with a preferred embodiment of the present invention. Fig. 11 is a diagram showing the probability of the memory cell changing from the ν state to the Ρ state, the self-turning state to the R state, and the transition from the R state to the s state, and then repeatable between the 8 state and the R state. Figure 12 depicts a circuit diagram of a biasing scheme that does not bias the 8 memory cells with a forward bias. Figure 13 is a circuit diagram showing the biasing scheme for biasing the three memory cells with a reverse bias. Figure 14 depicts a non-repetitive read_verify_write cycle to move the memory cells into the data state. 15a through 15c are cross-sectional views showing stages in the formation of a memory level formed in accordance with an embodiment of the present invention. 121890.doc -52- 200818204 Figure 16 is a cross-sectional view of a diode and a resistive switching element that can be used in an alternative embodiment of the present invention. Figure 17 is a diagram showing a preferred embodiment of a mixed-use memory array in which a first group of memory cells operate as a single-programmed memory cell and a second group of memory cells operate as Overwrite the memory unit. Figure 18 is a schematic illustration of a mixed-use memory array of the preferred embodiment in which a plurality of sets of single-programmable memory cells and rewritable memory cells are interleaved. Figure 19 is a diagram showing a circuit of a preferred embodiment showing a group of memory cells programmed with forward bias. Figure 20 is a schematic illustration of a circuit of a preferred embodiment showing the programming of a set of memory cells with a reverse bias. Figure 21 is a diagram showing a memory array of a preferred embodiment, wherein the first portion of the A fe body array stores two data states per memory cell and the first portion of the memory P train stores each memory Four data states of the body unit. Figure 22 depicts an illustration of a memory array in a non-better embodiment in which portions of each state of each memory cell and portions of four states of each memory cell are indicated by flag bits on each bay page. Figure 23 ',, day tf #又&gt; [Illustration of the memory array of the concrete embodiment, wherein each memory unit is indicated by a clock table stored in the memory array. The sorrow, the part, and the four states of each memory unit. Figure 24 is a block diagram of a memory array of a preferred embodiment, wherein the two states of each memory unit are indicated by a flag bit on each physical page. 121890.doc -53 - 200818204 can be a single stylized portion The two-state rewritable portion of each memory unit and the four-state single-programmed portion of each memory unit. Figure 25 depicts a flow diagram of a preferred embodiment using a wafer flag and an off-chip bad block mechanism. [Main component symbol description]

2 polycrystalline semiconductor diode 4 bottom heavily doped n^} region (Figure 2) 4 bottom heavily doped p-type region (Figure 8) 6 essential region 8 top heavily doped region (Figure 2) 8 top heavy miscellaneous N-type region (Fig. 8) 12 bottom conductor 14 dielectric rupture antifuse 16 top conductor 100 substrate 102 insulating layer 104 adhesive layer 106 conductive layer 108 dielectric material 109 flat surface 110 barrier layer 111 diode 112 bottom doping Miscellaneous Zone 114 Essential Layer 12I890.doc -54- 200818204

116 top heavily doped p-type region 117 switchable memory element 118 dielectric rupture anti-fuse layer 120 adhesive layer 122 conductive layer 200 conductor (first conductor; conductor; bottom conductor) (Fig. 15a-c) 200 memory Body array (Fig. 17) 210 The first group of memory units 220 The second group of memory units 230, 250 can be a single programd section 240, 260 rewritable section 270 flag bit 300 column 400 conductor (conductor implementation ; top conductor) A, A0, A1 word line B, BO, B1 bit line F, H semi-selected memory unit U non-selected memory unit M, P, R, S, V memory unit data status Ul, U2, U3 Unselected memory unit 121890.doc -55-

Claims (1)

200818204 X. Patent application scope: 1. A memory array, including: a plurality of memory cells, ^ mother-memory unit includes a ~K secret member, the memory component includes a group of a switchable resistive material of at least two buds; wherein the plurality of memory cells in the resistivity state comprises: - a first set of memory cells that broadly indicate X respective data states; and D The leather-like evil cousin - group reading, body unit, which uses Y kinds of electricity and not Y kinds of data status, of which χ ^. The shape is also shown in Table 2. If the memory of the request item is 锸 七 VII, the middle memory group of the memory unit # uses two resistivity states to make the 筮 one, not the two respective brooding states; In the basin, 兮-,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, The body unit makes the ~ resistivity state to represent the two respective data states, and its middle:::1: the memory cell uses four resistivity states to represent each of the four: 4·^ (4) Two sets of memory cell storage full page data, and wherein the first 'group memory unit is a full page of data. 5.: Please: Item 4 of the memory array 'where the first set of memory ^ one + page data. 6. If the memory array of the research project 1 is in the first group of memory, 121890.doc 200818204 and the predetermined number in the second group of memory cells - ▲ 里 里 忆 体 体 quot ; the first group of §   memory cells stored in the memory unit Less than the memory cells in the second set of memory cells = stored data. 7. The memory array of the request, wherein the first set of memory cells stores one or more of the items : content management bit, trim bit, 'manufacturer data or formatted data. 8. If the memory array of the item i, the first group of memory cells and the two groups of memory cells are both The operation is a single-programmed memory soap element.: The memory array of claim 1 wherein the first group of memory cells and the memory cells of the memory device operate as a single-cut memory-: The other one of the first group of memory cells and the second group of memory cells 70 operates as a rewritable memory cell 1. In addition: the memory array of claim 9 wherein the first group of records Billion unit transport body:: can be a flat program memory unit, and the second group of memory - early operation as a rewritable memory unit. 11 · If the memory of the item 9 is π w T, a group of memory cells, ^ early stylized memory cells, and Among them, the fine body of the body;; macro &quot; /, τ side of the first group # own thinking, operating as a rewritable memory unit. 12. If the memory of the requester - know a /, T to a group Both the memory unit and the memory unit operate as 13 · as requested in the article 』 』 』 里 fe fe fe 体 兀 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 体 体 体 体 体 体 体# I w The body of the memory is stored earlier, the column of memory cells stores the first number of pages 121890.doc 200818204, and wherein the second group of memory cells, the same size of the body size The first number of pages in the database. The music memory column, which is recorded in the switchable resistive material - the anti-refining wire. ^ Include series. 15. As requested by the memory array, it contains - semiconductor material. Knife-changing resistor package 16. The memory array of claim 15, wherein the semiconductor material comprises a polycrystalline germanium diode. The Z 11 body array of the slice 2=^1, wherein the array of each memory includes a single complex memory array, wherein the plurality of memory cells are arranged in the level of the memory layer, each memory level Formed on top of a single substrate and without any interposer. 18. A method of using a memory array, the method comprising: providing: a memory array 'the memory array comprising a plurality of memory-early elements, each memory unit comprising a memory element, The body element includes configurable to at least three of the resistivity states: a switchable resistive material; (b) in a first set of memory cells, x types of resistors are used to represent the respective data states of the X species; ~, (c) In a second group of memory cells, using γ kinds of resistivity to distinguish the respective data states, where X races 〇 19. as in May, the method of claim 18, where X system 2, tethered; 2 or more. 2. The method of claim 18, further comprising: 121890.doc 200818204 storing in the st-shaped array in a hundred-negative, τ a page of poor materials and an associated at least one configuration bit, The at least one buckle At, the bad position 70 indicates a first or second mode of operation. 21. The method of claim 20, wherein the method is at least the same as the entity column of the page material. The configuration bit is stored in phase 22. As in the request item 20, the configuration bits for the plurality of page data are stored in a _ ^ ^ ^ κ body of the memory array. In the column, the entity column is different The columns of entities that store the associated page data. 23. The method of claim 20, further comprising: reading the at least one configuration bit; if the at least - configuration bit indicates the first mode of operation, controlling the read circuit to identify a memory cell Two of the data states; and if the at least-configured bit indicates the second mode of operation, controlling the read circuit to identify at least three data states in a memory cell. The method of claim 2, further comprising: reading the at least one configuration bit; if the at least one configuration bit indicates the first operation mode, controlling the write circuit to be in a memory One of the two data states being programmed in the body unit; and if the at least one configuration bit indicates the second mode of operation, controlling the write circuit to program the at least three data states in a memory unit One. [25] The method of claim 20, wherein the at least one configuration bit comprises two materials 121890.doc 200818204 material status 'even for the data sheet of the two or more data states of the device . 26. The method of claim 18, further comprising before (b) and (c): testing the § memory array by a set of test memory cells in J; predicting the brother in the memory array J A set of memory cells will use two respective data states without proper programming; and predict that the second set of memory cells in the memory array will be properly programmed using two respective lean states. 27. The method of claim 18. ^ Further comprising: stylizing one or more of the following items in the first group of pity g - ^ body 7L: content management bit, pin, repair bit TL, manufacturer data or formatted data0 The method of claim 18, wherein the memory component comprises an antifuse connected in series with the switchable resistive material. The method of claim 18, wherein the switchable resistive material comprises half of the conductor material. The method of claim 29, wherein the semiconductor material comprises a polycrystalline spine. 31. The method of claim 18, wherein the memory array comprises a monolithic three-dimensional hidden array&apos; + + the plurality of memory cells are arranged in a plurality of layers. In the k-level, each memory level is formed over a single substrate and without any interposer. 121890.doc