200816413 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種非中心黏晶積體電路封裝構造， 特別係有關於一種防止翹曲之非中心黏晶積體電路、 裝構造。 封 【先前技術】 在以往的積體電路封裝構造中，晶片皆是設置在封裳構 造之基板中心線，可以避免單侧邊過於翹曲的問題。然而， • 隨著晶片設計之不同，在有限的基板空間内，於特定封裝型 態中晶片將無法對準在基板之中心線。 如第1圖所示，習知非中心黏晶積體電路封裝構造 100包含一基板H0、一晶片120以及一封膠體13〇。 該晶片120係設置於該基板11〇之一上表面u卜複數 個外接端子150則可設置於該基板11〇之一下表面 1 1 2。該晶片1 2〇係具有複數個非對稱排列之銲墊 1 21 (如第2圖所示）。可利用打線技術形成複數個銲線 馨 140 ,電性連接該晶片120之該些銲墊121至該基板 110。該封膠體130係形成於該基板之上表面 以密封該晶片1 2 0與該些銲線1 4 0。在有限的配置空 間内’該晶片1 20之中心無法對準在該基板丨丨〇之中 心’鋅線1 4 0配置在該基板11 〇之特定部位，導致該 晶片1 20之一晶片側距離對應該基板之側邊的間隔大 於該晶片12 0之其它晶片側。在前述缺乏晶片之間隔 處使得該封膠體1 3 0有較厚厚度且該基板丨i 〇有較弱 200816413 的結構強度，該封膠體1 3 0的固化收縮與熱循環作用 下，造成内應力不平衡而導致該封膠體i 3〇之單側邊 有較為嚴重的翹曲現象，甚至會導致與該基板11〇之 剝層（Delamination)。 【發明内容】 為了解決上述之問題，本發明之主要目的係在於提 供一種防止翹曲之非中心黏晶積體電路封襞構造，利 用應力平衡件在基板上設置方式可達到封膠體在非中 〜勒晶之基板兩侧内應力達到平衡，避免封膠體翹曲 甚至剝層（Delamination)之問題發生。 本發明之次一目的係在於提供一種防止翹曲之非 中心黏晶積體電路封裝構造，其應力平衡件除了可以 防止勉曲更可以作為接地匯流排，達到方便地接地連 接之功效。 本發明的目的及解決其技術問題是採用以下技術 方案來實現的。依據本發明，一種防止輕曲之非中心 勒晶積體電路封裝構造主要包含一基板、一晶片、至 少一應力平衡件以及一封膠體。該基板係具有一上表 面與一下表面，該上表面係具有對應平行之第一基板 侧與第二基板側。該晶片係非中心設置於該基板之該 上表面，其中該晶片係具有對應平行之第一晶片側與 第二晶片侧，該第一晶片側大致平行於該第一基板側 且相對該第二晶片側更接近該第一基板侧，該第一晶 片側至該第一基板側之距離係大於該第二晶片側至該 6 200816413 第二基板側之距離。該應力平衡件係設置於該基板之 該上表面且位於該第一晶片側至該第一基板側之間。 該封膠體係形成於該基板之該上表面上，以密封該晶 片與該應力平衡件。 本發明的目的及解決其技術問題還可採用以下技 術措施進一步實現。 在前述的防止翹曲之非中心黏晶積體電路封裝構 造中，該應力平衡件係為一矽質條。 在前述的防止龜曲之非中心黏晶積體電路封裝構 造中，該應力平衡件係選自於虛晶片或與該晶片之熱膨脹係 數相當之物質。 在前述的防止翹曲之非中心黏晶積體電路封裝構 造中，該晶片係、具有複數個非對稱排列之銲墊，該些鲜塾係 至少沿著該第一晶片侧設置於該主動面上。 在前述的防止翹曲之非中心黏晶積體f路封裝_ 造中’另包含有複數個銲線，其係電性連接該些銲墊至該基 板0 造中，該些銲線係跨越該應力平衡件 在前述的防止想曲之非中心黏晶積體電路封裝構 造中，該些鐸墊之排列方式係為_字形、L形或门型。 在前述的防止翹曲之非φ、、 中心黏晶積體電路封桊媸 造中，該上表面係更具有對應 Μ 卞仃之第二基板側與第四美; 側，該晶片係更具有對應平行 土板 之第二晶片側與第四晶片側， 7 200816413 . 該第二晶片侧大致平行於該第三基板側且相對該第四晶片 側更接近該第三基板侧，該第三晶片側至該第三基板側之距 係大於該苐四晶片側至該第四基板側之距離，並且另包含 另應力平衡件，其係設置於該基板之該上表面且位於該第 三晶片侧至該第三基板側之間。 在別述的防止勉曲之非中心黏晶積體電路封裝構 造中，另包含有複數個外接端子，其係設置於該基板之該下 表面。 _ 在前述的防止翹曲之非中心黏晶積體電路封裝構 &中’ β些外接端子係包含複數個銲球。 在前述的防止翹曲之非中心黏晶積體電路封裝構 造中’該些外接端子係包含複數個金屬墊。 在前述的防止翹曲之非中心黏晶積體電路封裝構 &中，該封膠體係為模封陣列處理（MAP)形成之模封膠體。 生在前述的防止翹曲之非中心黏晶積體電路封裝構 _ 迨中，該應力平衡件係為接地連接。 生在前述的防止翹曲之非中心黏晶積體電路封裝構 &中另包a至：一接地銲線，其係電性連接該晶片與該應 力平衡件。 【實施方式】 在本1月之第具體實施例中，揭示一種防止翹曲 之非中心黏晶積體電路封裝構造，第3圖係為該積體 電路封裝構造之截面示意、目，帛4@是為該積體電路 封裝構造未封膠前之頂面示意圖。 200816413 如第3及4圖所示，一種防止魅曲之非中心黏晶積 體電路封裝構造2 0 0主要包含一基板2 1 0、一晶片 220、至少一應力平衡件23〇以及一封膠體24〇。該基 板210係具有一上表面215與一下表面216，該上表 面2 1 5係具有對應平行之第一基板侧2 1 1與第二基板 側2 1 2以及對應平行之第三基板側2 1 3與第四基板側 214(如第4圖所示）。通常該基板210係為一種雙面電 性導通之印刷電路板。 # 如第3圖所示，該晶片220係非中心設置於該基板 2 1 0之該上表面2 1 5，即是該晶片220之中心點係不對 準在該基板210之一中心線2 01。其中，如第4圖所 示，該晶片220係具有對應平行之第一晶片側221與 第二晶片側222與對應平行之第三晶片側223與第四 晶片側224。該第一晶片侧221大致平行於該第一基 板側2 1 1且相對該第二晶片側222更接近該第一基板 側2 1 1，並且由該第一晶片側22 1至該第一基板側2 1 1 之距離係大於該第二晶片側222至該第二基板側2 1 2 之距離。 此外，該晶片220係具有複數個非對稱排列之銲墊 225，該些銲墊225係至少沿著該第一晶片侧221設置 於該主動面上。在本實施例中，該些銲墊225之排列 方式係為一字形。或者，該些銲墊225之排列方式亦 可為L形。 該應力平衡件2 3 0係設置於該基板2 1 0之該上表面 200816413 215且位於該第一晶片侧221至該第一基板侧21 it 間。較佳地，該應力平衡件2 3 0係可選自於虛晶片 (dummy chip)或與該晶片22〇之熱膨脹係數相當之物 質。在本實施例中，該應力平衡件23〇係可為一矽質 條。在不同實施例中，該應力平衡件23〇亦可為一硬 質金屬加固條。 可藉由複數個銲線250電性連接該非中心黏晶之 晶片220之該些銲墊225至該基板210。其中，該些 銲線2 5 0係可跨越該應力平衡件2 3 〇。 該封膠體240係形成於該基板21〇之該上表面215 上，以密封該晶片220、該應力平衡件23〇與該些銲 線250。在本實施例中，該積體電路封裝構造2〇〇另 包含有複數個外接端子260，例如銲球，其係設置於 該基板210之該下表面216，以供對外表面接合。 因此，該應力平衡件230除了可以加強該基板21〇 在缺少晶片部分（即第一基板侧2 1 1 )之抗翹曲強度，同 時減少該封膠體240在該基板2 1 0上缺少晶片部分之 厚度，避免該封膠體240在固化收縮時產生非中心黏 晶之内應力不平衡，減少封膠體翹曲甚至剝層之問題 發生。 再如第4圖所示，在本實施例中，該晶片220之該 第三晶片侧223大致平行於該第三基板側2 1 3且相對 該第四晶片侧224更接近該第三基板側21 3，該第三 晶片側223至該第三基板侧2 1 3之距離係大於該第四 10 200816413 晶片側224至該第四基板侧2 14之距離，故會有另一 側邊非中心黏晶之現象。可利用另一應力平衡件2 7 0， 其係設置於該基板2 1 0之該上表面2 1 5且位於該第三 晶片側2 2 3至該第三基板側2 1 3之間，解決該基板2 1 〇 另一側翹曲之問題。 在本發明之第二具體實施例中，揭示另一種防止勉 曲之非中心黏晶積體電路封裝構造300。如第5及6 圖所示，一積體電路封裝構造300主要包含一基板 310、一晶片320、至少一應力平衡件330以及一封膠 體3 40。該基板310係具有一上表面315與一下表面 3 1 6。如第6圖所示，該上表面3 1 5係具有對應平行之 第一基板侧3 11與第二基板側3 1 2。該上表面3 1 5係 更具有對應平行之第三基板侧3 1 3與第四基板側3 1 4。 該晶片3 2 0係非中心設置於該基板3 1 0之該上表面 3 1 5，其中該晶片3 20係具有對應平行之第一晶片側 321與第二晶片側322與對應平行之第三晶片側323 與第四晶片側324。該第一晶片侧321大致平行於該 第一基板側3 1 1且相對該第二晶片侧3 22更接近該第 一基板側3 1 1，該第一晶片侧3 2 1至該第一基板侧3 1 1 之距離係大於該第二晶片側322至該第二基板側3 12 之距離。在本實施例中，該第三晶片側3 2 3至該第三 基板側3 1 3之距離係约略等於該第四晶片側3 24至該 第四基板側3 1 4之距離，而不需要貼設應力平衡件。 該晶片3 2 0係具有複數個非對稱排列之銲墊3 2 5。 11 200816413 在本實施例中，該些銲墊3 25為门形排列，該些銲墊 3 2 5係沿著該第一晶片側3 2 1、該第三晶片側3 2 3及該 第四晶片側324設置於該晶片320之一主動面上。 又如第5及6圖所示，該應力平衡件3 3 〇係設置於 該基板3 1 0之該上表面315且位於該弟"—晶片侧3 2 1 至該第一基板側3 1 1之間，以加強該基板3 1 0缺乏晶 片部位之抗翹曲強度，以減少缺乏晶片部位之封膠體 厚度，以達到非中心黏晶之内應力平衡之功效。該應 力平衡件330係可選自於虛晶片或與該晶片32〇之熱 膨脹係數相當之物質。 並利用複數個銲線3 5 1電性連接該些銲墊3 2 5至該 基板310，其中連接在該第一晶片側321之銲墊325 至該基板之部分銲線351係跨越該應力平衡件33〇。 該封膠體340係形成於該基板31〇之該上表面315 上，以岔封該晶片3 2 0、該應力平衡件3 3 〇與該些銲 線351。在本實施例中，該封膠體34〇係為模封陣列 (M A P )形成之模封膠體，利用該應力平衡件$ $ 〇 更具有模流平衡之功效。此外，在本實施例中，該積 體電路封裝構造300另包含有複數個外接端子360， 例如金屬墊，其係設置於該基板3 1 0之該下表面3 i 6， 以供對外電接觸或焊接接合。 因此，可利用該應力平衡件3 3 0之設置方式解決習 β〇非中心黏晶之内應力不平衡引起的封膠體翹曲問 題進而避免了在該封膠體3 40與該基板310發生剝 12 200816413 層（delamination)之問題。 較佳地，該應力平衡件330係為接地連接。一種接 地連接方式為，該應力平衡件330之上表面形成有一 金屬層3 3 1。利用至少一接地銲線3 5 3電性連接該晶 片3 20與該應力平衡件330之一金屬層331，再藉由 至少一銲線3 5 2電性連接該應力平衡件3 3 0之該金屬 層331至該基板310(如第6圖所示）。使得該應力平衡 件3 3 0除了可以防止翹曲更可以作為接地匯流排，達 到方便地接地連接之功效。 以上所述，僅是本發明的較佳實施例而已，並非對 本發明作任何形式上的限制，雖然本發明已以較佳實 施例揭露如上，然而並非用以限定本發明，任何熟悉 本項技術者，在不脫離本發明之技術範圍内，所作的 任何簡單修改、等效性變化與修飾，均仍屬於本發明 的技術範圍内。 【圖式簡單說明】 第1圖：一種習知非中心黏晶積體電路封裝構造之截 面示意圖。 第2圖：習知積體電路封裝構造在封膠前之頂面示意 圖。 第3圖：依據本發明之第一具體實施例，一種防止勉 曲之非中心黏晶積體電路封裝構造之戴面示 意圖。 第4圖：依據本發明之第一具體實施例，該積體電路 13200816413 IX. Description of the Invention: [Technical Field] The present invention relates to a non-central bonded circuit package structure, and more particularly to a non-central bonded crystal circuit and package structure for preventing warpage. Seal [Prior Art] In the conventional integrated circuit package structure, the wafers are all placed on the center line of the substrate of the package structure, which avoids the problem that the one side is too warped. However, • Depending on the chip design, within a limited substrate space, the wafer will not be aligned at the centerline of the substrate in a particular package. As shown in FIG. 1, the conventional non-center bonded circuit package structure 100 includes a substrate H0, a wafer 120, and a gel 13 〇. The wafer 120 is disposed on one surface of the substrate 11 and includes a plurality of external terminals 150 disposed on a lower surface 1 1 2 of the substrate 11 . The wafer 12 has a plurality of asymmetrically arranged pads 1 21 (as shown in Figure 2). A plurality of soldering wires 140 may be formed by wire bonding techniques to electrically connect the pads 121 of the wafer 120 to the substrate 110. The encapsulant 130 is formed on the upper surface of the substrate to seal the wafer 120 and the bonding wires 140. In a limited configuration space, the center of the wafer 1 20 cannot be aligned at the center of the substrate. The zinc line 140 is disposed at a specific portion of the substrate 11 , resulting in a wafer side distance of the wafer 1 20 . The spacing of the sides of the corresponding substrate is greater than the other wafer sides of the wafer 120. In the foregoing gap lacking the wafer, the sealant 130 has a thick thickness and the substrate 丨i 〇 has a weak structural strength of 200816413, and the sealant 1300 has curing shrinkage and thermal cycling, causing internal stress. Unbalanced results in a relatively severe warpage on the one side of the encapsulant i 3 , and may even cause delamination with the substrate 11 . SUMMARY OF THE INVENTION In order to solve the above problems, the main object of the present invention is to provide a non-central bonded crystal circuit sealing structure for preventing warpage, and the sealing member can be disposed on the substrate by using a stress balance member. ~ The internal stress on both sides of the substrate is balanced to avoid the problem of sealant warpage or even peeling. A second object of the present invention is to provide a non-central bonded crystal circuit package structure for preventing warpage, in which the stress balance member can be used as a ground bus bar in addition to preventing distortion, thereby achieving the effect of convenient ground connection. The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. According to the present invention, a non-central crystallographic circuit package structure for preventing light curvature mainly comprises a substrate, a wafer, at least one stress balance member, and a gel. The substrate has an upper surface and a lower surface, the upper surface having a corresponding first substrate side and a second substrate side. The wafer is non-centered on the upper surface of the substrate, wherein the wafer has a corresponding first wafer side and a second wafer side, the first wafer side being substantially parallel to the first substrate side and opposite to the second The wafer side is closer to the first substrate side, and the distance from the first wafer side to the first substrate side is greater than the distance from the second wafer side to the 6 200816413 second substrate side. The stress balancing member is disposed on the upper surface of the substrate and between the first wafer side and the first substrate side. The encapsulation system is formed on the upper surface of the substrate to seal the wafer and the stress balance member. The object of the present invention and solving the technical problems thereof can be further achieved by the following technical measures. In the aforementioned warpage preventing non-central bonded circuit package structure, the stress balance member is a tantalum strip. In the aforementioned non-central bonded circuit package structure for preventing tortuosity, the stress balance member is selected from a virtual wafer or a material having a thermal expansion coefficient equivalent to the wafer. In the above-described warpage preventing non-center bonded circuit package structure, the wafer system has a plurality of asymmetrically arranged pads, and the fresh slabs are disposed on the active surface at least along the first wafer side. on. In the above-mentioned non-centralized non-central bonded body f-package_integration, a plurality of bonding wires are further included, which electrically connect the pads to the substrate 0, and the bonding wires are crossed In the above-described non-central bonded structure circuit package structure for preventing the distortion, the stress balance members are arranged in a zigzag shape, an L shape or a gate shape. In the above-mentioned anti-bending non-φ, center-bonded circuit circuit package, the upper surface has a corresponding second substrate side and a fourth side; the wafer system has a corresponding parallel a second wafer side and a fourth wafer side of the earth plate, 7 200816413. The second wafer side is substantially parallel to the third substrate side and closer to the third substrate side than the fourth wafer side, the third wafer side to The distance from the third substrate side is greater than the distance from the fourth wafer side to the fourth substrate side, and further includes a further stress balancing member disposed on the upper surface of the substrate and located on the third wafer side to the Between the third substrate sides. In the non-centralized non-central bonded circuit package structure described above, a plurality of external terminals are further provided on the lower surface of the substrate. _ In the aforementioned warpage preventing non-centered bonded circuit package structure, a plurality of external terminals include a plurality of solder balls. In the aforementioned warpage preventing non-center bonded circuit package structure, the external terminals comprise a plurality of metal pads. In the aforementioned warpage preventing non-centered bonded circuit package structure, the encapsulant system is a mold encapsulant formed by a mold array processing (MAP). Born in the aforementioned warpage preventing non-central bonded circuit package structure, the stress balance member is a ground connection. The above-mentioned non-centralized non-central bonded circuit package structure of the warpage is further provided to: a ground bonding wire electrically connecting the wafer and the stress balancing member. [Embodiment] In the first embodiment of the present invention, a non-central bonded crystal circuit package structure for preventing warpage is disclosed, and FIG. 3 is a schematic cross-sectional view of the integrated circuit package structure. @ is a top view of the integrated circuit package structure before unsealing. 200816413 As shown in FIGS. 3 and 4, a non-centered bonded circuit package structure for preventing temperament is mainly composed of a substrate 210, a wafer 220, at least one stress balance member 23, and a colloid. 24〇. The substrate 210 has an upper surface 215 and a lower surface 216. The upper surface 215 has a corresponding first substrate side 2 1 1 and a second substrate side 2 1 2 and a corresponding parallel third substrate side 2 1 . 3 and the fourth substrate side 214 (as shown in Fig. 4). Typically, the substrate 210 is a two-sided electrically conductive printed circuit board. As shown in FIG. 3, the wafer 220 is non-centered on the upper surface 2 15 of the substrate 210, that is, the center point of the wafer 220 is not aligned on a center line of the substrate 210. . As shown in Fig. 4, the wafer 220 has a first wafer side 221 and a second wafer side 222 which are parallel to each other, and a third wafer side 223 and a fourth wafer side 224 which are correspondingly parallel. The first wafer side 221 is substantially parallel to the first substrate side 2 1 1 and closer to the first substrate side 2 1 1 with respect to the second wafer side 222 and from the first wafer side 22 1 to the first substrate The distance of the side 2 1 1 is greater than the distance from the second wafer side 222 to the second substrate side 2 1 2 . In addition, the wafer 220 has a plurality of asymmetrically arranged pads 225 disposed on the active surface at least along the first wafer side 221. In this embodiment, the pads 225 are arranged in a line shape. Alternatively, the pads 225 may be arranged in an L shape. The stress balance member 203 is disposed on the upper surface 200816413 215 of the substrate 2 10 and between the first wafer side 221 and the first substrate side 21 it. Preferably, the stress balance member 230 is selected from a dummy chip or a substance having a thermal expansion coefficient equivalent to that of the wafer 22. In this embodiment, the stress balance member 23 can be a tantalum strip. In various embodiments, the stress balance member 23 can also be a rigid metal reinforcing strip. The pads 225 of the non-center bonded wafer 220 can be electrically connected to the substrate 210 by a plurality of bonding wires 250. Wherein, the bonding wires 250 can span the stress balance member 2 3 〇. The encapsulant 240 is formed on the upper surface 215 of the substrate 21 to seal the wafer 220, the stress balance member 23, and the solder wires 250. In the present embodiment, the integrated circuit package structure 2 further includes a plurality of external terminals 260, such as solder balls, disposed on the lower surface 216 of the substrate 210 for bonding to the outer surface. Therefore, the stress balance member 230 can not only strengthen the anti-warpage strength of the substrate 21 in the absence of the wafer portion (ie, the first substrate side 2 1 1 ), but also reduce the lack of the wafer portion of the encapsulant 240 on the substrate 210. The thickness of the sealant 240 prevents the internal stress imbalance of the non-centro-bonded crystal during the curing shrinkage, and reduces the problem of warpage and even delamination of the sealant. As shown in FIG. 4, in the embodiment, the third wafer side 223 of the wafer 220 is substantially parallel to the third substrate side 2 1 3 and closer to the third substrate side than the fourth wafer side 224. 21 3, the distance from the third wafer side 223 to the third substrate side 2 1 3 is greater than the distance between the fourth 10 200816413 wafer side 224 and the fourth substrate side 2 14 , so there is another side non-center The phenomenon of sticky crystals. Another stress balance member 270 may be disposed on the upper surface 2 15 of the substrate 2 1 0 and located between the third wafer side 2 2 3 and the third substrate side 2 1 3 to solve The substrate 2 1 has a problem of warping on the other side. In a second embodiment of the invention, another non-centered bonded circuit package construction 300 that prevents distortion is disclosed. As shown in FIGS. 5 and 6, an integrated circuit package structure 300 mainly includes a substrate 310, a wafer 320, at least one stress balance member 330, and a glue body 340. The substrate 310 has an upper surface 315 and a lower surface 316. As shown in Fig. 6, the upper surface 315 has a corresponding first substrate side 3 11 and a second substrate side 3 1 2 . The upper surface 3 1 5 has a corresponding parallel third substrate side 3 1 3 and a fourth substrate side 3 1 4 . The wafer 320 is non-centered on the upper surface 315 of the substrate 310, wherein the wafer 306 has a corresponding first wafer side 321 and a second wafer side 322 and a corresponding parallel third. Wafer side 323 and fourth wafer side 324. The first wafer side 321 is substantially parallel to the first substrate side 31 1 and is closer to the first substrate side 3 1 1 than the second wafer side 3 22, the first wafer side 3 2 1 to the first substrate The distance of the side 3 1 1 is greater than the distance from the second wafer side 322 to the second substrate side 3 12 . In this embodiment, the distance from the third wafer side 3 2 3 to the third substrate side 3 1 3 is approximately equal to the distance from the fourth wafer side 3 24 to the fourth substrate side 3 1 4 without Place the stress balancer. The wafer 320 has a plurality of pads 3 2 5 arranged asymmetrically. In the present embodiment, the pads 3 25 are gate-shaped, and the pads 3 2 5 are along the first wafer side 3 2 1 , the third wafer side 3 2 3 and the fourth The wafer side 324 is disposed on one of the active faces of the wafer 320. As shown in FIGS. 5 and 6, the stress balance member 3 3 is disposed on the upper surface 315 of the substrate 310 and is located on the wafer side 3 2 1 to the first substrate side 3 1 Between 1 and 1 to reduce the anti-warpage strength of the substrate portion of the substrate 310 to reduce the thickness of the encapsulant lacking the wafer portion to achieve the balance of stress within the non-central bonded crystal. The stress balance member 330 can be selected from a virtual wafer or a material having a thermal expansion coefficient equivalent to that of the wafer 32. And electrically bonding the pads 325 to the substrate 310 by using a plurality of bonding wires 315, wherein the bonding pads 325 connected to the first wafer side 321 to the portion of the bonding wires 351 of the substrate cross the stress balance Pieces 33〇. The encapsulant 340 is formed on the upper surface 315 of the substrate 31 to seal the wafer 320, the stress balance member 3 3 and the bonding wires 351. In this embodiment, the sealant 34 is a mold encapsulant formed by a die-sealed array (M A P ), and the stress balance member $$ 〇 has a function of mold flow balance. In addition, in the embodiment, the integrated circuit package structure 300 further includes a plurality of external terminals 360, such as a metal pad, disposed on the lower surface 3 i 6 of the substrate 310 for external electrical contact. Or solder joints. Therefore, the problem of the warpage of the sealant caused by the stress imbalance in the non-central bonded crystal of the β〇 can be solved by using the arrangement of the stress balance member 330, thereby avoiding the peeling of the sealant 340 and the substrate 310. 200816413 The problem of delamination. Preferably, the stress balancer 330 is a ground connection. A ground connection is formed by forming a metal layer 3 31 on the upper surface of the stress balance member 330. The metal layer 331 of the stress balance member 330 is electrically connected to the metal layer 331 of the stress balance member 330 by at least one grounding wire 353, and the stress balance member 3 3 0 is electrically connected by at least one bonding wire 325. Metal layer 331 to the substrate 310 (as shown in Fig. 6). In addition to preventing the warpage, the stress balance member 3 3 0 can be used as a ground bus bar to achieve a convenient ground connection. The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention. Any simple modifications, equivalent changes and modifications made without departing from the technical scope of the present invention are still within the technical scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view showing a conventional non-central bonded crystal circuit package structure. Figure 2: Schematic diagram of the top surface of the conventional integrated circuit package structure before sealing. Figure 3 is a perspective view of a non-centro-bonded circuit package structure for preventing distortion in accordance with a first embodiment of the present invention. Figure 4: The integrated circuit 13 according to the first embodiment of the present invention
200816413 封裝構造在封膠前之谓面# 81 第5圖··依據本發明之第二具#實施例’ 翹曲之非中心黏晶積艨電路#裝 不意圖。 第6圖：依據本發明之第二具贌實施例 封裝構造在封膠前之谓面$ 意圖 【主要元件符號說明】 100 非中心黏晶積體電路封裝構造 101 110 基板 111 上表面 112 120 晶片 121 銲墊 130 封膠體 140 銲線 150 200 非中心黏晶積體電路封裝構造 201 210 基板 211 苐一基板側 212 第二基板側 213 214 第四基板侧 215 上表面 216 220 晶片 221 第一晶片側 222 第二晶片側 223 224 第四晶片側 225 銲墊 230 第一應力平衡件 240 封膠體 250 銲線 260 270第二應力平衡件 300非中心黏晶積體電路封裝構造 310基板 3 11第一基板側 3 12第二基板侧 另一種防止 構造之截面 該積體電路 〇 中心線 下表面 外接端子 中心線 第三基板側 下表面 第二晶片側 外接端子 中心線 3 13第三基板侧 14 200816413 314 320 第四基板側 晶片 315 上表面 316 321 第一晶片侧 322 第二晶片侧 323 324 第四晶片侧 325 銲墊 330 應力平衡件 331 金屬層 340 351 3 60 銲線 外接端子 352銲線 353 下表面 第三晶片侧 封膠體 接地銲線200816413 The package structure is before the sealing. #81 Fig. 5 · The second embodiment according to the present invention. The non-central bonded crystal circuit of the warp is not intended. Fig. 6 is a view showing a package structure according to a second embodiment of the present invention before sealing. Intention [Description of main components] 100 non-center bonded crystal circuit package structure 101 110 substrate 111 upper surface 112 120 wafer 121 Pad 130 Sealant 140 Bonding wire 150 200 Non-center bonded crystal circuit package structure 201 210 Substrate 211 One substrate side 212 Second substrate side 213 214 Fourth substrate side 215 Upper surface 216 220 Wafer 221 First wafer side 222 second wafer side 223 224 fourth wafer side 225 pad 230 first stress balance member 240 sealant 250 bond wire 260 270 second stress balance member 300 non-center bonded crystal circuit package structure 310 substrate 3 11 first substrate Side 3 12 Second substrate side Another prevention structure cross section The integrated circuit 〇 Center line Lower surface External terminal center line Third substrate side Lower surface Second wafer side external terminal center line 3 13 Third substrate side 14 200816413 314 320 Fourth substrate side wafer 315 upper surface 316 321 first wafer side 322 second wafer side 323 324 fourth wafer side 325 pad 33 0 Stress balancer 331 Metal layer 340 351 3 60 Wire bond External terminal 352 Wire bond 353 Lower surface Third wafer side Sealant Ground wire
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