TW200814233A - Complementary metal-oxide-semiconductor device and fabricating method thereof - Google Patents

Abstract

A complementary metal-oxide-semiconductor (CMOS) device includes a substrate with a first active region and a second active region; a first gate structure and a second gate structure, respectively disposed on the first active region and the second active region; a first spacer structure and a second spacer structure, respectively disposed on sidewalls of the first gate structure and the second gate structure; a first LDD and a second LDD, respectively disposed in the substrate on sidewalls of the first gate structure and the second gate structure; an epitaxial material layer, disposed in the first active region and located on a side of the first LDD; and a passivation layer, disposed on the first gate structure, the first spacer structure, and the first LDD and covering the second active region, wherein the passivation layer comprises a carbon-containing oxynitride layer.

Description

。 。 。 。 。 。 。 。 。 。 。 And its manufacturing side to go [previous technology]

At present, the industry proposes a method for fabricating the source/> and the (S/D) region of a gold-oxygen half-day body using germanium (SiGe) technology to increase the mobility of electrons and two, (mobility). ), thereby improving the performance of the component. / In general, the application of SiGe technology to fabricate complementary gold's conductor elements is to form a p-type gate structure Zn-type gate structure on the substrate, and then sequentially form spacers and ldd. Next, a layer of HTO layer is deposited on each of the substrates. Then, using the surrounding layer as a mask, the “layer” above the _s region is removed, and the basal plane 3 of the source/drain region pre-formed in the PMOS region is exposed, and the P-type gate structure and its sidewall are exposed. A two-part temperature oxide layer remains on the gap wall to achieve the function of protecting the gate structure and the spacer wall: : = = case = resist layer. After that, the exposed bottom is removed to form == area _ 'filling the Wei's layer in the ditch', however, in the step of removing the patterned photoresist layer, the step of the trench of the area, and the pre- (pre_clean) process or pre-bake _ 制 简 ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 'Exposure P-type gate 200814233 ^χτΑν.^-ζ.ν; 05-0692 19042twf.doc/n part of the surface of the structure and the surface of the NMOS area. Therefore, the process is carried out to fill in the trench When the tantalum layer is formed, a tantalum layer is also formed on the exposed surface of the substrate and the top of the P-type gate structure, that is, so-called The use of poly bumps, which can seriously affect the reliability of the process and the performance of the components. In addition, some related technologies mentioned above are also disclosed in some U.S. patents, such as US 6573172B1 and US 6858506B2. SUMMARY OF THE INVENTION In view of the above, an object of the present invention is to provide a method for fabricating a complementary MOS device, which can avoid the problems of the generation of conventional polycrystalline germanium bumps and their derivatives, and The invention can improve the reliability of the process and the performance of the device. Another object of the present invention is to provide a method for fabricating a complementary MOS device, which can also avoid the occurrence of conventional polycrystalline germanium bumps and various problems arising therefrom, and can be The reliability of the process and the efficiency of the device are improved. Another object of the present invention is to provide a complementary MOS device, which can also avoid the occurrence of conventional polycrystalline germanium bumps, and various problems arising therefrom, and can improve the process. Reliability and component performance. A further object of the present invention is to provide A complementary MOS device can also avoid the occurrence of conventional polycrystalline slab bumps, and various problems arising therefrom, and can improve process reliability and device performance. The present invention provides a complementary MOS device. The component manufacturer 200814233 -m^.^〇5.〇692 19042twfd〇c/n method Firstly, a substrate is provided, which has an isolation structure, and the base region is separated from the active region and the second active region. The first active region has been formed with a first gate structure, a first spacer structure and a first LDD. The first active region has formed a second gate structure, a second spacer structure and a first Two LDDs. Then, a protective layer is formed conformally on the substrate, wherein the protective layer is a carbon-containing oxygen-nitride layer. Subsequently, a photoresist layer is formed on the protective layer of the second active region. Then, using the photoresist layer as a mask, an etching process is performed to retain the lower protective layer on the first gate structure and the first spacer structure, and then the photoresist layer is removed. Then, with the protective layer as a mask, the exposed portion of the substrate of the first active region is removed to form a trench in the substrate. Thereafter, a layer of epitaxial material is filled in the trench as the first conductivity type source/drain region, and then the protective layer is removed. Then, a doped region is formed in the substrate of the second active region as the second conductivity type source/drain region. According to the 'ie method of the complementary MOS device according to the embodiment of the present invention, the carbon-containing oxygen-nitride layer is, for example, a double TBT-based oxide layer (BTBAS). The formation method of the bis-tert-butylaminodecane oxide layer ϋ is, for example, a low pressure chemical vapor deposition (LPCVD). A method of fabricating a complementary MOS device according to an embodiment of the invention, wherein after the trench is formed, a cleaning process is further included. A method of fabricating a complementary MOS device according to an embodiment of the present invention, further comprising performing a heat treatment process on the protective layer before performing the cleaning process and after forming the protective layer. The temperature of the above heat treatment process is, for example, 750 to 800. (Between 3, the time is, for example, between 3 sec and ί ο, the pressure is, for example, between 5 and 50 torr, and the heat

7 200814233 um^u-zu05-0692 19042twf.doc/n The gas used in the treatment process is, for example, selected from the group consisting of helium (He), helium (Ne), argon (Ar), helium (Kr), and helium ( Xe) and the group of nitrogen combined with -. The method for fabricating a complementary MOS device according to the embodiment of the present invention further includes forming a stress layer over the substrate of the second active region after the formation of the doped region, and conformingly covering the second gate , community, second spacer structure and doped region. In one embodiment, the first source/drain region is a P-type source/drain region, and the epitaxial material layer is a germanium layer, and the stress layer is a tensile stress layer. In another embodiment, the =-conducting source/nomogram region is an N-type source pole region, and b is a tantalum carbide layer, and the stress layer is a compressive stress layer. The invention further proposes a method of fabricating a complementary MOS device. 1 First, a substrate is provided, the substrate has a - Ϊ region - a silk region and a second filament region, and the first filament region has = a brother-gate structure, a - _ wall structure and - the first LDD, second gate structure, second spacer structure and layer, (iv) - conformally formed + protective layer::: first -f and layer 'covers the first active region of the second active region (4) constituting the resist layer for the turn, performing the ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- , remove the first protective layer. 200814233 uivi^u-zu05-0692 19042twf.doc/n Thereafter, a second protective layer is formed conformally on the substrate, wherein the second protective layer is a carbon-containing oxygen-nitride layer. Then, a second photoresist layer is formed over the substrate to cover the first protective layer of the first active region. Thereafter, an etching process is performed using the second photoresist layer as a mask to retain the lower portion of the second protective layer on the second gate structure and the second spacer structure, and then the second photoresist layer is removed. Then, the second protective layer is used as a mask to remove the exposed portion of the substrate of the second active region to form a second trench in the substrate. Subsequently, a second layer of epitaxial material is filled in the first trench as a second conductivity type source/drain region. In the method for producing a complementary MOS device according to the embodiment of the present invention, the carbon-containing oxygen-nitride layer includes a double-tert-butylaminodecane oxide layer. The method for forming the bis-tertiary butylamine-based strontium oxide layer is, for example, a low pressure chemical vapor deposition method. The method for fabricating a complementary MOS device according to the embodiment of the present invention, wherein after the first trench is formed and/or after the second trench is formed, a cleaning process is further included. According to the method of manufacturing a complementary MOS device according to the embodiment of the present invention, the first and second protective layers are further included before the cleaning process and after the first and second protective layers are formed. Heat treatment process. The temperature of the above heat treatment process is, for example, between 〇 8 8 (8). For example, the time is, for example, between 30 seconds and 10 minutes, and the pressure is, for example, between 5 and 50 ton*, and the gas used in the heat treatment process is, for example, selected from the group consisting of nitrogen (He) and gas (Ne). One of the groups of argon (Ar), gas (Kr), helium (xe) and nitrogen.

9 200814233 um^l»-zu05-0692 19042tv/fd〇c/n According to the manufacturing method of the complementary gold-germanium semiconductor element according to the embodiment of the invention, the first conductivity type source/drain region is P-type 溽柘, polar region, second conductivity type source/drain region is N-type source/drain region, first epitaxial material layer is bismuth telluride layer, and second epitaxial material layer is strontium carbide layer, according to In the manufacturing method of the complementary MOS semiconductor device 9 according to the embodiment of the present invention, the first conductive type source/drain region is an N-type source 柘/, a polar region, and a second conductive source/drain The region is a P-type source/drain region, the first epitaxial material layer is a tantalum carbide layer, and the second epitaxial material layer is a germanium telluride layer i. According to the manufacturing method of the complementary MOS device according to the embodiment of the present invention, the first offset region and the second offset gap are both composed of an oxide layer and a nitride layer. The material of the oxide layer is, for example, a dish oxide material or a carbon-containing oxygen-nitride material. In one embodiment, the method of forming the first-offset spacer and the second offset spacer is an on-site deposition process. According to the manufacturing method of the complementary MOS device according to the embodiment of the present invention, the first spacer and the second spacer are both a second oxide layer, a nitride layer, and a second oxide layer. The material of the first and second oxide layers is, for example, a high temperature oxidizing material or a carbon-containing oxygen turbid material. In the embodiment, the method of forming the first spacer and the second spacer is, for example, a field deposition process. The present invention further provides a complementary MOS device comprising: a bottom, a first gate structure, a second gate structure, a first spacer structure, a second barrier layer structure, a first LDD, and a second LDD, the layer of epitaxial material is layered. The substrate has a first active region and a second active region, 200814233 ^^1^1^-^^05-0692 19042twf.doc/n and an isolation structure between the first active region and the second active region Separated. The first gate structure is disposed on the substrate of the first active region, the second gate structure is disposed on the substrate of the second active region, the first spacer structure is disposed on the sidewall of the first gate structure, and the second spacer structure The sidewall is disposed on the sidewall of the second gate structure. In addition, the LDD is disposed in the substrate on the side of the first gate structure, and the first LDD is disposed in the substrate on the side of the second gate structure. The epitaxial material layer is disposed in the substrate of the first active region and is located on the side of the first LDD to serve as a first conductivity type source/drain region. The protective layer is disposed on the first gate structure, the first spacer structure and the first LDD, and covers the second active region, wherein the protective layer is a carbon-containing oxygen-nitride layer. According to the complementary MOS device of the embodiment of the present invention, the first conductivity type source/drain region is a p-type source/drain region, and the epitaxial material layer is a bismuth telluride layer. According to the complementary MOS device of the embodiment of the present invention, the first conductivity type source/drain region is an N-type source/no-polar region, and the telecrystalline material layer is a carbonized chopping layer. According to the complementary MOS device according to the embodiment of the present invention, the carbon-containing oxygen-nitride layer is, for example, a double-tert-butylaminodecane oxide layer. The invention further provides a complementary MOS device, comprising: a substrate, a gate structure, a second gate structure, a first spacer structure, a second, a spacer structure, a first LDD, a second LDD, a first epitaxial material layer, a first parasitic material layer, and a protective layer. The substrate has a first active region and a second active region, and the first active region and the second active region are separated by an isolation structure. The first gate structure is disposed on the substrate of the first active region, the second gate structure is disposed on the substrate of the second active region, and the first spacer structure is disposed on the sidewall of the first gate structure, and the second gap The wall structure is disposed on a sidewall of the second gate structure. In addition, the first portion is disposed in the substrate on the side of the first gate structure, and the second LDD is disposed in the substrate on the side of the second gate structure. The first epitaxial material layer is disposed in the substrate of the first active region and located on the side of the first LDD to serve as a first conductivity type source

(Polar/A-pole region. The first transistor material layer is disposed in the substrate of the second active region and located on the side of the second LDD to serve as a second conductivity type source/drain region. a second gate structure, a second spacer structure, and a first LDD covering the first active region, wherein the protective layer is a carbon-containing oxygen-nitride layer. The complementary gold according to the embodiment of the present invention The oxygen semiconductor element, wherein the first conductive type source/drain region is a P-type source/drain region, and the second conductive Wei-polar region is an N-type source-level polar region, the first The material layer is a germanium telluride layer, and the second epitaxial material layer is a tantalum carbide layer. The first conductive source/drain region of the complementary metal oxide layer according to the embodiment of the invention is an N-type source. / bungee region, 苐-¥ electric source />; and the polar region is p-type source-level polar region, the material layer of the sarcophagus is carbon cut, H day (four) material Wei Miao. Cat day, for example, the case The above-mentioned carbon-containing vapor layer is, for example, a bismuth dibutylamino decane oxide layer.

The protective layer of the present invention is a carbon-containing oxygen-nitride layer, and the I-etch rate is such that the protective layer can be prevented from being properly formed during the manufacturing process of the new member.

12 200814233 uivi^u-zu05-0692 19042twf.doc/n Removed', resulting in the production of the conventional polycrystalline puplybump, and the problems it derives. On the other hand, the heat treatment performed in the method of the present invention can make the density of the protective layer more dense, so as to reduce the cost of the protective layer, and is more advantageous for the subsequent process. The above and other objects, features and advantages of the present invention will become more <RTIgt; 1A to 1H are schematic cross-sectional views showing a method of fabricating a complementary MOS device according to an embodiment of the invention. First, referring to FIG. 1A, a substrate 100 is provided. The substrate 100 has a first active region 102 and a second active region 1〇4, and an isolation structure is disposed between the first active region 1〇2 and the second active region 104. 6 zones. In the above, the isolation structure 106 is, for example, a shallow trench isolation structure (STI) or other suitable isolation structure. Then, a first gate structure 1〇8 and a second gate structure 110 are formed on the substrate 100 of the first active region 102 and the second active region 1〇4, respectively. The first gate structure 1〇8 is composed of the gate dielectric layer i〇8a and the gate conductor layer 108b, and the second gate structure 11〇 is composed of the gate dielectric layer n〇a and the gate conductor layer ii〇b. Composition. The materials and forming methods of the first gate structure 1〇8 and the second gate structure 110 are well known to those skilled in the art and will not be described herein. Then, referring to FIG. 1A, a first offset (〇 setset) gap wall 112 and a second offset spacer wall 114 are formed on sidewalls of the first gate structure 108 and the second gate structure 110, respectively. Wherein, the first offset gap 8 13 200814233 U gas 1^05-0692 19042twf.d〇c / n wall 112 is composed of an oxide layer 112 ^ 114 U2bmm J ^. The material of the nitrided layer (1)b, U4^H14a, and the nitrided layer _m(1) 2 is, for example, a nitride dream, and the material of the oxide layers 112a and 114a is, for example, high, w gas, and f-fraction to material. Subsequently, a doping 3 is formed to form the first-to-L coffee 6 and the second _18. Receiver 'Ming Cang according to Figure 1B, Yu Chuyi ^ 1τ, brother-offset gap 112 and

- Offset _ The side wall of the soil 114 is divided into two walls 122. Wherein, the spacers 120 are formed by the oxide layers 12a, 20b and the emulsion layer 12, and the second spacers (2) are composed of a layered layer 122a, a nitrided layer 122b and an oxide layer 122. . Composition. The material of the nitride layer 12213 is, for example, nitrogen cut, and the material of the oxide layers 12 (a), 120c, 122a, and 122c is, for example, a high temperature oxidation material. Then, please refer to item 1C to form a protective layer 124 over the substrate 1()(), compliantly covering the first-gate structure, the first-offset-wall 112, the first-gap m, the first-LDD 116, The second gate structure 110, the second offset spacer 114, the second spacer 122, the first: the LDDU 8 and the isolation structure 106. Next, a photoresist layer 126 is formed over the substrate 1 to cover the protective layer 124 of the second active region 104. Among them, the present invention is characterized in that the protective layer 124 is a carbon-contammg oxidenitride layer having a low etching rate. The carbon-containing oxygen-nitride layer may, for example, be a bis(tert-butylamino)silane (BTBAS) oxide layer, which refers to a BTBAS-based oxide layer (BTBAS_based 〇xide). BTBAS Oxygen 5 14 200814233 〇ivi^j^-zu05-0692 19042twf.doc/ The formation method of the n-layer is, for example, a low-pressure chemical vapor deposition process (LPCVD), the temperature is about 50 to 350 torr, and the temperature is about It is about 5 (10) to 75 〇 ° C, and the gas to be introduced includes BTBAS and nitrous oxide (ΚΟΚ or nitric oxide (N0)). BTBAS is used as a gas source for helium and carbon in the carbon-containing oxygen-nitride layer, and 0 (or NO) is used as a source of nitrogen for the carbon-containing oxygen-nitride layer. In an embodiment, the flow relationship between btbAS and N20 (or NO) is BTBAS/N20 (or NO) greater than 1/2. Referring to FIG. 1D, the photoresist layer 126 is used as a mask to perform an anisotropic The etching process is performed to retain the lower portion of the first gate structure 1 〇 8 , the first offset spacer 112 , and the first spacer 120 . Thereafter, the photoresist layer 126 is removed. Further, it is particularly noted that the protective layer 124 of the present invention is a carbon-containing oxygen-nitride layer having a low etch rate. Because of the step of removing the photoresist layer 126, part of the protective layer 124 of the second active region (10) is not removed, so that some of the substrate surface is not exposed, which causes various problems. In another embodiment, the material of the oxide layers 112a, 114a of the first and second offset spacers 112, 114 may also be the same as the material of the protective layer 124, for example, and the protective layer 124 may be formed. The formation conditions are the same. The method of forming the first and second offset spacers 112, 114 can be, for example, an in-situ deposition process. In another embodiment, the material of the oxide layers 120a, 120c, 122a, and 122c of the first and second spacers 12(), 122 may be the same as the material of the protective layer 124, for example, Protective layer 124; (S) 15 200814233 UMCD-2005-0692 19042twf.doc/n The conditions are the same. The method of forming the first and second spacers 12, 122 may be, for example, a field deposition process. Thereafter, referring to FIG. 1E, the protective layer 124 is used as a mask to remove the exposed portion of the substrate 1 of the first active region 102 to form a trench 128 in the substrate 1 . The method of forming the trench 128 is, for example, a cooking process. Similarly, since the protective layer 124 of the present invention is a carbon-containing oxygen-nitride layer having a low probability of engraving, the step of removing the portion of the substrate to form the f-channel 128 is not protected. Layer 124 has an effect. That is, in the step of forming the trench 128, part of the protective layer 124 at the top of the gate structure 1〇8 is not removed, and part of the surface of the gate structure 1〇8 is exposed. Next, please refer to ® 1F The trench material layer 128 is filled in the trench 128 as a first conductivity type source/drain region. In one embodiment, a process of cleaning (four) _dean is typically performed to fill the base surface of the bottom of the trench m prior to filling the layer of insecticidal material 130. Similarly, since the protective layer 124 of the present invention is a carbon-containing oxygen-nitride layer having a low I: rate, the first active region 1〇2 is not performed during the cleaning process. The protective layer m has an effect. That is to say, part of the protective layer 124 of the active region 102 is not removed, and a part of the surface of the gate structure 1〇8 is exposed. In addition, in the forming step of the epitaxial material layer 130, a pre-bake step is further performed to remove impurities generated after the trenches 128 are formed. In the above embodiment, if the first conductive type source/drain region is a P-type source 200814233 uivl^^u05-0692 19042 twf.doc/n pole/nopole region, the epitaxial material layer 130 is germanium telluride (SiGe). The layer is formed by, for example, a selective epitaxial growth (SEG) process. In more detail, the epitaxial material layer 13 is a boron-containing germanium telluride (SiGe) layer, which may be formed by a doping process in a field manner, or after forming a germanium material layer, and then performing a doping process. And formed. On the other hand, if the first conductivity type source/potential region is an N-type source/no-polar region, the epitaxial material layer 130 is a tantalum carbide (Sic) layer.

Hereinafter, a complementary MOS device = structure according to an embodiment of the present invention will be described. Referring again to FIG. 1F, the components of the present invention include: a substrate (10), a first, a pole structure 1〇8, a second gate structure 11G, a first offset spacer U2, a second offset spacer 114, and a first The LDD 116, the first spacer 120, the second LDD 118, the second spacer 122, and the layer of the parasitic material 13 are covered with a protective layer 124. The substrate 100 has a first active region 102 and a first region 104, and the first active region 1〇2 and the second active region 1〇4 are separated by a spacer structure 106. The first gate structure 108 is disposed on the substrate 100 of the first active region 1〇2, and the second gate structure 11 is disposed on the substrate 100 of the second active region. In addition, the first offset spacers 112 are disposed on the sidewalls of the pole structure 108, and the second offset spacers 114 are disposed on the second: junctions. The first offset spacer i 12 is composed of two and a nitride layer (10), and the second offset (four) is composed of a layer and a nitride layer (10). The material of the oxide layers ma, ma of the first and first gap walls 112, 114 is, for example, a chemical material or a carbon-containing oxygen-nitride material. . / Dish 3 17 200814233 uivil.u-z〇05-0692 19042twf.doc/n The first LDD 116 is disposed in the substrate 100 on the side of the first gate structure 1〇8. The second LDD 118 is disposed in the substrate 100 on the side of the second gate structure 11 . In addition, the first spacer 12 is disposed on the sidewall of the first offset spacer U2, and the spacer 122 is disposed on the sidewall of the second offset spacer Η* and located on the portion of the LDD 118. Wherein, the first spacer 120 is composed of an oxide layer i20a, a ratified layer 120b and an oxide layer i2〇c, and a wall 122 is composed of an oxide layer 122a, a nitride layer 122b and an oxidation layer. Layer 122c is formed. The material of the oxide layers 120a, 120c, 122a, 122c of the first and second spacers u, 122 is, for example, a high temperature oxidizing material or a carbon-containing oxygen-nitride material. The epitaxial material layer 130 is disposed in the substrate 1〇〇 of the first active region 1〇2 and located at the side of the first LDD 116 as the first conductive type source/drain region. The protective layer 124 is disposed on the first gate structure 1〇8, the first offset spacer 122, the first spacer 120, and the first LDD 116, and covers the entire second active region 104. The protective layer 124 is a carbon-containing oxygen-nitride layer which is, for example, a double-tert-butylaminodecyl oxide layer. Since the protective layer of the present invention is a carbon-containing oxygen-nitride layer having a low etch rate, the protective layer can be prevented from being improperly removed during the manufacturing process of the element, resulting in the conventional polycrystalline smectite The generation of the block (P〇ly]3Ump), and the problems it derives. Subsequently, following Fig. 1F, after the formation of the epitaxial material layer 13 is completed, the subsequent process can be continued. Referring to FIG. 1G, the protective layer 124 is removed. Thereafter, a doping process is performed to form a doping region 132 in the substrate 1〇〇 of the second active region 1〇4 as the second conductivity type source/drain region. Xi

18 200814233 uivicjj-2U〇5-0692 19042twf.doc/n, please refer to FIG. 1H, Yu Chu 134, compliantly covering the second active region 104 to form the stress layer H4, the second spacer 122 and the doping; Library == For example, the material of tantalum nitride or other suitable core layer 134 is chemical vapor deposition or other suitable method. And the forming method thereof is, for example, in the above embodiment, if the first - 遂 +

Π4 is a tensile stress layer. The other aspect is = pole - crystal material; ς = = zone Bay J stress layer 134 is a compressive stress layer. In addition to the bovine process, the method of the present invention can also be used to make the density of the protective layer 124 more dense before the steps of the cleaning process for forming the protective layer 124 and the fourth trench 128. , nni24: sufficiency rate 'is more conducive to the subsequent process of the process of processing h π processing, for example, the temperature is between 750 ~ _ =, between 30 seconds to 1 () minutes, pressure The gas used in the process of 5~5〇t(10) =, ^ heat f is selected from the group consisting of helium (4), helium (L) (4), nitrogen (Kr), helium (Xe) and nitrogen. The heat treatment process of the protective layer 124 may be further eliminated in the steps of removing the photoresist layer, forming the trench, and performing the beta cleaning process, thereby causing the conventional The generation of polycrystalline germanium bumps, which in turn affects component performance. In a preferred embodiment, what is the first active zone 1〇2? The type element region 5 19 200814233 UM (JD-20〇5&gt;〇692 19042twf.doc/n and the first active region 104 are examples of the N-type element region, and the lower portion of the layer is retained in the first active region 1〇2 and After the green shape is removed (as shown in FIG. 1D), the heat treatment process described above is performed, except that the density of the protective layer 124 can be densified, and the cost of the protective layer 124 is lowered. The stress conversion technique (10) ess t deletes the se seme) and does not degrade the performance of the component.

2A to 2D are schematic cross-sectional views showing a method of fabricating a complementary to a silicon oxide semiconductor device according to another embodiment of the present invention. 2A to 2D are schematic cross-sectional views of the process diagram iF, and the same components as those of FIGS. 1A to 1F are omitted in the drawings to the drawings, and are denoted by the same reference numerals. Please refer to FIG. 2A for removal protection. After the layer 124, a protective layer 136 is formed on the dead side of the substrate 100, and the first gate structure 1〇8, the first offset spacer 112, the first spacer 12〇, the first LDD 116, and the first gate are covered. The structure 110, the second offset spacer 114, the third spacer m, the first-LDD 118, the isolation structure 1〇6, and the layer of the remote material layer 13〇. The material and formation method of the protective layer m are the same as those of the protective layer m. Thereafter, a photoresist layer 138 is formed over the substrate to cover the protective layer 136 of the first active region 102. 々, then, referring to FIG. 2B, using the photoresist layer 138 as a mask, an anisotropic like coating is performed to the second gate structure, the second offset spacer 114, and the second spacer _122. The lower portion of the protective layer 136 is retained. Thereafter, the photoresist layer 138 is removed. Next, referring to FIG. 2C, the protective layer 136 is used as a mask to remove the exposed portion of the substrate from the 820 200814233 wivAv^x^-i^j〇5-0692 19042 twf.doc/n active region 104. That is, a trench 140 is formed in the substrate 1 .

Thereafter, referring to the object 2D, the layer of the smectic material 142 is filled in the trench 14 , as the second conductivity type source/drain region. In one embodiment, the cleaning process is performed to clean the surface of the substrate 100 at the bottom of the trench 140 prior to the intrusion of the layer of cryptic material 142. Further, in the step of forming the layer of the insect crystal material 142, the step of "pre-baking (four) - minus) is performed to remove the impurities generated after the trenches 140 are formed. ^ ～ △ 电 电 电 汲 汲 汲 汲 汲 汲 汲 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二142 is a carbonized stone layer. =Second-dipole-conducting source/drain region is Ν-type source/drain region, and layer region is Ρ-type source/drain region, then epitaxial material layer 3 is stone, fossil layer, insect The crystalline material layer 142 is a Shihua dislocation layer. 124#t&quot;s in removing the photoresist layer u "two; there is a low probability of engraving. Therefore, the step of 128, and in the ^ = sub-base 100 to form a trench cleaning process or pre-baking bottom = substrate 100 surface • Protective layer. =====_ Similarly, the material of the present invention is π ^ 7 ° effect month b. After that, and the groove is in the step of 'forming the protective layer 136 heat treatment process to make protection; D:: The J step of the J step is carried out - the _ rate of the low protective layer 14 ,, and more binary: the drop 21 200814233 UJVKJD-2005-0692 19042twf. doc / n The above = the condition of the heat treatment process is, for example, the temperature is between 75Q ~ 〇. Between 〇 时间 'time between 3G seconds to 1G minutes, the pressure is between 5~5 〇 _ 5, the gas used in the treatment process is selected from helium (He), helium il gas (Ar One of the groups of helium (Kr) and gas (combined with helium and nitrogen). The H layer 140 of the ocean mouth is subjected to a heat treatment process, which may further help to avoid the step of removing the protective layer 14G in the photoresist layer. The steps of forming the trench and performing the cleaning process are removed, resulting in the generation of conventional polycrystalline germanium bumps, which in turn affects device performance. In a preferred embodiment, the first active region 1〇2 is an N-type device region and the second active region 1〇4 is an ?-type device region, and the second active region 1〇4 remains as a lower portion. Protection 136 and after removing the photoresist layer (as shown in FIG. 2B), performing the above heat treatment process, in addition to making the density of the protective layer 124 more dense, and reducing the etching rate of the protective layer 136, The heat treatment process also facilitates stress conversion techniques without degrading element performance. Next, the structure of a complementary MOS device according to another embodiment of the present invention will be described. Referring again to FIG. 2D, the elements of the present invention include: The substrate 100, the first gate structure 108, the second gate structure u, the first offset spacer 112, the second offset spacer 114, the first LDD 110, the first spacer 120, the second LDD 118, and the second a spacer 122, an epitaxial material layer 130, an epitaxial material layer 142, and a protective layer 136. The epitaxial material layer 142 is disposed in the substrate 1 of the second active region 104 and is located on the side of the second LDD 118. As a second conductivity type source/drain region, the protective layer 136 is disposed on The second gate structure 110, the second offset spacer 1丨4, and the second spacer

22 200814233 UMCD-2005-0692 19042twf.doc/n 122 and the second LDD 118, and covering the entire first active area 1〇2. The protective layer 136 is a carbon-containing oxygen-nitride layer, which is, for example, a bis-dibutylamine-based dream oxide layer. • In summary, the protective layer of the present invention is a carbon-containing oxygen-nitride layer having a low probability of engraving, so that during the manufacturing process of the component, the protective layer is prevented from being undesirably removed, resulting in The production of the conventional polycrystalline sprite (p〇ly bur叩) and its various problems. In addition, the present invention applies a heat treatment process to the protective layer to make the density of the protective layer more dense, thereby reducing the etching rate of the protective layer, and is more advantageous for the subsequent process. 6 Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention to those skilled in the art, and may be modified and modified without departing from the spirit and scope of the invention. Therefore, the protection of the present invention is defined by the scope of the patent. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A to FIG. 1H are schematic cross-sectional views showing a method of fabricating a complementary MOS device according to an embodiment of the invention. 2D is a cross-sectional view showing a method of fabricating a complementary MOS device according to another embodiment of the present invention. [Main component symbol description] 100 : Base 102 : First active area 104 : Second active area 106 : Isolated structure 108 : Brother - gate structure 23 200814233 umuj-zu05-0692 19042twf.doc/n 108a, 110a : Electrical layer 108b, 110b: gate conductor layer • 110: second gate structure - 112: first offset spacer

112a, 114a, 120a, 120c, 122a, 122c: oxide layer 112b, 114b, 120b, 122b: nitride layer 114: second offset spacer 116: first LDD (% 118: second LDD 120: first gap Wall 122: second spacers 124, 136: protective layers 126, 138: photoresist layers 128, 140: trenches 130, 142: epitaxial material layer 132: doped regions i 134 · stress layers 24

Claims (1)

200814233 ^, ^^005-0692 19042twf.doc/n X. Patent application scope: 1 A method for manufacturing a complementary MOS semiconductor device, comprising: providing a substrate with an isolation structure, the substrate Zone 2 has a flute and a second active zone, and the first active zone has been shaped ==: pole structure, - first gap structure and - first - coffee, two - # move £ has formed - second gate Structure, the second spacer structure and a second LDD; the sequence, the soil, and the mouth (4) are on the base of the job--the layer, the towel is the slave-containing oxygen-nitride layer; Forming a photoresist layer on the protective layer of the active region; using a stone-shadow resist layer as a mask, performing a side process to remove the light on the pole structure and the first-gap wall structure to remove the light a protective layer is used as a mask to remove a portion of the substrate exposed by the first main secret to form a trench in the 13⁄4 substrate; the electrical type is derived from the trench filled with an epitaxial material layer , as a _th pole/drain region; 'removing the protective layer; and the base in the second active region Forming a doped region, second conductivity type source / drain regions. φ 2. A method for producing a complementary oxy-half half piece as described in the patent application of the present invention, wherein the carbon-containing oxygen-nitride layer comprises - a base amino group-burning (BTBAS) oxide layer. A further method of manufacturing a complementary oxy-semiconductor element 8 25 200814233 uivi^jj-zu05-0692 19042 twf.doc/n according to claim 2, wherein the bis-tert-butylamine-based money The method of the oxide layer includes a low pressure chemical vapor deposition (LPCVD) process. 4. Complementary gold=manufacturing method as described in the scope of application for patent application, in which after the formation of the sluice channel, it further includes the complementary gold described in item 4 of the body of the genus Oxygen semiconductor element Γ: The formation of the d is before the shot line and the protective layer of moxibustion further includes a heat treatment process for the protective layer. Item 2::Special: The complementary MOS element + in the 5th item of the surrounding area + ^ The temperature of the heat treatment process is between 750 and 80 (the TC of the TC is the complement of the fifth rhyme a semiconductor element minute method, wherein the heat treatment process has a time from the leap second to the 10th patent of the fifth aspect of the invention, wherein the pressure of the heat treatment process is between 5 &lt; The special product of the piece: 1! The complementary MOS semiconductor qi according to item 5 _, _ The damming frequency making gas is selected from the group of 氦 ^ ^ _ _ Wei (Ar), chaos (Kr), xenon (Xe), and nitrogen element 1 pin-shaped mutual-energy semiconductor ς# _ method, wherein after the doping region is formed, the method further includes: ... forming a stress layer above the substrate of the active region Compliance 8 26 200814233 UM^D-2005-0692 \9042twf.doc/n covering the second gate structure, the second spacer structure, and the doping region u· as described in claim 1 A method for fabricating a complementary gold-conducting semiconductor device, wherein the first conductive source/drain region is a p-body/drain region, The layer of the epitaxial material is a bismuth telluride layer, the stress layer/extension stress layer, and the method for manufacturing a complementary MOS device according to claim 10, wherein the first The conductive germanium source/drain region is N-type=pole/drain region, and the epitaxial material layer is a tantalum carbide layer, and the stress layer is a pound of 'shrinkage stress layer. I 13·-complementary type MOS The method for manufacturing a component includes: providing a substrate having an isolation/isolation structure region, separating the substrate from a first active region and a second active region, and the first active region has formed a first-, a gate structure, a first/gap structure 舆—the first LDD, the second active region has formed a second gate structure, a second spacer structure and a second LDD; forming conformally on the substrate a first protective layer, wherein the first protective layer is a carbon-containing oxygen-nitride layer; a first optical layer is formed over the substrate to cover the first protective layer of the second active region; The first photoresist layer is a mask, and an etching process is performed to the first gate The first structure and the first spacer structure retain the lower portion of the first protective layer; removing the first photoresist layer; using the first protective layer as a mask to remove the exposed portion of the first active region 27 200814233 um^zO〇5-〇692 19042twf.doc/n part of the county, for the base t formation - the first ditch; in the first ditch order filled with a first insect conductive source / bungee Zone; as Feng Di - remove the first protective layer; &quot; conformally formed on the substrate - second protection, the protective layer is the carbon-containing oxygen-nitride layer; /, X _ Forming a second wire layer, covering (10) the first active region is a process of the first protective layer; the second remaining of the lower portion of the second photoresist layer The second protective layer is a portion of the substrate of the mask, which is exposed in the second trench: the second channel of the gentry; and the conductive source/drain region/, the layer of the crystalline material, As a second - this 14*, as in the manufacturing method of the complementary all-oxygen semi-conducting element described in Item No. 13 of the medium μ patent, wherein the ^人^”κ Complementary Meng 3 cattle &gt; body butyl amide based Wei oxide layer ^ milk / nitride layer including - double third element term described in the complementary oxy-metal semiconductor formation method includes - low pressure base amine generalization The layer-shaped component is paid to the MOS semiconductor after the formation of the first trench and/or the second 28 200814233 -2 v)05-0692 19042twf.doc/n After the ditches are formed, the ride-cleaning process is more handsome. 17. If the complementary MOS semiconductor according to the application _(4) is applied before the cleaning process and after the cleaning layer is performed, the patent scope of the first and second protections is further included. _. The complementary MOS semiconductor 3 = #方法' wherein the temperature of the heat treatment process is between 750 and 800 U &lt; 19 · Such as Shen Qing patent Fan Jane praise element manufacturing method, item;; ΐ 金 金 金 分钟 分钟. The heat treatment process has a time between 30 seconds and the complementary MOS semiconductor described in Item 17 of the component: the pressure of the heat treatment process in the coating is between 5 and 50 t 〇 rr 21 . ^ i The manufacturing method of the component, i (4) The South member described the complement to the milk semiconductor helium (4), the treatment of the secret gas is selected from the group of gas (Ar), read Kr), listen ( Xe) and Nitrogen Element 13 of the mutual-imported semiconductor pole/no-polar zone, the first source of the conductivity type of the haixidi is p-type source ^~Le-type source/drainage zone is N Type source/drainage: Bayer&quot;Hai first epitaxial material layer is a bismuth telluride layer, and the second epitaxial material layer is a ruthenium carbide layer. 23) A method for manufacturing a component of a complementary MOS semiconductor according to claim 13 of claimant patent scope, wherein the first conductivity type source/ The drain region is a ^^ type source/drain region, and the second conductivity type source/drain region is a p-type source/drain region, and the first epitaxial material layer is a tantalum carbide layer, the first The second epitaxial material layer is a Shixihua fault layer. 24· a complementary MOS device, comprising: a substrate having an isolation structure, the substrate is separated from a first active region and a second active region; a first gate structure, Disposed on the substrate of the first active region; a second gate structure disposed on the substrate of the second active region; a first spacer structure disposed on a sidewall of the first gate structure; a second spacer structure disposed on the sidewall of the second gate structure; a first LDD disposed in the substrate on a side of the first gate structure; a second LDD disposed on the second gate structure a layer of the epitaxial material disposed in the substrate of the first active region and located at a side of the first LDD as a first conductivity type source/drain region; a protective layer disposed on the first gate structure, the first spacer structure, and the first LDD, and covering the second active region, wherein the protective layer is a carbon-containing oxygen-nitride layer . 25. The complementary MOS device according to claim 24, wherein the first conductivity type source/drain region is a p-type source/drain region, and the worm material layer is Shi Xi The wrong layer. 8 30 J05-0692 19042twf.doc/n 200814233 26. The application of the epitaxial material layer is tantalum carbide as claimed in claim 24, wherein the first conductivity type source/germanium body region is widened. Floor. The complementary oxynitride component of claim 24, wherein the carbon-containing oxygen-nitride layer comprises a pair of a third butylamine sinter oxide layer. 28· a complementary MOS device, comprising: a substrate having an isolation structure, the substrate is separated from a first active region and a second active region; a first gate structure, configured On the substrate of the first active region; a second gate structure disposed on the substrate of the second active region; and a sidewall structure disposed on the side of the first gate structure a second spacer structure disposed on the sidewall of the second gate structure; a first LDD disposed in the substrate on a side of the first gate structure; a second LDD disposed in the second a first doped material layer disposed in the substrate of the first active region and located on the side of the first LDD to serve as a first conductive source/ a second layer of smectic material disposed in the substrate of the second active region and located on a side of the second LDD to serve as a second conductive source/drain region; The germanium layer is disposed on the first gate structure and the second gap junction 31 200814233 -- -----J05-0692 19042twf.doc/n and the second LDD' and covering the first active region, wherein the protective layer is a carbon-containing oxygen-nitride layer. 1. The complementary MOS transistor according to claim 28, wherein the first conductivity source/drain region is? Type source/drain region, the second conductivity type source is the ν-type source/drain region of the polar region, (4) the first worm material layer is the Wei 锗 layer, and the second 四 (four) layer is the carbon carbide layer . - Politics 3 〇. ΓΓ 互补 专利 专利 专利 专利 互补 互补 互补 互补 互补 互补 互补 互补 互补 互补 互补 互补 互补 互补 互补 互补 互补 互补 互补 互补 互补 互补 互补 互补 互补 互补 互补 互补 互补 互补 互补~The cut layer, the layer of the stalk crystal material is the second 锗 31·如 (D 32