200803156 九、發明說明： 【發明所屬之技術領域】 本發明係有關一種功率放大器，特別是關於一種西格 瑪·德爾塔（sigma-delta)型功率放大器。 【先前技術】 ’ 傳統音訊功率放大器的效率低，造成產生的熱量高， _ 必須使用大型散熱器（heat sink)幫助散熱，因此實體裝置的 體積龐大。近年來為了縮小放大器的體積，便有高效率的 設計方案提出，其中最普遍的方式是使用D類（class D)放大 器’又稱為切換式放大器（switching amplifier)。此類放大 器的工作原理，乃是利用高頻調變方法將類比或數位的輸 入訊號轉換為二階(two-level)的輸出訊號，再將此二階的 訊號送給功率級(power stage)，以切換功率級當中的功率 開關（power switch)。這些功率開關產生的熱量極低，因此 # 放大器的效率大幅提高。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power amplifier, and more particularly to a sigma-delta type power amplifier. [Prior Art] The efficiency of the conventional audio power amplifier is low, resulting in high heat generation. _ A large heat sink must be used to help dissipate heat, so the physical device is bulky. In recent years, in order to reduce the size of the amplifier, a highly efficient design has been proposed, the most common of which is the use of a class D amplifier, also known as a switching amplifier. The working principle of such an amplifier is to convert the analog or digital input signal into a two-level output signal by using a high-frequency modulation method, and then send the second-order signal to the power stage to Switch the power switch in the power stage. The power generated by these power switches is extremely low, so the efficiency of the # amplifier is greatly improved.
在習知的D類放大器中，大多數的系統係採用脈寬調 ‘ 變（Pulse Width modulation; PWM)架構。典型的音訊PWM - 放大器可以在介於100 KHz到500 KHz之間的切換頻率工 作’更尚的切換頻率可以降低失真（(jistorti〇n)，卻會導致 較低的效率’這是因為輸出波形中超量的轉態（transiti〇n) 所造成的’每一次轉態都要耗費少許能量。以典型的35〇 kHz時脈頻率而言’習知的Pwm型d類放大器的失真/雜訊 性能表現並不是很好。 200803156 另一種較不普遍的調變技術係使用西格瑪-德爾塔調 變器將類比或數位的輸入訊號轉換為一串較高取樣頻率 的1和〇的數位訊號，典型的取樣頻率約為最高音訊頻率的 64倍。西格瑪_德爾塔調變器經常在類比數位轉換器 (Analog-to-Digital Converter; ADC)中使用，用來將類比的 =訊訊號轉換為數位的！位元串流。由於西格瑪-德爾塔調 • 變的精確度較高，使用西格瑪-德爾塔調變的架構比使用 鲁P WM調變的架構具有較佳的失真特性，但是切換頻率明顯 同出很多’因此效率較低。 、 為進一步說明，圖1顯示習知的西格瑪_德爾塔型功率 放大器10，其包括西格瑪_德爾塔調變器12將輸入訊號Vin 轉換後給輸出級14，輸出級14包括量化器16驅動功率級18 ，因而產生輸出訊號Vout以供推動剩υ八，量化器π的輸出 汛號亦經過反相器13產生負回授給西格瑪_德爾塔調變器 12。西格瑪-德爾塔調變器12和量化器16可以使用類比電路 •、數位電路或混合類比及數位電路來實現。在以類比電路 實現的系統中，輸入訊號Vin是類比信號，輸出訊號v〇ut • 是1位元數位訊號，西格瑪-德爾塔調變器12的積分器通常 - 是類比積分器，可以使用離散時間（discrete time)切換電容 (switching capacit〇r)技術或標準的連續時間（continu〇us time)類比線性技術實現。在以數位電路實現的系統中，輸 入訊號Vin是多位元數位訊號，輸出訊號乂⑴^是丨位元數位 訊號’西格瑪·德爾塔調變器12的積分器是離散時間積分器 ’以諸如加法器和暫存器等標準的數位硬體來實現。在以 200803156 混合類比及數位電路實現的系統中，例如前幾級的積分是 由類比電路完成，而後幾級是採用數位電路，輸入訊 是類比信號，輸出訊號Vout是1位元數值訊號。從量化^器16 提供給西格瑪_德爾塔調變器12的負回授可以大力地抑^制工 位兀量化所產生的量化雜訊，使得在有限頻帶中的訊噪比 (SignaMo-Noise Ratio; SNR)很高。 - 在此類電路的設計中，穩定性和抑制量化雜訊二者之 • 間必須妥協。量化雜訊的輸入對輸出的轉移函數(transfer function)通常被定義成某種古典的高通濾波器函數，例如 謝比謝夫（Chebychev)設計。穩定性和抑制量化雜訊之間的 關係可以簡單地說明如下：具有積極抑制雜訊的轉移函數 的電路在較低輸入準位變得不穩定，而具有較不積極抑制 雜訊的轉移函數的電路擁有在較大的輸入範圍仍然穩定 的特性。將西格瑪-德爾塔調變技術應用在D類放大器的缺 點之一在於，為維持系統之穩定度必須要有較高之轉態率 • (transition rate)，因而導致功率級18當中的切換損失 (switching loss)較大，因而降低了效率。以圖1所示的功 • 率放大器1〇為例，如果使用7級的西袼瑪-德爾塔調變器12 - 操作於12MHz的時脈速率，正常音訊取樣率為48 kHz，其 轉態率、可達到典型的350kHz頻率的PWM系統的10倍。除 了功率消耗高，高切換速率也會產生電磁干援 (Electro-Magnetic Interference; EMI)的問題。通常這類調 變器具有頻率在100kHz以上的強大頻譜成分，可能引發對 射頻（Radio Frequency; RF)或其他裝置的干擾。 200803156 概要地說’將西格瑪-德爾塔調變技術應用在D類放大 态日守，其切換速率與輪入訊號Vin的振幅大小是相關的， 切換速率太低時容易使西格瑪_德爾塔調變器丨2變得不穩 定，但是切換速率太高會增加功率消耗及EMI，利用切換 速率控制電路可以降低切換頻率，且兼顧西格瑪_德爾塔調 變器12的穩定度。 為了降低西格瑪·德爾塔調變器的切換頻率，美國專利 鲁弟6’924,757號挺出利用調整磁滯(々5^61^也)大小來達成。 圖2所示係該專利提出的西格瑪_德爾塔調變模組汕，其中 西格瑪-德爾塔調變器22與一般使用的裝置相同，但是量化 态24係具有可變磁滯的丨位元比較器，類比數位轉換器％ 將輸入訊號Vin轉換為數位訊號，藉以從檢索表“中選取 磁滯值，決定量化器24的磁滞大小，達到控制切換頻率的 目的。此系統的缺點之一是，由於引入量化器磁滯，高階 西格瑪-德爾塔調變器的穩定性將會降低，因此必須依昭輸 鲁人訊號·的每-個範圍預設在檢索表Μ中的磁滞值㈣ 佳值。另外’因為量.化器24的磁滞是離散的，容易弓j發其 ‘他的問題。再者，量化器24必須使用可變磁滞的裝置:電 -路較複雜也較昂貴，而增加的數位轉換器26和檢索表28二 晶片變大而且提高成本。 圖1的功率放大益還有另一項問題，由於功率級Μ 不是線性的，從量化器10的輸出產生負回授並未精確地表 達真實的輸出訊號V_,因此引人的誤差會讓放大器_ 性能劣化。 、 200803156 因此’ 一種改良的西格瑪-德爾塔型功率放大器，乃為 所冀。 【發明内容】 本發明的目的之一，在於提出一種可調整切換頻率的 西格瑪_德爾塔型功率放大器及其調變方法。 • 根據本發明，一種西格瑪-德爾塔型功率放大器包括一 ' 西格瑪-德爾塔調變器、一輸出級以及一介於該二者之間的 增斑控制态，該增盈控制器根據一與輸入訊號相關之訊號 將該西格瑪-德爾塔調變器提供給該輸出級的轉換訊號放 大或細小後再提供給該輸出級，藉以降低其調變的轉態率 〇 根據本發明，一種西格瑪-德爾塔型功率放大器的調變 方法包括在一西格瑪-德爾塔調變器提供一轉換訊號給一 輸出級之别，根據一與輸入訊號相關之訊號將該轉換訊號 • 放大或鈿小後再提供給該輸出級，藉以降低該調變的轉態 率0 _ 【實施方式】 〜 圖3顯不根據本發明的西格瑪_德爾塔型功率放大器扣 ，西格瑪-德爾塔調變器32用來將輪入訊號偷轉換為訊號s ，被增益控制器36放大或縮小為訊號gS，緣示增益，係 根據輸人訊號Vin的大小決定，輪歧％再從訊號妨產生 輸出訊號Vouux供推動私。在典型的祕中，輸出⑽ 200803156 包括1化器16及功率級18，但是在某些數位系統中，輸出 級34僅包括量化器16，沒有功率級18，量化器16的輸出就 疋輸出矾號Vout。較佳者，負回授係從輸出訊號Vout經反 相器33提供給西格瑪_德爾塔調變器，如此可以反應真實 的輸出’即使功率級18的線性度較差也不致使系統的性能 過於劣化。此類設計在某些應用，例如將功率級18與其他 控制電路32、33、36及16整合在同一晶片上時，比較合適 H °但在不同的實施例中，例如功率級18是外掛的，也可以 從里化益16的輸出產生負回授訊號，如圖3中的元件符號 35所示。在不同的實施例中，也可以將輸入訊號Vin放大 或縮小後做為決定增益g的控制訊號，如圖3中所示，具有 增iik的放大器38從輸入訊號Vin產生訊號kVin給增益控制 器36 ’控制其增益g。因為增益g隨著輸入訊號vin的大小 改變，所以西格瑪-德爾塔調變器32的切換頻率也跟著改變 〇 φ 圖4顯示增益控制器36的一個實施例，可變增益放大 器40的輸入端連接訊號S，輸出訊號gS，輸入訊號Vin控制 • 可變增益放大器40的增益。可變增益放大器40可以使用電 - 壓控制增益放大器或電流控制增益放大器。 圖5顯示一個全類比實現的西格瑪-德爾塔調變模組， 其使用7級的類比西格瑪-德爾塔調變器32，負回授係從輸 出訊號Vo u t經反相器3 3及電阻R F b的路徑提供。在增益控制 器中，運算放大器42的非反相輸入端連接一參考電壓，在 此實施例中為接地，運算放大器42的反相輸入端和輸出端 200803156 之間連接電阻44，可變電阻46連接在運算放大器42的反相 輸入端和西格瑪-德爾塔調變器32之間，電阻44和可變電阻 46的阻值決定增益控制器的增益，藉由改變可變電阻46的 阻值’即可改變增益控制器的增益。可變電阻46包含電阻 48及50串聯在運算放大器42的反相輸入端和西格瑪-德爾 塔調變器32之間，以及電晶體52及54分別並聯至電阻50, 電晶體52的閘極連接輸入訊號vill，電晶體54的閘極從反 相器56連接輸入訊號vin的反相訊號，電晶體52及54的導 通阻值隨輸入訊號Vin的大小改變。假設電阻48的阻值為 R1、電阻50的阻值為R2、電阻44的阻值為R3，當輸入訊 號Vin為0時，電晶體52及54完全關閉，可變電阻46等於電 阻48串聯電阻50，其等效阻值為R1+R2，因此增益控制器 的增益為 g=R3/(Rl+R2) [公式 1] 當輸入訊號Vin的絕對值很大時，電晶體52或54完全開啟 ’電阻50被旁通，可變電阻46的等效阻值為ri，因此增益 控制器的增益為 g=R3/Rl [公式 2] 當輸入訊號Vin的絕對值由〇逐漸變大時，電晶體52或54由 完全關閉而逐漸開啟，電晶體52的阻值為rm1、電晶體54 11 200803156 的阻值為RM2，可變電阻46的等效阻值為 R1+(RM1//R2//RM2)，因此增益控制器的增益為 g=R3/[Rl+(RM1//R2//RM2)] [公式 3] 圖6係一變化的實施例’可變電阻46的等效阻值只利用輸 ， 入訊號Vin控制電晶體52來決定。圖7係另一個變化的實施 _ 例’運算放大器58的反相輸入端和西格瑪-德爾塔調變器32 β 之間連接電阻60，可變電阻62連接在運算放大器58的反相 輸入端和輸出端之間，藉輸入訊號Vin調整可變電阻62的 阻值，以控制增益，當輸入訊號Vin的絕對值較大時，可 變電阻62的阻值也較大。在圖5至圖7這類實施例中，增益 控制器的增益是連續的值。 圖8顯示增益控制器36的另一個實施例，共輸入端的 多個放大器64各具有不同的增益，分別以gl到gn表示，第 φ j個放大器64的增益為gj，多工器64受輸入訊號Vin控制從 該多個放大器64中選擇一個，以產生訊號gS給輸出級34。 - 在一變化的實施例中，如圖9所示，多工器68受輸入訊號 - Vin控制，將訊號S連接至多個共輸出端的放大器70之中的 一個，以產生訊號gS給輸出級34。在圖8及圖9這類實施例 中，增益控制器的增益是離散的值。 圖10顯示增益控制器36的又一個實施例，放大器72將 訊號S放大或縮小為訊號gS給輸出級34，類比數位轉換器 74將輸入訊號Vin轉換為數位訊號，據以在增益表76中查 12 200803156 找，因而決定放大器72的增益g。 圖11顯示增益控制器36的再一個實施例，數位放大器 78將訊號S放大或縮小為訊號gS給輸出級34，類比數位轉 換器8 0將輸入訊號V i η轉換為數位訊號控制數位放大器7 8 的增益g。 為了與習知技術對照，圖12至圖14顯示圖3之功率放 大器30的模擬結果’圖15至圖20顯示不使用本發明之增益 控制器36(圖1)的模擬結果。如圖12所示，在-60dB的小輸 入訊號時，雜訊底層（noise floor)在-100dB以下，而且在音 訊頻帶（20Hz至20kHz)中的雜訊底層更可達_12〇dB以下， 顯示雜訊小，而在全尺度（full scale)的大輸入訊號時，如 圖13所示，雜訊仍然維持在低水準，顯示功率放大器3〇的 良好性能。圖14係切換頻率對輸入訊號大小的關係圖，當 輸入訊號大小Vin<0 · 5 Vmax時(Vmax表示輸入訊號Vin的最 大振幅），切換頻率約在370 kHz，而在輸入訊號大小vin 為0.7Vmax至〇.8Vmax時，切換頻率升高到約55〇kHz，選 擇適當的設計變數可以降低此範圍的切換頻率。圖15顯示 在小輸入訊號時，習知的功率放大器10可以正常工作，然 而在大輸入sil ?虎日守’如圖16所不，西格瑪-德爾塔調變器12 變得不穩定，所以雜訊底層上升至-50dB。圖17顯示在輸 入訊號大小Vin〉0.7Vmax時，西格瑪-德爾塔調變器12已經 變得不穩定。圖18至圖20所示係提高切換頻率後的結果， 為了在全尺度的輸入訊號時得到穩定的西格瑪-德爾技調 變器12，切換頻率必須高達ΙΜΉζ。因為切換頻率提高， 13 200803156 所以功率消耗和EMI也會跟著提高。 【圖式簡單說明】 圖1顯不習知的功率放大器； 圖2顯示習知具有磁滯控制的西格瑪-德爾塔調變模組 圖3顯示根據本發明的功率放大器； 圖4顯示增益控制器的一個實施例； 圖5顯示一個全類比實現的西格瑪-德爾塔調變模組； 圖6顯示圖5變化的一個實施例； 圖7顯示圖5變化的另一個實施例； 圖8顯示增益控制器的另一個實施例； 圖9頌示圖8變化的一個實施例； 圖忉顯示增益控制器的又一個實施例； 圖11顯示增益控制器的再一個實施例； 圖12顯不本發明的功率放大器在小輸入訊號時的模 擬結果； 圖13顯示本發明的功率放大器在全尺度輸入訊號時 的模擬結果； 圖14顯不本發明的功率放大器的切換頻率對輸入訊 號大小的關係圖； 圖15顯示習知的功率放大器在低切換頻率、小輸入訊 號時的模擬結果； 囷U示4知的功率放大器在低切換頻率、全尺度輸 200803156 入訊號時的模擬結果； 圖17顯示習知的功率放大器在低切換頻率下切換頻 率對輸入訊號大小的關係圖； 圖18顯示習知的功率放大器在高切換頻率、小輸入訊 號時的模擬結果； 圖19顯示習知的功率放大器在高切換頻率、全尺度輸 - 入訊號時的模擬結果；以及 ‘ 圖20顯示習知的功率放大器在高切換頻率下切換頻 率對輸入訊號大小的關係圖。 【主要元件符號說明】 10 功率放大器 12 西格瑪-德爾塔調變器 13 反相器 14 輸出級 • 16 量化器 18 功率級 # 20 西格瑪-德爾塔調變模組 . 22 西格瑪-德爾塔調變器 23 反相器 24 量化器 26 類比數位轉換器 28 檢索表 30 功率放大器 15 200803156In the conventional class D amplifier, most of the systems use a pulse width modulation (Pulse Width Modulation (PWM) architecture. Typical audio PWM - the amplifier can operate at switching frequencies between 100 KHz and 500 KHz. 'More switching frequency can reduce distortion ((jistorti〇n), but it leads to lower efficiency') because of the output waveform The “over-transition” (transiti〇n) causes a small amount of energy for each transition. The distortion/noise performance of the conventional Pwm-type class-D amplifier is in the typical 35〇kHz clock frequency. The performance is not very good. 200803156 Another less common modulation technique uses a sigma-delta modulator to convert an analog or digital input signal into a series of higher-sampling 1 and 数 digital signals, typically The sampling frequency is about 64 times the highest audio frequency. Sigma-delta modulators are often used in Analog-to-Digital Converters (ADCs) to convert analog signals to digital bits! Bit stream. Due to the high accuracy of the sigma-delta modulation, the architecture using sigma-delta modulation has better distortion characteristics than the architecture using Lu P WM modulation, but the switching frequency Obviously many are the same 'so that the efficiency is lower. For further explanation, FIG. 1 shows a conventional sigma-delta type power amplifier 10, which includes a sigma-delta modulator 12 to convert the input signal Vin to the output stage 14 The output stage 14 includes a quantizer 16 that drives the power stage 18, thereby generating an output signal Vout for boosting the remaining eight. The output nick of the quantizer π is also negatively fed back to the sigma delta modulator via the inverter 13. 12. The sigma-delta modulator 12 and the quantizer 16 can be implemented using analog circuits, digital circuits, or mixed analog and digital circuits. In systems implemented in analog circuits, the input signal Vin is an analog signal, and the output signal is v. 〇ut • is a 1-bit digital signal, the sigma-delta modulator 12 integrator is usually - an analog integrator, can use discrete time switching capacitor (switching capacit〇r) technology or standard continuous time (continu〇us time) is analogous to linear technology. In a system implemented by a digital circuit, the input signal Vin is a multi-bit digital signal, and the output signal 乂(1)^ is 丨The digitizer signal 'Integrator of Sigma Delta Transformer 12 is a discrete-time integrator' implemented in standard digital hardware such as adders and registers. In a system implemented with a mixed analog and digital circuit of 200203156 For example, the first few stages are completed by the analog circuit, and the latter stages are digital circuits. The input signal is an analog signal, and the output signal Vout is a 1-bit value signal. The quantized device 16 is supplied to the sigma-delta modulation. The negative feedback of the device 12 can greatly suppress the quantization noise generated by the station quantization, so that the signal-to-noise ratio (SNR) in the limited frequency band is high. - In the design of such circuits, the stability and suppression of quantization noise must be compromised. The transfer function that quantifies the input-to-output of the noise is usually defined as a classical high-pass filter function, such as the Chebychev design. The relationship between stability and suppression quantization noise can be briefly explained as follows: A circuit with a transfer function that actively suppresses noise becomes unstable at a lower input level, and has a transfer function that is less aggressive in suppressing noise. The circuit has features that are stable over a large input range. One of the disadvantages of applying the sigma-delta modulation technique to a class D amplifier is that a higher transition rate must be achieved in order to maintain system stability, resulting in switching losses in the power stage 18 ( The switching loss) is large, thus reducing efficiency. Taking the power amplifier 1〇 shown in Figure 1 as an example, if a 7-stage Simma-delta modulator 12 is used to operate at a clock rate of 12 MHz, the normal audio sampling rate is 48 kHz, which is the transition state. The rate is 10 times that of a typical 350 kHz PWM system. In addition to high power consumption, high switching rates also create problems with Electro-Magnetic Interference (EMI). Typically such modulators have strong spectral components above 100 kHz and may cause interference with radio frequency (RF) or other devices. 200803156 It is said that the application of the sigma-delta modulation technology to the D-class amplification state is related to the amplitude of the wheel-in signal Vin. When the switching rate is too low, it is easy to change the sigma-delta. The 丨2 becomes unstable, but the switching rate is too high, which increases power consumption and EMI. The switching rate control circuit can reduce the switching frequency and take into account the stability of the sigma-delta modulator 12. In order to reduce the switching frequency of the sigma delta modulator, the US patent Ludi 6'924, 757 is achieved by adjusting the hysteresis (々5^61^). Figure 2 shows the sigma-delta modulation module 该 proposed in the patent, wherein the sigma-delta modulator 22 is the same as the commonly used device, but the quantized state 24 is a 丨-bit comparison with variable hysteresis. The analog digital converter converts the input signal Vin into a digital signal, thereby selecting the hysteresis value from the retrieval table, determining the hysteresis size of the quantizer 24, and achieving the purpose of controlling the switching frequency. One of the disadvantages of this system is that Due to the introduction of the quantizer hysteresis, the stability of the high-order sigma-delta modulator will be reduced. Therefore, it is necessary to preset the hysteresis value in the search table according to each range of the Zhaolu Luren signal (4). In addition, because the hysteresis of the quantizer 24 is discrete, it is easy to solve its problem. Furthermore, the quantizer 24 must use a device with variable hysteresis: the electric-road is more complicated and more expensive. The increased digitizer 26 and the look-up table 28 are larger and costly. The power amplification of Figure 1 has another problem, since the power stage Μ is not linear, generating a negative return from the output of the quantizer 10. Not accurately expressed The true output signal V_, so the inductive error will degrade the performance of the amplifier. 200803156 Therefore, an improved sigma-delta type power amplifier is used. [Invention] One of the objects of the present invention is A sigma-delta type power amplifier with adjustable switching frequency and a modulation method thereof are proposed. According to the present invention, a sigma-delta type power amplifier includes a 'sigma-delta modulator, an output stage, and an a brightness increasing control state between the two, the gaining controller amplifying or minimizing the conversion signal supplied to the output stage by the sigma-delta modulator according to a signal related to the input signal, and then supplying the output to the output In order to reduce the rate of transition of the modulation, according to the present invention, a method of modulating a sigma-delta type power amplifier includes providing a conversion signal to an output stage in a sigma-delta modulator, according to A signal associated with the input signal is amplified or reduced and then supplied to the output stage to reduce the modulation Transition rate 0 _ [Embodiment] ~ Figure 3 shows the sigma-delta type power amplifier buckle according to the present invention. The sigma-delta modulator 32 is used to convert the wheeled signal into a signal s, which is controlled by gain. The device 36 is enlarged or reduced to the signal gS, and the gain is determined according to the size of the input signal Vin. The wheel % is then generated from the signal to generate the output signal Vouux for promoting private. In a typical secret, the output (10) 200803156 includes 1 16 and power stage 18, but in some digital systems, output stage 34 includes only quantizer 16, without power stage 18, and the output of quantizer 16 outputs an apostrophe Vout. Preferably, the negative feedback is slave. The output signal Vout is supplied to the sigma delta modulator via the inverter 33 so that it can reflect the true output 'even if the linearity of the power stage 18 is poor, the performance of the system is not deteriorated too much. Such designs are suitable for H° when certain applications, such as integrating power stage 18 with other control circuits 32, 33, 36, and 16 on the same wafer, but in different embodiments, such as power stage 18 is external. A negative feedback signal can also be generated from the output of Rihuayi 16, as indicated by component symbol 35 in FIG. In different embodiments, the input signal Vin can also be amplified or reduced as a control signal for determining the gain g. As shown in FIG. 3, the amplifier 38 with increasing iik generates a signal kVin from the input signal Vin to the gain controller. 36 'Control its gain g. Since the gain g varies with the magnitude of the input signal vin, the switching frequency of the sigma-delta modulator 32 also changes 〇φ. Figure 4 shows an embodiment of the gain controller 36 with the input of the variable gain amplifier 40 connected. Signal S, output signal gS, input signal Vin control • Gain of variable gain amplifier 40. The variable gain amplifier 40 can use an electric-voltage controlled gain amplifier or a current controlled gain amplifier. Figure 5 shows a full analog implementation of the sigma-delta modulation module, which uses a 7-level analog sigma-delta modulator 32, and a negative feedback system from the output signal Vo ut through the inverter 3 3 and the resistor RF The path of b is provided. In the gain controller, the non-inverting input of the operational amplifier 42 is connected to a reference voltage, which is grounded in this embodiment, and a resistor 44 is connected between the inverting input terminal and the output terminal 200803156 of the operational amplifier 42. The variable resistor 46 Connected between the inverting input of the operational amplifier 42 and the sigma-delta modulator 32, the resistance of the resistor 44 and the variable resistor 46 determines the gain of the gain controller by changing the resistance of the variable resistor 46' The gain of the gain controller can be changed. The variable resistor 46 includes resistors 48 and 50 connected in series between the inverting input of the operational amplifier 42 and the sigma-delta modulator 32, and the transistors 52 and 54 are respectively connected in parallel to the resistor 50, and the gate of the transistor 52 is connected. The input signal viill, the gate of the transistor 54 is connected from the inverter 56 to the inversion signal of the input signal vin, and the on-resistance values of the transistors 52 and 54 are changed according to the magnitude of the input signal Vin. Assume that the resistance of the resistor 48 is R1, the resistance of the resistor 50 is R2, and the resistance of the resistor 44 is R3. When the input signal Vin is 0, the transistors 52 and 54 are completely closed, and the variable resistor 46 is equal to the resistor 48 series resistor. 50, the equivalent resistance is R1+R2, so the gain of the gain controller is g=R3/(Rl+R2) [Equation 1] When the absolute value of the input signal Vin is large, the transistor 52 or 54 is fully turned on. 'The resistor 50 is bypassed, and the equivalent resistance of the variable resistor 46 is ri, so the gain of the gain controller is g=R3/Rl [Equation 2] When the absolute value of the input signal Vin is gradually increased from 〇, The crystal 52 or 54 is gradually turned on by being completely turned off, the resistance of the transistor 52 is rm1, the resistance of the transistor 54 11 200803156 is RM2, and the equivalent resistance of the variable resistor 46 is R1+ (RM1//R2//RM2). Therefore, the gain of the gain controller is g=R3/[Rl+(RM1//R2//RM2)] [Equation 3] FIG. 6 is a variation of the embodiment. The equivalent resistance of the variable resistor 46 is only utilized. The incoming signal Vin controls the transistor 52 to determine. Figure 7 is another variation of the implementation _ example of the operational amplifier 58 having an inverting input coupled to a sigma-delta modulator 32?, a resistor 60 coupled to the inverting input of the operational amplifier 58 and Between the output terminals, the resistance of the variable resistor 62 is adjusted by the input signal Vin to control the gain. When the absolute value of the input signal Vin is large, the resistance of the variable resistor 62 is also large. In the embodiment of Figures 5 through 7, the gain of the gain controller is a continuous value. 8 shows another embodiment of the gain controller 36. The plurality of amplifiers 64 at the common input have different gains, respectively represented by gl to gn, the gain of the φj amplifiers 64 is gj, and the multiplexer 64 is input. The signal Vin control selects one of the plurality of amplifiers 64 to generate a signal gS to the output stage 34. - In a variant embodiment, as shown in Figure 9, the multiplexer 68 is controlled by the input signal - Vin to connect the signal S to one of the plurality of amplifiers 70 of the common output to generate the signal gS to the output stage 34. . In the embodiment of Figures 8 and 9, the gain of the gain controller is a discrete value. 10 shows yet another embodiment of the gain controller 36. The amplifier 72 amplifies or reduces the signal S to the output stage 34. The analog-to-digital converter 74 converts the input signal Vin into a digital signal, which is used in the gain table 76. Check 12 200803156 to find, thus determining the gain g of the amplifier 72. 11 shows a further embodiment of the gain controller 36. The digital amplifier 78 amplifies or reduces the signal S to the output stage 34. The analog digital converter 80 converts the input signal V i η into a digital signal control digital amplifier 7 . The gain of 8 g. For comparison with the prior art, Figures 12 through 14 show the simulation results of the power amplifier 30 of Figure 3. Figures 15 through 20 show simulation results without the use of the gain controller 36 (Figure 1) of the present invention. As shown in Figure 12, at a small input signal of -60dB, the noise floor is below -100dB, and the noise floor in the audio band (20Hz to 20kHz) is less than _12〇dB. The display noise is small, and when the large input signal is full scale, as shown in FIG. 13, the noise is still maintained at a low level, showing good performance of the power amplifier 3 。. Figure 14 is a diagram showing the relationship between the switching frequency and the input signal size. When the input signal size Vin < 0 · 5 Vmax (Vmax indicates the maximum amplitude of the input signal Vin), the switching frequency is about 370 kHz, and the input signal size vin is 0.7. When Vmax is 〇8Vmax, the switching frequency is increased to approximately 55 kHz, and selecting the appropriate design variable can reduce the switching frequency of this range. Figure 15 shows that the conventional power amplifier 10 can work normally when the input signal is small, but in the case of a large input sil?, the Sigma-delta modulator 12 becomes unstable, so the miscellaneous The bottom layer of the signal rises to -50dB. Figure 17 shows that the sigma-delta modulator 12 has become unstable when the input signal size Vin > 0.7Vmax. Figures 18 through 20 show the results of increasing the switching frequency. In order to obtain a stable sigma-delphi modulator 12 when inputting signals at full scale, the switching frequency must be as high as ΙΜΉζ. Because the switching frequency is increased, 13 200803156, so power consumption and EMI will also increase. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows a conventional power amplifier; FIG. 2 shows a conventional sigma-delta modulation module with hysteresis control. FIG. 3 shows a power amplifier according to the present invention; FIG. 4 shows a gain controller. One embodiment of the present invention; Figure 5 shows a sigma-delta modulation module implemented in a full analogy; Figure 6 shows an embodiment of the variation of Figure 5; Figure 7 shows another embodiment of the variation of Figure 5; Another embodiment of the apparatus; FIG. 9 illustrates an embodiment of the variation of FIG. 8; FIG. 11 shows still another embodiment of the gain controller; FIG. 11 shows still another embodiment of the gain controller; Figure 13 shows the simulation results of the power amplifier of the present invention when inputting signals at full scale; Figure 14 shows the relationship between the switching frequency of the power amplifier of the present invention and the input signal size; 15 shows the simulation results of the conventional power amplifier at low switching frequency and small input signal; 囷U shows that the known power amplifier is at low switching frequency, full scale input 200803156 The simulation result at the time of the signal; FIG. 17 shows a relationship between the switching frequency of the conventional power amplifier at the low switching frequency and the input signal size; FIG. 18 shows the simulation result of the conventional power amplifier at the high switching frequency and the small input signal; Figure 19 shows the simulation results of a conventional power amplifier at a high switching frequency, full scale input-in signal; and Figure 20 shows a conventional power amplifier switching frequency at a high switching frequency versus input signal size. [Main component symbol description] 10 Power amplifier 12 Sigma-delta modulator 13 Inverter 14 Output stage • 16 Quantizer 18 Power stage # 20 Sigma-delta modulation module. 22 Sigma-delta modulator 23 Inverter 24 Quantizer 26 Analog to Digital Converter 28 Retrieve Table 30 Power Amplifier 15 200803156
32 西格瑪-德爾塔調變器 33 反相器 34 輸出級 35 量化器的輸出訊號 36 增益控制器 38 放大器 40 可變增益放大器 42 運算放大器 44 電阻 46 可變電阻 48 電阻 50 電阻 52 電晶體 54 電晶體 56 反相器 58 運算放大器 60 電阻 62 可變電阻 64 放大器 66 多工器 68 多工器 70 放大器 72 放大器 74 類比數位轉換器 16 200803156 76 增益表 78 數位放大器 類比數位轉換器 8032 Sigma-delta modulator 33 inverter 34 output stage 35 quantizer output signal 36 gain controller 38 amplifier 40 variable gain amplifier 42 operational amplifier 44 resistor 46 variable resistor 48 resistor 50 resistor 52 transistor 54 Crystal 56 Inverter 58 Operational Amplifier 60 Resistor 62 Variable Resistor 64 Amplifier 66 Multiplexer 68 Multiplexer 70 Amplifier 72 Amplifier 74 Analog Digit Converter 16 200803156 76 Gain Table 78 Digital Amplifier Analog Digital Converter 80