200809237 九、發明說明·· 【發明所屬之技術領域】 種邏輯線路之點距分析方法’特別是指一種利用測 試點電路區域定義手段減少分析 量的點距分析方法。 【先前技術】200809237 IX. INSTRUCTIONS··············································································· [Prior Art]
現今的電路設計中，為有效管理線路設計、節省時間、 金錢與人力成本’電路佈局皆經由設計人員配合專用的邏 路I體進仃m同時載人不同電路板所需的設計限 較準確的線路設定值。但隨著科技 複雜性也p之;:ΓΓ功能逐步増加，因此設計PCB的 二^之增加’相對的量產之前的測試就變得十分重 一般電路板在進行測試之前， 能，並選定其功能線路的相關連接：先：，預心測試的功 作業若以現下業者的作法，I，為測試點’此流程 …其乃先載入並解析一邏; 點 點 包含的所有測試點的編碼與相對應之座桿資訊，、，二 =斤規則逐-比對各測試點之間的距離:並將= ::=:試=來’最後把分析結果匯整二 =“。的測4點。此外’也有些許業者是以目視 — 進仃測試關錯除，所謂目•查方 j : 輯電路軟縣储製出—賴點配置圖，相人 1視各測試點的編排狀態，並以手動方式選取不合糾 200809237 測試點。 但是，習知之技術有著無法避免之缺失，其如下列所 述： (1) 錯誤率高。所謂的目視檢查檢視測試點即是指以 肉眼檢視各個測試點之間的距離，若是功能較少，複雜性 較低的電路板，其功能電路的測試點也許只有數十個，若 以肉眼檢視其測試點是否設計適當，檢示結果的錯誤率也 不會太高，但是相較於功能性較為繁多的電路板，如：電 腦主機板，其功能電路所需所標示的記錄點少說也以千點 計算，並不易檢視出測試點之錯誤所在，如此即難以產生 正確的線路測試輸出；其次，依現今邏輯電路軟體而言， 當匯入分析結果檔案時，其所能取得之分析資訊多為文字 列表，即是列出錯誤的測試點編碼資訊與相對應之座標設 定，再由逐一比對以尋求測試點之設置位置，若數量眾多， 則資訊比對容易錯誤而產生不必要的人為疏失。 (2) 時間成本過高，習知之技術中，若以人工作業， 則為逐步審視每一測試點之配置距離，但舉凡任一種電路 板，如電腦主機板，其所標示的記錄點即千點以上，若逐 一省視，十分耗費時間成本；其次，若是當匯入分析結果 檔案於到邏輯電路軟體時，也多以文字列表呈現，研發人 員需逐步比對不合格之測試點於電路板上之定點配置，但 測試點數量較多時，配置錯誤之測試點相對應較為增加， 如此研發人員於比對作業即會花費大量的時間；再者，即 使便是配合邏輯電路軟體分析測試點，但也是將各測試點 200809237 逐一與其它測試點相比對，即可能重複檢測到測試點之間 的距離，或是將明顯於不同位置之測試點進行不必要的點 距比對，進而花費不必要的時間成本。 【發明内容】 有鑑於此，為改進習知技術之缺失，增進使用者之便 利性，並簡化邏輯電路測試流程以提高生產效率，本發明 係提出邏輯線路之點距分析方法。 本發明係一種邏輯線路之點距分析方法，係應用一邏 輯電路設定檔案直接產生可匯入邏輯電路軟體之測試點距 離分析結果，其邏輯電路軟體可為現今業者常使用的邏輯 電路設計軟體Allegro，係透過邏輯電路軟體先輸出一邏 輯電路設定檔案，其檔案具有電路板進行測試時，所需之 各測試點的相關資訊，包含各測試點編碼資訊以及與測試 點編碼貢訊相對應之測試點座標設定’接者利用一點距分 析程序以逐步比對字串的方式，遵循一編碼規則以取得包 φ 含於邏輯電路設定檔案中的複數個測試點編碼資訊，並以 同樣方式取得所有測試點編碼資訊的測試點座標設定，然 後載入一電路區域劃分規則以將電路板劃分複數個電路區 域，係依這些測試點座標設定以指定各測試點編碼資訊所 對應之電路區域，再載入一點距分析規則，分析於同電路 區域中，各成對的測試點座標設定之間的預測距離值為多 少，最後再將不符合點距分析規則的測試點座標設定標記 出來，並將其測試點編碼資訊、成對的測試點座標設定與 對應電路區域記錄生成一分析結果槽案，以匯入遊輯電路 200809237 軟體。 -當避輯電路軟體匯入分析結果槽案時，會以圖像來顯 示其分析絲。㈣電妹體會先載人電路板之線路設定 與測試點配置，接著載人分析結練案，係顯示電路區域 的劃分與各測試點所對應的電路區域，然後依照分析結果 將不符合點距分析規則的測試點與所屬的電路區域以顯眼 的顏色或是特殊符號加以標記，藉此協助研發人員快速了 解線路設計之錯誤所在，以便進行修正。、 本發明係一種邏輯線路之點距分析方法，係具備下求 數點優於先前技術之作法，並具備如下所述之顯著功效= 進。 一 （1)錯誤率小，於習知技術中，測試點之點距分析多 半由人工以肉眼檢視其電路圖上測試點之配置，或是將分 析結果職匯人邏輯f路軟體以人卫比對錯_試點之配 置位置，但隨著電路板的魏性增加，所t檢視的測試點 也增加，相對的，發生人為疏失的機率也相對性提高；而 本發明係以點距分析程序自動於電路板上劃分數個電路區 域’並自動分析各電路區域中成對職點座標設定之間的 預娜距離值’且能以特定圖式加以標記錯誤的測試點座桿 設定以及所在之電路區域，如此研發人員完 古 錯誤測試點之所在，以降低賴絲的錯誤率。 析多間成本’於習知技射，賴點之點距分 方式進行作# ’錢電路板的功能複雜，所 ㈣置之測試點會㈣性增加，以肉眼檢視 200809237 時間，若以邏輯電路軟體協助分析，係為逐—比對各测試 點其它測试點之間的距離，則可能重複檢測到測試點之間 的距離；而本發明係利用點距分析程序全自動分析成對的 測試點座標設定之間的預剜距離，並標記突顯錯誤之測試 點所在位置與對應之電路區域，使研發人員於省視時大幅 節省時間成本，j：匕外利用劃分電路區域可避免成對的測試 點座標设疋重複檢視，而且若是電路區域內無測試點或只 有個/則试點，則無需檢挪，同時也能減少檢測所需 間成本。 τ 钩1之不發明的 j W〜、稱造特徵及其功能有進一步的 了解’兹配合相關實施例及圖式詳細說明如下： 、 【實施方式】 ^照弟1 ® ’其為本發明之线架構 表達的意義在於-般通用的邏輯電路_時常= 的便利性’係在邏輯電路較體 =2分析 析程序12° «及儲存各種點距資訊的點：：距分 助邏輯電路敕體11()進行 貝4庫13G來協 析132，區域資料庫131係儲存複數個電路區域‘ /刀規則’而分析資料庫132儲存複數個點距 “ 電路區域劃分規則與各點距分析規則係適= =狀。邏㈣路軟㈣G係能輪出—邏輯電路=二 案111且具有一檢修程序112，邏輯電路設定槽安;;疋知 9 200809237 包含所有測試點編碼:#訊以及相對應的賴點座標設定， 檢修程序112用以喊示匯入檔案所包含的資可。 點距分析程序120包含-擷取程序121、—分析程序 122與-檢視程序123,擷取程序m係用以擷取邏輯電路 設定標案111中所包含的所有測試點編碼資訊以及相對應 的測試點座標設定，且能從區域資料庫131中載入一電路 區域劃分規則，係藉由測試點座標設定以區分各個測二點 編碼設定所義的電路區域’並形成區分結果:#訊以傳送 至分析程序122。 、而檢視程序123係檢視所取得的電路區域劃分規則是 否適用於此私路板的線路設定，所需得的規則劃分方式若 不適用於此線路設定，則可令揭取程序121取得一個新的 電路區域劃分規則以重新劃分電路區域。 刀析私序122於取得區分結果資訊後，自分析資料庫 、載個點距分析規則，係逐步檢視與分析同一電路 _ =域裡’、鱗_點鍊設定之_賴雜值，若任何 電路區^，有檢視到有不符合點距分析規狀成對的測 ‘叹疋存在時，除了會記錄此成對的測試點座標設 疋。通胃圮錄其對應的測試點編碼資訊與測試點座標設定 斤_的迅路區域。但於檢視過程當中，檢視到對應此電路 2或之測4點座標設定只有一個或是是零個時，會標記此 :r品或 <一不進行點距分析，而是直接檢視下一個電路 區域。當分析完成時，分析程序122會將分析結果生成分 析結果檔案並匯入至邏輯電路軟體11〇，以利用檢修程序 200809237 112顯示分析結果。檢修程序112會載入電路板的線路設 定並以圖像顯示，再將測試點依其測試點座標設定以圖示 映射於圖中且標明測試點編碼資訊，最後將不合格的測試 點以及所在的電路區域用特殊顏色、圖示或符號作視覺化 的突顯標記，以協助研發人員明確知道不合格的測試點之 所在位置。 請參考第2圖，其為本發明之方法流程圖，係應用一 邏輯電路設定檔案111直接產生可匯入邏輯線路軟體之測 試點距離分析，其方法含下列步驟： 步驟S201，透過字串比對方式查找邏輯電路設定檔案 111中複數個測試點編碼資訊，此邏輯電路設定檔案111 係由一邏輯電路軟體110輸出，並利用一擷取程序121以 字串比對方式查找出所有測試點編碼資訊。 步驟S202，自邏輯電路設定檔案111擷取對應各測試 點編碼資訊之複數個測試點座標設定，擷取程序121係以 φ 測試點編碼資訊為基本字串，再次進行查找並取得所有對 應各測試點編碼貢訊的測試點座標設定。 步驟S203，載入一電路區域劃分規則，依照此些座標 設定以指定各測試點編碼資訊所對應之複數個電路區域， 擷取程序121係從一區域資料庫131以載入電路區域劃分 規則以將電路板劃分成各個不同之電路區域’並將各测試 點編碼資訊依照其測試點座標設定指定每一測試點編碼資 訊所對應的電路區域，以形成一區分結果資訊再傳送至一 分析程序122。 11 200809237 y驟S2Q4載入-點距分析規則’依序自各電路區今 刀析區域中所包g各成對之測試點座標設定之間所對應之 -預測距離值。分析程序122於接收區分結果資訊時1 從分析資料庫132载入點距分析規則，並逐步檢視在同電 路區域中各成對的測試點座標設定之間的預测距離值，紙 而於檢視過程中’若檢视出某電路區域中未包含有成_ 測試點座標設定’即是指僅一個測試點座標設定或沒 何測試點座標設定對應此雷政卩々 不進行點距分析。“紅域’則標把此電路區域值 步驟迦’當任1測輯值不符點 規士 =預測距離值所對應成對之測試點座標設定及斤= 區域，並記錄於一分析結果稽案’以匯入邏輯電略 110。當進行分析預測距離值時，如果有任 人體 座標設定所分析出來的預測距離值並不符人試點 則，則將其成對的測試點座標設定進行襟規 ，資：。然而’在分析結果播案中更記錄屬:; 讯，以提供邏輯電路軟體110讀取進行差里貝 於進行點距分析時，係會遇到各種二：果，點 =結果槽案中，崎不同的顯示設定;=同= 點座5二合格的賴_紅線圈選&，則在記錄測試 ”、，占座軚坟疋的所對應資訊時，將紅線的顯 — =座標設定的對應資訊以記錄於分析綠果二;= 电路軟體11G ®人分析、纟#果麟時 結果係由檢修程序輸出顯示，此時不合格二=: 12 200809237 線圈選標示，如此研發人員便能快速了解_ 刀析：果並進行電路的設計修正。 ·、、、巨 範例‘式圖’ t為本發明之邏輯電路設定檔案⑴ 包含電路把“ ’如稽案格式圖300所示之檔案格式，其 板編碼，係用以擷取相對應之I 以及點距分她。TP即綱則 應的測試點編碼資訊與測試點座標設定Γ匕314其對 叫八圖與f4B圖’其分為本發明之電路區域 』刀剛_分後的簡衫意圖，_點配 齡程序⑵從邏輯電路設錢案lu取得測試二， /未載入區域劃分規則。而區域劃分圖繼即代 時， 禪μ以二 域並依照所有測試點座 _ 二疋叫續制電㈣域，此相獨各個電路 進行編碼與是標上測試點編碼資訊。 °° 3 t照第5圖’此為本發明之測試點標記圖，各分析 私序122將所有分析結果整合形成 : 邏輯電路軟體110時，邏輯電路 "^ ’亚匯入 案所包含之資訊映射至電路、體110 θ將分析結果槽 電路軟體110係先將電路板的以頟不其分析結果。邏輯 载入，接著匯入分析結果幹t路設定與測試點配置設定 規則以劃分電路區域，其:亚梅取出所使用的區域劃分 未進行點距分析的電路區域以路區，的分析結果，將 一…、色粗框標記，不合格測試 200809237 點座標設定則以紅線圈選，其所對應的電路區域係以紅色 粗框標記，並將標記完成的電路板相關貧料以檢修程序輸 出並以視覺化顯示，其顯示方式如標記圖500所示，電路 區域B6包含的测試點皆不符合點距分析規則，而不合格的 理由在於（1)其中有兩個測試點位置重疊，（2)其中三個測 試點的記置位置重疊，(3)其中有兩個測試點之點距太過相 近。而上述不合格的測試點皆以紅線圈選標記，電路區域 B6本身則以紅色粗框標記，藉以顯示出此電路區域内有不 合格的測試點存在。而電路區域C4與C6所具有之測試點 不滿兩點，所以並未進行點距分析，因此以黑色粗框標記。 請參照第6圖，其為本發明之分析結果檔案格式範 例’分析結果格式圖6 0 0中所不之檀案格式包含有電路板 編碼、所使用之電路區域劃分規則、不合規則之測試點編 碼資訊、測試點座標設定以及預測距離值，並以【M】表明 不合規則之測試點資訊；此外分析結果檔案具有的資訊還 可以包含未進行分析的電路區域’係將其電路區域的編碼 寫入其中，並以【N】表示此電路區域並未進行點距分析。 雖然本發明之實施例揭露較佳方式如上所述，然其並 非用以限定本發明，任何熟習相關技藝者，在不脫離本發 明之精神和範圍内，當可作些許之更新與潤飾，因此本發 明之專利保護範圍須視本說明書所附之申請專利範圍所界 定者為準。 【圖式簡單說明】 第1圖係本發明之系統架構圖； 14 200809237 第2圖係本發明之方法流程圖； 第3圖係本發明之邏輯電路設定檔案格式示意圖； 第4A圖係本發明之測試點配置圖； 第4B圖係本發明之電路區域劃分不意圖 第5圖係本發明之測試點標記示意圖；以及 第6圖係本發明之分析結果檔案格式示意圖。 【主要元件符號說明】In today's circuit design, in order to effectively manage the circuit design, save time, money and labor costs, the circuit layout is designed by the designer to cooperate with the dedicated logic circuit, and the design requirements required for carrying different boards at the same time are more accurate. Line set value. However, with the complexity of technology, the function of 科技 is gradually increased, so the increase of the design of the PCB is increased. The test before the relative mass production becomes very heavy. Before the board is tested, it can be selected. Related connection of function line: First: If the work of the pre-test is based on the current practice, I, as the test point 'this process... it loads and parses a logic first; the code of all the test points contained in the point And the corresponding seatpost information,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, In addition, there are also some operators who are looking at the test-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Manually select the 200809237 test point. However, the conventional technology has inevitable defects, as described below: (1) High error rate. The so-called visual inspection test point refers to visual inspection of each test point. The distance between the functions For a circuit board with less complexity and less complexity, there may be only dozens of test points for its functional circuits. If the test points are properly designed by the naked eye, the error rate of the test results will not be too high, but compared with the function. A more versatile circuit board, such as a computer motherboard, the number of recorded points required for its functional circuit is also calculated in thousands of points, and it is not easy to check the error of the test point, so it is difficult to produce the correct line test output. Secondly, according to the current logic circuit software, when the analysis result file is imported, the analysis information that can be obtained is mostly a text list, that is, the wrong test point code information and the corresponding coordinate setting are listed, and then The comparison is made one by one to find the setting position of the test point. If the number is large, the information comparison is easy to be mistaken and unnecessary human error is caused. (2) The time cost is too high, and in the conventional technology, if it is manually operated, it is gradually Examine the configuration distance of each test point, but for any kind of circuit board, such as a computer motherboard, the recorded points are more than a thousand points, if one by one, It takes time and cost; secondly, if the data of the analysis result is imported into the logic circuit software, it is often presented in a text list. The R&D personnel need to gradually compare the unqualified test points to the fixed-point configuration on the circuit board, but the test points When the number is large, the test points of the configuration errors are relatively increased, so that the research and development personnel will spend a lot of time in comparing the operations; in addition, even if the test points are matched with the logic circuit software analysis, the test points will be 200809237. Compared with other test points one by one, it is possible to repeatedly detect the distance between the test points, or to perform unnecessary dot-to-point comparison on the test points which are obviously at different positions, thereby taking unnecessary time cost. In view of this, in order to improve the lack of the prior art, improve the convenience of the user, and simplify the logic circuit testing process to improve the production efficiency, the present invention proposes a method of analyzing the pitch of the logic line. The invention relates to a method for analyzing the pitch of a logic line, which is a logic circuit setting file directly generating a test point distance analysis result which can be imported into a logic circuit software, and the logic circuit software can be a logic circuit design software commonly used by the current industry Allegro The logic circuit software first outputs a logic circuit setting file, and the file has the relevant information of each test point required for testing the circuit board, including the coding information of each test point and the test corresponding to the test point code Gongxun. The point coordinate setting 'sender uses the one-point distance analysis program to gradually compare the strings, follows an encoding rule to obtain the plurality of test point coded information contained in the logic circuit setting file of the package φ, and obtains all the tests in the same manner. Point code information test point coordinate setting, and then load a circuit area division rule to divide the circuit board into a plurality of circuit areas, according to the coordinates of the test point coordinates to specify the circuit area corresponding to each test point code information, and then load One-point analysis rule, analyzed in the same circuit area, each The value of the predicted distance between the test point coordinates is set. Finally, the test point coordinate setting that does not meet the point distance analysis rule is marked, and the test point coding information, the paired test point coordinate setting and the corresponding circuit area are set. The record generates an analysis result slot to be imported into the game circuit 200809237 software. - When the evasion circuit software is imported into the analysis result slot, the analysis wire is displayed as an image. (4) The electric sister realizes the line setting and test point configuration of the first manned circuit board, and then the manned analysis and the knot practice, which shows the division of the circuit area and the circuit area corresponding to each test point, and then according to the analysis result will not conform to the point distance. The test points of the analysis rules and the associated circuit areas are marked with conspicuous colors or special symbols to assist the R&D personnel to quickly understand the error of the circuit design for correction. The present invention is a method for analyzing the pitch of a logical line, which has the advantage of lowering the number of points than the prior art, and has the significant effect = advance as described below. One (1) error rate is small. In the prior art, the point distance analysis of the test points is mostly by manual inspection of the configuration of the test points on the circuit diagram by the human eye, or the analysis result is the person of the logic of the software. Right or wrong _ pilot configuration location, but as the board's superiority increases, the test points of the t-view are also increased, and the probability of human error is relatively increased. The present invention automatically uses the point distance analysis program. Dividing a plurality of circuit areas on the circuit board and automatically analyzing the pre-regressive distance value between the pair of coordinate coordinates in each circuit area and the test point seat bar setting and the circuit in which the error can be marked with a specific pattern The area, where the R&D personnel completed the error test point, to reduce the error rate of Lys. Analysis of multiple costs 'in the knowledge of technology, the point of the point of the way to make # ' money circuit board function is complex, the (four) set the test point will (four) increase, to visually check the 200809237 time, if the logic circuit The software assists the analysis by comparing the distance between other test points of each test point, and the distance between the test points may be repeatedly detected; and the present invention uses the point distance analysis program to fully analyze the paired test. The pre-twist distance between the point coordinates is set, and the position of the test point highlighting the error and the corresponding circuit area are marked, so that the research and development personnel can save time and cost in a timely manner, and j: the use of the divided circuit area can avoid pairing. The test point coordinates are set to repeat the view, and if there is no test point or only one / then pilot in the circuit area, there is no need to check, and the cost of the test can be reduced. τ hook 1 does not invent the j W ~, the characteristics and functions of the invention have a further understanding of the following examples and drawings are described in detail as follows: [Embodiment] ^ Zhaodi 1 ® 'is the invention The meaning of the line architecture expression is that the general-purpose logic circuit _time constant = convenience is in the logic circuit body = 2 analysis program 12 ° « and the point of storing various point information:: distance help logic circuit body 11() carries out the 13G library 13G to parse 132, the regional database 131 stores a plurality of circuit areas '/knife rules' and the analysis database 132 stores a plurality of dot pitches. "Circuit area division rules and various point distance analysis rule systems Suitable = = shape. Logic (four) road soft (four) G system can turn out - logic circuit = two case 111 and has a maintenance procedure 112, the logic circuit sets the slot security;; know 9 9092239 contains all test point codes: #讯 and corresponding The point of view coordinates setting, the maintenance program 112 is used to call the resources included in the import file. The point distance analysis program 120 includes a capture program 121, an analysis program 122 and a view program 123, and the program m is used. Take the logic circuit setting All the test point coding information included in 111 and the corresponding test point coordinate setting, and a circuit area division rule can be loaded from the area database 131, and the test point coordinate setting is used to distinguish each measurement point code setting. The circuit area of the meaning is formed and the result is differentiated: the signal is transmitted to the analysis program 122. The inspection program 123 checks whether the obtained circuit area division rule is applicable to the line setting of the private board, and the required rule. If the division mode is not applicable to the line setting, the stripping program 121 may obtain a new circuit area division rule to re-divide the circuit area. The knife analysis private sequence 122 obtains the difference result information, and then analyzes the database and carries the data. The point distance analysis rule is to gradually check and analyze the _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 'When the sigh exists, in addition to recording this pair of test point coordinates set. Tongwei 圮 recorded its corresponding test point coding information and test point coordinates set jin _ Xun Road area However, during the inspection process, when it is checked that there is only one or zero coordinate setting corresponding to the circuit 2 or the measurement, the r mark or < does not perform the point distance analysis, but directly under the inspection. A circuit area. When the analysis is completed, the analysis program 122 generates an analysis result file and imports it into the logic circuit software 11〇 to display the analysis result using the maintenance program 200809237 112. The inspection program 112 loads the circuit board circuit. Set and display as an image, and then set the test point according to its test point coordinates to map the map and indicate the test point code information, and finally use the special test color and the circuit area where the test area and the circuit area are in special colors, icons or Symbols are visually highlighted to assist developers in clearly identifying the location of unqualified test points. Please refer to FIG. 2 , which is a flowchart of the method of the present invention. The method 1 includes a logic circuit setting file 111 to directly generate a test point distance analysis of the software that can be imported into the logic circuit, and the method includes the following steps: Step S201, through the string ratio The plurality of test point coding information in the file 111 of the mode search logic circuit setting file 111 is outputted by a logic circuit software 110, and all the test point codes are searched by a string comparison program by a string comparison method. News. In step S202, a plurality of test point coordinates corresponding to each test point coded information are retrieved from the logic circuit setting file 111, and the capture program 121 uses the φ test point coded information as a basic string, and searches again and obtains all corresponding tests. Point code test coordinates set by Gongxun. Step S203, loading a circuit area division rule, according to the coordinate settings to specify a plurality of circuit areas corresponding to each test point coded information, the capture program 121 is from a regional database 131 to load the circuit area division rule. Dividing the circuit board into different circuit areas' and designating the circuit area corresponding to each test point coded information according to the test point coordinate setting of the test point coordinates to form a differentiated result information and transmitting to the analysis program 122 . 11 200809237 y S2Q4 load-pitch analysis rule' is the predicted distance value from the pair of test point coordinates set in the current analysis area of each circuit area. When the analysis program 122 receives the discrimination result information, 1 loads the point distance analysis rule from the analysis database 132, and gradually checks the predicted distance value between each pair of test point coordinate settings in the same circuit area, and examines the paper. In the process, if you check that a certain circuit area does not contain the _ test point coordinate setting, it means that only one test point coordinate setting or no test point coordinate setting corresponds to this Lei Zheng 卩々 does not perform the point distance analysis. "Red Field" is marked with the value of this circuit area step can be 'incumbence 1 measurement value does not meet the point ruler = predicted distance value corresponding to the pair of test point coordinates set and kg = area, and recorded in an analysis result 'To import logic Logic 110. When analyzing and predicting the distance value, if there is a trial distance value analyzed by the human coordinate setting, it is not suitable for the pilot, then the paired test point coordinates are set. Capital: However, 'in the analysis results broadcast case is more recorded:; News, to provide logic circuit software 110 to read the difference Ribe in the point distance analysis, the system will encounter a variety of two: fruit, point = result slot In the case, the different display settings of Saki; = the same = the seat of the 5 second qualified Lai _ red coil selection &, in the record test", when the information corresponding to the tomb of the tomb, the red line is displayed - = The corresponding information set by the coordinates is recorded in the analysis of green fruit 2; = circuit software 11G ® human analysis, 纟 #果麟 results are displayed by the inspection program output, at this time unqualified 2 =: 12 200809237 coil selection, so R & D personnel Can quickly understand _ knife analysis: And design correction circuit. ·, , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , And the point distance is divided into her. The TP is the test point code information and the test point coordinate setting Γ匕314, which is called the eight figure and the f4B picture, which is divided into the circuit area of the invention. Intention, _ point ageing program (2) from the logic circuit set money case lu to obtain test two, / unloaded area division rules. And the area division map is followed by the generation, Zen μ to two domains and according to all test points _ Called the continuous power (four) domain, this separate circuit is coded and marked with test point coding information. ° ° 3 t according to Figure 5 'This is the test point marker map of the invention, each analysis private sequence 122 will analyze all The result is integrated: When the logic circuit software 110 is used, the information contained in the logical circuit "^ 'Ahui is mapped to the circuit, and the body 110 θ will analyze the result slot circuit software 110 to first analyze the result of the circuit board. Logical loading, then import the analysis results The t-channel setting and the test point configuration setting rule are used to divide the circuit area, and the area used by the yamei extraction is divided into the circuit area where the point distance analysis is not performed, and the analysis result of the road area is marked with a... Qualification test 200809237 Point coordinates setting is selected by red coil, the corresponding circuit area is marked with red thick frame, and the board-related poor material marked with the mark is output as a maintenance program and displayed visually. As shown in FIG. 500, the test points included in the circuit area B6 do not conform to the point distance analysis rule. The reason for the failure is that (1) two test points are overlapped, and (2) the positions of the three test points are recorded. Overlap, (3) The distance between the two test points is too close. The above unqualified test points are marked with a red coil, and the circuit area B6 itself is marked with a thick red frame to show the area of the circuit. There are unqualified test points, and the test points of circuit areas C4 and C6 are less than two points, so the point distance analysis is not performed, so it is marked with a thick black frame. Please refer to Figure 6. It is the example of the analysis result file format of the invention. The analysis result format is not shown in the figure. The format of the tile file includes the circuit board code, the circuit area division rule used, the test point coding information of the irregular rule, and the test point. The coordinate setting and the predicted distance value, and [M] indicates the test point information of the irregular rule; in addition, the information of the analysis result file may also include the circuit area that is not analyzed, by writing the code of the circuit area into it, and [N] indicates that the circuit area is not subjected to the point distance analysis. Although the preferred embodiments of the present invention are as described above, it is not intended to limit the present invention, and those skilled in the art can avoid the spirit of the present invention. And the scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a system architecture diagram of the present invention; 14 200809237 FIG. 2 is a flowchart of a method of the present invention; FIG. 3 is a schematic diagram of a logic circuit setting file format of the present invention; FIG. 4B is a schematic diagram of the test point marking of the present invention; and FIG. 6 is a schematic diagram of the analysis result file format of the present invention. [Main component symbol description]
110 邏輯電路軟體 111 邏輯電路設定檔案 112 檢修程序 120 點距分析程序 121 擷取程序 122 分析程序 123 檢視程序 130 點距資料庫 131 區域貧料庫 132 分析資料庫 300 檔案格式圖 401 測試點配置圖 402 區域劃分圖 500 標記圖 600 分析結果格式圖 15110 Logic Circuit Software 111 Logic Circuit Setup File 112 Overhaul Program 120 Pitch Analysis Program 121 Capture Program 122 Analysis Program 123 View Program 130 Point Distance Library 131 Area Poor Library 132 Analysis Library 300 File Format Diagram 401 Test Point Configuration Diagram 402 Area Dividing Diagram 500 Marking Diagram 600 Analysis Result Format Figure 15