200807843 九、發明說明： 【發明所屬之技術領域】 略模式之電源轉換器，尤指 調整脈波省略料控制訊號 本發明係指一種可操作於脈波省 一種可隨輸入電壓與輸出電壓而自動 之脈波寬度的電源轉換器。 【先前技術】 =何電子裝置的勒《I在有電秘應的 此’對於電抒置㈣，领供敎麵 應器就顯得非常重要。 卩關電源供 凊參考第1圖，第1圖為一習知電源轉換器1〇〇之示意圖。 電源轉換器觸用來提供電源至一負載電路112，其包含有一驅動 電路102、一電源輸出電路1〇3及一回授電路1⑴。電源輸出電路 1〇3包含有電晶體1〇4、1〇6及一輸出電感應。驅動電路撤可 根據回授電路110的回授訊號，調整電晶體顺、慨的開啟及關 閉’以控制輪出電感画的輸出電壓ν〇υτ。首先，驅動電路脱 =電曰日體1〇4導通並將電晶體觸關閉，則電晶體刚的源極電 μ曰机向輪出電感108，使得輸出電感1〇8儲存能量。然後，驅動 電路102將電晶體1〇4 _閉並將電晶蹲1〇6導通，此時電源停止 輸入至輸出電感108，因而產生極性相反的電流經由電晶體106 6 200807843 導通至系統地端。因此，壤過切換電晶體1〇4及1〇ό的開啟及關 閉時間，驅動電路102可控制輸出電感1〇g的輸出電壓v〇LrT。 因此，透過電源轉換器1〇〇所提供的電源，電子裝置可正確 運作。然而’ Pi|著節能觀念越來越被重視，降低電源供應器在待 機時的電I肖耗已成為業界所努力的目標。習知技術已發展出許 多用於電_換||之極域或無餅，降低切換損失和額定損失 的方法。常見的方法有脈衝省略模Μ_)、叢 發模式（BurstMode)及非導通時間調變（〇ffTimeM〇duiati〇n)。 脈衝省略模式的技術是由SGS_Thompson及Nati〇nal —⑽dU_所提出，其係根據負載__度，來決定省略切 換脈衝與否，以達到降低電源損失的目的。請參考第2圖，第2 圖為脈衝省略模式之概念示意圖。脈衝省略模式駐要概念，是 於系統操作於極輕載或域時，省略部分切換脈衝，崎低電晶 體的切換辭，從而滿足在輕_低損耗要求。 .* 因此’脈衝@略模式係透過降低電晶體的切換鮮，達到降 低電源轉換!i刚輕载時的電源消耗。.習知技術已揭露許多相關 的，路木構’用以實現脈衝省略模式n習知技術通常採用 固定電感峰值驗（CGnstantIndu_eakc_) _制 ΐ此電源供應器觸之輪出電感⑽的峰值電流會被限制在一定 犯圍在此It七下’為了避免脈衝省略模式下輸出電感刚的電 200807843 舉例來說，美國專利第5,745,352號「dc_to_dc c__ FuncUoning in a Pulse-skipping M〇de with Low P〇wer Conation an Inhlblt」揭路一種可操作於脈衝省略模式的直流對直流 轉換器’其為固定輸出電感峰飾_構姻專利第讽说 號之直流對直流轉換器，係於輕載時__外部電阻的電壓以 獲得電流的資訊’再與固定電壓概來控制峰值電流。當輸出電 壓低於設纽時，便會切換電晶體，以輸人電流至輸出電感，累 積電流並輸㈣錄。其缺點在於#操作於不同的輸人電壓及輸 出電壓下’有可能造成脈衝省略模式下輸出電感的電流大於正常 模式（即連續導賴式）下的電流，所以為了避免此情況發生， 輸出電感的選用上會受到限制。 另外，美國專利第6,661，679號「PWM C〇咖ller Having Adaptive Off-time Modulation for Power Savingj 導通時間機節省電源雜舰波寬度觀控㈣。美國專利第 ,661,679號之脈波寬度調變控制€係先伽彳貞載的回授電壓及輸 入電壓’並轉換成電流，再彻含有回授龍及輸人電壓之資訊 的電流來調整料通時間。因此，非導輯間是這兩個變數（回 授電壓及輪人電壓）的函數，而導通時間是由固定峰值電流的時 間決定，與美國專利第5,745,352號之直流對直流轉換器相同，且 8 200807843 電壓 C Continuous 美國專_，_9_朗料 成比例的_，但沒有㈣與操作 ㈣及輸入 rnnHll,f. Ayr」 逑續導通模式（Continuu丨 MGde，CCM)時的導通時間和非導通時間是否有相關 【發明内容】 種可操作於脈波省略 因此，本發明之主要目的即在於提供一 模式之電源轉換器。 •： 本發明揭露一種可操作於脈波 在輕載系統時將一電源產生所、；、源轉換益’用以 =雷: 電源轉換器裝置包含有-驅動電路、-二 =一回授電路及—脈波省略模式控制電路 = 用來根據-回授訊號及—脈波省略模式 訊號。該電源輸出電樓於該電源產:器: =來根據該閘_號，轉__ 源至貞倾路。該峨電路輪料 :來根據該負載電路之一回授•產二=電 路。該脈波省略模式__接動 == 電路，並根據該電源產生器所式控制訊號至該驅動 ⑽，調整該脈波省略模===_所輸 驅動電路’控制該電源輪出電路所輪出:電^ 200807843 【實施方式】 請參考第3圖’第3_圖為本發明一實施例可操作於脈波省略 模式（Pulse-skipping m〇de)之電源轉換器3〇〇之示意圖。電源轉 換器3〇〇用來接收-電源產生器逝所輸出之電源，並轉換為適 當大小後輸出至一負載電路304。電源轉換器3〇〇包含有一驅動電 路306、一電源輸出電路,、一回授電路31〇及一脈波省略模式 控制電路阳。電源輸出電路3〇8較佳地包含複數個電晶體，用以 根據驅動電路裏所輸出·之閘驅動訊號，切換電晶體的開啟與關 閉，以輸出特定大小的電壓至負載電路綱。回授電路31〇可根據 負載電路304 #回授電壓，產生回授訊號至驅動電路裏。脈波省 #、气控電路312可輸出脈波省略模式控制訊號至驅動電路 306,並可根據電源產生器3〇2所輸出的輸入電壓㈣及電源輸出 電路308所輸出之電壓ν〇υτ，調整脈波省略模式控制訊號的導 通時間。因此’驅動電路3〇6可根據回授電路训所輸出的回授 虎及^波省略模式控制電路312所輸出的脈波省略模式控制訊 =電路3〇8之電晶體的開啟與關閉時間，以滿足 在輕載的低損耗要求。 根據電因脈波省略模式控制電路312係 所輸出之電壓V0UT，== 壓簡及電源輸出電路廳 以控制驅動電路咖戶^波切模式控制訊號的導通時間， 斤輪出的閘驅動訊號。如此一來，脈波省略 200807843 $式下電源輸㈣路獨之輸出電感的蜂值電流會與連續導通模 ’下的電流值維持-定比例_係，因而不會發生脈波省略模式 下輸出電叙電鱗波（Ripple)大於操作於連續導賴式時的情 況因此’相較於習知固定輸出.電感峰值電流之架構的控制方式， 本發明中輸出械的獅範圍有較大彈性。 請參考第4 _，第4圖為第3圖中脈波省略模式控制電路312 之不意圖。脈波省略模式控制電路312包含有一電流源、4〇〇、_電 谷402、一比較器404及一 SR正反器406。電流源400可根據電 源產生器302所輸出的輸入電壓VIN，提供與輸入電壓刪成比 例的電流，例如，將輸入電壓VIN導入一電阻R，則可產生大小 為(VIN/R)的電流。電流源4〇〇所產生的電流會對電容4〇2充電， 而比較器404則用來比較電容402的電壓VP與電源輸出電路3〇8 所輸出之電壓VOUT的直流資訊VOUTEQ，並將比較結果輸出至 SR正反器406。SR正反器406的設定（Set)端S耦接於一時脈 產生器（未緣於第4圖中），用以接收一時脈訊號CLK;重置（Reset) 端R耦接於比較器404，用以接收比較器404的比較結果；輸出 端Q則耦接於驅動電路306，用以輸出脈波省略模式控制訊號。 關於脈波省略模式控制電路312的操作，請參考第5圖及第 6圖。第5圖為SR正反器406^^真值表，第6圖為脈波省略模式 控制電路312之相關波形示意圖。在第6圖，由上至下分別顯示 時脈訊號CLK、電源輸出電路308所輸出之電壓VOUT的直流資 200807843 訊VOUTEQ、電容402的電壓VP及脈波省略模式控制訊號PSM。 首先，當時脈訊號CLK：觸發時，SR正反器406操作於設定狀態， 電流源400開始對電容402充電，一直到電容402的電壓VP超過 VOUTEQ時，SR正反器406進入重置狀態，電容402開始放電到 〇電位。簡言之，脈波省略模式控制訊號的啟始係由時脈訊號CLK 觸發，而其結束位置則相關於電壓VP是否超過VOUTEQ，亦即， 電壓VP大於VOUTEQ時比較器404所產生的脈波，決定了脈波 省略模式控制訊號的脈波寬度。 由於輸入電壓VIN故變時，電流源4〇〇的輸出電流(VIN/R) 曰跟著改I ,輸出電壓VOUT改變時，觸發sr正反器406重置 =需要的時間也會不-樣。因此，脈波省略模式㈣訊號的脈波 寬度會隨著輸人賴VIN與賴V〇UT而改變。如此__來，脈波 省略模式下輸出電感的峰值電流會與連續導通模式下的電流值維 持-定_的_，科會發生脈波省略模式下輪出電感之電流 =大於操作於連續導通模式時的情況’使得輪出電 圍有較大彈性。 下式^領域具通常知識者·知，電麵電鱗錢特性可以 i · dt 二 C, dv 因此’若電容402的電容值為c流 认 對電請恤船⑽物 200807843 VIN 了200807843 IX. Description of the invention: [Technical field of the invention] A power mode converter of a mode, especially an adjustment pulse wave omitting material control signal. The invention refers to a type that can operate on a pulse wave and can automatically follow an input voltage and an output voltage. The pulse width of the power converter. [Prior Art] = The electronic device's "I have a secret in the electric" is very important for the electric device (4).电源Power supply 凊 Refer to Figure 1, which is a schematic diagram of a conventional power converter. The power converter contacts are used to provide power to a load circuit 112, which includes a drive circuit 102, a power output circuit 1〇3, and a feedback circuit 1(1). The power output circuit 1〇3 includes transistors 1〇4, 1〇6 and an output inductor. The driving circuit is removed according to the feedback signal of the feedback circuit 110, and the transistor is turned on and off ‘ to control the output voltage ν〇υτ drawn by the wheel inductance. First, the drive circuit is turned off and the cell is turned on and the transistor is turned off. Then, the source of the transistor is turned on and out of the inductor 108, so that the output inductor 1〇8 stores energy. Then, the driving circuit 102 turns on the transistor 1〇4_ and turns on the transistor 〇1〇6, at which time the power supply stops inputting to the output inductor 108, thereby generating a current of opposite polarity to be conducted to the system ground via the transistor 106 6 200807843. . Therefore, the drive circuit 102 can control the output voltage v 〇 LrT of the output inductor 1 〇 g over the turn-on and turn-off times of the switching transistors 1〇4 and 1〇ό. Therefore, the electronic device can operate correctly through the power supply provided by the power converter. However, the concept of energy saving is becoming more and more important. It has become the goal of the industry to reduce the power consumption of the power supply while it is waiting. Conventional techniques have developed a number of methods for reducing the switching loss and the rated loss for many poles or without cakes. Common methods are pulse omitting mode _), burst mode (BurstMode), and non-conduction time modulation (〇ffTimeM〇duiati〇n). The technique of the pulse omitting mode is proposed by SGS_Thompson and Nati〇nal - (10)dU_, which determines whether to omit the switching pulse or not according to the load __ degree to achieve the purpose of reducing power loss. Please refer to Figure 2, which is a conceptual diagram of the pulse omitting mode. The pulse omission mode resident concept is to omit a part of the switching pulse when the system operates in a very light load or domain, and to switch the word of the low-voltage crystal to meet the light-low loss requirement. .* Therefore, the 'pulse@slight mode system' achieves a reduction in power conversion by reducing the switching of the transistor! i is the power consumption at the time of light load. The prior art has revealed a number of related, road-wood structures used to implement the pulse omitting mode. The conventional technique usually uses a fixed-inductance peak-test (CGnstantIndu_eakc_) _ 峰值 电源 ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ It is limited to a certain circumstance in this It's seven 'in order to avoid the output of the inductor in the pulse omitting mode. 200807843 For example, US Patent No. 5,745,352 "dc_to_dc c__ FuncUoning in a Pulse-skipping M〇de with Low P〇wer Conation an Inhlblt" uncovers a DC-to-DC converter that can operate in pulse-oval mode. It is a fixed-output inductor peak-shaped _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The voltage of the resistor is used to obtain the current information 'and the fixed voltage is used to control the peak current. When the output voltage is lower than the setting voltage, the transistor will be switched to input the current to the output inductor, accumulate the current and input (4). The disadvantage is that #operating at different input voltages and output voltages may cause the current of the output inductor in the pulse omitting mode to be larger than the current in the normal mode (ie, continuous conduction mode), so in order to avoid this, the output inductor The selection will be limited. In addition, U.S. Patent No. 6,661,679 "PWM C ller Having Adaptive Off-time Modulation for Power Savingj Turn-On Time Machine saves power supply wave width control (4). US Patent No. 661,679 pulse width modulation control € is the feedback voltage and input voltage of the first gamma load and converted into current, and then the current containing the information of the feedback dragon and the input voltage is used to adjust the material pass time. Therefore, the non-guidebook is the two. The function of the variable (reward voltage and wheel voltage), and the on-time is determined by the time of the fixed peak current, which is the same as the DC-to-DC converter of US Patent No. 5,745,352, and 8 200807843 Voltage C Continuous US _, _9 _Large ratio _, but not (4) and operation (4) and input rnnHll, f. Ayr" Whether the conduction time and non-conduction time in the continuous conduction mode (Continuo丨MGde, CCM) are related [invention] Operation in Pulse Wave Omissions Therefore, the main object of the present invention is to provide a mode power converter. •: The invention discloses that a pulse wave can be used to generate a power source when the light load system is used; and the source conversion benefit is used for = lightning: the power converter device includes a drive circuit, and the second=one feedback circuit And - pulse wave omission mode control circuit = used to illuminate the mode signal according to the - feedback signal and - pulse wave. The power output of the power supply in the power supply:: = according to the brake _ number, turn __ source to 贞 贞. The circuit circuit turns: to return a circuit according to one of the load circuits. The pulse wave omitting mode __ 接 == circuit, and according to the power generator control signal to the drive (10), adjusting the pulse omitting mode === _ the drive circuit is controlled to control the power wheel circuit Turning out: electric ^ 200807843 [Embodiment] Please refer to FIG. 3 'FIG. 3' is a schematic diagram of a power converter 3 可 operable in Pulse-skipping mode according to an embodiment of the present invention. . The power converter 3 is used to receive the power output from the power generator and convert it to an appropriate size and output it to a load circuit 304. The power converter 3A includes a driving circuit 306, a power output circuit, a feedback circuit 31A, and a pulse omitting mode control circuit. The power output circuit 〇8 preferably includes a plurality of transistors for switching the opening and closing of the transistor according to the output of the gate driving signal in the driving circuit to output a voltage of a specific magnitude to the load circuit. The feedback circuit 31 can generate a feedback signal to the driving circuit according to the load circuit 304 # feedback voltage. The pulse wave #, the air control circuit 312 can output a pulse wave omitting mode control signal to the driving circuit 306, and can input the voltage ν 〇υ τ according to the input voltage (4) output by the power source generator 3 〇 2 and the power output circuit 308. Adjust the pulse wave to omit the on-time of the mode control signal. Therefore, the driving circuit 3〇6 can control the opening and closing times of the transistors of the pulse-mode omni-directional circuit 3〇8 according to the pulse wave omitting mode outputted by the feedback tiger circuit and the omitting mode control circuit 312 outputted by the feedback circuit training device. To meet the low loss requirements at light loads. According to the electric pulse wave, the mode control circuit 312 outputs the voltage VOUT, and the voltage output circuit hall controls the driving circuit to control the on-time of the signal, and the gate drive signal of the pin. In this way, the pulse wave omits the output voltage of the output inductor of the power supply (four) way, and the current value of the output inductor of the continuous conduction mode is maintained proportional to the current value of the continuous conduction mode, so that the output of the pulse wave omitting mode does not occur. The electric scalar wave (Ripple) is larger than the case of operating in the continuous conduction mode. Therefore, the lion range of the output device in the present invention has greater flexibility than the conventional fixed output. Please refer to FIG. 4, and FIG. 4 is a schematic diagram of the pulse wave omitting mode control circuit 312 in FIG. The pulse omitting mode control circuit 312 includes a current source, a NMOS, a valley 402, a comparator 404, and an SR flip flop 406. The current source 400 can provide a current proportional to the input voltage according to the input voltage VIN output from the power generator 302. For example, by introducing the input voltage VIN into a resistor R, a current of a magnitude (VIN/R) can be generated. The current generated by the current source 4〇〇 charges the capacitor 4〇2, and the comparator 404 compares the voltage VP of the capacitor 402 with the DC information VOUTEQ of the voltage VOUT outputted by the power output circuit 3〇8, and compares The result is output to the SR flip-flop 406. The set terminal S of the SR flip-flop 406 is coupled to a clock generator (not shown in FIG. 4) for receiving a clock signal CLK, and the reset terminal R is coupled to the comparator 404. For receiving the comparison result of the comparator 404, the output terminal Q is coupled to the driving circuit 306 for outputting the pulse omitting mode control signal. For the operation of the pulse omitting mode control circuit 312, please refer to FIGS. 5 and 6. Fig. 5 is a SR flip-flop 406^^ truth table, and Fig. 6 is a waveform diagram of the pulse wave omitting mode control circuit 312. In Fig. 6, the DC signal CLK, the voltage VOUT output from the power supply output circuit 308, and the voltage VP of the capacitor 402 and the pulse omitting mode control signal PSM are displayed from top to bottom. First, when the pulse signal CLK: is triggered, the SR flip-flop 406 operates in the set state, and the current source 400 starts charging the capacitor 402 until the voltage VP of the capacitor 402 exceeds VOUTEQ, and the SR flip-flop 406 enters the reset state. Capacitor 402 begins to discharge to zeta potential. In short, the start of the pulse omitting mode control signal is triggered by the clock signal CLK, and its end position is related to whether the voltage VP exceeds VOUTEQ, that is, the pulse wave generated by the comparator 404 when the voltage VP is greater than VOUTEQ. , determines the pulse width of the pulse omitting mode control signal. When the input voltage VIN is changed, the output current (VIN/R) of the current source 4〇〇 is changed to I, and when the output voltage VOUT is changed, the triggering of the sr flip-flop 406 is reset = the time required is also not the same. Therefore, the pulse width of the pulse omitting mode (4) signal changes with the input VIN and 〇V〇UT. In this way, the peak current of the output inductor in the pulse-omitting mode will be maintained as the current value in the continuous conduction mode, and the current will be generated in the pulse-omitting mode = greater than the continuous conduction. The situation at the time of the mode makes the wheel power outlet have greater flexibility. The following formula ^ field has the general knowledge of the knowledge, the electric surface electric scale money characteristics can i · dt two C, dv therefore 'if the capacitor 402 capacitance value c cognition electric invitation ship (10) 200807843 VIN
Tpsm -C VOUT RC· VOUT ^ΥΪΝ~ (式1) ，此’脈波省略模式控制訊號的脈波寬度，即電容術 壓V〇UT所需的充電時間為Τ酸，是由VIN、V0UT、R ^ 疋莊而爾/vIN是連續導通模式時導糊4的比例。因此， C之值’使得進樣波省略模式時的TpSM ⑷舉嫩，可選擇^為^輯Tpsm -C VOUT RC· VOUT ^ΥΪΝ~ (Formula 1), the pulse width of the pulse wave omitting mode control signal, that is, the charging time required for the capacitance voltage V〇UT is tantal acid, which is VIN, VOUT, R ^ 疋 而 尔 / vIN is the ratio of the guide paste 4 in the continuous conduction mode. Therefore, the value of C makes TpSM (4) in the omitting mode of the injection wave, and can be selected as ^
TPSM I^D-Ton 2 2 其中’ VOUT/ν腳，1為單位時脈訊號CLK的時間。在此情形 下，即使種、VQUT改變時，TpsM也都會自動調整到τ〇Ν/2。 因此，藉由電源轉換器300，脈波省略模式控制訊號的脈波 寬度會隨著輸人電壓VIN與輸^電壓ν〇υτ岐變，則脈波省略 模式下輸itjf：感的峰值電流會與連續導賴式下的電流值維持一 定比例_係，科會發生脈波省略模式下輸料狀電流漣波 大於操作於賴導通模式時的情況，使得輸”感的選擇範圍有 較大彈性。 在本發明中’電源輸出電路308及回授電路31〇分別用來輸 出電壓及產生回授訊號，其實現方式可根據不同需求而改變。举 例來說，回授電路310可以包含一誤差放大器及一比較器，誤差 13 200807843 放大器可放大負載電路304的回授電壓與一參考電壓間的誤差， 以產生一誤差結果，而比較器則根據誤差結果與一預設波形間的 差異’調整回授訊號的工作週期（Duty Cycle)。另外，電源輸出 電路308可以如第1圖所示之電源輸出電路1〇3 一樣，包含有二 電晶體及一電感，由驅動電路308控制電晶體的開啟及關閉，以 調整電感所接收之電源。在此情形下，在脈波省略模式控制電路 312中’輸出電壓V0UT的直流資訊v〇UTEQ可透過一低通滤波 器由電源輸出電路3〇8的電晶體輸出端獲得，其優點為可從晶片 内部直接連接，不需要從外部的輸出端取出，以節省接腳數。當 然’低通濾波H不限於特定型式，只要能實現低職波即可。: 例來說’請參考第7圖，第7圖為-低通慮波器7〇〇之示意圖。 低通慮波器700透過-接收端7〇2接收電源輸出電路鄕的電晶 體所輸出的賴’經過電阻幻及電容C1、C2的低通滤波處 理後’由一輸出端704輸出至比較器4〇4。 綜上所述，透過本發明之脈波省略模式控制電路，脈波省略 模式控制訊_脈波寬度會隨著輸人Μ與輸出龍而自動調 整’則，波省略模式下輸出電感的峰值電❹與連續導通模式時 下的電w值維持—定比例的關係，而不會發生脈波省略模式下輸 出電感之電流連波大於操作於連續導通模式時時的情況，使得^ 出電感的選擇範圍有較大瘅性。· 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範 14 200807843 圍所做之均㈣化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖為一習知電源轉換器之示意圖。 第2圖為_省略模式之概念示意圖。 H圖為本㈣—實關可操作於脈波省略模式之電源轉換器 第4圖為第3圖中脈波省略模式控制電路之示意圖。 第5圖為-SR正反器之真值表。. 第6圖為第3圖中—脈波省略模式控制電路之相關波形示意圖。 第7圖為-低通慮波器之示意圖。 【主要元件符號說明】 100、300 112 102、 306 103、 308 110、310 312 104 ^ 106 108 電源轉換器 負載電路 驅動電路· 、 電源輸出電路 回授電路 脈波省略模式控制電路 電晶體 輪出電感 15 200807843 400 電流源 402、C卜 C2 電容 404 比較器 406 SR正反器 700 低通慮波器 702 接收端 704 輸出端 R1 ^ R2 電阻 CLK 時脈訊號 PSM 脈波省略模式控制訊號 VIN、VOUT 電壓 VOUTEQ 直流資訊. ..、 16TPSM I^D-Ton 2 2 where 'VOUT/ν pin, 1 is the time of unit clock signal CLK. In this case, even if the species and VQUT change, TpsM will automatically adjust to τ〇Ν/2. Therefore, with the power converter 300, the pulse width of the pulse omitting mode control signal is changed according to the input voltage VIN and the input voltage ν 〇υ τ, and the pulse current omitting mode is input to the itjf: the peak current of the sense Maintain a certain ratio with the current value under the continuous conduction mode. The system will generate a ripple in the pulse wave omitting mode, which is greater than the operation when the sigma conduction mode is used, so that the selection range of the transmission sensation has greater flexibility. In the present invention, the power output circuit 308 and the feedback circuit 31 are respectively used for outputting a voltage and generating a feedback signal, and the implementation manner thereof may be changed according to different requirements. For example, the feedback circuit 310 may include an error amplifier. And a comparator, error 13 200807843 The amplifier can amplify the error between the feedback voltage of the load circuit 304 and a reference voltage to generate an error result, and the comparator adjusts back according to the difference between the error result and a preset waveform. The duty cycle of the signal is provided. In addition, the power output circuit 308 can include the second transistor and the same as the power output circuit 1〇3 shown in FIG. Inductance, the driving circuit 308 controls the opening and closing of the transistor to adjust the power received by the inductor. In this case, the DC information v〇UTEQ of the output voltage VOUT can be transmitted through the pulse omitting mode control circuit 312. The pass filter is obtained by the transistor output terminal of the power output circuit 3〇8, and has the advantage that it can be directly connected from the inside of the chip without being taken out from the external output terminal to save the number of pins. Of course, the 'low pass filter H is not limited to For specific types, as long as the low-level wave can be realized: For example, 'Please refer to Figure 7, Figure 7 is a schematic diagram of the low-pass filter 7〇〇. Low-pass filter 700 through-receiver 7 〇2 The output of the transistor receiving the power output circuit 鄕 'after the low-pass filtering process of the resistor phantom and the capacitors C1 and C2' is outputted from an output terminal 704 to the comparator 4〇4. Invented pulse wave omitting mode control circuit, pulse wave omitting mode control signal _ pulse width will be automatically adjusted with input and output dragons, then peak output power and continuous conduction mode of the output inductor in wave omitting mode Electric w value dimension Maintaining a proportional relationship without causing the current-connected wave of the output inductor in the pulse-omitting mode to be larger than when operating in the continuous conduction mode, so that the selection range of the inductor is more flexible. It is only the preferred embodiment of the present invention, and all the modifications and modifications made in accordance with the patent application No. 14 200807843 of the present invention are within the scope of the present invention. [Simple Description of the Drawing] FIG. 1 is a Schematic diagram of the power converter. Fig. 2 is a conceptual diagram of the _ omitted mode. H is the current (4) - the power converter can be operated in the pulse omitting mode. Figure 4 is the pulse omitting mode control circuit in Fig. 3. Fig. 5 is a truth table of the -SR flip-flop. Fig. 6 is a schematic diagram of the relevant waveform of the pulse wave omitting mode control circuit in Fig. 3. Figure 7 is a schematic diagram of a low pass filter. [Main component symbol description] 100, 300 112 102, 306 103, 308 110, 310 312 104 ^ 106 108 Power converter load circuit drive circuit · Power supply output circuit feedback circuit pulse wave omission mode control circuit transistor wheel inductance 15 200807843 400 Current Source 402, C Bu C2 Capacitor 404 Comparator 406 SR Forwarder 700 Low Pass Filter 702 Receiver 704 Output R1 ^ R2 Resistor CLK Clock Signal PSM Pulse Wave Mode Control Signal VIN, VOUT Voltage VOUTEQ DC Information. .., 16