TW200807726A - Nonvolatile memory having modified channel region interface - Google Patents

Abstract

The technology relates to nonvolatile memory with a modified channel region interface, such as a raised source and drain or a recessed channel region.

Description

200807726

达达编号号: TW3135PA • IX. Invention Description: [References to Related Applications] The present invention claims the priority of the inventor of the United States Patent Application No. 60/806,840 filed on July 1, 2006. Recess-Channel Non-Volatile Memory Cell Structure, Manufacturing Methods and Operating Methods. [Technical Field of the Invention] The present invention relates to non- Volatile memory, and particularly non-volatile memory having a varying channel region interface, such as a lifted source and drain or a recessed channel region. [Prior Art] It is called EEPRQM and (4), and the electrical (4) memory structure can be programmed and erased. Unless it is purely recorded, it is purely used in various modernizations. A plurality of domain element ages are used for EEpR〇M and flash memory. When the size of the integrated circuit is reduced, the importance of the structure of the unit based on the capture dielectric layer is increasing, which is due to the simplification of the capability and process. Based on charge trapping = record: the meta-structure contains, for example, the industry called the smashing, the structure of the cage ^ by the negative charge is captured when the memory of the Zhao unit is limited to electricity 5 200807726,

A face 3 / several . . 'W3135PA • The threshold voltage of the body unit is reduced by removing the negative charge from the charge trapping layer / / 〇 The conventional non-volatile nitride cell structure is planar to oxidize A material-nitride-oxide structure is formed on the surface of the substrate. However, this planar structure has the ability to have a small size, a high stylization and erasing power, and a high sheet resistance value. This structure is described in ΥΕΗ, C·C· et al., ''PHINES: A new low-power stylized/erased, small-interval, single-cell dual-bit flash memory (PHINES: A Novel Low Power) Program/Erase, Small Pitch, 2-Bit per

Cell Flash Memory)", Electronic Devices Conference, 2002, IEDM Ό 2. Digest·International, 8-11, December 2002, pp. 931-934. Therefore, it is necessary to modify this conventional non-volatile nitride cell structure. a planar structure to address one or more of the above disadvantages.

The present invention is directed to a non-volatile memory having a varying channel region interface. X In accordance with a first aspect of the present invention, a non-volatile memory cell integrated circuit is provided that includes a charge trapping structure, source and gate regions, and a dielectric structure. The charge trapping structure stores charge to control one of the logic states stored by the non-volatile a memory cell. In various embodiments, the charge trapping structure stores one bit or multiple bits. The source region and the drain region are separated by a channel region which is part of a circuit that undergoes inversion to electrically connect the source and drain regions. Dielectric structure in the absence of a power 6 200807726

—s^a/u · TW3135PA 'The field is electrically isolated from the multiple parts of this circuit to overcome the dielectric structure. The dielectric structure is at least partially located between the charge trapping structure and the channel region and at least partially between the charge trapping structure and a gate voltage source. An interface separates a portion of the one or more dielectric structures from the channel region. One of the first ends of the interface ends in an intermediate portion of one of the source regions, and one of the second ends of the interface ends in an intermediate portion of one of the regions. To implement this interface, an embodiment lifts the source and drain regions away from one of the non-volatile memory cell integrated circuits. In another embodiment, the channel region is recessed into one of the substrates of the non-volatile memory cell integrated circuit. According to a second aspect of the present invention, a method of fabricating a non-volatile memory cell integrated circuit includes the steps of: forming a charge trapping structure to store charge to control storage by a non-volatile memory cell integrated circuit a logic state, wherein in various embodiments, the charge trapping structure stores one bit or multiple bits; forming a source region and a drain region separated by a channel region; and forming a dielectric structure, at least a portion thereof Located between the charge trapping structure and the channel region, and at least partially between the charge trapping structure and a gate voltage source. An interface separates one of the one or more dielectric structures from the channel region, and one of the first ends of the interface ends in an intermediate portion of the source region, and the second end of the interface ends in a middle portion of the drain region . In order to implement this interface, an embodiment adds a layer of material to the integrated body 7 200807726

Second violation · a / ΰ · TW3135PA . Road source (four) and the bungee area lifted off a single substrate of non-volatile memory. Another embodiment forms a trench in the substrate to form a cut-and-trap structure and a dielectric structure in the trench. In the other aspects of the present invention, the electro-radio structure is a nanocrystal structure rather than a charge trapping structure. In other embodiments of the handle, the dielectric structure at least partially located between the channel regions of the charge trapping structure comprises, for example, a germanium structure disclosed herein. - To make the above description of the present invention more apparent, the following is a special The preferred embodiment, together with the drawings, is described in detail as follows: [Embodiment] FIG. 1 is a schematic diagram of a non-volatile memory unit in a source region and a 汲There is a recessed channel between the pole regions. Gate 102, in most embodiments a partial word line, has a gate voltage Vg. In some embodiments, the gate structure comprises a material, The function is greater than the intrinsic work function of the N-type ,, or greater than about 4.1 eV, and preferably greater than about 4·25 ev, such as greater than about 5 eV. Representative gate materials include P-type polycrystalline germanium, titanium nitride, and platinum. And other high work function metals and materials. Other materials having a relatively high work function suitable for embodiments of the present invention include: metals including, but not limited to, ruthenium (RU), ruthenium (lr), nickel (Ni) and (Co); metal alloy, including but not limited Ru - Ni and Ti - titanium; metal nitride; and metal oxides, including but not limited to ruthenium oxide (Ru〇2) a high work function gate material generating electrode 8 than the typical n-type polysilicon gate.

200807726: TW3135PA has a higher injection tunneling barrier for electron tunneling. The right-hand-N-type polycrystalline (four)-pole injection barrier is in the outer dielectric layer. The embodiment of the present invention uses the gate for the gate and the outer gate. Thus ' has a human barrier, which is above about 315 e: the material is preferably above about 4 eV. With respect to a polycrystalline slab gate having a thickness of about 3.4 eV, the barrier of the injection is about the N-type poly' e of the p-type dielectric layer containing the dioxide of the outer dielectric layer, and has a lifetime The threshold of the convergence unit is reduced: about;: the unit's dielectric structure 104 is located between the idle poles 1〇2. The other-dielectric structure 108 is stored in the system, . Between 106 m. Representative Jie Lei _ ^ electric storage structure h) 6 and channel area sound _ material family contains about 2 to 1G too half a degree of reduction and nitrogen oxidation dream master 1G Naiqiu 'its contain Hua 20;);, he reads the logic state of the high dielectric constant charge storage structure 106 storage unit. The first 41 is made of non-volatile memory, such as polycrystalline 矽 J J J 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存& ώ The charge storage structure that spreads the stored charge throughout the electricity and nanocrystals is the charge-trapping charge storage, which calls for a newer implementation of the material, which will save the charge. The position of the structure L initiates the logical state of the structure at different locations. The representative charge trap is from the third to the ninth of the thickness of the nitride. ~ and the pole voltage v °, there is - source voltage Vs, and the drain region (1) has a middle portion of the Λ, the polar region (10) and the 〉 and the polar region 112 in most of the embodiment element lines, and is characterized by a junction depth 12〇. Body Area 200807726 Erda HV3135PA 122 is, in most embodiments, a substrate or well and has a body voltage vb. The channel 114 is electrically connected to the source 110 and the drain 112 in response to a suitable biasing configuration applied to the gate 1, 2, and 11 of the body 122. The upper edge of the source and drain regions 116 is higher than the interface 118 between the channel 114 and the dielectric structure 108. However, the interface 118 between the channel 114 and the dielectric structure 108 is maintained above the lower edge of the source and drain regions. Thus, the interface 118 between the channel 114 and the dielectric structure 〇8 terminates in the middle of the source region 110 and the drain region 112. The source region no and the upper edge of the drain region 112 are aligned with the upper edge of the body region 122. Thus, the non-volatile memory cell of the first diagram is an embodiment of a recessed channel. Figure 2 is a schematic illustration of a non-volatile memory cell having a source region and a germanium region lifted off the semiconductor substrate. The non-volatile memory cells of Figures 1 and 2 are substantially similar. However, the source region 210 and the upper edge of the drain region 212 are located above the upper edge of the body region 122. Therefore, the non-volatile memory cell of Fig. 2 is an example of the source and > and the pole of the lift. Between channel 214 and dielectric structure 208; 1 face 218 still ends in the middle region of source region 21 and region 212. The source region 210 and the polar region 212 are characterized by a junction depth 220 〇 Figure 3A is a schematic diagram of electrons being injected from the gate to the charge storage structure in a non-volatile memory cell having a recessed channel. The gate region 302 has a gate voltage Vg of -10V. Source area 304 with 10

200807726 A beta class 7; child. TW3135PA has ιον or floating source voltage Vs. The drain region 3〇6 has a 〇ν or floating drain voltage Vd. The body region has a body voltage vb of 1 GV. The 3rd element of the sexual memory has a non-volatile map of the source and the polar regions of the lift. The schematic of the 1st pole to the charge storage structure in Fig. 3 is similar to the 3rd 151. The fourth diagram is a schematic diagram of the non-volatile memory cell gate region 402 in which the electrons are injected from the substrate in the gas, the Antograph, with a charge storage structure. There is a 0V or floating green = the idle voltage Vg. The source region 404 has a active drain voltage Vd. Too much pressure Vs. The drain region 406 has -ιόν or float. FIG. 4B is a body voltage Vb having _10 V in the region. In the memory unit, the non-volatile map of the source and bungee regions of the lift. The figure is intended to be from the substrate, the main entry into the charge storage structure. Figure 5A is a diagram similar to the first diagram. Medium-band (band-to-ban) non-volatile memory cell diagram. The hot-electron injection into the charge storage structure of the schematic gate region 502 has a source of -5V. The drain voltage Vg°P+ type source region 504 has a drain voltage of ~1 (grave/.1) + type drain region 506 has 〇乂 or float. FIG. 5B is ^(4)_body voltage with 〇V Vb. In the memory unit, you have a non-volatile map of the source and drain regions of the lift. The schematic of the partial/hot electron injection into the charge storage structure in Fig. 5B is = set /糸 is similar to the first figure. The schematic diagram of the channel's hot electron injection/non-volatile memory cell to the charge storage structure.

200807726 One lung m · TWj135PA The gate region 602 has a gate voltage of 10V. The Vg^+ type source region 6〇4 has a source voltage Vs of -5V. The n + -type drain region 606 has a drain voltage of 〇V. The Vd-type body region 608 has a body voltage vb of 〇v. Fig. 6B is a schematic view showing the injection of channel hot electrons into the charge storage structure in the non-volatile memory single τ ο having the source region and the drain region of the lift. The bias configuration of Figure 0B is similar to Figure 6A. A 7A is a schematic diagram of the substrate's hot electron injection into the charge storage structure in a non-volatile memory cell having a recessed channel. The gate region 702 has a gate voltage of 10V vgcn+s. The source region 7〇4 has a source voltage Vs of 0V. The type of drain region 7〇6 has a drain voltage Vd of germanium. The N-type body region 708 has a body voltage vb of -6V. The p-type well region 710 has a well voltage Vw of ·5 ν. The source region and the immersion zone are in the well zone 710, and the well zone 71 is located in the body zone 7〇8. Figure 7B is a schematic diagram of the substrate's thermoelectron injection into the charge storage structure in a non-volatile = memory single it with raised source and non-polar regions. The bias configuration of Figure 7B is similar to Figure 7a. The non-volatile memory cell of the recessed channel is electrically shunted and the gate gate is injected into the charge storage structure. There is ^8〇2 with a voltage Vg of 1〇V. The source region 804 has a source voltage VS of ':. And the polar region 806 has a V or a floating voltage W. The body region 808 has a body voltage Vb of . The π map is a non-volatile swallowing unit in the source region and the non-polar region of the lift, the hole is connected from the gate, and the FI ^ δΐ5 ^ ^ gate, the main input to the electrical storage structure The bias configuration of Figure 8 is similar to Figure 8-8. 12 200807726

The f 9A diagram in the TW3135PA is a schematic diagram of a hole injected into a charge storage structure from a substrate in a non-volatile memory cell with a recessed channel. The gate region 902 has a gate voltage % of -i〇v. The source region $(10) has a source voltage VS of 10V or floating. The No. 9〇6 has i〇v# moving and the pole voltage Vd. The body region 90S has a body voltage Vb of 1 GV. Fig. 9B is a sound diagram of a non-volatile I-hidden unit of the lifted source region and the drain region from the substrate to the charge storage structure. The bias configuration of Figure 9B is similar to Figure 9A. Figure 10A is a schematic illustration of the inter-band thermoelectric injection into a charge storage structure in a non-volatile memory cell having a recessed channel. The gate region has a tearing gate voltage... The source region has a source voltage Vs of 5V. The η+ type bungee region has a (b) or eccentric buckling voltage Vd. ? The body body region 1〇〇8 has a 〇ν voltage Vb. The first picture shows the purpose of the thermoelectric hole in the source zone and the bungee zone with the lifting source. The bias configuration of the first phase is similar to that of the first figure. Figure 11A is a schematic diagram of a non-volatile memory single 70-channel thermoelectric hole having a recessed channel implanted into the charge storage structure. 11〇4 1102 has a gate voltage Vg of . The p+ type source region brain has a source voltage Vs of 0V. P+ type bungee area secret and ^ voltage type body area! (10) The body voltage % with GV. (4) 2: For the cookware: the source of the lift and the non-swattering of the non-polar zone, the introduction of the 'hot spring hole' into the charge storage structure 13 200807726

二适编沈·TW3135PA '" Figure 1: Figure 2:: is similar to the first, elementary, substrate thermoelectric ~==== memory Zhao single gate area 1202 i have him, exhaust,,, ° Do not think about it. U04 has a gate dust % of 0V source. The P+ type source region has a drain voltage type. The second Vs ° P+ type drain region 1 has a 〇v N type well region 1210 having 5V: 1208 having a body voltage Vb of 6V. Zone 1206 is located in the well zone 12] Λ \ well voltage VW. Source area 1 and bungee. In the middle, the well region 1210 is located in the body region 1208. The source memory has a non-swing of the source region and the non-polar region. Figure 12B, d::, into the charge storage structure. Figure 13A is at 1 = continued to appear in the first figure. In the yuan, it is used to read the (4) picture of the non-volatile memory one-way read operation that is stored in the same way. One of the right-handed data of the memory structure is the reverse gate region 1302 I right", 1304 has the gate of the source of (10) M VgQn + type source region has no pole (four) Vd. The P-type VS ° n+-type non-polar region (10) has 〇v The 133th figure has the reverse reading operation of the source region and the non-volatile data of the rising source memory cell in the present invention. The right side of the charge storage structure is similar to the 13th map. π 忍 图. The 13th 之 之 么 配置 配置 配置 配置 第 第 第 第 第 第 第 第 第 第 第 ι ι ι ι ι ι ι

-TW3135PA 200807726 Schematic diagram of the operation. The gate region 1402 has a source voltage of 0 V and a voltage of 0 V. η+ source region

The drain voltage Vc^P type 俨n+ type and the pole region 1406 have 1,5V (10) system 1408 has a body voltage of 0V. The non-swing of the 15 liter source region and the bungee region in the memory device unit The reverse reading operation of the data is based on the soil sub-bit, and the left side of the storage structure is similar to the 14th map. V thinking. The bias configuration of the 14th diagram is a non-volatile memory single reading operation of the two recessed channels. One of the data on the right side of the structure is the gate region 1502 1 right

Let the gate voltage % of the source voltage with a floating source. The immersion source region of the metering source region (4) (9) has 2V, and the 15B diagram is the right and female disk/, and has a body voltage Vb of 〇V. Memory cell unit, with: + liter source and the non-volatile area of the bungee area - read the right side of the load storage structure similar to Figure 15A. /, thinking. The bias configuration of Fig. 15B is shown in Fig. 16A as having a concave enthalpy for storing the charge storage and light sifting. Inter-band reading of the data on the left 1604 = with < gate voltage source region of the pole 1 ^ VS. Π+魏极区秘 has a floating ... £ Vd °P type body region 1608 has a body voltage Vb of 0V. 15 200807726

Erda "Only *rwsmPA brother 16B picture is in the presentation memory unit, using the 2 Λ, polar region and the bungee region of the non-swept data between the reading operation of the sound sub-bit = electricity The left side of the structure is similar to Figure 16A. ~θ蒂16B diagram of the bias configuration class due to, 5 vertical and transverse electric field, · ^ Niang Beiyi also recall the body unit structure of the inter-electron electricity "quote" non-volatile record of the specific part of the charge Storage is accurate; 1 degree determines the large inter-band current of the charge storage structure. A straight and transverse electric field causes 1 , and the slant bias configuration is applied to various ends of the intermediate production 2 and 2 bands are bent enough to be in non-volatile memory The body unit structure ^,, S motor, while holding the %* bit line between the non-volatile memory unit nodes to be pure, so that stylized or smeared material will be generated. In the example of bias configuration, The non-volatile memory cell structure is opposite = the active source region or the non-polar region and the body region are reversely biased to produce a reverse bias junction. In addition, the voltage of the gate structure causes these bands to bend enough to cause the band Inter-tunneling is produced via a non-volatile memory cell structure, in which: "a non-volatile memory cell structure node (in most embodiments, a source region or a drain region) has a high doping concentration. Where the structure node has a production The high charge density of the space charge region and the voltage change of the space charge region over a short distance contribute to the generation of an irritating band of electrons in the valence band on the side of the junction of the reverse bias. The gap of ', traverses to the conduction on the other side of the junction of the reverse bias and drifts down to the potential hill, deeper into the N-type node of the junction of the reverse bias. Similarly The hole drifts over the potential energy hill, away from the N-type node of the junction of the reverse bias, and faces the junction of the reverse bias p 200807726

Sanda number: TW3135PA ‘type node. The voltage in the gate region controls the voltage at the junction of the reverse bias voltages near the charge storage structure. When the voltage of the gate structure becomes more negative, the voltage at the portion of the junction of the reverse bias located near the charge storage structure becomes more negative, resulting in a deeper band bend in the diode structure. As a result of at least some of the following combinations of (1) and (2), more current between the bands will flow: (1) the occupied electron energy level on one side of the bending energy band and the other side of the bending energy band The increasing overlap between the unoccupied electron energy levels; and (2) the narrower barrier width between the occupied electron energy level and the unoccupied electron energy level (Sze, Physics of Semiconductor Devices, 1981) The net negative or net positive charge stored on the charge storage structure further affects the band curvature. According to Gauss's law, when the junction of the negative voltage and the reverse bias is applied to the gate region, the stronger electric field is connected by the reverse bias of the portion of the charge storage structure having a relatively high net negative charge. Partial experience. Similarly, when a positive voltage is applied to the gate region with respect to the reverse bias, the stronger electric field is the portion of the junction of the reverse bias that is close to the portion of the charge storage structure having a relatively high net positive charge. Experienced. The different bias configurations for reading and the biasing configuration for stylization and erasing show a careful balance. With respect to reading, the potential difference between the junction nodes of the reverse bias should not cause a substantial number of charge carriers to pass through a dielectric material to the charge storage structure and affect the charge storage state (ie, the programmed logic level). . In contrast, about stylization and erasure, at 17 200807726

Erda number: TW3135PA * The potential difference between the junction nodes of the reverse bias is sufficient to cause the substantial number of carriers to pass through a dielectric material and affect the charge storage state by inter-band hot carrier injection. Figure 17 is a manufacturing flow diagram of a non-volatile memory cell array having a recessed channel showing various possible combinations of process steps of Figures 19-23. Figure 17 discloses the following combinations of process flows: Figures 19 and 22; Figures 19 and 23; Figures 20 and 22; Figures 20 and 23; Figures 21 and 22; and Figures 21 and 23. These combinations are accompanied by backend processing. 18A and 18B are manufacturing flow diagrams of a non-volatile memory cell array having lifted source and drain regions. Figure 18A is a manufacturing flow diagram of a NOR non-volatile memory cell array having one of the source and drain regions of the lift, showing various possible combinations of the process steps of Figures 24-27. Figure 18A discloses the following combination of process flows: Figures 24, 25 and 27; and Figures 24, 26 and 27. These combinations are accompanied by backend processing. Figure 18B is a manufacturing flow diagram of a NAND non-volatile memory cell array having one of the source and drain regions of the lift, showing various possible combinations of the process steps of Figures 28-30. Figure 18B discloses the following combination of process flows: Figures 28 and 29; and Figures 28 and 30. These combinations are accompanied by backend processing. 19A to 19C are process steps for forming a groove in a non-volatile memory cell having a grooved channel before the 22nd or 23rd. In Figure 19A, oxide 1910 is deposited on the base 200807726

Two feed muscles · FW3135PA board 1900. The photoresist is deposited and patterned, and the patterned photoresist is used to remove portions of the oxide in accordance with the photoresist pattern. In Figure 19B, the residual photoresist 1922 protects the residual oxide 1912. The remaining photoresist is removed and the substrate not covered by the oxide is etched. In Figure 19C, trench 1930 is etched into substrate 1900 that is not covered by germanide 1912. 20A to 20E are process steps for reducing the length of a gate before forming a trench in the non-volatile memory cell before the 22nd or 23rd. 20A to 20E are process steps for reducing the length of a gate before forming a trench in a non-volatile memory cell before the 22nd or 23rd. Figures 20A through 20C are similar to Figures 19A through 19C. In Fig. 20D, a spacer 2040 is deposited into the trench leaving the next smaller trench 1932. In Fig. 20E, the portion of the spacer next to the bottom of the groove is engraved by the surname, leaving the spacer 2042. This reduction in gate length can result in a smaller gate length than in Figure 19. 21A to 21E are process steps for expanding a gate length before forming a trench in the non-volatile memory cell before the 22nd or 23rd. Figures 21A through 21B are similar to Figures 19A through 19B. In Figure 21C, the residual patterned photoresist is removed to expose the patterned emulsion 1912. In Figure 21D, the patterned oxide is etched leaving a smaller patterned oxide 2112. In Fig. 21E, the trench 2132 is etched into the substrate 1900 which is not covered by the oxide 2112. This gate length scaling will result in a longer gate length than in Figure 19. 19 200807726

Sanda number: TW3135PA. From 2nd to 22th, the system is the process step after the 19th, 2G or 21th drawing to form the -N0R non-volatile memory cell array, each ray memory material The m-channel is such that each non-volatile memory cell has a recessed channel. In Fig. 22a, a dielectric material such as a germanium layer and a charge storage structure 225 are formed in the trench, thereby leaving a smaller trench 2232. In the second order, the deposition example ^ polycrystalline stone etched gate material 2260. In Fig. 22C, the closed-pole material is surnamed so that the lower gate material 2262 remains inside the trench. In the figure, a dielectric material 227 such as SiN is deposited on the idler material. In Fig. 22E, the dielectric material is engraved and the remaining dielectric material 2272 is left inside the trench. In Figure 22F, the residual patterned oxide is removed. At this point, the stack of gate material 2262 and oxide 2272 rises above the surface of the substrate. In Figure 22, ion implantation forms source region 2280 and drain region 2282. In Fig. 22H, an oxide 229 例如 such as HDP oxide is deposited. In Fig. 221, the excess oxide covering the oxide 2272 is removed, for example, by CMP, dip-back or etch back. In Figure 22J, oxide 2272 is removed. In Figure 22K, an additional gate material is deposited to form a gate region 2264. The 23rd to 23rd graphs are the steps for forming the NAND non-volatile memory cell array at the end of the 19th, 20th or 21st, and each NAND non-volatile memory cell is located in a trench. In order to have each of the non-volatile memory cells have a concave channel. In Fig. 23A, a dielectric material such as a germanium layer and a charge storage structure 225 are formed in the trenches, thereby leaving the smaller trenches 2232. In the 23rd Β ,, Shen 20 200807726

A dwto/u . FW3135PA • A gate material such as polysilicon 2260. In Fig. 23C, the excess gate material is removed, for example, by CMp, thereby exposing the 0N layer. In the 23D image, the residual patterned halide is removed. At this point, the gate material 2262 rises above the surface of the substrate. In Fig. 23E, ion implantation forms source region 2380 and drain region 2382. Figures 24A through 24D are the steps of the pre-fabrication process prior to Figure 25 or 26 for forming the lifted source and drain regions of one of the non-volatile memory cells in an N?R array. In Fig. 24A, a dielectric material such as a germanium layer and a charge storage structure 241 are deposited on the substrate 2400. In Fig. 24B, a gate material such as polysilicon is deposited, for example, an oxide material of SiN is deposited on the gate material to form a photolithographic structure, and a stack of SiN 2430, polysilicon 2420 and 0N0 2412 remains. In Fig. 24c, a spacer 244 is formed. In Fig. 24D, the spacer is etched while the lower spacer sidewall 2442 remains. The 25th to 25th drawings are the steps after the 24th and 27th, which use the epitaxial enthalpy to form a N 〇 R array = one of the non-volatile memory cells. Source area and bungee area. In Fig. 25A, an epitaxial 矽 255 沉积 is deposited. In Fig. 25B, ion implantation forms source region 2560 and drain region 2562. 26A to 26C are process steps after the 24th and before the 27th, which use polysilicon to form the lift source region of the non-volatile Z memory cell in an N〇R array. Bungee area. In Figure 26A, polycrystalline germanium 2650 is deposited. In Figure 26B, this multi-turn is etched back to leave polysilicon 2652. In Figure 26C, ion implantation is performed = 21 200807726

Sanda number: TW3135PA * Polar zone 2660 and nourishing zone 2662. 27A through 27D are process steps before the 25th or 26th drawing to form a NOR non-volatile memory cell array, each NOR non-volatile memory cell having a source region and a lift Polar zone. In Fig. 27A, a dielectric material such as HDP oxide is deposited to cover the structure including the spacer sidewalls and oxide 2430. In Figure 27B, the excess oxide covering the oxide 2430 is removed, e.g., by CMP, dip-back, or back-to-back, while the remaining oxide 2772 surrounds the sidewalls of the spacer. In Figure 27C, oxide 2430 is removed. In Figure 27D, additional gate material is deposited to form gate region 2722. 28A to 28D are process steps starting before the 29th or 30th drawing to form a NAND non-volatile memory cell array, each NAND non-volatile memory cell having a source region and a lift Polar zone. In Fig. 28A, a dielectric material such as a germanium layer and a charge retention structure 2810 are deposited on the substrate 2800. In Fig. 28, a gate material such as a polycrystalline stone is deposited to form a photolithographic structure, and a stack of polycrystalline spine 2820 and ΟΝΟ 2812 remains. In Fig. 28C, a spacer 2840 is formed. In Figure 28D, the spacer is engraved, and the remaining spacer sidewalls 2842 〇 29th to 29th are the process steps after the 28th graph, which uses epitaxial germanium to form a NAND non-volatile memory. The cell array, each NAND non-volatile memory cell has a raised source region and a non-polar region. In Figure 29A, epitaxy is deposited at 2950. In the FIG. 29B diagram, the ion implantation method forms the source region 2960 and the non-polar region 2962. 22 200807726

2 违 2 2 / ΰ · TW3135PA The 30th to 30th drawings are the process steps after the 28th figure, which uses polysilicon to form a NAND non-volatile memory cell array, each NAND non-volatile memory cell It has a source area for lifting and > and a polar region. The 30th to 30thth drawings are the process steps after the 24th and the 27th, which use polysilicon to form the source region of one of the non-volatile memory cells in an N〇R array. With the bungee area. In Fig. 30A, polycrystalline germanium 3050 is deposited. In Figure 30B, the last name of the polycrystalline stone is left to leave the polycrystalline stone eve 3052. In Fig. 30C, the ion implantation method forms source region 3060 and drain region 3062. The 31st is a block diagram of a non-volatile memory volume circuit having an exemplary channel region as disclosed herein. The integrated circuit 3150 includes a memory array 3100 of a non-volatile memory unit located on a semiconductor substrate. Each of the memory cells of array 3100 has a varying channel region interface, such as a recessed channel region, or a raised source region and a drain region. The memory cells of array 3100 may be individual cells' interconnected in an array or interconnected into multiple arrays. Column decoder 3101 is coupled to a plurality of word lines 31〇2 that are arranged along the array of memory arrays 3100. Row decoder 3103 is coupled to a plurality of bit lines 3104 that are arranged along the line of memory array 31. The address on the bus bar 31〇5 is supplied to the row decoder 3103 and the column decoder 31〇1. The sense amplifier and data input structure 3106 is coupled to the row decoder 3103 via data bus 31〇7. The data is supplied to the data in block 3106 via the data input line 311, from the input/output port on the integrated circuit 3150, or from other sources internal or external to the integrated circuit 315A.

Sanda number: TW3135PA into the structure. The data is supplied from the sense amplifiers on block 31〇6 to the input/output transistors on integrated circuit 315 via data output line 3115, or to other data objects internal or external to integrated circuit 3150. A bias configuration state machine 3109 controls the application of the bias configuration supply voltage 31〇8 (e.g., erase confirmation and stylized verify voltage) and the configuration for programming, erasing, and reading the memory cells. Figure 32 is a schematic illustration of a non-volatile memory cell having a recessed channel between the source and drain regions, whereby the lower dielectric structure has a three-layered germanium structure. This structure is similar to the non-volatile memory cell of the figure, but the dielectric structure 1〇8 (between the charge storage structure 1〇8 and the channel region 1H) is replaced by the three-layer thin structure 32〇8. The 〇N〇 structure 3208 has a small hole with a barrier stop, such as less than or equal to about 4·5 eV, or preferably less than or equal to about ι·9 eV. The approximate thickness range of the ΟΝΟ structure 3208 is as follows. Regarding the lower oxide: < 2 angstroms, 5-20 angstroms, or < 15 angstroms. Regarding the intermediate nitride: < 20 angstroms or 1 〇 -2 angstroms. Regarding the upper oxide: < 20 angstroms or 15-20 angstroms. Some embodiments of the memory cell of Figure 32 are represented by SONONOS or bandgap engineered (BE)-SONOS. Additional details of various embodiments of the three-layer thin 〇ν〇 纟士构3208 are disclosed in U.S. Patent Application Serial No. 11/324,540, the disclosure of which is incorporated herein by reference. Figure 33 is a schematic illustration of a non-volatile memory cell having a source region and region lifted off the semiconductor substrate such that the lower dielectric structure has a three-layered germanium structure 3208. In summary, although the present invention has been disclosed above in a preferred embodiment, 24 200807726

—·^/ivrom · TWj135PA - It is not intended to limit the invention. It will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims. 25 200807726

—:3⁄4 纲 m · TW3135PA ^ [Simple diagram of the diagram] Figure 1 is a schematic diagram of a non-volatile memory unit with a concave channel between the source and drain regions. . Figure 2 is a schematic illustration of a non-volatile memory cell having a source region and a drain region lifted off the semiconductor substrate. Figure 3A is a schematic illustration of the injection of electrons from a gate into a charge storage structure in a non-volatile memory cell having a recessed channel. Figure 3B is a schematic illustration of the injection of electrons from a gate into a charge storage structure in a non-volatile memory cell having raised source and drain regions. Figure 4A is a schematic illustration of the injection of electrons from a substrate into a charge storage structure in a non-volatile memory cell having a recessed channel. Figure 4B is a schematic illustration of the injection of electrons from a substrate into a charge storage structure in a non-volatile memory cell having lifted source and drain regions. Figure 5A is a schematic illustration of the injection of hot electrons between the strips into the charge storage structure in a non-volatile memory cell having recessed channels. Figure 5B is a diagram showing the injection of hot electrons into the charge storage structure between the non-volatile memory cells having the raised source and drain regions. Figure 6A shows the non-volatile in the recessed channel. In the memory cell, a schematic diagram of channel hot electron injection into the charge storage structure. Figure 6B is an illustration of the channel hot electron injection into the charge storage structure in a non-volatile memory cell having a source region and a drain region of lift 26 200807726

—^E/iywjj/yu * TW3135PA A picture. Figure 7A is a schematic diagram of the substrate's hot electron injection into the charge storage structure in a non-volatile memory cell having a recessed channel. Fig. 7B is a schematic view showing the injection of hot electrons into the charge storage structure of the substrate in the non-volatile memory cell having the lifted source region and the drain region. Figure 8A is a schematic illustration of the injection of a hole from a gate to a charge storage structure in a non-volatile memory cell having a recessed channel. Figure 8B is a schematic illustration of the injection of a hole from a gate into a charge storage structure in a non-volatile memory cell having a lifted source region and a drain region. Figure 9A is a schematic illustration of the injection of a hole from a substrate into a charge storage structure in a non-volatile memory cell having a recessed channel. Figure 9B is a schematic illustration of the injection of a hole from a substrate into a charge storage structure in a non-volatile memory cell having a lifted source region and a drain region. Figure 10A is a schematic illustration of the injection of inter-band thermoelectric holes into a charge storage structure in a non-volatile memory cell having recessed channels. Fig. 10B is an illustration of the injection of inter-band thermoelectric holes into a charge storage structure in a non-volatile memory cell having a raised source region and a drain region. Figure 11A is a schematic illustration of the injection of channel thermowells into a charge storage structure in a non-volatile memory cell having recessed channels. Figure 11B shows the 诵, 刼+, and 音图 in the non-volatile 27 200807726 Sanda number: TW3135PA hair memory unit with lift source and bungee regions. I", the hole of the hole> is shown in Fig. 12A of the charge storage structure. The non-volatile hole with the concave channel is injected into the charge storage structure. Non-swinging with the bungee zone. The injection of the substrate thermoelectric hole into the charge storage structure - by the Tiantian 13A* system for the non-volatile eating (four)--with the concave human channel for reading and storing the charge Schematic diagram of the early reading operation of the storage structure. One of the reverse readings of the magical scorpion is the reverse reading operation of the non-swing data of the source region and the bungee region. The schematic diagram of the non-volatile memory single-fetch operation for storing the channel on the right side of the structure. The reverse reading of the data on the left side of the storage structure is in the case of a lifting memory unit. The 15th image of the reverse reading operation of the non-volatile data of the source region and the drain region of the gate is on the left side of the charge storage structure, and is stored in the charge. Schematic diagram of a single-cell read operation of a non-volatile memory. σ: sub, The right side of the data area of the first configuration ° i5B FIG lifting system as having recurrent memory unit Yin, ^ with no non-polar region and the region on the right to play V Unpickling charge storage structures 28,200,807,726

- Heart - TW3135PA • A schematic of the inter-band read operation. Figure 16A is a schematic illustration of an inter-band read operation for storing data located to the left of the charge storage structure in a non-volatile memory cell having a recessed channel. Figure 16B is a schematic illustration of inter-band read operations for storing data located on the left side of the charge storage structure in a non-volatile memory cell having raised source and non-polar regions. Figure 17 is a manufacturing flow diagram of a non-volatile memory cell array having a recessed channel showing various possible combinations of process steps of Figures 19-23. Figure 18A is a manufacturing flow diagram of a NOR non-volatile memory cell array having one of the source and drain regions of the lift, showing various possible combinations of the process steps of Figures 24-27. Figure 18B is a manufacturing flow diagram of a NAND non-volatile memory cell array having one of the source and drain regions of the lift, showing various possible combinations of the process steps of Figures 28-30. 19A to 19C are process steps for forming a trench in a non-volatile memory cell having a recessed channel before the 22nd or 23rd. 20A to 20E are process steps for reducing the length of a gate before forming a trench in the non-volatile memory cell before the 22nd or 23rd. 21A to 21E are diagrams for expanding a gate length before forming a trench in a non-volatile memory cell before the 22nd or 23rd graph.

The second process is a/π · rW3135PA process steps. 22A to 22K are process steps after the 19th, 2nd, or 21th drawing, for forming a non-volatile memory cell array, each NOR non-volatile memory (four) cell is located in the trench, So that each non-volatile memory cell has a recessed channel. 23A to 23E are the end of the process of the 19th, 2nd or 21th process. The process step 'for forming NAND _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ So that each non-volatile memory cell has a recessed channel. Figure 24A to 24D Figure #A in the complex? S bucket, or m mouth, you Feng Xiaodi 25 or 26 map before the start of the process steps, used to form a NOR array ^ ^ 一 一 ^, flat correction T one of the non-volatile memory early rise of the source Polar zone and bungee zone. The 25th to 25th map of Yidi is the process step after the 帛24 map and before the 27th graph, which makes the sound to form a non-volatile nucleus in the -ν〇 Polar zone. The 26th to 26th drawings are after the 24th figure and the end of the process (4), which makes the good crystal formation in the source area of the volatility memory unit. Polar zone. Step scale, used to form - dirty non-volatile upper bundle = N〇R, hair (four) (four) single conversion forest rights = ^ 28A to 28D diagram is in the 29th or 3rd cabinet, the process steps to form a _ Non-volatile memory begins with J NAND non-volatile memory cells with 30 200807726TW3 dirty regions. 29A to 29B are process steps after the 28th drawing, which use epitaxial germanium to form a NAND non-volatile memory cell array, each NAND non-volatile memory cell having a source of lift District and bungee area. 30A to 30C are process steps after the 28th drawing, which use polysilicon to form a NAND non-volatile memory cell array. Each NAND scaly memory fresh element has a source region for lifting and Bungee area. Figure 31 is a block diagram of a non-volatile memory volume circuit having an exemplary interface of the varying channel region as disclosed herein. Figure 32 is a schematic diagram of a #volatile 5 memory cell having a recessed channel between the source region and the drain region, whereby the lower dielectric structure has a three-layer thin crucible structure. /, Figure 33 is a schematic diagram of a non-volatile memory cell having a source region and a drain region lifted off the semiconductor substrate, whereby the lower dielectric structure has a three-layer thin 0Ν0 structure. 31 200807726

2 followed by 2/ΰ. TW3135PA ^ [Main component symbol description] 102, 302, 402, 502, 602, 702, 802, 902, 1002, 1102, 1202, 1302, 1402, 1502, 1602, 2264, 2722: gate /Gate region 104: Dielectric structure 106: Charge storage structure 108: Charge storage structure / Dielectric structure 110, 210, 304, 404, 804, 904, 1204, 2280, 2380, 2560, 2660, 2960, 3060: Source Pole/source regions 112, 212, 306, 406, 806, 906, 1206, 2282, 2382, 2562, 2662, 2962, 3062: bungee region/dipole 114, 214: channel region/channel 116: source and Bungee region 118: interface 120: junction depth 122: body/body region 208: dielectric structure 218: interface 220: junction depth 308, 408, 808, 908, 1208: body region 504, 1104: p+ source Regions 506, 1106: p+ type drain regions 508, 708, 1108: N-type body regions 604, 704, 1〇〇4, 1304, 1404, 1504, 1604: n+ type source 32 20_ZUTM pole regions 606, 706, 1006 1306, 1406, 1506, 1606: n+ type drain regions 608, 1008, 1308, 1408, 1508, 1608: P-type body regions 710, 1210 · Well regions 1900, 2400, 280 0: substrate 1910, 1912, 2112, 2290, 2772: oxide 1922: photoresist 1930, 1932, 2232: trenches 2040, 2042, 2440, 2840 · spacer 2250: dielectric material and charge storage structure 2260, 2262 : Gate material 2270, 2272 · Dielectric material 2410: Dielectric material and charge storage structure 2412 : ΟΝΟ Polycrystalline chips 2420, 2650, 2652, 2820, 3050, 3052 2430: SiN/oxide 2442, 2842: spacer Sidewalls 2550, 2950: epitaxial germanium 2810: charge storage structure 2812: ΟΝΟ 3100: memory array 3101: column decoder 3102: word line 33 200807726

- send m · rW3135PA • 3103 · row decoder 3104: bit line 3105: bus 3106: sense amplifier and data input structure 3107: data bus 3108: bias configuration supply voltage 3109 · · bias configuration state Machine 3111: data input line 3115: data output line 3150: integrated circuit 3208: ΟΝΟ structure 34

Claims (1)

2008013⁄4 Hall X. The scope of application for patents: 1·. A non-volatile memory cell integrated circuit comprising: · a structure: a capture structure for storing a charge to control a logic state stored by the non-volatile ~ jujube integrated circuit; a polar region and a bungee region Separating a channel region, and 舆辕% solid f4 a plurality of dielectric structures, at least partially located between the surface of the charge trapping structure, and at least partially located in the charge trapping structure and a gate Between the eight-to-one, one-W, one of the W regions, such that the first end of the interface ends between the inter-source portions, and the second end of the interface ends In the bungee zone, the boundary zone j is as in the circuit of claim 1, wherein the first component of the non-volatile memory cell integrated circuit is recessed by the technique and the first of the interfaces is The end ends in the middle portion of the source region, and the second end of the four faces ends in the middle portion of the non-polar region. The company of the invention is the circuit described in claim 1, wherein the charge ~ 椽 stores one bit. For example, the company has applied for the circuit described in item 1 of the patent scope, in which the charge and the storage are multi-bit. And reading the %...w interface to separate a portion of the one or more dielectric structures to divide the area, the first end of the interface ends at the middle end of the source region, and the first end of the W-plane ends The j: and the middle part of the polar region. The circuit of the first aspect of the invention is the circuit of claim 1, wherein the anode region is lifted away from the non-volatile memory unit 35 200807726 2 violent grasping TW3135PA • 6. Apply The circuit of claim 1, wherein the dielectric structure at least partially located between the charge trapping structure and the channel region comprises: a lower yttrium oxide layer; an intermediate tantalum nitride layer on the lower yttrium oxide layer And an upper yttrium oxide layer on the intermediate tantalum nitride layer. 7. The circuit of claim 6 wherein the lower ruthenium oxide layer has a thickness of less than about 20 angstroms. 8. The circuit of claim 6 wherein the intermediate tantalum nitride layer has a thickness of less than about 20 angstroms. 9. The circuit of claim 6 wherein the upper ruthenium oxide layer has a thickness of less than about 20 angstroms. 10. The circuit of claim 6 wherein the lower ruthenium oxide layer has a thickness of between about 5 and 20 angstroms. 11. The circuit of claim 6 wherein the intermediate tantalum nitride layer has a thickness of between about 10 and 20 angstroms. 12. The circuit of claim 6 wherein the upper ruthenium oxide layer has a thickness of between about 15 and 20 angstroms. 13. The circuit of claim 6 wherein the lower ruthenium oxide layer has a thickness of less than about 15 angstroms. 14. A method of fabricating a non-volatile memory cell integrated circuit, comprising the steps of: forming an electrical capture structure to store power to control a logic state stored by the non-volatile memory cell integrated circuit; 200807726 ~·达达号: TW3135PA forms one source region and one non-polar region of the ^-channel region; and forms one or a dielectric structure, the one or more dielectric structures are located at the charge trapping Between the structure and the channel region, and between at least a location capture structure and a gate voltage source, the factory and the medium force surface are separated from the one or more dielectric structures; The first end ends in the middle portion of the source region and the second end of the crucible 7 ends in the middle portion of the drain region. The method of claim 14, wherein the forming step of the source and drain regions comprises: == to a substrate of the integrated circuit such that the source and the source are 〇+ leaving the substrate of the non-volatile memory cell integrated circuit. Step:: μ The method described in claim 14 further includes forming a trench in the substrate to make the charge The method of forming the capture structure of the one or more dielectric structures occurs by the method of storing a H-caption of the item 14 in the method of the present invention, wherein the electric bucket I8 is as claimed in claim 14 The method described, how to capture the structure to store multiple bits. The method of claim 14, wherein the step of forming the dielectric capture structure between the charge trapping structure and the channel region comprises: $ ', and mouth structure 37 200807726 二逹Compilation: TW3135PA forms an oxide breakdown layer; forms an intermediate tantalum nitride layer on the lower hafnium oxide layer; and forms an upper hafnium oxide layer on the intermediate tantalum nitride layer. 20. The method of claim 19, wherein the lower ruthenium oxide layer has a thickness of less than about 20 angstroms. 21. The method of claim 19, wherein the interdigit nitride layer has a thickness of less than about 20 angstroms. 22. The method of claim 19, wherein the upper ruthenium oxide layer has a thickness of less than about 20 angstroms. 23. The method of claim 19, wherein the lower ruthenium oxide layer has a thickness of between about 5 and 20 angstroms. 24. The method of claim 19, wherein the intermediate tantalum nitride layer has a thickness of between about 10 and 20 angstroms. 25. The method of claim 19, wherein the upper ruthenium oxide layer has a thickness of between about 15 and 20 angstroms. 26. The method of claim 19, wherein the lower layer of oxidized stone has a thickness of less than about 15 angstroms. 27. A non-volatile memory cell integrated circuit comprising: a nano crystal structure for storing charge to control a logic state stored by the non-volatile memory cell integrated circuit; a source region and a drain a polar region separated by a channel region; and one or more dielectric structures at least partially between the nanocrystal structure and the channel region and at least partially located in the nanocrystal structure and a gate voltage source Between, 38 200807726 Erda pulping: TW3135PA one of the interfaces separates one of the one or more dielectric structures from the channel region, and the first end of one of the interfaces ends in the middle portion of the source region, and The second end of one of the interfaces terminates in a middle portion of the drain region. 28. The circuit of claim 27, wherein the source region and the drain region are lifted off a substrate of the non-volatile memory cell integrated circuit such that the interface is first The end ends in an intermediate portion of the intermediate portion of the source region, and the second end of the interface ends in a middle portion of the drain region. 29. The circuit of claim 27, wherein the first end of the interface ends in the source region because the channel region is recessed into a substrate of the non-volatile memory cell integrated circuit The intermediate portion, and the second end of the interface ends in a middle portion of the drain region. 30. The circuit of claim 27, wherein the nanocrystal structure stores one bit. 31. The circuit of claim 27, wherein the nanocrystal structure stores multiple bits. 32. A method of fabricating a non-volatile memory cell integrated circuit, comprising the steps of: forming a nanocrystal structure to store a charge to control a logic state stored by the non-volatile memory cell integrated circuit; a channel region separating one of the source region and a drain region; and forming one or more dielectric structures at least partially between the nanocrystal structure and the channel region, and at least partially located in the nanocrystal structure And a gate voltage source, 39 200807726 Sanda number: TW3135PA one of the interfaces separates one of the one or more dielectric structures from the channel region, and the first end of the interface ends in the source region a middle portion, and one of the second ends of the interface ends in a middle portion of the drain region. 33. The method of claim 32, wherein the forming step of the source region and the drain region comprises: adding a layer of material to a substrate of the integrated circuit to make the source region and the germanium The polar region is lifted off the substrate of the non-volatile memory cell integrated circuit. 34. The method of claim 32, further comprising the steps of: forming a trench in a substrate such that the forming step of the nanocrystal structure and the one or more dielectric structures This forming step occurs in the trench. 35. The method of claim 32, wherein the nanocrystal structure stores one bit. 36. The method of claim 32, wherein the nanocrystal structure stores multiple bits.