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TW200717003A - Integrated circuit test method and apparatus thereof - Google Patents

Integrated circuit test method and apparatus thereof

Info

Publication number
TW200717003A
TW200717003A TW094136904A TW94136904A TW200717003A TW 200717003 A TW200717003 A TW 200717003A TW 094136904 A TW094136904 A TW 094136904A TW 94136904 A TW94136904 A TW 94136904A TW 200717003 A TW200717003 A TW 200717003A
Authority
TW
Taiwan
Prior art keywords
integrated circuit
test
testing
computer host
test method
Prior art date
Application number
TW094136904A
Other languages
Chinese (zh)
Other versions
TWI279571B (en
Inventor
qi-dong Zhang
Guang-Ting Hu
Original Assignee
Alcor Micro Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcor Micro Corp filed Critical Alcor Micro Corp
Priority to TW94136904A priority Critical patent/TWI279571B/en
Application granted granted Critical
Publication of TWI279571B publication Critical patent/TWI279571B/en
Publication of TW200717003A publication Critical patent/TW200717003A/en

Links

Landscapes

  • Test And Diagnosis Of Digital Computers (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)

Abstract

The present invention relates to a low cost integrated circuit test method and apparatus thereof, which incorporates a personal computer host and related software and hardware to control testing process of integrated circuits. When the testing process is initiated, the computer host drives a load/unload device to place the integrated circuit under test on a test module and polls to check if a test station connected to the test module is normally working, if it is normally working, the test station will start testing the integrated circuit, and results of which will be collected and classified into the normal integrated circuit and abnormal integrated circuit, respectively. Because the test process of testing integrated circuits is controlled by the personal computer host, cost can be reduced and testing control can be easily implemented.
TW94136904A 2005-10-21 2005-10-21 Method and device for testing integrated circuit TWI279571B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW94136904A TWI279571B (en) 2005-10-21 2005-10-21 Method and device for testing integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW94136904A TWI279571B (en) 2005-10-21 2005-10-21 Method and device for testing integrated circuit

Publications (2)

Publication Number Publication Date
TWI279571B TWI279571B (en) 2007-04-21
TW200717003A true TW200717003A (en) 2007-05-01

Family

ID=38645459

Family Applications (1)

Application Number Title Priority Date Filing Date
TW94136904A TWI279571B (en) 2005-10-21 2005-10-21 Method and device for testing integrated circuit

Country Status (1)

Country Link
TW (1) TWI279571B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI686810B (en) * 2019-07-31 2020-03-01 全何科技股份有限公司 Memory chip overclocking test method

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8271226B2 (en) * 2008-06-26 2012-09-18 Cadence Design Systems, Inc. Testing state retention logic in low power systems

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI686810B (en) * 2019-07-31 2020-03-01 全何科技股份有限公司 Memory chip overclocking test method

Also Published As

Publication number Publication date
TWI279571B (en) 2007-04-21

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees