TW200703916A - Clock and data recovery circuit and method thereof - Google Patents
Clock and data recovery circuit and method thereofInfo
- Publication number
- TW200703916A TW200703916A TW095124057A TW95124057A TW200703916A TW 200703916 A TW200703916 A TW 200703916A TW 095124057 A TW095124057 A TW 095124057A TW 95124057 A TW95124057 A TW 95124057A TW 200703916 A TW200703916 A TW 200703916A
- Authority
- TW
- Taiwan
- Prior art keywords
- voltage
- integration
- proportional
- circuit
- current
- Prior art date
Links
- 238000011084 recovery Methods 0.000 title abstract 2
- 238000000034 method Methods 0.000 title 1
- 230000010354 integration Effects 0.000 abstract 5
- 230000009977 dual effect Effects 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
- H03L7/0893—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump the up-down pulses controlling at least two source current generators or at least two sink current generators connected to different points in the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
- H03L2207/06—Phase locked loops with a controlled oscillator having at least two frequency control terminals
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US69543105P | 2005-07-01 | 2005-07-01 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW200703916A true TW200703916A (en) | 2007-01-16 |
| TWI311865B TWI311865B (en) | 2009-07-01 |
Family
ID=37597872
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW095124057A TWI311865B (en) | 2005-07-01 | 2006-06-30 | Clock and data recovery circuit and method thereof |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US7330058B2 (zh) |
| CN (1) | CN1893331B (zh) |
| TW (1) | TWI311865B (zh) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI548965B (zh) * | 2014-08-15 | 2016-09-11 | 佳世達科技股份有限公司 | 顯示裝置 |
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| US8259890B2 (en) * | 2009-02-18 | 2012-09-04 | Mediatek Inc. | Phase-locked loop circuit and related phase locking method |
| US8169265B2 (en) * | 2009-04-29 | 2012-05-01 | Mediatek Inc. | Phase lock loop circuits |
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| US20120126854A1 (en) * | 2009-08-04 | 2012-05-24 | Nec Corporation | Frequency regeneration circuit and frequency regeneration method |
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| US9077386B1 (en) | 2010-05-20 | 2015-07-07 | Kandou Labs, S.A. | Methods and systems for selection of unions of vector signaling codes for power and pin efficient chip-to-chip communication |
| US9251873B1 (en) | 2010-05-20 | 2016-02-02 | Kandou Labs, S.A. | Methods and systems for pin-efficient memory controller interface using vector signaling codes for chip-to-chip communications |
| US8179162B2 (en) * | 2010-07-13 | 2012-05-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Phase-lock assistant circuitry |
| US8588358B2 (en) | 2011-03-11 | 2013-11-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Clock and data recovery using LC voltage controlled oscillator and delay locked loop |
| US8494092B2 (en) * | 2011-04-07 | 2013-07-23 | Lsi Corporation | CDR with sigma-delta noise-shaped control |
| GB2496673B (en) * | 2011-11-21 | 2014-06-11 | Wolfson Microelectronics Plc | Clock generator |
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| JP5738749B2 (ja) * | 2011-12-15 | 2015-06-24 | ルネサスエレクトロニクス株式会社 | Pll回路 |
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| JP5966986B2 (ja) * | 2013-03-21 | 2016-08-10 | 富士通株式会社 | Pll回路及びpll回路における位相比較方法 |
| KR102241045B1 (ko) | 2013-04-16 | 2021-04-19 | 칸도우 랩스 에스에이 | 고 대역폭 통신 인터페이스를 위한 방법 및 시스템 |
| JP6163860B2 (ja) * | 2013-05-15 | 2017-07-19 | 株式会社リコー | 位相比較回路とクロックデータリカバリ回路 |
| EP2997704B1 (en) | 2013-06-25 | 2020-12-16 | Kandou Labs S.A. | Vector signaling with reduced receiver complexity |
| US9806761B1 (en) | 2014-01-31 | 2017-10-31 | Kandou Labs, S.A. | Methods and systems for reduction of nearest-neighbor crosstalk |
| JP6317474B2 (ja) | 2014-02-02 | 2018-04-25 | カンドウ ラボズ ソシエテ アノニム | 制約isi比を用いる低電力チップ間通信の方法および装置 |
| EP3111607B1 (en) | 2014-02-28 | 2020-04-08 | Kandou Labs SA | Clock-embedded vector signaling codes |
| US9509437B2 (en) | 2014-05-13 | 2016-11-29 | Kandou Labs, S.A. | Vector signaling code with improved noise margin |
| US9112550B1 (en) | 2014-06-25 | 2015-08-18 | Kandou Labs, SA | Multilevel driver for high speed chip-to-chip communications |
| EP3138253A4 (en) | 2014-07-10 | 2018-01-10 | Kandou Labs S.A. | Vector signaling codes with increased signal to noise characteristics |
| US9432082B2 (en) | 2014-07-17 | 2016-08-30 | Kandou Labs, S.A. | Bus reversable orthogonal differential vector signaling codes |
| CN106664272B (zh) | 2014-07-21 | 2020-03-27 | 康杜实验室公司 | 从多点通信信道接收数据的方法和装置 |
| KR101949964B1 (ko) | 2014-08-01 | 2019-02-20 | 칸도우 랩스 에스에이 | 임베딩된 클록을 갖는 직교 차동 벡터 시그널링 코드 |
| TWI559723B (zh) * | 2014-08-11 | 2016-11-21 | 聯詠科技股份有限公司 | 時脈資料回復裝置 |
| US9674014B2 (en) | 2014-10-22 | 2017-06-06 | Kandou Labs, S.A. | Method and apparatus for high speed chip-to-chip communications |
| JP6469474B2 (ja) * | 2015-02-19 | 2019-02-13 | ルネサスエレクトロニクス株式会社 | Pll回路及びその制御方法 |
| CN113225159B (zh) | 2015-06-26 | 2024-06-07 | 康杜实验室公司 | 高速通信系统 |
| US10055372B2 (en) | 2015-11-25 | 2018-08-21 | Kandou Labs, S.A. | Orthogonal differential vector signaling codes with embedded clock |
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| US10003454B2 (en) | 2016-04-22 | 2018-06-19 | Kandou Labs, S.A. | Sampler with low input kickback |
| EP3446403B1 (en) | 2016-04-22 | 2021-01-06 | Kandou Labs S.A. | High performance phase locked loop |
| WO2017185070A1 (en) | 2016-04-22 | 2017-10-26 | Kandou Labs, S.A. | Calibration apparatus and method for sampler with adjustable high frequency gain |
| US10153591B2 (en) | 2016-04-28 | 2018-12-11 | Kandou Labs, S.A. | Skew-resistant multi-wire channel |
| US10193716B2 (en) | 2016-04-28 | 2019-01-29 | Kandou Labs, S.A. | Clock data recovery with decision feedback equalization |
| EP3449379B1 (en) | 2016-04-28 | 2021-10-06 | Kandou Labs S.A. | Vector signaling codes for densely-routed wire groups |
| WO2017190102A1 (en) | 2016-04-28 | 2017-11-02 | Kandou Labs, S.A. | Low power multilevel driver |
| CN107787003A (zh) * | 2016-08-24 | 2018-03-09 | 中兴通讯股份有限公司 | 一种流量检测的方法和装置 |
| US9906358B1 (en) | 2016-08-31 | 2018-02-27 | Kandou Labs, S.A. | Lock detector for phase lock loop |
| US9973197B2 (en) * | 2016-09-07 | 2018-05-15 | Toshiba Memory Corporation | Phase-locked loop circuit |
| US10411922B2 (en) | 2016-09-16 | 2019-09-10 | Kandou Labs, S.A. | Data-driven phase detector element for phase locked loops |
| US10200188B2 (en) | 2016-10-21 | 2019-02-05 | Kandou Labs, S.A. | Quadrature and duty cycle error correction in matrix phase lock loop |
| US10372665B2 (en) | 2016-10-24 | 2019-08-06 | Kandou Labs, S.A. | Multiphase data receiver with distributed DFE |
| US10200218B2 (en) | 2016-10-24 | 2019-02-05 | Kandou Labs, S.A. | Multi-stage sampler with increased gain |
| CN115333530A (zh) | 2017-05-22 | 2022-11-11 | 康杜实验室公司 | 多模式数据驱动型时钟恢复方法和装置 |
| CN107086895B (zh) * | 2017-06-09 | 2018-11-30 | 上海胜战科技发展有限公司 | 基于交流供电电压相位差修正的高精度网络授时方法 |
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| US10686583B2 (en) | 2017-07-04 | 2020-06-16 | Kandou Labs, S.A. | Method for measuring and correcting multi-wire skew |
| US10203226B1 (en) | 2017-08-11 | 2019-02-12 | Kandou Labs, S.A. | Phase interpolation circuit |
| US10347283B2 (en) | 2017-11-02 | 2019-07-09 | Kandou Labs, S.A. | Clock data recovery in multilane data receiver |
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| US10554380B2 (en) | 2018-01-26 | 2020-02-04 | Kandou Labs, S.A. | Dynamically weighted exclusive or gate having weighted output segments for phase detection and phase interpolation |
| US10523411B2 (en) * | 2018-03-29 | 2019-12-31 | Intel Corporation | Programmable clock data recovery (CDR) system including multiple phase error control paths |
| CN112868181B (zh) | 2018-06-12 | 2023-11-21 | 康杜实验室公司 | 低延迟组合式时钟数据恢复逻辑网络及电荷泵电路 |
| CN111697966B (zh) * | 2019-03-13 | 2023-08-04 | 瑞昱半导体股份有限公司 | 时钟产生电路以及产生时钟信号的方法 |
| US10630272B1 (en) | 2019-04-08 | 2020-04-21 | Kandou Labs, S.A. | Measurement and correction of multiphase clock duty cycle and skew |
| US10673443B1 (en) | 2019-04-08 | 2020-06-02 | Kandou Labs, S.A. | Multi-ring cross-coupled voltage-controlled oscillator |
| US10958251B2 (en) | 2019-04-08 | 2021-03-23 | Kandou Labs, S.A. | Multiple adjacent slicewise layout of voltage-controlled oscillator |
| US11341904B2 (en) | 2019-08-13 | 2022-05-24 | Novatek Microelectronics Corp. | Light-emitting diode driving apparatus and light-emitting diode driver |
| US20210049952A1 (en) * | 2019-08-13 | 2021-02-18 | Novatek Microelectronics Corp. | Light-emitting diode driving apparatus |
| CN112653451B (zh) * | 2019-10-11 | 2024-02-09 | 瑞昱半导体股份有限公司 | 时钟数据恢复装置 |
| CN113839668B (zh) * | 2020-06-23 | 2024-07-05 | 円星科技股份有限公司 | 双模锁相环电路、振荡电路及振荡电路的控制方法 |
| TWI739571B (zh) | 2020-08-28 | 2021-09-11 | 崛智科技有限公司 | 時脈資料回復電路 |
| US11463092B1 (en) | 2021-04-01 | 2022-10-04 | Kanou Labs Sa | Clock and data recovery lock detection circuit for verifying lock condition in presence of imbalanced early to late vote ratios |
| US11563605B2 (en) | 2021-04-07 | 2023-01-24 | Kandou Labs SA | Horizontal centering of sampling point using multiple vertical voltage measurements |
| US11496282B1 (en) | 2021-06-04 | 2022-11-08 | Kandou Labs, S.A. | Horizontal centering of sampling point using vertical vernier |
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| US5180993A (en) * | 1990-01-15 | 1993-01-19 | Telefonaktiebolaget L M Ericsson | Method and arrangement for frequency synthesis |
| DE69535087T2 (de) * | 1994-03-11 | 2006-12-21 | Fujitsu Ltd., Kawasaki | Schaltungsanordnung zur Taktrückgewinnung |
| US5740213A (en) * | 1994-06-03 | 1998-04-14 | Dreyer; Stephen F. | Differential charge pump based phase locked loop or delay locked loop |
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-
2006
- 2006-06-30 TW TW095124057A patent/TWI311865B/zh active
- 2006-06-30 US US11/477,951 patent/US7330058B2/en active Active
- 2006-07-03 CN CN2006101005332A patent/CN1893331B/zh active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI548965B (zh) * | 2014-08-15 | 2016-09-11 | 佳世達科技股份有限公司 | 顯示裝置 |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI311865B (en) | 2009-07-01 |
| US20070001723A1 (en) | 2007-01-04 |
| CN1893331A (zh) | 2007-01-10 |
| US7330058B2 (en) | 2008-02-12 |
| CN1893331B (zh) | 2010-06-16 |
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