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TW200637317A - Process of and apparatus for encoding a digital input - Google Patents

Process of and apparatus for encoding a digital input

Info

Publication number
TW200637317A
TW200637317A TW094135511A TW94135511A TW200637317A TW 200637317 A TW200637317 A TW 200637317A TW 094135511 A TW094135511 A TW 094135511A TW 94135511 A TW94135511 A TW 94135511A TW 200637317 A TW200637317 A TW 200637317A
Authority
TW
Taiwan
Prior art keywords
type
operations
logical
inverse
cryptographic process
Prior art date
Application number
TW094135511A
Other languages
Chinese (zh)
Inventor
Sean O'neil
Original Assignee
Synaptic Lab Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from AU2004905897A external-priority patent/AU2004905897A0/en
Application filed by Synaptic Lab Ltd filed Critical Synaptic Lab Ltd
Publication of TW200637317A publication Critical patent/TW200637317A/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
    • H04L9/0618—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Storage Device Security (AREA)

Abstract

A cryptographic process (10) that receives input (11) and produces output (2). The cryptographic process (10) produces each block of output (20) by performing on a block of input (11), in any order, at least one operation (15) of a first type; at least one operation (19) of a second type; at least one operation (13, 17) of a third type; and at least one operation (12) of a fourth type. The operations of the first type (15) are swapping (SWAP) and bit order reversal. The operations of the second type (19) are bitwise rotation to the left (ROTL) and bitwise rotation to the right (ROTR). The operations of the third type (13, 17) are addition (ADD), subtraction (SUB) and negation (NEG). The operations of the fourth type (12) are exclusive-or (XOR), inverse exclusive-or (XNOR), logical AND, inverse logical AND (NAND), logical OR, inverse logical OR (NOR) and logical inverse (NOT). When both the first operation and the last operation in the cryptographic process (10) are swap operations (15), the cryptographic process includes a further swap operation (15).
TW094135511A 2004-10-13 2005-10-12 Process of and apparatus for encoding a digital input TW200637317A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
AU2004905897A AU2004905897A0 (en) 2004-10-13 Process of and apparatus for encoding a digital input

Publications (1)

Publication Number Publication Date
TW200637317A true TW200637317A (en) 2006-10-16

Family

ID=36118193

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094135511A TW200637317A (en) 2004-10-13 2005-10-12 Process of and apparatus for encoding a digital input

Country Status (2)

Country Link
TW (1) TW200637317A (en)
WO (1) WO2006040682A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9128698B2 (en) * 2012-09-28 2015-09-08 Intel Corporation Systems, apparatuses, and methods for performing rotate and XOR in response to a single instruction

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6182216B1 (en) * 1997-09-17 2001-01-30 Frank C. Luyster Block cipher method
US6269163B1 (en) * 1998-06-15 2001-07-31 Rsa Security Inc. Enhanced block ciphers with data-dependent rotations
US6483918B2 (en) * 1999-06-09 2002-11-19 Microsoft Corporation Technique for producing a parameter, such as a checksum, through a primitive that uses elementary register operations
US20020114451A1 (en) * 2000-07-06 2002-08-22 Richard Satterfield Variable width block cipher

Also Published As

Publication number Publication date
WO2006040682A3 (en) 2006-07-27
WO2006040682A2 (en) 2006-04-20
WO2006040682A9 (en) 2006-06-08

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