TW200533257A - Circuit board structure and method for fabricating the same - Google Patents
Circuit board structure and method for fabricating the same Download PDFInfo
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- TW200533257A TW200533257A TW93106918A TW93106918A TW200533257A TW 200533257 A TW200533257 A TW 200533257A TW 93106918 A TW93106918 A TW 93106918A TW 93106918 A TW93106918 A TW 93106918A TW 200533257 A TW200533257 A TW 200533257A
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- 238000000034 method Methods 0.000 title claims abstract description 56
- 229910052751 metal Inorganic materials 0.000 claims abstract description 60
- 239000002184 metal Substances 0.000 claims abstract description 60
- 239000010410 layer Substances 0.000 claims description 168
- 238000004519 manufacturing process Methods 0.000 claims description 32
- 239000011241 protective layer Substances 0.000 claims description 18
- 239000012792 core layer Substances 0.000 claims description 14
- 238000007747 plating Methods 0.000 claims description 14
- 229910000679 solder Inorganic materials 0.000 claims description 14
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 13
- 239000010949 copper Substances 0.000 claims description 13
- 229910052802 copper Inorganic materials 0.000 claims description 11
- 239000000463 material Substances 0.000 claims description 11
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical group [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 10
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 6
- 238000007772 electroless plating Methods 0.000 claims description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 5
- 229910052737 gold Inorganic materials 0.000 claims description 5
- 239000010931 gold Substances 0.000 claims description 5
- 229910052759 nickel Inorganic materials 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 229920005989 resin Polymers 0.000 claims description 4
- 239000011347 resin Substances 0.000 claims description 4
- 229910052763 palladium Inorganic materials 0.000 claims description 3
- 230000000149 penetrating effect Effects 0.000 claims description 2
- 229910000881 Cu alloy Inorganic materials 0.000 claims 1
- 230000004888 barrier function Effects 0.000 claims 1
- 238000009713 electroplating Methods 0.000 abstract description 6
- 238000000059 patterning Methods 0.000 abstract description 3
- 239000000758 substrate Substances 0.000 abstract 3
- 230000001681 protective effect Effects 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 8
- 238000011161 development Methods 0.000 description 5
- 230000005611 electricity Effects 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000009413 insulation Methods 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 239000000654 additive Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000000945 filler Substances 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 235000012431 wafers Nutrition 0.000 description 3
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 2
- 238000005234 chemical deposition Methods 0.000 description 2
- 238000012217 deletion Methods 0.000 description 2
- 230000037430 deletion Effects 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 239000003365 glass fiber Substances 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000001659 ion-beam spectroscopy Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 238000012827 research and development Methods 0.000 description 2
- 230000001568 sexual effect Effects 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 description 1
- 241000283690 Bos taurus Species 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 241000272470 Circus Species 0.000 description 1
- 229910000599 Cr alloy Inorganic materials 0.000 description 1
- 229910052688 Gadolinium Inorganic materials 0.000 description 1
- 241001611138 Isma Species 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- GXDVEXJTVGRLNW-UHFFFAOYSA-N [Cr].[Cu] Chemical compound [Cr].[Cu] GXDVEXJTVGRLNW-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 239000000788 chromium alloy Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 239000004643 cyanate ester Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- UIWYJDYFSGRHKR-UHFFFAOYSA-N gadolinium atom Chemical compound [Gd] UIWYJDYFSGRHKR-UHFFFAOYSA-N 0.000 description 1
- 150000003949 imides Chemical class 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920003192 poly(bis maleimide) Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 239000011135 tin Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
200533257 五、發明說明(1) 【發明所屬之技術領域】 本發明係關於一種電路板結構及其製法,尤指一種於 多層電路板中利用電鍍導通孔結構以導電連接上、下層線 路層之電路板結構及其製法。 【先前技術】 隨著電子產業的蓬勃發展,電子產品亦逐漸邁入多功 能、高性能的研發趨勢。為滿足半導體封裝件高積集度( 11^62^1^011)及微型化(^^1^31:111^231:1〇11)的封裝需求, 以供更多主、被動元件及線路載接,承載半導體晶片之電 路板亦逐漸由雙層板演變成多層板(Mul t丨―Uyer b〇ard) ,俾在有限的空間下,運用層間連接技術(InterUyer connect ion)來擴大電路板上可供利用的線路佈局面積, 藉此配合高線路密度之積體電路(Integrated circuit)f 要以在相同電路板單位面積下容納更多數量的線路及元 為因應微處理器、具y Λ ^ 運算需要,電路板;需d綠圖晶片等高效能晶片之 控制阻抗等功能,來成==;、;^遞4'片訊號、改善頻寬、 為符合半導體封裝件輕薄:/裝j牛的▲發展。然而’ 的開發…電路板已功能、南速度及高頻化 路板製程從傳統1 00微米< 及小孔^發展。現有電 …删、線路間距(Spac:)i;= :Α=線寬度(L- 縮減至30微米以下,並持接(Aspect ratio)等, 發。 卜並持續朝向更小的線路精度進行研200533257 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a circuit board structure and a manufacturing method thereof, and more particularly to a circuit for electrically connecting upper and lower circuit layers in a multi-layer circuit board by using a plated through-hole structure to conduct electricity. Plate structure and its manufacturing method. [Previous technology] With the vigorous development of the electronics industry, electronic products have gradually entered the trend of multi-function and high-performance research and development. In order to meet the packaging requirements of semiconductor packages with high accumulation (11 ^ 62 ^ 1 ^ 011) and miniaturization (^^ 1 ^ 31: 111 ^ 231: 1011), for more active and passive components and circuits Carrying, the circuit board carrying the semiconductor wafer has also gradually evolved from a double-layer board to a multi-layer board (Mul t 丨 —Uyer b〇ard). In a limited space, the use of InterUyer connect ion to expand the circuit board The available circuit layout area can be used to match the integrated circuit with high circuit density. The integrated circuit f should be based on the same circuit board unit area to accommodate a larger number of circuits and elements. ^ Operational requirements, circuit boards; high-performance chips such as d green map chips, and impedance control functions are required to achieve == ;;; ^ 4 'chip signal, improve bandwidth, and conform to the thinness and lightness of semiconductor packages: / 装 j Development of cattle. However, the development of… the circuit board has been functional, the south speed and the high frequency circuit board process has developed from the traditional 100 micron < and the small hole ^. Existing power… delete, line spacing (Spac:) i; =: Α = line width (L- reduced to less than 30 microns, and hold (Aspect ratio), etc., and continue to research towards smaller line accuracy
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為提高電路板之佈線精密度,業界發展出一種增層技 術(Build-up),亦即在一核心電路板(c〇re circu^ boar d)表面利用線路增層技術交互堆疊多層絕緣層及線路 層,並於該絕緣層中開設導電盲孔(c〇nducUve via)以供 上下層線路之間電性連接。其中,線路增層製程係影塑電 路板線路密度的關鍵,依照現行技術,業者多以增層^ 來製作多層電路板。 t 請參閱第1A至丨⑽,係採用一例如半加成法(^…一 additive process, SAP)之線路增層製程,首先,提供一 _心電路板1 0,並在其表面形成一絕緣層i卜利用雷射鑽 孔(Laser drill ing)技術於該絕緣層丨丨上形成開孔11〇, 以連通該核心電路板1 〇之内層線路層i 2 (如第丨Α圖所示)。 接著’於该絕緣層11上以無電解鏟銅方式形成一導電晶種 層1 3 ’在該晶種層1 3上施加一圖案化阻層1 4後進行電鍍, 以於該晶種層1 3表面形成圖案化線路層1 5 (如第1 Β圖所示) 。之後’剝離該阻層1 4並進行蝕刻,以移除先前覆蓋於阻 層1 4下之晶種層1 3 (如第1 C圖所示);如此,運用此等步驟 重複形成絕緣層及增層線路層,即製成一具有多層線路結 構之電路板。 ® 惟,按一般習用藉由增層方式所製作之多層電路板, 若電子訊號欲由電路板上層傳送至下層時,該訊號必須從 上部增層線路層、上部線路層間之導電盲孔、而至核心電 路板上層線路層,再穿過該核心電路板内部之電鐘導通孔 (Plated through hole,ΡΤΗ)、核心電路板下層線路層、In order to improve the wiring accuracy of the circuit board, the industry has developed a build-up technology, that is, a core circuit board (co circu ^ boar d) is used to interactively stack multiple layers of insulation and A circuit layer, and a conductive blind via (conductUve via) is opened in the insulation layer for the electrical connection between the upper and lower lines. Among them, the process of increasing the thickness of the circuit is the key to the density of the circuit board of the shadow plastic circuit board. According to the current technology, the industry often uses multilayers to make multilayer circuit boards. t Please refer to Sections 1A to ⑽, which adopt a circuit layer-adding process such as a semi-additive process (^ ... an additive process, SAP). First, a core circuit board 10 is provided and an insulation is formed on its surface. Layer i1 uses laser drilling ing technology to form an opening 11o in the insulating layer 丨 丨 to communicate with the inner circuit layer i2 of the core circuit board 10 (as shown in FIG. 丨 A) . Next, 'a conductive seed layer 1 3 is formed on the insulating layer 11 in an electroless copper shovel manner' and a patterned resist layer 14 is applied on the seed layer 13 to perform electroplating on the seed layer 1 3 A patterned circuit layer 15 is formed on the surface (as shown in FIG. 1B). After that, the resist layer 14 is peeled off and etched to remove the seed layer 1 3 previously covered under the resist layer 14 (as shown in FIG. 1C). In this way, using these steps to repeatedly form the insulating layer and Adding a circuit layer is to make a circuit board with a multilayer circuit structure. ® However, the multilayer circuit board produced by the build-up method is generally used. If the electronic signal is to be transmitted from the upper layer of the circuit board to the lower layer, the signal must be from the upper build-up circuit layer, the conductive blind hole between the upper circuit layers, and To the upper circuit layer of the core circuit board, and then pass through the plated through hole (PTT) inside the core circuit board, the lower circuit layer of the core circuit board,
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五、發明說明(4) 幾 其 同 乎與晶片同大(約僅為晶片之h 2倍)時,如何開 搭配的細線路(Flne circuU)舆高線路 路了人 時不致提高過多製造成本,益又,甩路板, 相關電子產業進入下一世代& f Z V肢產業乃至其他 【發明内容】 世代技術之重要研發課題。 #於以上所述習知技術之缺點’本發明之主要 於提供:種電路,結構及其製法,係可直接在電鍍導= 上形成電性連接端,同時提供雷敗 、 電線路具縝密之細線路結構i、 八〃性連接端與導 •本為月之#目的在於提供一種電路板結構及 摩導電盲孔佈線空,並供該導電盲孔錢層:: 鐘導通孔形成較佳之電性連接關係。 —本發明之又一目的在於提供一種電路板結構及其製法 藉以縮短訊號傳輸路徑,以避免串擾、雜訊之產生而進 •步提昇電路板之電性品質。 本發明之又一目的在於提供一種電路板結構及其製法 ’藉以擴大電路板的線路佈局面積,並且提高層間線路( Interlayer c i r c u i t s )之佈局靈活性。 為達成上述及其他目的,本發明揭露一種半電路板結 •製法,係包括:提供一芯層板,該芯層板表面具有金屬 層,且形成有多數之電鍍導通孔;於顯露出該芯層板之電 鑛導通孔端部表面形成導電層;圖案化該芯層板表面之金 屬層以形成一圖案化線路;於該具圖案化線路結構之芯層 板上形成一導電膜;於該導電膜上形成一第一圖案化阻層V. Description of the invention (4) When it is almost the same size as the chip (about 2 times the size of the chip), how to open a matching thin line (Flne circuU) to pass the high-pass line will not increase the manufacturing cost. In addition, the road-striking boards, the related electronics industry entered the next generation & f ZV limb industry and even other [invention content] important research and development issues of the generation technology. #Disadvantages of the known technology described above 'The main purpose of the present invention is to provide: a circuit, a structure and a manufacturing method thereof, which can directly form an electrical connection terminal on the electroplating guide, and at the same time provide a lightning failure and a meticulous electrical circuit. Thin circuit structure i, octagonal connection terminal and guide • 本 为 月 之 # The purpose is to provide a circuit board structure and a conductive blind hole wiring space for the conductive blind hole money layer: Bell conductive vias to form better electricity Sexual connection. —Another object of the present invention is to provide a circuit board structure and a manufacturing method thereof to shorten the signal transmission path to avoid crosstalk and noise from occurring and further improve the electrical quality of the circuit board. Another object of the present invention is to provide a circuit board structure and a manufacturing method thereof, thereby increasing the circuit layout area of the circuit board and improving the layout flexibility of the interlayer circuits (Interlayer c i r c u i t s). In order to achieve the above and other objectives, the present invention discloses a method for manufacturing a semi-circuit board. The method includes: providing a core board, the core board having a metal layer on the surface, and forming a plurality of plated through-holes; A conductive layer is formed on the end surface of the through hole of the electrical slab of the laminate; the metal layer on the surface of the core board is patterned to form a patterned circuit; a conductive film is formed on the core board with the patterned circuit structure; Forming a first patterned resist layer on the conductive film
17660 全懋.ptd 第14頁 200533257 五、發明說明(5) ,藉以形成有複數之開口而顯露出部分導電膜,其中,至 少有一開口係對應至該電鍍導通孔之端部;移除未為該第 一圖案化阻層所覆蓋之導電膜;在該芯層板上形成一第二 圖案化阻層,以覆蓋住殘露於該第一阻層開口内之導電膜 ;在該芯層板上形成一第三阻層,以覆蓋住位於該電鍍導 通孔以外之開口;進行電鍍製程,以在外露出該第二圖案 阻層之該電鍍導通孔端部上形成一金屬層。如此,即可選 擇性在部分之電鍍導通孔上形成一供後續作用為電性連接 端之金屬層。之後,復可移除該第三阻層,並進行電鍍製 程,以在該電性連接端(包含該電鍍導通孔端部之金屬層) 表面形成一金屬保護層,接著,移除該第二、第一圖案化 阻層、以及覆蓋其下之導電膜,再於該表面完成圖案化線 路之芯層板上形成一圖案化拒銲層,以外露出該電性連接 端表面之部分金屬保護層。 亦即,透過上述製程,本發明係先利用阻層覆蓋住形 成圖案化細線路之區域,再選擇性於部分電鍍導通孔之端 部形成金屬層,而不致影響電路板線路佈局空間與細線路 之製程,同時更可進一步應用在線路增層製程中,藉由在 電鍍導通孔上所形成之電性連接端,以減少承接導電盲孔 所需之電性連接端之設置與接線所佔電路板空間,俾有效 提升線路佈線之密度。 此外,經前述製程,本發明亦揭示出一種電路板結構 ,係包括:一芯層板,其表面形成有圖案化線路與多數貫 穿該芯層板之電鍍導通孔,其.中,至少一電性連接端係形17660 Quan 懋 .ptd Page 14 200533257 V. Description of the Invention (5), by forming a plurality of openings to expose part of the conductive film, at least one of the openings corresponds to the end of the plated through-hole; A conductive film covered by the first patterned resist layer; forming a second patterned resist layer on the core layer board to cover the conductive film remaining in the opening of the first resist layer; on the core layer board A third resist layer is formed thereon to cover the opening outside the plating via hole; a plating process is performed to form a metal layer on an end of the plating via hole exposing the second pattern resist layer. In this way, a metal layer can be optionally formed on a part of the plated through-holes for subsequent use as an electrical connection terminal. After that, the third resistive layer is removed, and a plating process is performed to form a metal protective layer on the surface of the electrical connection end (including the metal layer at the end of the plated via hole). Then, the second resistive layer is removed. , A first patterned resist layer, and a conductive film covering the surface, and a patterned solder resist layer is formed on the surface of the core board on which the patterned circuit is completed, and a portion of the metal protective layer on the surface of the electrical connection end is exposed. . That is, through the above process, the present invention first covers the area where the patterned fine lines are formed by using a resistive layer, and then selectively forms a metal layer at the end of a part of the plated-through hole without affecting the layout space of the circuit board and the fine lines. At the same time, it can be further applied in the process of layer buildup of the circuit. The electrical connection terminals formed on the plated through holes can reduce the electrical connection terminals and the circuit occupied by the conductive blind holes. Board space, effectively increasing the density of circuit wiring. In addition, through the foregoing process, the present invention also discloses a circuit board structure including: a core board, the surface of which is formed with a patterned circuit and a plurality of plated through holes penetrating through the core board, among which at least one electric Sexual connection
17660 全懋.ptd 第15頁 五 成 通 與 保 可 接 電 該 盲 需 活 此 藉 層 之 電 200533257 、發明說明(6) 於該電鍍導通孔上;一金屬保護層,係包覆於該電鍍導 孔上之電性連接端之上表面及其餘電性連接端之上表面 側邊;以及一圖案化拒銲層,係形成在該電路板表面上 俾使該拒銲層形成有複數個開口以外露出該電性連接端 且至少一開口係對應至該電鍍導通孔端部之電性連接端 可藉由該拒銲層包覆部分之金屬保護層,而強化該金屬 護層得以有效附著於該電性連接端上。其中,該芯層板 為一完成前段製程之多層電路板。 因此,藉由本發明之電路板結構及其製法,係可選擇 丨在部分欲形成電性連接端之電鍍導通孔上形成該電性連 端,以供後續接置有導電元件,俾提供該電路板與其他 子元件(半導體晶片或電路板)之電性導接,亦或可於 電鍍導通孔上之電性連接端形成有線路增層結構之導電 孔(C ο n d u c t i v e v i a ),以減少習知形成導電盲孔時,所 延伸出連接墊(P a d )之空間,藉以增加佈線路密度與靈 性,並可縮短導電路徑,減少電感、串擾及雜訊產生; 外,該電鍍導通孔上之電性連接端係於製程中獨立形成 而不影響該電路板其餘電性連接端及導電線路之製程, 以避免習知技術中在電鍍導通孔上欲形成電性連接端時 I 必需在整體電路板上形成一厚度過厚或厚度不均之金屬 ,導致後續在圖案化製程中形成導電線路及電性連接端 精度困擾,而無法形成一具細線路結構之電路板等缺失 而得以提供一具細線路(F i n e c i r c u i t)與高佈線密度之 路板結構。17660 Quan 懋 .ptd Page 15 Wuchengtong and Baoke can be connected to electricity. The blind electricity needs to be borrowed by this borrowing layer. 200533257, description of the invention (6) on the plated through hole; a metal protective layer is coated on the plated The upper surface of the electrical connection terminal on the via hole and the upper surface sides of the remaining electrical connection terminals; and a patterned solder mask layer formed on the surface of the circuit board so that the solder mask layer has a plurality of openings. The electrical connection end which exposes the electrical connection end and at least one opening corresponding to the end of the plated through hole can be reinforced by the metal protection layer of the solder resist layer covering portion to effectively adhere to the metal protection layer. The electrical connection terminal. The core board is a multi-layer circuit board that has completed the previous process. Therefore, with the circuit board structure and the manufacturing method of the present invention, it is optional to form the electrical connection terminal on a part of the plated through-holes where the electrical connection terminal is to be formed for subsequent connection with conductive elements, and to provide the circuit. The electrical connection between the board and other sub-components (semiconductor wafers or circuit boards), or a conductive layer (C ο nductivevia) of the circuit build-up structure can be formed at the electrical connection end of the plated through hole to reduce the habit When a conductive blind hole is formed, the space of the connection pad (P ad) is extended to increase the density and spirituality of the wiring, and shorten the conductive path, reduce inductance, crosstalk, and noise. In addition, the electricity on the plated through hole The electrical connection terminals are formed independently in the manufacturing process without affecting the remaining electrical connection terminals and conductive lines of the circuit board. This is to avoid the need to form the electrical connection terminals on the plated through holes in the conventional technology. An excessively thick or uneven thickness metal is formed on the top, resulting in subsequent difficulties in forming conductive lines and electrical connection ends in the patterning process, which prevents the formation of a thin Deletion circuit configuration of a circuit board or the like to provide a fine line (F i n e c i r c u i t) and high-density wiring board structure.
17660全想.ptd 第16頁 200533257 五、發明說明(7) 【實施方式】 以下係藉由特定的具體實施例說明本發明之實施方式 ,熟習此技藝之人士可由本說明書所揭示之内容輕易地瞭 解本發明之其他優點與功效。本發明亦可藉由其他不同的 具體實施例加以施行或應用,本說明書中的各項細節亦可 基於不同觀點與應用,在不悖離本發明之精神下進行各種 修飾與變更。 以下即以第2A圖至第2M圖詳細說明本發明之電路板結 構及其製法之較佳實施例。其中,須注意的是,該等圖式 均為簡化之示意圖,僅以示意方式說明本發明之電路板架 構。惟該等圖式僅顯示與本發明有關之元件,其所顯示之 元件非為實際實施時之態樣,其實際實施時之元件數目、 形狀及尺寸比例為一種選擇性之設計,且其元件佈局型態 可能更行複雜。 如第2 A及2 B圖所示,首先,提供一表面形成有金屬薄 層之芯層板2 0,該芯層板2 0亦可為一完成前處理之多層電 路板。於本實施例之圖式中,該芯層板2 0係由一絕緣層 2 0 0及形成於該絕緣層2 0 0表面之金屬薄層2 0 1所構成;復 以機械或雷射鑽孔等方式於該芯層板2 0中鑽設多個貫穿孔 2 0 2 (如第2 B圖所示)。其中,該絕緣層2 0 0可為環氧樹脂 (Epoxy resin)、聚乙醯胺(Polyimide)、氰 S旨(Cyanate Ester)、玻璃纖維、雙順丁烯二酸醯亞胺/三氮阱( B i s m a 1 e i m i d e T r i a z i n e,B T )或混合環氧樹脂與玻璃纖維 之F R 5材質所製成,該金屬薄層2 0 1—般係以導電性較佳之17660 全 想 .ptd Page 16 200533257 V. Description of the Invention (7) [Embodiments] The following is a description of specific embodiments of the present invention. Those skilled in the art can easily read the contents disclosed in this specification. Learn about other advantages and effects of the present invention. The present invention can also be implemented or applied by other different specific embodiments, and various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the spirit of the present invention. Hereinafter, the preferred embodiments of the circuit board structure and the manufacturing method of the present invention will be described in detail with reference to FIGS. 2A to 2M. It should be noted that these drawings are simplified schematic diagrams, and the circuit board structure of the present invention is only illustrated schematically. However, the drawings only show the elements related to the present invention. The elements shown are not the actual implementation. The number, shape, and size ratio of the elements during actual implementation are an optional design. The layout pattern may be more complicated. As shown in FIGS. 2A and 2B, first, a core board 20 having a thin metal layer formed on its surface is provided. The core board 20 may also be a multilayer circuit board that has been subjected to pretreatment. In the drawing of this embodiment, the core layer board 20 is composed of an insulating layer 200 and a thin metal layer 2 01 formed on the surface of the insulating layer 200; further, a mechanical or laser drill is used. A plurality of through holes 2 0 2 are drilled in the core layer plate 20 in a manner such as holes (as shown in FIG. 2B). Wherein, the insulating layer 200 may be epoxy resin, Polyimide, Cyanate Ester, glass fiber, bismaleimide / imide / triazine trap. (B isma 1 eimide Triazine, BT) or FR 5 material mixed with epoxy resin and glass fiber, the metal thin layer 2 0 1-generally is better conductive
17660 全懋.ptd 第17頁 ¥?1 200533257 五、發明說明(8) 銅(Cu )為主,以作為訊號傳遞的導線材料,且該金屬薄層 2 0 1可先壓合或沉積於該絕緣層2 0 0上,或使用樹脂壓合銅 箔(Resin coated copper,RCC)予以製作。本實施例採用 一樹脂壓合銅落(RCC)為例進行說明。 如第2 C圖所示,接著,利用物理氣相沈積(P VD )、化 學氣相沈積(CVD )、無電電鍍或化學沈積等方式,例如濺 鏡(Sputtering)、蒸鍵(Evaporation)、電弧蒸氣沈 積(Arc vapor deposition)、離子束濺鑛(Ion beam sputter ing)、雷射熔散沈積(Laser ab 1 at i on 參posit ion)、電漿促進之化學氣相沈積或無電電鍍等, 以於該芯層板2 0及其貫穿孔2 0 2表面形成一導電層(未圖 示),俾藉由該導電層作為電流傳導路徑,以在該芯層板 2 0表面上以及於該貫穿孔2 0 2孔壁上電鍍形成有一具足夠 厚度之金屬層203。 如第2 D圖所示,復以〆填充材2 0 4 (如油墨樹脂等)填 滿該貫穿孔2 0 2,俾形成,電鍵導通孔(PTH ) 2 0 5,藉以電 性導通該芯層板2 0上下表面之金屬層2 0 3。 接著,於顯露出該芯層板2 0之電鍵導通孔2 0 5端部表 面形成一導電層。其可於該怒層板2 〇上進行直接鍵覆方式 direct plating, DP)等製程,以在該芯層板之表面上形 成一例如把(p d )之導電膜2 〇 3 a,再經化學剝除製程’以使 該鈀金屬層依附於該電鍍導通孔2 0 5之填充材2 0 4端部表面 ,亦或進行化學銅等製移’以使該電鑛導通孔2 〇 5之填充 材2 0 4端部表面覆蓋有一導電膜2 0 3 a ;此外’如第2 D ’圖所17660 Quan 懋 .ptd Page 17 ¥ 1 200533257 V. Description of the invention (8) Copper (Cu) is mainly used as a signal transmission wire material, and the thin metal layer 2 01 can be first laminated or deposited thereon. The insulating layer 200 is formed on the insulating layer 200 or is made of resin-coated copper foil (RCC). This embodiment is described by using a resin-compressed copper drop (RCC) as an example. As shown in Figure 2C, next, physical vapor deposition (PVD), chemical vapor deposition (CVD), electroless plating, or chemical deposition are used, such as sputtering, evaporation, and arcing. Arc vapor deposition, Ion beam sputter ing, Laser ab 1 at i on posit ion, plasma-assisted chemical vapor deposition or electroless plating, etc. A conductive layer (not shown) is formed on the surface of the core board 20 and its through-holes 202, and the conductive layer is used as a current conduction path to pass on the surface of the core board 20 and the through-holes. A metal layer 203 having a sufficient thickness is formed on the hole wall by electroplating. As shown in FIG. 2D, the through hole 2 0 2 (such as an ink resin) is filled with a gadolinium filler material (such as an ink resin) to form a key hole (PTH) 2 0 5 to electrically conduct the core. The metal layers 2 0 3 on the upper and lower surfaces of the layer 2 0. Next, a conductive layer is formed on the surface of the end of the key via 250 that exposes the core board 20. It can perform processes such as direct plating (DP) on the laminated board 20 to form a conductive film 2 0a on the surface of the core board such as (pd), and then chemically Stripping process 'to make the palladium metal layer adhere to the end surface of the filling material 204 of the plated through hole 205, or to perform chemical copper etc.' to fill the electric mine through hole 205 The surface of the end of the material 2 0 4 is covered with a conductive film 2 0 3 a; in addition, as shown in FIG. 2 D
17660 全懋.ptd 第18頁 20053325717660 懋 .ptd page 18 200533257
五、發明說明(9) 示,亦可透過無電% 一導電層(未圖示、i錢等方式先在該怒層板20之表面形成 M ^ ^ ^ aw h俾藉由該導電層作為電流傳導路徑, 以在該芯層板2 0表而^ _ 面(包含該電鍍導通孔2 0 5之填充材204 端部)上電鍍形成一仏h t γ r h、曾十$威0,γ后#、s ^ 例如銅(C u )之導電薄層2 1 (厚度通常 可為3至10/z m)。其中,該電鍍導通孔2 0 5之填充材204 端部表面所形成之導電薄層2丨或導電膜2 〇 3 a,主要係作為 電流傳導路徑,俾於後續進行電鍍製程時,得以選擇性在 該電鍍導通孔2 0 5上形成有電鍍金屬層。以下後續製程說 明,主要係以在該芯層板2 0上形成一可例如鈀或銅之導電 膜2 0 3 a加以說明,而於該電鍍導通孔2 0 5之填充材2 0 4端部 覆蓋一電鍍銅之方式,其後續製程方式係相近於以下所述 之製程步驟,故於此不再多所贅述,先予敘明。 如第2 E圖所示,圖案化該芯層板表面之金屬層以形成 一圖案化線路。其係可於該芯層板2 0上形成一例如乾膜或 光阻之阻層(未圖示),並經過曝光(Exposure)、顯影 (D e v e 1 〇 p m e n t )等製程,以使該阻層形成有多數開口以外 露出該芯層板2 0之表面金屬層,俾經由蝕刻製程以移除未 為該阻層所覆蓋之金屬層部分,藉以形成一圖案化線路2 2 如第2 F圖所示,於該具圖案化線路2 2之芯層板2 0上形 成一導電膜23,該導電膜2 3主要作為後述進行電鍍金屬層 所需之電流傳導路徑,其可由金屬、合金或堆疊數層金屬 層所構成,並可選自銅、錫、鎳、鉻、鈦、銅—鉻合金所 構成之組群之金屬所形、成。該導電膜2 3可藉由物理氣相沈V. Description of the invention (9) shows that it is also possible to form M ^ ^ ^ aw h through the conductive layer (not shown, i money, etc.) on this surface. The conductive path is formed on the surface of the core board 20 and the surface of the core plate (including the end of the filler 204 of the plated through-holes 205) to form a 仏 ht γ rh, Zeng Shiweiwei 0, γ 后 # , S ^ For example, a conductive thin layer 2 1 of copper (C u) (thickness may be generally 3 to 10 / zm). Among them, the conductive thin layer 2 formed on the end surface of the filling material 204 of the plated through hole 2 0 5丨 or conductive film 2 03a, which is mainly used as a current conduction path, and can be selectively formed with a plated metal layer on the plated through hole 205 during the subsequent plating process. The following description of the subsequent process is mainly based on A method of forming a conductive film 2 0 3 a which can be, for example, palladium or copper is formed on the core layer board 20, and an end of a filling material 2 0 4 of the plated through hole 2 0 5 is covered with a plated copper method. The subsequent process method is similar to the process steps described below, so it will not be repeated here, and will be described first. As shown in Figure 2E The metal layer on the surface of the core board is patterned to form a patterned circuit. A resist layer (not shown) such as a dry film or a photoresist can be formed on the core board 20 and exposed ( Exposure), development (Development), etc., so that the resist layer is formed with a metal layer on the surface of the core board 20 outside the majority of the opening, and an etching process is performed to remove the resist layer that is not covered by the resist layer. As shown in FIG. 2F, a conductive film 23 is formed on the core layer board 20 of the patterned circuit 22, and the conductive film 23 is mainly described later. The current conducting path required for the electroplated metal layer may be composed of metal, alloy or stacked metal layers, and may be selected from the group consisting of copper, tin, nickel, chromium, titanium, copper-chromium alloy The conductive film 23 can be formed by physical vapor deposition.
200533257 五、發明說明(10) 積(P V D )、化學氣相沈積(C V D )、無電電鍍或化學沈積等方 式形成’例如藏鑛(Sputtering)、蒸錢(Evaporation)、 電弧蒸氣沈積(Arc vapor d epos i t ion)、離子束濺鍍(Ion beam sputtering)、雷射溶散沈積(Laser ablation deposition)、電漿促進之化學氣相沈積或無電電鍍等方 法形成。惟依實際操作的經驗,該導電膜2 3較佳係由無電 鏡銅粒子所構成。 如第2 G圖所示,於該導電膜2 3上形成一第一圖案化阻 層2 4,俾使該阻層2 4形成有複數個開口 2 4 0以外露出該圖 籲化線路2 2之欲形成電性連接端部分,且至少一阻層開口 2 4 0係選擇性外露出該電鍍導通孔2 0 5端部。該些阻層開口 2 4 0即係用以外露出後續作為電路板之電性連接端.部分。 該阻層2 4可為一乾膜或光阻,以供後續進行電鐘製程時作 為電鍍阻層之用。 如第2 Η圖所示,移除未為該第一圖案化阻層2 4所覆蓋 之導電膜23部分。 如第2 I圖所示,在該芯層板上形成一第二圖案化阻層 2 5,以覆蓋住殘露於該第一阻層開口 2 4 0内之導電膜2 3。 如第2 J圖所示,在該芯層板2 〇上形成一第三阻層2 6, 淨覆蓋住位於該電鍍導通孔2 0 5以外之第一圖案化阻層開 口 2 4 0,並進行電鍍製程,以在外露出該第二圖案化阻層 2 5之該電鍍導通孔2 0 5端部上形成一金屬層,如此,即可 選擇性在部分之電鍍導通孔2 〇 5上直接形成一供後續作用 為電性連接端2 7之金屬層。其中,由於該電鍍金屬層僅係200533257 V. Description of the invention (10) PVD, chemical vapor deposition (CVD), electroless plating or chemical deposition and other methods to form 'such as Sputtering, Evaporation, Arc vapor d epos it ion), ion beam sputtering, laser ablation deposition, plasma-assisted chemical vapor deposition, or electroless plating. However, according to actual operation experience, the conductive film 23 is preferably composed of copper particles without a mirror. As shown in FIG. 2G, a first patterned resist layer 2 4 is formed on the conductive film 23, and the resist layer 24 is formed with a plurality of openings 2 4 0 to expose the patterned circuit 2 2 An electrical connection end portion is to be formed, and at least one resistance layer opening 240 is to selectively expose the end of the plated through hole 205. The openings of these resistance layers 240 are used to expose the subsequent electrical connection ends of the circuit board. The resist layer 24 can be a dry film or a photoresist, which can be used as a plating resist layer in the subsequent clock process. As shown in FIG. 2, the portion of the conductive film 23 that is not covered by the first patterned resist layer 24 is removed. As shown in FIG. 2I, a second patterned resist layer 25 is formed on the core layer board to cover the conductive film 23 remaining inside the first resist layer opening 240. As shown in FIG. 2J, a third resistive layer 26 is formed on the core layer board 20, and the first patterned resistive layer opening 2 4 0 located outside the plated through hole 2 05 is cleanly covered, and A plating process is performed to form a metal layer on the end of the plated through hole 205 where the second patterned resist layer 25 is exposed. In this way, a portion of the plated through hole 205 can be selectively formed directly. A metal layer for subsequent use as an electrical connection terminal 27. Among them, since the electroplated metal layer is only
17660 全懋.ptd 第20頁 200533257 五、發明說明(11) 選擇性形成於部分該電鍍導通孔2 0 5上,因此除了可在電 鍍導通孔2 0 5上形成有外,同時又可在芯層板其餘區域上 形成有圖案化之細線路。 如第2 K圖所示,在該電鍍導通孔2 0 5上形成電性連接 端2 7後,即可將該第三阻層2 6移除,俾將該芯層板表面之 圖案化線路中欲作為電性連接端2 2 1之部分顯露於第一圖 案化阻層開口 2 4 0。 如第2 L圖所示,進行電鍍製程以在顯露出該第一圖案 化阻層開口 2 4 0中之電性連接端2 7、2 2 1表面上形成一金屬 保護層2 8,如鎳/金金屬層,俾藉由該金屬保護層2 8可提 供電性連接端有效與導電元件(如銲線、錫球、或金屬凸 塊等)電性連接。 如第2 Μ圖所示,接著,移除該第二圖案化阻層、第一 圖案化阻層、以及覆蓋其下之導電膜,然後再形成一圖案 化拒銲層2 9,俾外露出該電性連接端2 7、2 2 1表面之部分 金屬保護層2 8。 此外,請參閱第2 Μ ’圖,其係如先前第2 D ’圖所示,在 該芯層板2 0之表面(包含該電鍍導通孔2 0 5之填充材2 0 4端 部)形成一如銅(Cu )之導電薄層2 1時,復經由前述製程以 選擇性在部分電鍍導通孔2 0 5上形成供後續作用為電性連 接端2 7之金屬層,並在電性連接端2 7表面形成有金屬保護 層2 8,所製得之一電路板結構。 如第2 Μ及2 Μ ’圖所示,透過前述製程,本發明亦揭示 一種電路板結構,係包括有一芯層板2 0,其表面形成有圖17660 Quan 懋 .ptd Page 20 200533257 V. Description of the invention (11) It is selectively formed on part of the plated through hole 2 05, so in addition to being formed on the plated through hole 2 05, it can also be formed on the core at the same time. Patterned fine lines are formed on the remaining areas of the laminate. As shown in FIG. 2K, after the electrical connection terminal 27 is formed on the plated through-hole 250, the third resistance layer 26 can be removed, and the patterned circuit on the surface of the core layer board can be removed. The portion which is intended to be the electrical connection terminal 2 2 1 is exposed in the first patterned resist layer opening 2 4 0. As shown in FIG. 2L, a plating process is performed to form a metal protective layer 28 on the surface of the electrical connection terminals 2 7, 2 2 1 exposed in the first patterned resist opening 2 4 0, such as nickel. / A gold metal layer, through which the metal protective layer 28 can provide an electrical connection end to be effectively connected to a conductive element (such as a wire, a solder ball, or a metal bump, etc.). As shown in FIG. 2M, the second patterned resist layer, the first patterned resist layer, and a conductive film covering the second patterned resist layer are removed, and then a patterned solder resist layer 29 is formed, and the outer surface is exposed. A part of the metal protective layer 28 on the surface of the electrical connection terminals 27 and 2 2 1. In addition, please refer to FIG. 2M ′, which is formed on the surface of the core board 20 (the end of the filler material 2 0 4 including the plated-through holes 2 0 5) as shown in the previous 2 D ′ drawing. When the thin conductive layer 21 is copper (Cu), the foregoing process is used to selectively form a metal layer on a part of the plated through hole 2 0 5 for subsequent use as an electrical connection terminal 2 7 and electrically connect A metal protective layer 28 is formed on the surface of the terminal 27, and a circuit board structure is obtained. As shown in Figs. 2M and 2M ', through the foregoing process, the present invention also discloses a circuit board structure including a core layer board 20 with a pattern formed on its surface.
17660 全懋.ptd 第21頁 200533257 五、發明說明C12) 案化線路22與多數貫穿該忽層板20之電锻導通孔205 ’其 Ϊ ,至少一電性連接端係形成於該電锻導通孔2 0 5上;一 1金屬保護層2 8,係包覆於該電鍛導通孔2 〇 5上之電性連接 端之上表面以及其餘電性連接端之上表面與側邊;以及一 圖案化拒銲層2 9,係形成在該芯層板表面上’俾使該拒銲 層2 9形成有複數個開口以外露出該圖案化線路2 2之電性連 接端2 7、2 2 1,且至少一開口係對應至該電鍍導通孔2 0 5端 部之電性連接端,以藉由該拒銲層2 9包覆部分之金屬保護 層2 8,而強化該金屬保護層2 8得以有效附著於該電性連接 _27上。 其中,該電鍍導通孔2 〇 5上之電性連接端2 7上表面係 覆蓋有一如鎳/金之金屬保護層2 8,而在其餘電性連接端 2 2 1之上表面及側邊係完整覆蓋有金屬保護層2 8,之後才 於該完成有金屬保護層2 8之圖案化線路結構上形成一拒銲 層29。 此外,如第3圖所示,在芯層板30中之電鍍導通孔3〇 5 之端部形成有電性連接端後,亦可作為後續線路增層結構 31中承接導電盲孔32用,俾得以直接在該電鍍導通^ 3〇5 上形成導電盲孔32,如此,即可減少承接導電盲孔32之電 參連接端之設置與接線所佔電路板空間,縮短導電、余%, 且有效增加線路佈設空間’提升線路佈局靈活声 ^位 復可持續進行線路增層製程,俾形成一呈=^ ’之後’ 之電路板結構。 成具有多層線路結構 另,雖本發明先前之圖示係以雙層板作為說明,本發17660 Quan 懋 .ptd Page 21 200533257 V. Description of the invention C12) The patterned circuit 22 and most of the electroforged vias 205 'through which the laminated board 20 passes, at least one electrical connection end is formed in the electroforged via A hole 2 0 5; a 1 metal protective layer 2 8 covers the upper surface of the electrical connection terminal and the upper surface and sides of the remaining electrical connection terminals on the electroforged via hole 2 05; and 1 The patterned solder resist layer 29 is formed on the surface of the core board, so that the solder resist layer 29 is formed with a plurality of openings to expose the electrical connection ends 2 of the patterned circuit 2 2 and 7, 2 2 1 And at least one opening is an electrical connection end corresponding to the end of the plated through hole 205, so as to strengthen the metal protection layer 28 by covering the metal protection layer 28 of the solder resist layer 29. Can be effectively attached to the electrical connection _27. Among them, the upper surface of the electrical connection terminal 27 on the plated-through hole 2 05 is covered with a metal protective layer 28 such as nickel / gold, and the upper surface and side edges of the remaining electrical connection terminals 2 2 1 are The metal protective layer 28 is completely covered, and then a solder resist layer 29 is formed on the patterned circuit structure with the metal protective layer 28 completed. In addition, as shown in FIG. 3, after the electrical connection end is formed at the end of the plated-through hole 305 in the core layer board 30, it can also be used to receive the conductive blind hole 32 in the subsequent layer buildup structure 31.俾 It is possible to directly form a conductive blind hole 32 on the electroplating continuity 305, so that the space of the circuit board occupied by the setting and connection of the electrical parameter connection end of the conductive blind hole 32 can be reduced, and the conductivity and the remaining percentage can be shortened. Effectively increase the space for circuit layout 'Improve the flexibility of the layout of the circuit ^ Continue to carry out the process of adding layers to the circuit, and form a circuit board structure that is equal to' ^ '. In addition, although the previous illustration of the present invention uses a double-layer board as an illustration, the present invention
200533257 五、發明說明(13) 明之製程亦可應用於多層板中,亦即先前圖式之該芯層板 係可為一已完成前段製程之多層板,即可依前述製程形成 一具多層線路結構之電路板結構,如第4A圖及4B圖所示, 係為應用本發明前述製程所得之具四層線路結構之電路板 4 0 A,以及具六層線路結構之電路板4 0 B。當然本發明之應 用非侷限於前述之二層、四層、或六層電路板,實際係可 應用於任一具多層線路結構之電路板。 因此,藉由本發明之電路板結構及其製法,係可選擇 性在部分欲形成電性連接端之電鍍導通孔上形成該電性連 接端,以供後續接置有導電元件以提供該電路板與其他電 子元件(半導體晶片或電路板)之電性導接,亦或可於該 電鍍導通孔上之電性連接端形成有線路增層結構之導電盲 孔,以及減少習知形成導電盲孔(Conduct i ve v i a)時, 所需延伸出連接墊(Pad)之空間,藉以增加佈線路密度 與靈活性,並可縮短導電路徑,減少電感、串擾及雜訊產 生;此外,該電鍍導通孔上之電性連接端於製程中係獨立 形成,而不影響該電路板其餘電性連接端及導電線路之製 程,藉以避免習知技術中在電鍍導通孔上欲形成電性連接 端時,必需在整體電路板上形成一厚度過厚或厚度不均之 金屬層,導致後續在圖案化製程中形成導電線路及電性連 接端之精度困擾,而無法形成一細線路結構等缺失,俾提 供一具細線路(F i n e C i r c u i t)與高佈線密度之電路板結 構。 以上所述僅為本發明之較佳實施例而已,並非用以限200533257 V. Description of the invention (13) The process of the invention can also be applied to multilayer boards, that is, the core board of the previous diagram can be a multilayer board that has completed the previous process, and a multilayer circuit can be formed according to the aforementioned process The structure of the circuit board structure, as shown in FIG. 4A and FIG. 4B, is a circuit board 40 A with a four-layer circuit structure and a circuit board 400 B with a six-layer circuit structure obtained by applying the foregoing process of the present invention. Of course, the application of the present invention is not limited to the aforementioned two-layer, four-layer, or six-layer circuit board, but it can be applied to any circuit board with a multilayer circuit structure. Therefore, with the circuit board structure and the manufacturing method of the present invention, the electrical connection terminal can be selectively formed on a part of the plated through-holes where the electrical connection terminal is to be formed, so that a conductive element is subsequently connected to provide the circuit board. Electrically conductive connection with other electronic components (semiconductor wafers or circuit boards), or conductive blind holes with a layer build-up structure can be formed at the electrical connection ends of the plated vias, and the formation of conductive blind holes can be reduced. (Conduct i ve via), it is necessary to extend the space of the pad to increase the density and flexibility of the wiring, shorten the conductive path, reduce inductance, crosstalk, and noise; in addition, the plated via The above electrical connection terminals are formed independently in the manufacturing process without affecting the process of the remaining electrical connection terminals and conductive lines of the circuit board. In order to avoid the formation of electrical connection terminals on the plated through holes in the conventional technology, it is necessary to A metal layer with an excessively thick or uneven thickness is formed on the overall circuit board, which causes the subsequent precision of forming conductive lines and electrical connection terminals in the patterning process, and A method of forming a fine wiring structure deletion, serve to provide a fine line (F i n e C i r c u i t) and high-density wiring circuit board construction. The above descriptions are merely preferred embodiments of the present invention, and are not intended to be limiting.
17660 全懋.ptd 第23頁 200533257 五、發明說明(14) 定本發明之實質技術内容範圍,本發明之實質技術内容係 廣義地定義於下述之申請專利範圍中,任何他人完成之技 術實體或方法,若是與下述之申請專利範圍所定義者係完 全相同,亦或為同一等效變更,均將被視為涵蓋於此申請 專利範圍中。17660 Quan 懋 .ptd Page 23 200533257 V. Description of the invention (14) The scope of the essential technical content of the present invention is defined broadly within the scope of the patent application described below. Any technical entity completed by others or If the method is exactly the same as defined in the patent application scope described below, or the same equivalent change, it will be considered to be covered by this patent application scope.
17660 全懋.ptd 第24頁 200533257 圖式簡單說明 【圖式簡單說明】 第1 A圖至第1 C圖係習知之半加成法的電路板結構製作 流程不意圖, 第2 A圖至第2 Μ圖係本發明之電路板結構製法之製程剖 面示意圖; 第2 D ’圖及第2 Μ ’圖係本發明之電路板結構製法另一實 施態樣之剖面示意圖; 第3圖係本發明之電路板結構製法應用於增層結構之 剖面示意圖;以及 第4 Α圖及第4 Β圖係本發明之電路板結構製法應用於多 層板之剖面示意圖。 10 核心電路板 11 絕緣層 110 開孔 12 内層線路層 13 晶種層 14 阻層 1 5 圖案化線路層 2 0 芯層板 2 0 0 絕緣層 201 金屬薄層 2 0 2 貫穿孔 2 0 3 金屬層17660 Quan 懋 .ptd Page 24 200533257 Simple description of the drawings [Simplified illustration of the drawings] Figures 1A to 1C are the conventional semi-additive circuit board structure manufacturing process, which is not intended. Figures 2A to 2 Figure 2M is a schematic sectional view of the manufacturing process of the circuit board structure manufacturing method of the present invention; Figures 2D 'and 2M' are schematic sectional views of another embodiment of the circuit board structure manufacturing method of the present invention; Figure 3 is the present invention A schematic cross-sectional view of the circuit board structure manufacturing method applied to the build-up structure; and FIGS. 4A and 4B are schematic cross-sectional views of the circuit board structure manufacturing method of the present invention applied to the multilayer board. 10 Core circuit board 11 Insulating layer 110 Opening hole 12 Inner circuit layer 13 Seed layer 14 Resistive layer 1 5 Patterned circuit layer 2 0 Core board 2 0 0 Insulation layer 201 Thin metal layer 2 0 2 Through hole 2 0 3 Metal Floor
17660 全懋.ptd 第25頁 200533257 圖式簡單說明 2 0 3a導電膜 2 0 4 填充材 2 0 5 電鍍導通孔 21 導電薄層 22 圖案化線路 221 電性連接端 23 導電膜 2 4 阻層 24 0 阻層開口 _ 阻層 2 6 阻層 27 電性連接端 2 8 金屬保護層 2 9 拒焊層 3 0 芯層板 3 0 5 電鑛導通孔 31 線路增層結構 32 導電盲孔 40A 四層電路板 ft B六層電路板17660 Quan 懋 .ptd Page 25 200533257 Brief description of the diagram 2 0 3a conductive film 2 0 4 filling material 2 0 5 plated through hole 21 conductive thin layer 22 patterned circuit 221 electrical connection end 23 conductive film 2 4 resist layer 24 0 Resistive layer opening_ Resistive layer 2 6 Resistive layer 27 Electrical connection terminal 2 8 Metal protective layer 2 9 Solder resist layer 3 0 Core board 3 0 5 Electrical vias 31 Line build-up structure 32 Conductive blind hole 40A Four layers Circuit board ft B six-layer circuit board
17660全懋.ptd 第26頁17660 懋 .ptd Page 26
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