TW200531429A - Class-D amplifier - Google Patents

Abstract

A class-D amplifier includes: an operational amplifier and capacitors, which constitute an integrator for integrating a difference between a plus-sided input signal and a minus-sided input signal which constitute analog input signals; delay circuits for delaying a phase of a triangular wave by a desirable very small angle; resistors, which constitute a synthesizing circuit for synthesizing an output of the integrator, the triangular wave, and outputs of the delay circuits with each other; comparators for comparing outputs of the synthesizing circuit with each other; AND circuits which constitute a buffer for inputting outputs of the comparators; and resistors feeding back an output of the buffer to an input side of the integrator.

Description

200531429 IX. Description of the invention: [Technical field to which the invention belongs] The present invention relates to a class D amplifier. [Previous technology] D display amplification is to perform power amplification through pulsed signal modulation (pUlse_width-m0duiating; PWM), and is used to perform power amplification of audio signals as a traditional class D amplifier, a type of such class D amplifier. The amplifier is configured as an integrator for integrating an analog input signal, a comparator for comparing the output signal of the integrator with a predetermined triangle wave, and a buffer for amplifying the output signal of the comparator to output a pulse signal (pulse amplifier ). This traditional D 颍 is amplified to medium, and the pulse signal output from the buffer is fed back to the input side of the integrator. A low-pass filter constructed by the coil and capacitor then filters the output signal of the buffer to obtain an analog signal that drives a load (such as a speaker). As a traditional pulse-width modulation amplifier, one such PWM amplifier is configured as a comparator for comparing an analog input signal with a triangular wave, an amplifier for amplifying an output of a specific car, and an inversion between the amplifier and a load. Jie (for example, 'refer to Japanese Patent Publication No. Sho-56-27001'). In addition, 'as a traditional digital amplifier circuit using a digital signal processing circuit, one such digital amplifier circuit is equipped with a noise shaper, a converter, a switch, a switch, and a filter and a wave filter (for example, reference Japanese Patent Publication No. 2000-5050625). The noise shaper performs frequency shaping on the quantization noise of the digital input signal. The converter converts the PCM (Pulse Code Modulation) signal corresponding to the output of the noise shaper into a PWM (Pulse Width Modulation) signal 95456.doc 200531429. Logic 轾 + q々, upper ^ The linearity of the turn-out signal of the complement detection switch. The switch is controlled by the wheel of the logic circuit-unique. The switch connects the input side of the filter to the power supply. ..., 'In the above-mentioned conventional class D amplifier, the buffer is composed of two buffers, a P-side buffer and a minus-side buffer. Even when there is no input signal. Wait for the two buffers to output signals with opposite polarities. The load ratio is 50%. Therefore, in a conventional class 0 amplifier, even in the case where there is no input signal, the current can pass through the low-pass filter, which causes a large loss. In Japanese Patent Publication No. Sho_56_27001, the technical idea of turning off the output amplifying element at the day of no input t is described in order to avoid the power loss when there is no input letter 2. However, the conventional pulsed visibility amplifier described in the above Patent Publication 1 has a problem in that a transformer is required to convert the impedance and cut off the DC voltage ', which increases the scale of the equipment and increases its cost. In addition, the conventional pulse-width-modulated k-amplifier described in Japanese Patent Laid-Open No. Sho-56-27001 has another problem, that is, the distortion of the triangle signal and the input h-number 'output signal is relatively large because the comparator is simple. On the other hand, the digital amplifier circuit described in Japanese Patent Laid-Open No. 2000-500625 uses three-value or four-value (switching state) output complaints, sub-amplifies digital input signals, and digital circuits such as logic circuits are used for Improve linearity. Therefore, the digital amplifying circuit described in Japanese Patent Disclosure No. 2000-5005625 has a problem in that since this digital amplifying circuit cannot be configured by using an analog circuit, it is impossible to amplify the analog turn-in signal at the same time. Keep it better linear. In other words, in this conventional digital amplifier circuit, when a smaller signal pulse is input, the output switching distortion in the compensation circuit is compensated because a compensation pulse is added to the smaller signal pulse. However, this circuit for compensating < output output distortion is constructed only by using digital circuits such as logic circuits ' so the traditional digital amplifier circuit cannot amplify the analog input signal under better linear conditions. [Summary of the Invention] This month, the above-mentioned problems are solved, so a class D amplifier capable of operating with low distortion and small power loss will be provided. In addition, the present invention will provide a Class D amplifier that can operate with low distortion and low power loss, while not using a transformer. In addition, the present invention will provide a class D amplifier capable of reducing the DC voltage component in its output to zero volts on the babe. To solve the above problems, the class D amplifier of the present invention has the following structure. (1) A class D amplifier, which includes: an integral gain, which integrates analog input signals; a -th comparator, which compares one of the integrator outputs with a triangle wave; a second comparator, which compares the Wave, the second triangle wave is equal to an angle (180 degrees plus a minimum angle waveform; the output of the product and a second r: angle shifts one of the first triangle waves, or a minimum negative angle) The obtained __ is based on the output of one of the comparators and the second taste: output output—the plus-side output signal and a minus-side output signal; a circuit that combines the plus-side round-out signal with the One of the subtractive losses is fed back to one of the input sides of the integrator. 95456.doc 200531429 (2) According to (1), Class D Fangshitu, Gu ^ Di Da Yi, where the buffer includes:-brother-buffer 'which calculates the first comparator of the round-comparator The logical output of the output is calculated using one of the rounds; one of the two: and the second one; and · ,,, and ^ minus the side-wheel outgoing letter-the second buffer, which calculates the. ^ Σσ σσ 疋 * ϋ 海 output Ik Xi Zeng—a logical product of the output that is better than Che Fuyi—takes the output as: one of the two calculation results. ϋ Side output letter (3) Class D put female $ # ^ > Female cry "" according to (1), wherein the feedback circuit includes a differential-differential. (4) A Class D amplifier between the side input signal and the subtracted output signal includes: a plus input signal and an integrator that integrates a difference between an analog input signal and a subtracted input signal ; A delay circuit, will be one or two degrees; ,, = angular wave-phase delay-predetermined minimum angle-synthesis circuit, which outputs one of the integrator, the triangle wave delay circuit-output to each other to output The plurality of outputs are numbered.-When the comparator 'its multiple outputs of the synthesis circuit; the number each other-the buffer' its input is one of the outputs of the comparator; and one of its outputs is fed back to one of the integrators. A feedback circuit, which buffers the input side of the device, wherein: (5) the class D amplification according to (4). The angular wave is composed of a first triangular wave and a first angular wave. The 95456.doc -9- 200531429 triangular wave Corresponding to a waveform generated by shifting one phase of the first triangular wave by an angle of 180 degrees; the delay circuit includes a first delay circuit for delaying the phase of the first triangular wave by the predetermined Very small angle, and a first A delay circuit for delaying a phase of the third triangular wave by the predetermined minimum angle; the synthesizing circuit synthesizes the subtracted side output of the integrator and the first triangular wave to generate a first synthesized wave; synthesizes the integral Synthesizing the plus-side output and the second triangular wave to generate a second synthesized wave; synthesizing the minus-side output of the integrator and an output of the second delay circuit to produce a third synthesized wave; and synthesizing the third The plus-side output of the integrator and an output of the first delay circuit to generate a fourth synthesized wave; the comparator includes a -th-compare n, which is used to compare the first-synthesized wave with the second synthesized wave And-a second comparator for comparing the third synthesized wave with the fourth synthesized wave; the buffer includes a -th-buffer for calculating an output of the first comparator and the first One of the two comparators-a logical product of the output; and a second buffer for calculating a logical product of the output of the first comparator and the output of the second car owner; and the feedback circuit Includes a first feedback , Which is used to feed the output of the first buffer to the plus-side input of the integrator; and a second ballast circuit, which is used to feed the output of the second buffer to the integrator (6) — Class D amplifier, which includes:-an integrator that adds one of the analog input signals to the plus input signal 95456.doc -10- 200531429 and a subtracted input signal Integrating. A synthesizing circuit that synthesizes one's output and a triangular wave, and occupies the output of the integrator and has a triangular wave with a phase opposite to that of the triangular wave. Round, '旻 several signals, where the two opposite-phase angular waves correspond to a waveform, 苴 ia ^ /, the phase is shifted 180 degrees with respect to the phase of the first-mentioned triangular wave; the output signals are compared with each other; And a comparative benefit of an output feedback to the integrator, which buffers one of the synthesizing circuits', which feeds one of the comparators to a feedback circuit, which inputs the buffer, and a plurality of resistors of two resistance values Such The resistance value and the complex numbers of the output of the comparison circuit, wherein the synthesizing circuit includes a circuit having at least one and configured to generate a phase difference between the signals corresponding to the synthesized signals based on an input capacitance of one of the plurality of resistors. (7) The class D amplifier according to (6), wherein:. . The synthesizing circuit includes: a first synthesizing section for synthesizing a subtracted side output of the integrator and the triangular wave to generate a first synthesizing wave; and a second synthesizing section for synthesizing one of the integrators. The plus side outputs a triangular wave with the opposite phase to generate a second synthesized wave; a third combining part for synthesizing the subtracted side output of the integrator and the opposite phase triangle wave to generate a third synthesized wave ; And-a fourth synthesizing section for synthesizing the plus-side output of the integrator and the triangular wave to generate a forty-eight percent wave; a terminal and the integral of the first synthesizing section including a first resistor 95456.doc -11-200531429 Jie Zhi's side-wheel out connection, and a second resistor in which the three-trend wave is applied to its _ _ mountain ~

/, 1U ☆ Erzi; and the other terminal of the first resistor is connected to the other terminal of the second lightning P ^ σσ so as to constitute an output terminal thereof; W _, the trowel includes a second resistor One of the terminals is connected to the integral side of the plus side wheel, and a fourth resistor, in which the three waves are applied to the complex—to ,,, and the sub; and the other of the third resistor One terminal is connected to the other terminal of the fourth thunder, so as to constitute an output terminal thereof; K ° Hi = the synthesis section includes a fifth resistor, one terminal of which is connected to the integral side of the integral side, and a first Six resistors in which one of the opposite < an angular wave is applied to one of its terminals; and one of the fifth resistors is connected to the other terminal of the sixth resistor to form one of its output terminals; cry 4 The four-combination part includes a seventh resistor, one terminal of which is connected to the integral, the Hega side output, and an eighth resistor, in which the triangular wave is applied to one of its terminals; and the seventh resistor The other terminal is connected to the eighth resistor The other terminal so as to constitute an output terminal thereof; the comparator includes a first-comparator having an input terminal connected to the first-combination part = the Hailun output terminal, and a second-combination part-two Another input terminal connected to the output terminal; and a second comparison, which has an input terminal connected to the output terminal of the third combining section, and another input terminal connected to the output terminal of the fourth combining section Input terminal;: the buffer includes a first buffer, which is used to calculate a logical product of the -round out of the first comparator and the output of one of the second comparators; and a 95456.doc -12- 200531429 brother A buffer, which is used for a logical product of the output of the first comparator and the output of the second comparator; a feedback product including a first-feedback circuit, It is used to feed back the output of the first device to the plus side input of the integrator; and a first feedback circuit is used to feed back the output of the second buffer to the integral: the minus side Input; and, suppress the first power The resistance value of the resistor, the second resistor, the second thunderstorm state, and any of the fourth resistors are different from the fifth resistor, the sixth resistor, and the seventh resistor. The resistor and the resistance value of one of the eighth resistance μ8 1 1.类 The class D amplifier according to (7), wherein the resistance value of each of the first resistor, the second resistor, the third resistor, and the fourth resistor is the fifth resistor A resistance value obtained by multiplying the resistance value of each of the sixth resistor, the seventh resistor, and the eighth resistor by a value other than 1. (9) A class D amplifier comprising: an integrator that integrates a difference between an input signal on the plus side and a input signal on the minus side of one of the analog input signals; a triangle wave generating circuit including a current source and A capacitor; a comparison benefit, which compares an output of the integrator with an output of the triangle wave generating circuit; a buffer, which inputs an output of the comparator; and a feedback circuit, which returns the output of the buffer To one of the input sides of the integrator. 95456.doc -13- 200531429 (10) The class D amplifier according to (9), in which Lu Hai Electric Valley's' terminal ^ terminal gold ^ is used for comparison and one of the input terminals is coincidentally connected, and The current source switches the output direction of one of the Thunder and the Star, so as to repeat the charging and discharging of the capacitor. (11) A class D amplifier according to (10), where one of the ends of the current source and the capacitor The one end is connected, and the current source flows a current in the negative direction of charging the capacitor when one potential of the capacitor is lower than a first potential, and the capacitor is driven along the capacitor when the potential of the capacitor is higher than a second potential. A current flows in one direction of the discharge, and a first potential of δ is set at the first potential. (12) Class D amplifier according to (9), wherein:. The Habib state includes a first comparator for comparing a subtracted side output of the integrator with the output of the triangle wave generating circuit, and a second comparison eight is used to compare one plus side output of the integrator. And the output of the triangle wave generating circuit, the buffer includes a first buffer for calculating a logical product of an inverted value of one output of the first comparator and an output of one of the second comparators, And a second buffer for calculating a logical product of an inverted value of the first comparator and one of the second comparators, and the feedback circuit includes a first feedback circuit for The output of the buffer buckle is fed back to a minus side input of the integrator, and a second feedback packet circuit is used to feed back one output of the second buffer to one plus side input of the integrator. According to the present invention, a class D amplifier capable of operating 95456.doc -14-200531429 with low distortion and small power loss can be provided. In addition, the present invention can provide a class D amplifier that can operate with low distortion and small power loss without using a transformer, and the DC voltage component in its output can be reduced to substantially zero volts. [Embodiment] Various specific embodiment modes of the present invention will now be described with reference to the drawings. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Fig. 1 is a circuit diagram showing a structural example of a class D amplifier according to a specific embodiment i of the present invention. This Class D amplifier is equipped with resistors R1, r2, r3, r4, R5, R6, R7, R8, R9, Ri0, RUAR12, capacitors C1 & C2, operational amplifier state 11, comparison 12 and 13, delay circuit 21 and 22. AND circuit (low activity) 31 and another -AND circuit 32. In this figure, the predetermined triangle wave signals "&" and "b" are respectively applied to one terminal of the resistor R9 & RU. The triangular wave signal "~" and the dihedral wave signal "b" are such signals having the same waveform, and their phases are different from each other by 180 degrees. One terminal of the resistors R1 and R2 respectively constitutes a differential input terminal of an analog input signal. Therefore, one terminal of the resistor ^ constitutes the plus-side input terminal (+ IN), and one terminal of the resistor R2 constitutes the minus-side input terminal (输入 ν). The op amp 11 and the capacitor ci & c2 constitute an integrator. This integrator integrates the analog input signals of resistor R2 and R2 that have been differentially input, and outputs the integrated signals to resistors R5, R6, R7, and R8. The resistors R5, R6, R7, R8, R9, R10, RU, and R12 form a synthesis circuit, which synthesizes the triangular wave signal "a," or "b," with the output of this integrator 95456.doc * 15-200531429 signal. The triangle wave signal "a" and "b 'are generated by delaying the triangle wave signal" a "and the triangle wave signal" h 0 "by a minimum angle" Θ "(that is, θ < < 180 degrees). This synthesis circuit generates the first There are a total of four synthetic waves c J, t "," g ", and" h "up to the fourth. The minus-side turn-out signal and the triangular wave signal "a" (the -triangular wave) of the operational amplifier u constituting the integrator are synthesized to generate the first-combined wave% ". A second synthetic wave "f" is generated by synthesizing the addition-side output signal and the triangular wave signal "b" (second triangular wave) of the operational amplifier that constitutes the integrator. A third composite wave "g" is generated by synthesizing the subtracted-side output signal of the operational amplifier u and the triangular wave signal, b "constituting the integrator. A fourth synthetic wave "dagger" is generated by synthesizing the addition-side output signal of the operational amplifier 11 constituting the integrator and the triangular wave signal "~" generated by the delayed triangular wave signal "a". The comparator 12 (first comparator) compares the first synthesized wave% "with the second synthesized wave" f "'to output-compare the result. When the first synthetic wave% "is greater than the second port and becomes 2 f"% 'the first comparator 12 outputs a predetermined "low" level signal (e.g., "quad level") and when the first-synthetic wave "e" is less than the first When the second composite wave is "f", the first comparator 12 outputs a predetermined "high" level signal. The comparator 13 (the -comparator) compares the third synthetic wave "g" with the fourth synthetic wave ~, to compare the results with the comparison results. When the second composite wave "g" is larger than the fourth composite wave "h", the second comparator 13 outputs a predetermined "low" level signal (for example, the zero level), and when the third composite wave "g" is smaller than the first In the case of quadrature wave ..., the second comparator 13 outputs a predetermined "high-level drought Lbl. Comparators 12 and 13 can also be implemented by using an operational amplifier. The Na circuit 31 corresponds to a delay of 95456 with a negative logic input function. .doc -16-200531429 Next, Na Jiaming-Na Liao (low activity), the output of Shiqi Seven Daggers is 12 and the output of the second comparator 13 is the factory low "4. This AND circuit 31 turns out" Ancient you

问 铷 问 出 问 ”level signal and output the result of this calculation as the minus side of this class D amplifier | ^ ψ“ 出 −〇UT ”. The resistor R3 forms a first feedback circuit. The first feedback circuit feeds back the output of the Na circuit 31 serving as a buffer to the addition side input of the operational amplifier liu. —The packet 32 corresponds to a buffer circuit with an AND calculation function. The AND calculation operation between the output of the% 12 and the output of the comparator 13 is then output to the plus-side output of the Class D amplifier + 〇 UT ". The resistor R4 constitutes a second feedback circuit. The second feedback circuit feeds back the output of the AND circuit 32 used as a positive return to the minus side input of the operational amplifier Η. Connect the load (speaker, etc.) through the low-pass ferrule between the plus-side output "+ _" of this Class D amplifier and its minus-side input -OUT. Because these circuit configurations are used, this class D amplifier can amplify the analog input with low distortion.

+ IN "and" _IN ", without using a transformer, can drive the negative cut while reducing power loss. Next, FIG. 2 to FIG. 4 illustrate examples of operation using the class D amplifier configured as described above according to this specific embodiment 1. As shown in FIG. 2 to 4 are waveform diagrams showing the operation of individual circuit portions of the class D amplifier shown in FIG. 1. FIG. Next, "Figure 2 shows that when the value of the analog input signal" pass "is equal to the value of the analog input signal" -IN ", that is, when the differential input becomes zero volts (no round-in signal), Waveforms of individual circuit sections. Figure 3 represents when (analog round-in signal "+ IN") > (analog input signal "_IN"), that is, when the differential input 95456.doc -17- 200531429 input becomes positive, the analogue of the class D amplifier (analog Input signal "+ IN") < (analog ^; ^ heart ° Figure 4 represents when the differential input becomes negative, W, "), that is, the waveform of the individual circuit part when the gain is amplified. First, the operation related to FIG. 2 (ie, a differenceless main / volt value input) will be explained. The triangle wave competition "the other f moon shape (the phase phase degree of zero T two" M. 'ua "constitutes this-signal generated by the triangle wave letter I Γ θ". The triangle static U "constitutes by The triangular wave signal "a" is delayed by the minimum angle "θ"; this signal is generated. In this case, the predetermined noise of "from> \% is dithering" is applied to the triangular wave signal a, a Each triangle wave η Lu · ^ will dither this chaotic: angular wave ^ 仏 tiger 'can correct the distortion of the output wave. In addition to ^, ^, coffee, you can also use the wrong tooth waveform, integral waveform cry 11 :: Pei :: ΐa "," a '"and the addition side output of the integrator (the operation side is amplified by the addition side output of 1 1)" d ^ The angular wave signals "b", "b, two? The relationship is qualitatively equal to each other The phase relationship between "3" and the output of the minus side of the product (the op amp 11 / Bay 1) is substantially equal to each other. =: The 12th and 13th turn-in 'the first to fourth synthetic waves The synthesized waveforms of the integrator wheels e, f, g, and ^. Therefore, the phase of the first synthesized wave "e" and the second synthesized wave "f" differ by approximately ⑽ degrees. The phase of the third combination ... 1 "differs from the phase of the fourth composite wave" h "by about 180: the waveform of the second composite wave"% "is substantially equal to the fourth composite wave" h "/ ,,, 'The first— The phase of the fourth synthetic wave Ί "h" is different from each other by a small angle "Θ". The waveform of the second synthetic wave "f" is substantially equal to 95456.doc • 18 · 200531429 The synthetic wave "f" and "qj second synthesis" The waveform of the wave "g", the phases of the second and first phases differ from each other by an extremely small angle Γ Q. The output "j" of the comparator 12 becomes ((synthesized wave%)) > ^ "" f ") "Low", becomes "High" when (the second composite wave "e") < (the second composite wave 4). The output "k" of the comparator 13 is at (the third composite wave) and the fourth composite wave "h "" To "Low" when (the third synthesized wave is synthesized to "High". When the "k" of the second wheel of comparators 12 and 13 is "Low", the output of the AND circuit 31 (-0UT ) Becomes "ancient" When the outputs "" and "k" of comparators 12 and 13 are ",, and back". The output (+ OUT) of circuit 32 becomes "high". 'This Class D zoom The output on the plus side is “high level during the +0 cycle, and the next day is + m”, and the period between 4 and M t is synonymous with the first composite e ”and the second composite wave“ f _ / pico synthesis ” Another point (time) between the wave "g" and the fourth synthetic wave "") to Di Erchang t9, L ". The subtraction output in this class D amplifier becomes “high level” during the period. The time period is defined as the period between the first-human skin cycle and the second synthetic wave “f”, & ^ The wave "... another point between the father's point (at time" t3 ") and the third synthesis gj brother four synthesis wave" h "— in this case, the plus side outputs" + 〇υτ 七, "" t4 " ) ° is the high level 廿 * J or the minus side output “-OUT” is adjusted to this—the interval between the knowing can be determined by the phase difference between the triangles b, b, the angle circuit 2! And X θ in 22 "). Therefore, since the delay angular wave H ^ is sufficiently shortened to the required value, in order to reduce the phase of the three bucket anti-Is 5 tiger a, a 丨 plate two, and the α α Θ Θ m / 5 b, b ' The difference (minimum angle "'Mussels," + 0UT ", and minus side wheels leave the factory. _" Becomes high 95456.d〇c -19- 200531429 The standard time period can be shortened sufficiently to the required value. At this time, the integral Both the minus side output “C” and the plus side output rd ”become extremely low voltages. In other words, in the case of no input signal (that is, a zero volt value to be applied to the following situation), the plus side output + ουτ and minus side output -ουτ The high level k / month can be α and 疋 is a load ratio of 0 to several%. For example, the plus-side output "+ 〇UT" and the minus-side output " _〇υτ ”is supplied to the load, such as the gain. Therefore, in the case of no input signal, because the high level period in the plus-side output + OUT and the minus-side output _0UT is 0 to several 0 / 〇 load Ratio, the current of the low-pass filter and the load becomes extremely small. Therefore, the class D amplifier in this specific embodiment is used for this small signal. In the form, the above-mentioned low-pass filter (lc filter, etc.) arranged between the output terminal and the load can be omitted.-When using the above configuration, according to the class D amplifier of the specific embodiment, no one can input a signal. —In the case (that is, the case where a zero volt value is input to a person), since the time period of the turn-out signal to a high level is sufficiently shortened to the required value, compared with the prior art class D amplifier, the power loss can be greatly reduced. Next, Zhu Ming (analog input signal "+ IN") > (analog input signal "_in") In 幵 y, that is, when the differential input becomes positive as shown in Figure 3, this type of d amplifier is Operation. It should be noted that the dihedral wave signal in the triangle wave signal ah is the same. The phase relationship between the triangular wave signal a, a ', b, b' and the output c, d of the multiplier (the output of the operational amplifier u) is shown in the figure. The relationship shown in the moon shape is the same. In Figure 3, the first to fourth synthetic waves e have eight waveforms that are accumulated by people, and they are synthesized by this round. Therefore, the first synthetic wave "e" The phase is significantly different from the phase of the second synthetic wave "f" ㈣ 95456.doc -20- 200531429 degrees' and The three synthetic waves differ by about 180 degrees. The point of intersection between the third synthetic wave "g" and the fourth synthetic wave "h" after the phase of "g" and the phase of the fourth synthetic wave "h" (time t3 ') The time period from the other-cross point (time t4') to the first composite wave "e" and the second composite wave "f" is longer than the time period in the case of Fig. 2 'plus side output "+ 0UT ”To a high level, and then repeat these operations. Η In Figure 3, the difference between the subtracted output" C "of the integrator and the Η output d of the integrator at the same time is larger than that shown in Figure 2. The difference. Therefore: the phase difference between the first and the fourth composite waves, and the other phase difference between the second and third composite waves "f" and "g" is greater than that shown in Figure 2. The phase difference of the situation. Therefore, it is defined that the time period from the crossing point between the first synthetic wave "e" and the second synthetic wave "f" to another crossing point (time t2 ') is longer than in the case of Fig. 2 In the time period (from time t1 to time t2), the time period during which the plus-side output "+ 〇υτ" becomes high is longer than the time period in the case shown in FIG. 2. In FIG. 3, it is defined that from the time ⑵ the output "J" of the comparator 12 is from the intersection point (time tr) between the first synthetic wave "e" and the second synthetic wave "f" to the next first synthetic wave The intersection (time t4,) between "e" and the next second synthetic wave "f" becomes "high". Next, the output "j" of the comparator 12 becomes "low" from time t4 to another intersection (time t5,) between the next first composite wave re "and the second composite wave" f ", Subsequently, the above operation is repeated. In other words, each intersection of the output "" of the comparator 2 between the first composite wave "e" and the second composite wave rf changes its state from "high" to "low" or from "low" To "high". 95456.doc -21-200531429 The output "k" of the comparator 13 is from the intersection (time t2,) between the third synthesized wave rg and the fourth synthesized wave "h" to the next third synthesized wave "g" The intersection point (time t3,) with the next fourth synthetic wave "h" becomes "low". Next, the output "k" of the comparator 13 goes from time t3 to another intersection (time t6,) between a third synthetic wave "g" and a fourth synthetic wave "h", which becomes "high" After I1 is free, repeat the above operations. In other words, each intersection of the output "dagger" of the comparator 13 between the second synthetic wave "g" and the fourth synthetic wave rh "changes its shape from" 咼 "to" Low "or from" Low " Change to "High". Next, since the plus-side output r + 〇UT ″ gas output j) AND (output “k”), the force-side output + 〇UT ″ is in the time period from time t1 ′ to time t2, from time t3 ′ to time t4, Time period and from time t5 to time ^, when: the period becomes "high" level. Therefore, the load ratio of the time period during which the plus-side output "+ 〇υτ" becomes two levels is substantially proportional to the magnitude of the positive value of the analog input signal. In other words, adding "+ Ru Ding" on the plus side can constitute this signal, which is obtained by adjusting the positive value (differential value) within the analog input k number by means of pulse width modulation (PWM). , On: The minus side output "-" goes low continuously. This is from the time period when the two T ratio input signals are "predicated" > (the analog turn-in signal does not exist and the outputs of the comparators 12 and 13 are low. K "I is changed next, and the (analog input signal) "+" -IN ") The information is from ^ ^, (Issued in the round signal month, that is, the differential input is prepared as shown in this Class D amplification cry. When the mouth 4 is not negative, the desire is large. It should be noted that the triangle wave signal a, & shows the situation Φ accounted for / 7-Modal, b 'is the same as the diagonal wave signal in Figure 2 small. The triangle is used and 仏 # ua, a ,, b , B, 95456.doc -22- 200531429 and the phase relationship between the integrator wheel output c, d (that is, the output of the operational amplifier ㈣) is the same as the relationship shown in Figure 2. It should be understood that In this case, the phase of the integrator output "c" and "d" is reversed (that is, shifted by 180 degrees) from the above situation of Figs. 2 and 3. The first-synthesis e "and the first synthesis The time relationship between the point of intersection between waves "f" and the point of intersection between the third synthetic wave "g" and the fourth synthetic wave "h" is opposite to the situation shown in Figure 3. 输出 The output rj of the comparator 12 is "One synthetic wave%" and the second synthetic wave "f" from the father point (time t2M) to the intersection of the next first synthetic wave "call" and the next first synthetic wave "f" (time t3) (,,)) becomes "High." Next, the output "", which is compared to 12, is from time 0, to another crossover point between the next first synthetic wave "~" and the first synthetic wave "f" ( At time t6 ,,) becomes "Low", and then the above operation is repeated. In other words, each intersection of the output "j" of the comparator 12 between the 5th wave e "and the second synthesized wave" f "will be Its state changes from "high" to "low" or from "low" to "high." The output rk of the comparator 13 changes from the third synthetic wave "§" to the fourth synthetic wave "h". Point (time t1 ,,) to the point of intersection between the next third synthetic wave "§" and the next fourth synthetic wave "h" (time M. becomes "low". Next, the comparator 13 Turning out "k" from time M, to the next-another intersection (time t5 ,,) between the third synthetic wave "g" and the fourth synthetic wave "h" becomes 冋 "'Ik 'Repeat the above operation. In other words, each intersection of the output "k" of the comparator 3 between the second synthetic wave "g" and the fourth synthetic wave "dagger" changes its state # "高" to " "Low" or 1 "Low" changes to "Toward." 95456.doc -23- 200531429 Then, because the plus side outputs Γ + πττ, .χ ουτ "= (output J) and (output k), this output" + OUT ”Continuously becomes the low level. When (output D and (output k) :: becomes“ low ”, the output of the minus side“ na ”becomes“ high ”, and the time of the minus side“ tear ”becomes the high level The duty ratio of the cycle is substantially proportional to the magnitude of the negative value (differential value, differential value) of the analog turn-in signal. In other words, the minus side output -ουτ ″ can constitute this signal, which is obtained by modulating the negative value (differential value) of the analog input signal with pulse width modulation (p-dimension). Therefore, according to a specific embodiment A class amplifier that can convert an analog input signal into a tiger with three values (consisting of zero volts, positive and negative values), and then can output these converted signals, according to D of specific embodiment 1. In the case of analog amplifiers, in the case where the value of the analog input signal is higher than or equal to the pre-amplification value, its round-out signal becomes any of the plus-side round-out "+ OUT" and the minus-side output "na" as shown in Figs. This switching waveform of only one side of a term. Therefore, according to a specific embodiment, the switching loss of the class amplifier can be about one and a half of the switching loss of a conventional class D amplifier that switches between the plus and minus sides. According to the specific embodiment Class D amplifier of Class 1, because the analog feedback is realized by using resistors and R4, the Class D amplifier can amplify the analog input signal under better linear conditions, instead of implementing this digital bit described in Patent Publication 2 above. According to the specific embodiment 1, the class D amplifier is different from the amplifier described in the above Patent Publication No. 1, and the transformer for impedance conversion and for cutting off the DC voltage is no longer needed, which can provide low power loss and low The DC output component of this class-D amplifier with distortion is almost equal to zero volts. Specific Embodiment 2 95456.doc -24- 200531429 Next, a specific embodiment 2 of the present invention will be described with reference to FIG. 5. FIG. 5 is used to indicate the basis. A circuit diagram of a structural example of a class D amplifier of the specific embodiment 2 of the present invention. This class D amplifier is configured with resistors R5 1, R52, R53, H54, R55 and R56, capacitors C51, operational amplifiers 61 and 64, and comparator 62. And 63, an AND circuit (low activity) 71, and another AND circuit 72. The triangle wave signal a "is applied to the input terminal of the comparator 62 and the other triangle wave number" b '"is applied to the comparator 63 Plus input terminal.

The triangular wave signal "b '" corresponds to this triangular wave signal, which is further delayed by delaying the phase of the triangular wave signal "b" obtained by inverting the two-sided wave signal "a" (that is, the delayed phase j 80 degrees). A very small angle "㊀" arises. Therefore, the triangle wave signal "a" and the triangle wave signal rb, "are signals of the same waveform, and their phases are different from each other (180 degrees + minimum angle r㊀"). In this case, a predetermined noise called "dithering" may also be applied to the triangular wave signals a and b, respectively. Since this dithering noise is applied to each triangle wave signal, it can be modified

Distortion of positive output wave. In addition to the triangular wave signals a & b, a sawtooth waveform, an integrated waveform, etc. may also be used. One terminal of the resistance state R5 1 constitutes the input terminal of the analog input signal. Or, connect the other terminal of resistor R51 to the operational amplifier, minus the input terminal. Both the operational amplifier 61 and the capacitor C51 constitute an integrator t. The comparator 62 compares the triangular wave signal "a" with the output% of the integrator ", and the comparison result is output (output" j "). The comparator 63 compares the output "e" 'of the triangular wave signal "with the integral Θ and outputs the comparison result ㈣%). AND Tun Road 71 corresponds to a slow-type circuit with a low-activity outline gate function. Then 'when the output of the first-comparator M "" and the second ratio 95456.doc -25- 200531429 output "k" is "low", the AND circuit 71 outputs a "high" level signal and outputs This calculated signal is the minus side output r_〇υτ ″ of this class D amplifier. The AND circuit 72 corresponds to a buffer circuit having an AND gate function. Then, when the output "j" of the first comparator 62 and the "k" of the second comparator 63 are "high", the AND circuit 72 outputs a "high" level signal and outputs it as the class D amplifier. The adding side outputs this calculated signal of "+ 〇υτ". # ° Operational amplifier 64 and resistor scales 53, R54, R55, R56 constitute a differential amplifier, which amplifies a difference between the plus-side output r + 〇UT ″ and the minus-side output factory _〇u 丁 ″. The output of this differential amplifier is fed back to the input side of the operational amplifier A 61 (ie, the input side of the class D amplifier) via the resistor R52. Therefore, the operational amplifier 64 and the resistors R52, R53, R54, R55, R56 Form a circuit. Next, the operation of the class D amplifier according to this specific embodiment 2 using the circuit configuration described above will be described. In the case where the analog input signal is equal to zero volts (no input signal), # "IN" is equal to "1 "/ 2/2", the plus-side output, "+ 〇υτ" and the minus-side output "-〇υτ" are all shown in Figure 6, and the load ratio in the high level period is almost equal to zero to several%. Therefore, when the class signal is equal to zero volts (no input signal), the current flowing to the load through the filter 2 becomes a minimum. Ningda In the case where the analog input signal is positive, the plus-side output "D" and the minus-side output "-OUT" become the same as in FIG. Therefore, the signal “+ 〇υτ” on the plus side becomes this signal, which is produced by modulating the positive value of the signal (ie, “positive” when using zero volts as the reference value) by means of pulse width modulation. 1. 95456.doc -26- 200531429 On the other hand, the minus side output "__" continuously goes low. In the case where the analog input signal is negative, the 'plus-side output "+ 〇υτ" and the minus-side output "-OUT" become the same as in Fig. 4. Therefore, the minus side output "_" becomes this-signal, which is generated by modulating the negative value of the analog input signal (that is, "negative" when using 1 / 2VDD as the reference value) by means of pulse width modulation. On the other hand, the plus-side output "+ ουτ" becomes continuously low. And according to the above specific embodiment! Class 0 amplifiers are the same. When using the above configuration, according to the specific embodiment, the class amplifiers are numbered without analog input: this: in the case (that is, the case of zero-volt input), because the output signal is crossed to the south level. The time period is sufficiently shortened to the required value, which significantly reduces power loss compared to prior art Class D amplifiers. Therefore, according to the class 0 amplifier of the specific embodiment 2, the analog input signal can be converted into a 仏 sign with three values (consisting of a zero volt value, a positive value, and a negative value), and then these converted values can be obtained. The pwM signal turns out. According to the class D amplifier of the specific embodiment 2, in the case where the analog input signal value is higher than or equal to a predetermined value, its output signal becomes the same as the plus side output "+ 0UT" and Any one of the minus side output "_〇υτ" = this switching waveform of only the-side signal. Therefore, according to the D 颏 amplifier according to the specific embodiment 2, the switching loss of the D 之一 amplifier can be about one and a half of the switching loss of the conventional ϋ amplifier that switches between the plus side and the minus side. ,,. . According to the specific embodiment of the class amplifier, since the use of the operational amplifier ^ 4, the resistors R52, R53, R54, R55, r56mi ^., The second class amplifier can amplify the analog input signal under a better linear condition without implementing the above. This digital processing operation is described in Patent Publication 2. According to the specific 95456.doc -27- 200531429) class 2 amplifier of embodiment 2, unlike the amplifier described in the above patent publication i, a transformer for impedance conversion and for cutting off dc power is no longer needed, can be provided With low power loss and low distortion, its DC output component is almost equal to zero volts. Next, Figs. 7A to 7C show examples of output waveforms in a situation, which is an analog signal input terminal such as a sine wave input type D amplifier according to the specific embodiment i or specific embodiment shown in Fig. I or Fig. 5. Specific embodiment] and in specific embodiment 2, in the case of inputting a sine wave to a human than a signal to a terminal 2 ', the output waveforms are the same as each other. FIG. 7 (4 shows the low-pass filter and the load (electrical device R)) and the plus-side output "+ OUT" and the minus-side output "_〇υτ" of the class D amplifier according to the specific embodiment or the specific embodiment 2. "The two are connected. Figure 7 (b) indicates that the plus-side output" + 〇υτ "of this Class D amplifier has passed through the low-pass filter and this waveform is displayed as the output rp〇UT." In Figure 8 ..., this The reduced-side output "-0UT" of the class 〇 amplifier has passed through the low-pass filter and this waveform is displayed as the output "N0UT". The output ρ〇υτ and the output No. ^^ have only the upper half of the sine wave This waveform of the internal waveform. However, the output "out" corresponding to the signal applied to the load as shown in Fig. 7 (c) becomes a sine wave. This reason is given as follows: That is, because the load (speaker, etc.) is connected Between output ρ〇υτ and output NOUT (that is, between the plus-side output terminal "ρουτ" and the minus-side output terminal "NOUT" of the low-pass filter), as shown in Fig. 7 (c), corresponding to the application of this load The output “0UT” of this signal becomes the difference between the round-out pOUT and the output NOUT (0UT = P0UT-n〇UT), so as to construct Sine wave. In the class 0 amplifier according to the first embodiment and the second embodiment shown in FIG. 1 and FIG. 5, at least both the triangular wave signal ra ”and the triangular wave signal“ b, 95456.doc -28- 200531429 are used. The triangular wave signal "b," is obtained by inverting the triangular wave signal "a" and further delaying this inverted diagonal wave signal "a". Therefore, even when the D-type amplifier according to Embodiment 1 and Embodiment 2 is used There is no analog input ##, which is the same as Figure 2 and Figure 6. Both the plus-side output "+ 〇υτ" and the minus-side output "-OUT" are output in a short time (the duty ratio of the high level cycle is set to zero to A few%), making the voltage output to the low-pass filter slightly smaller (output pout, nout). At this time, because this voltage defined by the output Pooτ • Output No οτ is applied to the load, corresponding to the application to this load The output OUT of the signal becomes zero volts. Therefore, in the case where the analog input terminal is changed from a state without signal to a state where a smaller signal is input, even if the state of the signal changes according to the specific embodiment 1 and Specific embodiment 2 A class d amplifier can supply an amplified signal with low distortion to a load. Specific Embodiment 3 Next, a specific embodiment 3 of the present invention will be described with reference to FIGS. 8 to 11. FIG. 8 is a diagram showing a specific implementation according to the present invention. The circuit diagram of the structure example of the class 0 amplifier of Example 3. Unlike the class D amplifier according to the specific embodiment 1, in this class D amplifier, the delay circuits 21 and 22 are not used as structural elements. In this class D amplifier, a triangular wave is used. The signal "ra" is applied to one terminal of the resistor ruler 10, and the other triangular wave signal "b" is applied to one terminal of the other resistor R12. In addition to the above circuit configuration in the class D amplifier shown in FIG. 8, The structural circuit configuration is the same as the class D amplifier according to the specific embodiment 1 shown in FIG. It should be understood that the individual resistance values of the resistors R5, R6, R7, R8, R9, R10, R11 and R12 constituting the synthesis circuit in this class D amplifier have been set under a condition, and this condition is not defined in accordance with the specific embodiment Class D 95456.doc -29- 200531429 Amplifier resistors R5, R6, R7, R8, R9, R10, Sichuan and old 2. The structural circuit configuration of this class D amplifier will be explained in detail. This Class D amplification | § is equipped with resistors R1, R2, r3,, ^, R6, R7, R8, R9, RIO, R11 and R12, capacitors 0 and 0, operational amplifier 11, comparator 12 and 13, and AND circuit (Low activity) 31 and another—AND circuit 32. In this figure, a predetermined triangle wave signal is applied to the-terminals of the resistors R9 and RU, respectively. In this figure, predetermined triangle wave signals are applied to

-Terminals of resistors R11 and R12. The triangular wave signal, "" and the triangular wave signal "b" are such signals having the same waveform, and their phases differ by "o" from each other. Now suppose that the triangular wave signal "a" in the present invention is not necessarily a triangular wave as claimed in claim 6, Then, the triangular wave signal "b" in the present invention corresponds to a triangular wave having an opposite phase.

One terminal of the resistors R1 and R2 respectively constitutes a differential input terminal of an analog input signal. Therefore, the-terminal of the resistor R1 constitutes a plus-side input terminal (+ IN) 'and the-terminal of the resistor R2 constitutes a minus-side input terminal (_take). The operational amplifier 11 and the capacitor cwC2 constitute an integrator. This integrator integrates the resistor ^ and the analog input signal that has been used to differentially input people to the resistor R5W… the tiger resistance is composed of R5, R6, R7, RS, R9, R10, R1 ^ R12 'The synthesized triangle wave signal "a'" or "b," and the integrator's crazy number form a circuit to generate the first to fourth four synthetic waveforms "factory" g "," h ". w. One ▲ One ... The individual t resistance values of 8, 8, 80, and R12 are determined by the one-dollar formula, and the mode is 95456.doc -30- 200531429 between "e" and the second synthetic wave rf. The time difference (phase difference) between the third composite wave "g" and the fourth composite wave "h" is generated, which corresponds to the output signal of this resistance circuit based on these resistance values. ) And the input capacitance of the comparator 13 (the second comparator). In this circuit, the resistor R5 corresponds to the first resistor related to claim 7 in the present invention, and the resistor R6 corresponds to the fifth resistor in the present invention. The resistance R7 corresponds to the third resistor in the present invention. The resistor corresponds to the second resistor in the present invention. The resistor R10 corresponds to the eighth resistor in the present invention. The private resistance state R11 corresponds to the fourth resistor in the present invention. The resistor R12 corresponds to a sixth resistor in the present invention. One of the above-mentioned packet forming routes includes a first synthesis unit to a fourth synthesis unit. The first synthesizing unit synthesizes the subtraction output of the operational amplifier u constituting the integrator and the triangular wave signal "a" to generate a first synthesized wave "e". Next, the first human element has a resistor R5 (first resistor), one terminal of which is connected to the minus side output of the operational amplifier 11 and a resistor R9 (second resistor). The triangular wave signal "a" is applied to one terminal of this resistor ruler 9. The other resistor is connected to the other terminal of the resistor R9 to form an output: a sub. ^ The addition side output of the two synthesizing unit and the triangular wave signal:? "Are generated to generate a second synthesized wave" f ". Next, the second synthesizing unit has a resistor (a third resistor), and one terminal thereof is connected to the side of the operational amplifier ^: and a resistor RU (fourth resistor). Apply the triangular wave signal to one terminal of this resistor RU. Resistor R7 has another stand. Sub 2: Connect the other terminal of $ ri 丨 to form an output terminal. The third synthesizing unit synthesizes the minus side output of the operational amplifier and the triangular wave signal 95456.doc -31-200531429, b "to generate a second synthesized wave" g ". Next, the third combining unit has a resistor R6 (fifth resistor), one terminal of which is connected to the minus side output of the operational amplifier ", and a resistor R12 (sixth resistor). Apply a triangle wave signal to one terminal of this resistor R12. The other terminal of the resistor is connected to the other-terminal of the resistor HR12 to form an output terminal. The plus-side output of the fourth synthesizing unit 70 synthesizing the operational amplifier Π and the triangular wave signal "a" 'to generate a fourth synthesizing wave "h". Next, the fourth combining unit has a resistor R8 (seventh resistor), one terminal of which is connected to the plus-side output of the operational amplifier, and a resistor R10 (eighth resistor). A triangular wave signal "a" is applied to one terminal of this resistor R10. The other terminal of the resistor ... is connected to the other terminal of the resistor HR1G to form an output terminal. The individual resistance values of the resistors 115, 117, 119, and 1111 (first to fourth resistors) connected to the comparator 丨 2 are preferably set to such resistance values by connecting with the comparator 13 The individual resistance values of the resistors R6, R8, R10, and R12 (fifth to eighth resistors) are obtained by multiplying such values except "1". For example, the resistance values of resistors R5, R7, R9 & R11 and the resistance values of resistors R6, R8, R10 and R12 are set as follows: R6 = R8 = R5Xa, r5 = R7,

R10 = R12 = R9Xa, R9 = RU,. In formulas such as Hai, the symbol r a ″ is not equal to i. It can be seen from the conditions of the above formula that the following resistance value setting conditions can also be established:, or R5 = R7 is not equal to R9 = RU. 95456.doc -32- 200531429 Then 'under this condition of (116 =; ^ 8) and (& 1〇 = 1112), it is assumed that (1 ^ 6, 118, RIO, R12) is equal to (R5, R7, R9, R11) multiplied by "α" (otherwise it is 1 / α). For example, let ’s assume that the individual resistance values of resistors R5, R7, R9, and R11 are set to 1 [KΩ], R6, R8, R10, and R12. Individual resistance values can also be set to 2 [KΩ] or 5 00 [Ω]. At this time, the symbol "α" is equal to 0.05.

Now the individual resistance values of the resistors R5, R7, R9, and R11 are set to 20 [KΩ], and the individual resistance values of the resistors R6, R8, Ri0, and R12 can also be set to 30 [KΩ]. At this time, the symbol "α" is equal to 15. It is now assumed that the individual resistance values of the resistors R5, R7, R9, and R11 are set to j [ΚΩ] 'The individual resistance values of R6, R8, R10, and R12 can also be set to 3 [KΩ]. At this time, the symbol "α" is equal to 30. As can be seen from the foregoing description, the above-mentioned synthesis circuit can be used by using a resistor connected to the comparator 12, a resistor ^ milk and a connection with the comparator ^, the difference between the resistors R6, R8, RIG, R12 And comparative heart

The input capacitances of 13 and 13 establish a time difference (phase difference) between the first composite wave "e" and the second composite wave "I" and between the _th composite wave "g" and the fourth composite wave "h". The comparator 12 (the first comparator) compares the first synthesized wave% "with the second synthesized wave" f "'to output a comparison result. When the first composite wave is "greater than the second composite wave" f ", the first comparator 12 outputs a predetermined" low "level signal (e.g.," order level ") and the #th composite wave" e "is smaller than the second When the composite wave is "f", the first comparator i2 outputs a predetermined "high" level signal. The comparison center (second comparator) compares the third synthetic wave "g" with the fourth synthetic wave "h", and outputs 95456.doc -33- 200531429 to obtain the second comparison result. When the third synthetic wave "g" is greater than the fourth synthetic wave "h", said n—a comparator 13 outputs a predetermined "low" level signal (for example, zero level), and the first port is formed / pico g "is less than When the fourth composite wave is "h", the second comparator 13 outputs a predetermined "high" level signal. The AND circuit 31 corresponds to a buffer circuit having a gate control function of a negative logic input. Then, the AND circuit 31 performs an interesting calculation (low activity), where when the output of the first-comparator 12 and the output of the second comparator 12 are "low", the AND circuit 31 outputs a "high" level signal and outputs This calculation result is output as "-0UT" as the minus side of this Class D amplifier. The resistor phantom constitutes a first feedback circuit. The first feedback circuit feeds back the output of the and circuit 31 serving as a buffer to the addition side input of the operational amplifier u. The AND circuit 32 corresponds to a buffer circuit having an AND calculation function, and performs an AND calculation operation between the output of the comparator 12 and the output of the comparator 13 ', and then outputs the calculation result as the plus-side output of the class D amplifier + 〇UT ". The resistor R4 forms a second feedback circuit. The second ballast circuit feeds back the output of the AND circuit 32 serving as a buffer to the minus side input of the operational amplifier. A load (speaker, etc.) is connected via a low-pass filter between the plus-side output "+ 〇υτ" and its minus-side output "-OUT" of this class D amplifier. Due to the use of these circuit configurations, this Class D amplifier can amplify the analog input signals "+ IN" and "-IN" with low distortion, without using a transformer, and can drive the load while reducing power loss. Next, an example of the operation of the class D amplifier according to this specific embodiment 3 using the above configuration will be described with reference to Figs. 9 to 11. Figs. 9 to 11 are waveform diagrams showing the operation of individual circuit portions of the class D amplifier shown in Fig. 8 at 95456.doc • 34-200531429. Next, Fig. 9 shows that when the value of the analog input signal "+ IN" is equal to the value of the analog input signal "-IN", that is, when the differential input becomes zero volt value (no input signal), the individual class D amplifiers The waveform of the circuit part. Fig. 10 represents the waveforms of individual circuit parts of the class D amplifier when (analog input signal "+ IN") > (analog input signal "· IN"), that is, when the differential input becomes positive. Figure u represents the waveforms of individual circuit parts of the Class D amplifier when (analog input signal "+ IN") < (analog input signal "-IN"), that is, when the differential input becomes negative. field

The main operation parts of the individual circuit parts are the same as the individual circuit parts in the class D amplifier according to the embodiment shown in Figs. However, the class amplifier has the following different operation m angular wave signals ^ used as triangular wave signals, which is different from the Class D benefits according to the specific embodiment t, which uses four sets of triangular wave signals a, a ·, b, and b. The operation of the individual circuit sections of this class D amplifier is explained in detail. Sf first ’will be illustrated in Figure 9; f product you B A- ^

Special value input). Triangle wave ㈡ Zero volts Phase difference _. These two signals are respectively applied to the triangular wave and the predetermined noise of "trembling". Each triangular wave signal can prevent the output wave from being misaligned. In addition to Xiwang No.1 a and b, you can also use a mixed signal ′, Λ, and angular waves. You can use sawtooth waveforms, integral waveforms, and so on. Diagonal wave signal "a" 蛊 穑 eight cry plus side round out) Between "d" ..., "round out (the m-bit relationship of the operational amplifier II is substantially equal to each other ... No. b" and the integrator's subtraction of an angular wave Letter side turn-out (minus side turn-out of the nose amplifier 11 Kc 95456.doc -35- 200531429) The phase relationship between the phase turns out is substantially equal to each other. The turns-in of the comparators 12 and 13 are the first to fourth synthesized waves e, Bu tear has a waveform synthesized with the output of the integrator. Then, the phase of the first composite wave, "" and the phase of the second composite wave "f" differ by about 80 degrees. The phase of the third upper wave jg "and the fourth The phase of the synthesized wave "h" differs by approximately 180 degrees. The waveform of the first synthesized wave "e" is substantially equal to the waveform of the fourth synthesized wave ', and the first and fourth synthesized waves "e" 卩 "h" The phases differ from each other by an extremely small angle "θ". The waveform of the second synthetic wave "f" is substantially equal to the waveform of the third synthetic wave "g", and the phases of the second and third synthetic waves "f" and "seven" are mutually The phase difference is extremely small, "㊀I". As mentioned earlier, the first synthesized waveform "e" and the fourth synthesized waveform "e" The reason why the extremely small angle θ ′ is generated between h ”and between the second synthesized waveform rf” and the third synthesized waveform “g” is as follows. That is, the resistors R5, R7, R9, and R11 connected to the comparator 12 The individual resistance values have been set to such resistance values, which are obtained by multiplying the individual resistance values of the resistors R6, R8, R10, and R12 connected to the comparator 13 by such values other than "丨". In other words, according to the resistance values and the input capacitances of the comparators 12 and 13, the phase difference of the extremely small angle θ ′ described above is generated. It should be understood that this extremely small angle θ corresponds to the class D amplifier according to the specific embodiment 1 shown in FIG. 2 The extremely small angle 出现 appearing in the operating waveform. Then, this extremely small angle θ 'can be adjusted in a simple manner by adjusting the resistance values of the resistors R5 to R12. The outputs "j" and "k" of the comparators 12 and 13 have The output of the comparator 12 and π of the class D amplifier according to the specific embodiment 1 shown in FIG. 2 is the same waveform as "k". The plus-side output of this class D amplifier is "+ 0lJT" and the minus-side output is 95456. ".doc -36- 200531429 out of 0UT" has the same as shown in Figure 2 The waveforms of the “+ 〇υτ” and the minus output “_〇υτ” on the plus side of the d-type amplifier in Embodiment 1 are the same. The comparators 12 and 13 and the AND circuit for the class D amplifier are described above. The operations of 31 and 32 are the same as those of the comparators 12 and 13 of the class D amplifiers according to the specific embodiment 1. AND pen circuits 3 1, 32. The feedback circuits (children R3 and R4) for this type of amplifier are The operation of the integrator (the operational amplifier 11 and the capacitors Cl, C2) is the same as the operation of the feedback circuit and the integrator used in the class D amplifier according to the specific embodiment 1.

It is the same as the class D amplifier according to the specific embodiment 1. When the class D amplifier-Nakita does not supply an input signal, the period of the 咼 level in the plus-side output + 0υτ and the minus-side output -OUT can be set to 0 to a few. % Load ratio. Therefore, in the case where the amplifier of this specific embodiment is used for small signals, it may be omitted to be arranged at the output terminal and the negative, etc.). The above-mentioned low-pass filter (LC filter using the above-mentioned configuration of the D amplifier) is the same as the d_4 of the specific embodiment 1 in the case of no analog input signal (that is, zero volt value 'U-shaped ) Since the time period for changing the output signal to a high level can be charged to the desired value, compared with the prior art class D amplifier, the power loss can be greatly reduced. 'Mingzhuang than the input signal is "stiff")> ; (Analog input signal ") in the U shape, that is, when its differential input is shown in Figure 10 ,. 〇One angular wave uses two sets of triangular wave signals "a" and "b." Therefore, even in the case where the differential wheel input is positive, this class D amplifier can be used in addition to the synthesis circuit section 95456.doc -37- 200531429. Do the same in the same way = when the D input of the specific embodiment 1 is amplified and the input is positive, the force-output +0: = ^ ^ is a signal, which is caused by the positive value of the input signal of the bucket and analogy ( Differential value)

The output and the minus side output "_〇TT 0UT" continuously go to the low level. Next, it will be explained in the f-month shape (analog "TM & Mind + IN" h (analog input signal N ")), that is, when the operation of the Class D amplifier of the agricultural difference ... the input becomes negative as shown in Figure U When comparing D 1 and Fig. 11 with Fig. 4, the only difference is that the triangle wave in this μ state uses two sets of triangle wave signals "a" and "b". W is the difference between the negative and the differential wheel—in this case, except The synthesizing circuit section calls this D-class amplification gain in the same way as the D-type amplification according to the specific embodiment 1. Therefore, in this class D amplifier, when the differential input is soil, ”Becomes this signal, which is generated by modulating the negative value (differential value) of the analog input signal in the form of pulse visibility 以及, and the plus-side output" + 〇υτ "continuously goes to a low level. Therefore ' Same as the class amplifier of the specific embodiment, according to the amplification gain of D of specific implementation 4, the analog input signal can be converted into a PWM signal with three values (consisting of one of ▽ volt value, positive value and negative value) , And then the pwM signal obtained by the 4th conversion can be output. According to the specific embodiment 3/6 Amplifier is enlarged to 'in the case where the value of the analog input signal is higher than or equal to a predetermined value', and the output signal becomes any of the plus-side output "+ OUT" and the minus-side output "-0UT" as shown in Figs. 10 and 11 This switching waveform of only one side of a term. Therefore, according to the class D amplifier of the specific embodiment 3, the switching loss can be about 95456.doc of the switching loss of the conventional class D amplifier switching between the plus and minus sides. -38- 200531429 half. According to the specific embodiment of the pseudo-amplifier, because by using resistors and to achieve analog feedback, Class D amplifiers can amplify the pseudo-input signal under better linear conditions without implementing the above-mentioned special H According to this digital processing operation of the second case, according to the _amplifier of the specific embodiment 3, unlike the amplifier described in the aforementioned patent publication i, it is no longer necessary to use for impedance conversion and transformer to cut off the DC voltage. It is said that the under-amplified state can provide the Class-D amplifier with low power loss and low distortion. Its Dc output component is almost equal to zero volts. In addition, according to this specific embodiment, the Class-O amplifier has a delay The channels 21, 22, and 81 are not used as structural elements. Because the resistance value of the resistor is adjusted to ⑽, the third composite wave "e" and the second composite wave "f", the third composite wave "g", and the fourth The time difference (phase difference) between the synthesized waves "h" can be generated, which is different from the amplifier of the specific embodiment described above. Because of this, the class D amplifier of this specific embodiment 3 can be designed and manufactured in a simple manner, and can provide high performance Class D amplifier. Specific embodiment 4 Next, a specific embodiment 4 according to the present invention will be described with reference to FIGS. 12 to 17. FIG. 12 shows a configuration of a class 0 amplifier according to the specific embodiment 4 of the present invention. Circuit diagram. Common components used in class iiD amplifiers according to specific embodiments use the same reference numerals. The difference between the class D amplifier according to the specific embodiment 4 and the class d amplifiers according to the specific embodiments 1 and 2 is that a single dihedral wave generating circuit is provided. The class D amplifier will be described in detail below. Class D amplifiers include resistor rulers, R2, and capacitors, capacitors C1, C2, and cioo, operational amplifier u, comparators 112 and 113, inverters 121 and 95456.doc -39- 200531429 122, AND circuits 131 and 132 and child machine / original 140. The capacitor loo and the current source constitute a triangle wave generating circuit, and the two /, f angle waves are output to the minus input sides of the comparators 112 and 113. One of each of the resistors R1 and R2 is used in the differential input terminal of the analog input signal. One of the resistors IU is the plus-side input terminal (+ IN) in the winter, and one of the ends of the resistor R2 is the minus-side input terminal early (while thousands of N). The operational amplifier 11 and the capacitors C1 and C2 constitute an integrator. Integral pair Integrates the analog input signals of the resistors R1 and R2 in a dynamic manner to integrate them to output them to the comparators μ and ⑴. The minus-side output of the operational amplifier 11 is connected to the plus-side input terminal of the comparator 112 (first-comparator). The operator Shi ^, ^ is connected to the plus side output of the open Tai U and the plus side input terminal of the comparator 113 (second comparator). Comparator 112 and the minus input terminal of ⑴ are connected to the-terminal of 电容 (capacitor), respectively. The other end of the capacitor is connected to ground, and the other end of the current source is connected to ground. With this configuration, the comparator 112 & compares the output of the minus side of the operational amplifier u with the output of the triangle wave generating circuit and outputs the comparison result. The comparator 113 compares the addition-side output of the operational amplifier 11 with the output of the triangle wave generating circuit and outputs a comparison result. The output of the comparator 112 is connected to one of the input terminal of the inverter 121 and one of the input terminals of the AND circuit 132 (second buffer). The output of the comparator 113 is connected to one of the input terminal of the inverter 122 and one of the input terminals of the AND circuit (first buffer). The output of the inverter 21 is connected to the other input terminal of the AND circuit 131. The output of the inverter 122 is connected to the other round-in terminal of the AND circuit 132. With this configuration, the AND circuit 131 calculates a logical product of the signal inverted from the output of the comparator 112 and the output of the comparator 113, and outputs the result of calculation 95456.doc -40-200531429. The AND circuit 132 calculates a logical product of the signal inverted from the output of the comparator 113 and the output of the car parent benefit 112, and outputs a calculation result. The output of the AND circuit 131 is the plus-side output of the class D amplifier + 0υτ. The plus side output + 0UT is fed back to the minus side input of the op amp through resistor R4. The output of the AND circuit 132 is the minus-side output of the class 0 amplifier_〇υτ. The subtraction output-0UT is fed back to the addition input of the operational amplifier through the resistor R3. Figure 13 is a circuit diagram showing a specific configuration of the current source 140. The current source 14 and the capacitor 100 constitute a triangle wave generating circuit. Transistor and ", switches si and S2, comparators 141 and 142 # & NAND circuits 143 and 144 constitute a current source 140. Transistors T1 and T2 are composed of field effect transistors (field effect transistor; fet). Will be used A voltage VBp for controlling the charging current value of the capacitor 100 is applied to the gate of the transistor T1. A voltage νBN for controlling the discharge current value of the capacitor is applied to the gate of the transistor T2. The switches S1 and S2 include analog switches , And can be composed of FETs. The switches 81 and 82 switch the direction of the current output from the current source 14o, that is, the charging and discharging of the switching capacitor i 00. The current input / output terminal of the electric body τι, the switch 81 And §2 and transistor D2's current input / output terminals are connected in series with each other, as shown in Figure 13. The minus side input terminal of comparator 141 and the plus side input terminal of comparator 142 are connected to the connection point of switch "and S2 . The connection point is also connected to the capacitor 100 and constitutes an output terminal of the triangle wave generating circuit. The comparison 142 compares the expected first potential 乂 b with the potential of the connection point, and outputs the comparison result. The comparator 141 compares the expected second potential VH and the connection point 95456.doc -41-200531429 and outputs the comparison result. It is assumed that the second potential VH is higher than the first potential VL. The difference between the second potential VH and the first potential VL sets the amplitude of the triangular wave. The NAND circuits 143 and 144 are connected to form a flip-flop circuit. The flip-flop circuit has an input, which is an output of the comparators 141 and 142. The output control switches S1 and S2 of the flip-flop circuit are opened / closed. That is, the flip-flop circuit switches out the charging and discharging of the capacitor 100 to switch the rise and fall of the triangular wave. FIG. 14 is a diagram illustrating the operation of the current source 140. Hundreds of times, the operation when the triangular wave G as the potential of the connection point is lower than the first potential VL (in the case of the dotted line K1) will be described. In the case of the dotted line, the output of the comparator 142 becomes low, causing the switch S1 to be turned on and the switch S2 to be turned off. Thus, the charging current flows through the transistor T1 and the switch S1 into the capacitor 100. Therefore, the triangular wave G, which is the potential of the capacitor 100, rises. When the triangular wave F exceeds the first potential VL and reaches the second potential ^^^^, the output of the comparison 141 becomes low, which causes the switch S2 to open and the switch to close. Thus, the discharge current of the capacitor 100 flows to the ground through the transistor T2 and the switch S2. Therefore, the triangular wave G decreases. When the triangle wave G reaches the first potential milk, the output of the comparator 142 becomes low, which causes the switch 81 to be turned on, and S2 is turned off. ㈣ The charging current flows again, and the two-corner wave G rises. By repeating these operations later, a graph as shown in the figure is generated. " One of the angular waves G shown can set the slope of the triangular wave g by the voltage Vbn for controlling the discharge current and the capacitance of the capacitor j 00. Next, the triangular wave G is higher than the second potential VH (that is, the dotted line) ^ 2)) operation. In the case of dashed line 〇, the output of the comparator 141 becomes low, which causes switch s 2 to open and switch s _. Thus, the discharge of capacitor 〇 100 〇 95456.doc 200531429 The transistor T2 and the switch S2. Therefore, the triangular wave G, which is the potential of the capacitor loo, drops. Thereafter, as described above, the charging and discharging of the capacitor 100 is repeated and the triangular wave G shown in FIG. 14 is generated. Accordingly, using this The class D amplifier of the specific embodiment can provide a triangle wave generating circuit having a simple structure composed of a capacitor 100 and a current source 140. Therefore, the class D amplifier has high efficiency and can provide a low-distortion class D amplifier with low cost. Next, the operation of the class 0 amplifier according to the specific embodiment 4 will be described with reference to FIGS. 15 to 17. FIGS. 15 to 17 are waveform diagrams showing the operation of each part of the class 0 zoom shown in FIG. 15 display (analog input signal + IN) > (analog input signal _in), that is, the waveform of each part of the class D amplifier when the differential input is positive. The triangular wave G is the first potential VL is the smallest and the second potential is ¥ 11 The largest triangle wave ... Because the differential input of the integrator is positive, the subtracted side output A of the integrator is low compared to the added side output B of the integrator. Figure 15 shows the drive of the switches S1 and S2 of the current source 14 Waveform. The switch of the current source 14 ° makes a high-level signal; the rising segment of the angular wave G is turned on. The switch S1 responds to the low-level signal and turns off in the falling segment of the triangular wave G. The switch S2 of the current source 140 is The low level signal responds, and the S2 responds to the level signal in the rising region ㈣ of the triangular wave G, and turns on in the falling section of the triangular wave g. The comparison result of the continuous triangle wave G output of the subtracting side of the integrator is a > g, The output c goes high 'when compared As a result, the turn-out ^ becomes low. When the comparison result of the integrator plus the side wheel 屮 A Tianren dihedral wave G becomes b > g, the turn-out of the comparator 113 d 辔 ancient fire '§ The comparison result becomes B < G, turn-out d becomes low. 95456.doc -43- 200531429 When both the value of the output C of the comparator 112 and the turn-out d of the comparator 113 are high, the output of the AND circuit 13 1 (+ 〇UT) E becomes higher. Therefore, the load ratio of the period when the dog plus side output + OUT is high is substantially proportional to the amplitude of the positive value (differential value) of the analog turn-in signal. In other words, the plus-side output + ο U D is the pulse width modulation signal of the positive value (differential value) of the analog input signal. On the other hand, when the output of the comparator 112 and the value of the D-reversal output from the comparator 113 are both high, the output (-0lrr) F of the AND circuit 132 becomes high. Here the 'minus side output -OUT is always low. Figure 16 shows the waveform of each part of the Class D amplifier when (analog input signal + IN) = (analog input signal _IN), that is, when the differential input is zero (0 volt input). The triangular wave G shown in FIG. 16 is the same as the triangular wave G shown in FIG. 15. Since the operations of the switches S1 and S2 of the current source 140 with respect to the triangular wave F are the same as those shown in FIG. 15, the driving signals of the switches 81 and 82 are omitted in FIG. Since the differential input of the integrator is (+ IN) = (_ in), the output A of the integrator and the output B of the integrator have the same level. Since the output a is equal to the output B, the output c of the comparator 112 and the output 0 of the comparator 113 have the same waveform and the same phase. Since the output (+ 〇1; D) of the AND circuit 131 is (inverted value of the output c) * (output D), the output E is at a low level for most of the entire cycle. Since output (-〇UT) F is (output C) * (inverted value of output 0), output F is at a low level for most of the entire week / month. As shown in Figure 6, the difference in delay time due to the non-identical offset voltages of the operational amplifier 121, the components constituting the comparators 112 and 114, and the inverters 121 and 122, the plus side output + 〇υτ and the minus side The output -OU Ding has some high level periods. Therefore, the plus-side output 95456.doc 200531429 + 〇υτ and minus-side round out .τ can simply be assumed to be strictly low levels throughout the cycle. As described above, according to the class D amplifier of the specific embodiment 4, since the analog input signal is not applied (in the case of an input of 0 volts), the period in which the output signal is at a high level can be shortened very easily, which is in line with the tradition of simple structure Compared with equipment, it can greatly reduce power loss. Figure η shows the waveform of each part of the class D amplifier when (analog input signal + IN) < (analog input signal-IN), that is, when the differential input is negative. The triangular wave 卩 is the same as the triangular wave G shown in FIG. 15. Because the switch of the current source 14 and the operation with respect to the diagonal wave G are the same as those shown in FIG. 15, the driving waveforms of the switches S1 and S2 are omitted in FIG. 17. The high-side output B is at a high level. When the comparison result of the subtractor-side output A and the triangular wave G of the integrator is A & G, the output C of the comparator 112 becomes high, and when the comparison result is A < G, the output c becomes low. When the addition side output B of the integrator and the triangular wave Gg B> G, the output E of the comparator 113 becomes high, and when the comparison result becomes b < g, the output E becomes low. When the output C of the comparator 112 and the comparator 113 When the inversion value of the output D is high, the output (-OUT) F of the AND circuit 132 becomes higher. Therefore, the load ratio of the period when the minus side output -OUT is high is substantially negative compared to the analog input signal. (Differential value) The amplitude is proportional. In other words, the minus side output _〇υτ is a pulse width modulation signal with a negative value (differential value) of the analog input signal. On the other hand, when the output C of the comparator 112 is inverted When both the value and the output D of the comparator n3 are high, the output (+ 〇UT) E of the AND circuit 13 1 becomes high. Here The plus-side output + OUT is always low. 95456.doc -45- 200531429 As mentioned above, according to the class D amplifier of the specific embodiment 4, the analog input signal can be converted to 0 volts, positive and negative values. Composed of a 3-valued PWM signal and output it. According to the class D amplifier of the specific embodiment 4, when the analog input signal becomes a value other than the 0 volt value, the switching waveform appears only as shown in Figs. 15 and 17 One of the plus side output + OUT and the minus side output -OUT. According to the class D amplifier of the specific embodiment 4, because the resistors R3 and R4 constitute the analog feedback circuit, the analog input signal can be amplified with good linearity without performing as in Japan The digital processing described in Patent Disclosure No. 2000-500625. In addition, according to the Class D amplifier according to the specific embodiment 4, the direct output component can be substantially eliminated, and it is not provided for impedance conversion and direct voltage cut-off (such as Japanese patent Illustrated in Publication No. Sho-56-27001). Therefore, a 'class D amplifier with low distortion and high power efficiency can be provided. Although the McCaw pattern has been described in detail in the specific embodiment of the present invention, The specific structure is not limited to this specific embodiment mode, but it can obviously cover the structure defined within the scope of not departing from the technical spirit of the present invention. For example, in the class D amplifier of the above specific embodiment, the integrator is integrated by the primary stage. However, the present invention is not limited to this, and the integrator may be composed of the same integrator. With this structure, the loop gain can be increased and the distortion rate can be further reduced. In the above description, the present invention has been described as a class 0 amplifier. However, the present invention is not limited to this. Accordingly, the present invention can be applied to signal processing circuits other than Class D amplifiers, and various pulse width modulation amplifiers. [Brief description of the drawings] ”FIG. 1 is a circuit diagram for indicating a structural example of a rigid type 95456.doc 200531429 according to a specific embodiment mode of the present invention. FIG. 2 is a circuit diagram for indicating D shown in FIG. 1. A waveform diagram of the operation of the Class D amplifier with zero volts applied to the Class D amplifier. Figure 3 is a waveform diagram for indicating the operation of the Class D amplifier when a positive value is applied to the Class 0 amplifier shown in Figure 1. Figure 4 FIG. 5 is a waveform diagram for indicating the operation of the class D amplifier when a negative value is applied to the class d amplifier shown in FIG. 丨 FIG. 5 is a structure for illustrating a class 0 amplifier according to a specific embodiment 2 of the present invention. An example circuit diagram. Fig. 6 is a waveform diagram for indicating the operation of the class D amplifier when zero volts are applied to the class 0 amplifier shown in Fig. 5. Figs. 7A to 7C are diagrams for showing a specific implementation according to the present invention. A diagram of an example of a waveform appearing in a load when a sine wave is input to a Class D amplifier of Example i or Embodiment 2. FIG. 8 is a circuit diagram showing a structure example of a class 0 amplifier according to Embodiment 3 of the present invention. Figure 9 is used for instructions A waveform diagram of the operation of the class D amplifier when a zero volt is applied to the class d amplifier shown in Fig. 8. Fig. 10 is a diagram for indicating the operation of the class D amplifier when a positive value is applied to the class D amplifier shown in Fig. 8 FIG. 11 is a waveform diagram for indicating the operation of the class D amplifier when a negative value is applied to the class D amplifier shown in FIG. 1. FIG. 12 is a diagram illustrating a fourth embodiment according to the present invention. Circuit diagram of structural example of Class D amplifier. 95456.doc -47- 200531429 Figure 13 is a circuit diagram showing a structural example of a class D amplifier current source. Figure 14 is a waveform diagram showing the operation of the current source. Waveform diagram of operation when Class _ amplifier is applied with a positive value. Figure 16 is a waveform diagram showing operation when zero volt is applied to a Class D amplifier. Figure 17 is a waveform diagram showing operation when a negative value is applied to a Class D amplifier. Description of main component symbols] 1 Output 11 Operational amplifier 12 Comparator 13 Comparator 21 Delay circuit 22 Delay circuit 31 AND circuit 32 AND circuit 61 Operational amplifier 62 Comparator 63 Comparator 64 Operational amplifier 71 AN D circuit 72 AND circuit 100 capacitor 112 comparator 113 comparator 95456.doc -48- 200531429 121 inverter 122 inverter 131 AND circuit 132 AND circuit 140 current source 141 comparator 142 comparator 143 N AND circuit 144 N AND Circuit VL first potential VH second potential e first composite wave f second composite wave g third composite wave h fourth composite wave T1 transistor T2 transistor Cl capacitor C2 capacitor C51 capacitor C100 capacitor Vbh voltage V bn voltage V BP Voltage

95456.doc -49 200531429 R resistor R1-R12 resistor R51-R56 resistor + OUT plus side output + IN plus side input terminal -OUT minus side output -IN minus side input terminal A minus side output B plus side output SI Switch S2 switch F triangle wave G triangle wave a triangle wave signal b triangle wave signal a 丨 triangle wave signal b 丨 triangle wave signal tl time tlf time tl, time t2 time t2, time t2M time t3 time 95456.doc -50- 200531429 t3, time t3M t4 time t4, time t4M time t5, time t5M time t6, time t6ff time c output d output C output D output E output j output k output NOUT output POUT output

95456.doc -51-

Claims (1)

200531429 10. Scope of patent application: 1. A class d amplifier, which includes an integrator that integrates an analog input signal; a comparator that is used to compare a triangle wave of the integrator; A first music-comparison 'compares an angular wave of the round of the integrator with the second triangular wave equal to the phase of one of the r ^ ^ waves produced by shifting the first: the second-180 degrees plus a minimum angle. "Monthly, or a waveform obtained from a very small negative angle; angle-obtained-buffer, which outputs a plus side according to the output of one of the comparators of the first comparator, and the second ratio. The output signal and ~; and the minus side round-out signal feedback circuit, which feeds back the difference between the plus-side output signal and 誃 to the input side of the integrator. … Output signal 2 · If requested: the Class D amplifier of item 1, wherein the buffer includes: a first buffer that calculates the first-. ,, .., I ^ of this round out Comparing the logic of the output of one of the logic / ... Haidi, Kezu product, using the rotation to make one of the Λ output signals; and a second buffer for the far-reduction side, which calculates the first —-士 # For example, the output of the car 乂 笛 is more than the logical product of the output of the car 笛, and the result is calculated by using one of the output signals from the factory. ’,,, and W plus side input 3. For example, a request item such as a class amplifier, in which the amplifier is used to amplify the plus side wheel out ... 'Road Dagger-one differential within the differential amplifier. Between the palpitations and the minus side turn-out signal 95456.doc 200531429 4. A class D amplifier comprising: an integrator 'pair constituting an analog input signal and a differential integration between a plus-side input signal and a minus-side input signal; a delay circuit which delays a phase of a triangular wave by a predetermined Extremely small angle; w port Cheng Honglu, which combines one of the integrator output, the triangle wave and the output of the delay circuit with each other to output a plurality of output signals; The two output signals are compared with each other; a buffer that inputs one of the outputs of the comparator; and a feedback circuit that feeds back one output of the buffer to one input side of the integrator. 5. The Class D amplifier of claim 4, wherein the triangle wave is composed of a first triangle wave and a second triangle wave, and the second triangle wave corresponds to one of the phase deviations of the first triangle wave and the second triangle wave. A waveform generated by the angle, the delay circuit includes a first delay two music delay circuit, which is used to delay the phase of the first triangular wave by the predetermined minimum angle n ^, and a second delay circuit, which is The third triangular wave «political < phase delay of the predetermined minimum degree, the synthesizing circuit synthesizes the subtracted side output of the integrator and the -2nd angle = generated-the -th synthesized wave, synthesizes the plus side output of the integrator ^ The second triangle wave is used to generate-the second synthetic wave, to synthesize the integral world :; the subtracted side output and the second delay circuit-the output to produce the two shown one synthesis 95456.doc 200531429 wave and the 5050 integrator The plus-side wheel output and one of the first delay circuits output to generate a fourth synthesized wave. The comparator includes a first comparator for comparing the first synthesized wave with the first wave of the first wave, and a second Compare The buffer is used to compare the third composite wave with the fourth composite wave. The buffer includes a first buffer for calculating a logical product of an output of the first comparator and an output of the second comparator. The second buffer is used to calculate a logical product of the output of the first comparator and the output of the second comparator, and the feedback circuit includes a first feedback circuit for the output of the first buffer The plus-side round-in feedback to the integrator; and a second feedback circuit for returning the output of the second buffer to the minus-side input of the integrator. 6. A class D amplifier, comprising:-an integrator 'which constitutes-an analog input signal-a difference integration between an input signal on the plus side and a input signal on the subtract side; a synthesis circuit that synthesizes the integrator -Turn out and a triangle wave, and combine the output of the sigma integral and the -phase-triangle wave with the phase opposite to the first-mentioned triangle wave to output a plurality of signals, where the triangle wave of the opposite phase corresponds to a waveform , Whose phase is shifted by 180 degrees with respect to the phase where the triangular wave is first mentioned; a comparator that compares the output signals of the synthesis circuit with each other; a buffer that rotates one of the outputs of the comparator into it; And-feedback circuit 'which feeds back one of the buffers to one of the input sides of the integrator 95456.doc 200531429, wherein the synthesis circuit includes a plurality of resistors having at least two resistance values, and is configured to The resistance values of the plurality of resistors and an input capacitance of the comparator generate a phase difference between the two or more signals corresponding to the output of the synthesis circuit. 7_ The Class D amplifier of claim 6, wherein the synthesis circuit includes:-a -synthesizing section for synthesizing one of the subtractor side output of the integrator and the triangle wave to generate a first synthesized wave, -A second synthesizing section 'which is used to synthesize one of the integrator's plus side outputs a triangular wave of the opposite phase to produce a second synthesizing wave; a third synthesizing section' which is used to synthesize the subtractive side of the integrator Outputting a triangular wave opposite to the target position to generate a third synthesized wave; and a fourth synthesizing section for synthesizing the plus-side output of the integrator and the triangular wave to produce a fourth synthesized wave ; The first synthesizing section includes the sub-side output connection of a first divider and applies a triangle wave to one of its terminals; the sub-connector is connected to the output terminal of the second resistor; For this plus side wheel out connection, a two-angle wave is applied to one of its terminals; a standoff is connected to the out terminal of the fourth resistor; a resistor, one terminal of which is connected to the product and a second resistor, Which will and will One other terminal of a resistor, so as to constitute one of its two resistances, one of its terminals and the fourth resistor 'wherein this and the other terminal of the third resistor, so that The second synthesizing part that constitutes one input is 95456.doc 200531429. The second synthesizing part includes a fifth resistor, a terminal of which is connected to the minus side output of the integrator, and a sixth resistor, in which the triangular wave of the opposite phase is applied At one terminal thereof; and connecting the other terminal of the fifth resistor to the other terminal of the sixth resistor so as to constitute an output terminal thereof; the fourth combining section includes a seventh resistor having one terminal Connected to the plus-side output of the integrator, and an eighth resistor, wherein the two-corner wave is applied to one of its terminals; and the other pin of the seventh resistor is connected to the eighth resistor The other terminal so as to constitute an output terminal thereof; the: the comparator includes a first comparator having a wheel-in terminal connected to the output terminal of the first combining part, and The other input terminal connected to the output terminal of the second synthesizer; and a second comparator having an input terminal connected to the output terminal of the third synthesizing section; and the second terminal of the fourth synthesizing section; The other input terminal connected to the output terminal; the buffer includes a first buffer for calculating a logical product of an output of the first comparator and an output of the second comparator; and a second buffer A comparator for calculating a logical product of the output of the first comparator and the output of the second comparator; ° the Xuan feedback circuit includes a first feedback circuit for the first buffer The output is fed back to the plus-side input of the integrator, and a first feedback private circuit, which is used to feed back the output of the second buffer to the minus side turn-in of the toothblade, and 95456. doc 200531429 The resistance value of any one of the first resistor, the second resistor, the third resistor, and the fourth resistor is different from the fifth resistor, the sixth resistor, and the seventh resistor Resistor and the first The resistance value of any one of the eight resistors. 8. The Class D amplifier of claim 7, wherein the resistance value of each of the first resistor, the second resistor, the third resistor, and the fourth resistor is the fifth resistor A resistance value obtained by multiplying the resistance value of each of the resistor, the sixth resistor, the seventh resistor, and the eighth resistor by a value other than 1. 9. A class D amplifier comprising: an integrator that integrates a difference between an input signal on the plus side and a input signal on the subtract side that constitutes an analog input signal; a triangle wave generating circuit including a current source and A capacitor; a comparator comparing an output of the integrator with an output of the triangle wave generating circuit; a buffer inputting an output of the comparator; and a feedback circuit outputting one of the buffers Feedback to one of the input sides of the integrator. 10. The Class D amplifier of claim 9, wherein: one end of the capacitor is connected to one of the input terminals of the comparator; and the current source switches one direction of the output current so as to repeat the charging and discharging of the capacitor. 11. The class D amplifier of claim 10, wherein: one end of the current source is connected to the one end of the capacitor, 95456.doc -6- 200531429 the potential of the current source at one of the capacitors is lower than a first band A current flows in the -direction of the capacitor during charging, and the electric current flows higher in the direction of discharging the capacitor in the direction of the second potential than the second potential is higher than the first potential. L and 12. The Class D amplifier of claim 9, wherein: the comparator includes a first comparator for comparing a minus side output with the output of the triangle wave generating circuit; to: two; two = way It is used to compare one of the integrator plus the side wheel output with the triangle: the output of the circuit is generated, the buffer includes a first buffer, the mountain is recognized, and the first comparison wheel is used to count the nose The output-inverted value is logically one of the output of the second comparator and a second buffer, which is used to calculate the logical product of the inverted value of the second comparator And ::: Feed: The circuit includes a first feedback circuit that is used to buffer the first—the output is fed back to the integrator—minus the side input; and a second! The-output of the second buffer is fed back to one of the product side plus inputs.