200523935 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種半導體記憶裝置，特別是有關 種具有增強測試能力之半導體記憶裝置，用以發現在 插置模式中之半導體記憶裝置操作中的錯誤。 【先前技術】 一種半導體記憶裝置包括多數個記憶單元。假如在 體裝置中之任一個單元係超出操作順序，該半導體記 置是無法使用的。在半導體記憶裝置製造過程之後， 是需要一個測試程序用來發現在此半導體記憶裝置中 疵單元。 一般來說，該半導體記憶裝置具有一個附加用在測 路的區域，此電路能測試在半導體裝置處於高速時所 單元（cell)。不過，依據半導體裝置積體化的增加， 需要很多的時間與努力來測試半導體裝置的單元，以 與發展該半導體裝置。 因此，爲了節省測試半導體裝置的時間，一壓縮測 式則是被用來使用的。在該壓縮測試模式中，資料被 經由一部分的輸入/輸出腳（pin)DQs，而非經由所有 入/輸出腳 DQs，輸入至所有包括在半導體中的 (bank )。用以確認自每一個單位單元所輸出的資料 一個輸出的資料係不是同時經由所有的輸入/輸出腳 自所有的排址輸出，其中這些多數個閘，例如AND N〇R閘，每一個皆對應至每一個輸入/輸出腳D Q s被傻 於一 排址 半導 億裝 在此 的瑕 試電 有的 在此 硏究 試模 同步 的輸 排址 ，每 DQs 閘或 ί用。 200523935 第1圖係顯示一用在習知半導體記憶裝置的一測試區塊 之方塊圖。 如圖所示，該測試區塊包括一內部排址位址產生器1 0、 一讀取解碼區塊2 0、一壓縮控制區塊3 0、一資料壓縮區 塊4 0、一寫入解碼區塊5 0，一寫入控制區塊6 0與一寫入 驅動區塊7 0。 該內部排址位址產生器10轉換排址位址（bank address ) 如ΒΑ0與BA1以成爲多數個內部排址位址，如 a，/a，b，/b， c，/c，d，/d。該多數個內部排址位址如a，/a，b，/b，c，/c，d， /d皆被輸入至讀取解碼區塊20。讀取解碼區塊20將多 數個內部排址位址如a，/a，b，/b，c，/c，d，/d解碼，藉以 產生多數個讀取排址操作訊號 rd_bank0，；rd_bankl， rd一bank2與rd_bank3以回應附加的閂鎖訊號AL0。壓縮 控制區塊3 0是用以控制資料壓縮區塊4 0以回應多數個讀 取排址操作訊號 rd_bank0， rd—bankl， rd—bank2 與 rd_bank3。資料壓縮區塊40具有多數個DQ輸出緩衝器， 例如D Q輸出緩衝器3 6是用來壓縮每一排址資料輸出之 資料。 此外，部分多數個內部排址位址如a，/a5 b，/b被輸入至 寫入解碼區塊50。寫入解碼區塊50解碼部分多數個內部 排址位址如a，/ a，b，/ b，藉此產生多數個寫入排址操作訊 號 wt — bankO、wt_bankl、wt_bank2、wt — bank3。寫入控制 區塊6 0係用來控制寫入驅動區塊7 0以回應寫入啓動訊號 W丁en與多數個寫入排址操作訊號 wt_bank0、wt bankl、 200523935 wt —bank2、Wt_bank3。寫入驅動區塊 70係儲存在每一排 址所包括之單元陣列（cell array) 80所輸入之資料。 此外，內部排址位址產生器1 〇包括一緩衝區塊，一問 鎖區塊與一路由區塊。緩衝區塊包括兩個緩衝區，例如緩 衝器1 2，每一個緩衝器係用來接收一第一位元排址位址 ΒΑ0與一第二位元排址位址BA1以及轉換第一位元排址 位址ΒΑ0與第二位元排址位址B A 1成爲內部排址位址如 baO — add，baO — addb，b a 1 _add 與 bal—addb，每一緩衝器對 應於第一位元排址位址B A 0與第二位元排址位址B A 1。 閂鎖區塊包括兩個閂鎖器，例如閂鎖器1 4，每一閂鎖器 係被壓縮測試訊號tpara控制用以傳輸內部排址位址如 baO — add, baO — addb，bal—add 與 bal—addb 至路由區塊如 部分多數個內部排址位址a, /a，b，/b。路由區塊也包括兩 個路由器，例如路由器16，每一路由器用以延遲部分多 數個內部排址位址如a，/a，b，/b，藉以產生其他多數個內 部排址位址如c5 /c，d，/d。 更仔細地說，壓縮控制區塊3 0包括讀取控制區塊3 2與 一選通訊號產生區塊3 4。讀取控制區塊3 2包括多數個讀 取控制器，每一控制器被一讀取啓動訊號RDen控制以接 收讀取排址操作訊號；選通訊號產生區塊3 4包括多數個 選通訊號產生器，每一選通訊號產生器用以產生多數個選 通訊號，例如i 〇 s t b。 在此，每一讀取控制器，每一選通訊號產生器與每一 D Q 輸出緩衝器係個別的對應至每一個包括在習知半導體記憶 200523935 裝置中之排址。此外，每一個緩衝區，每一個閂鎖器與每 —個路由器在內部排址位址產生器1 〇中是個別地對應至 每一排址位址之位元。 在此之後，描述該半導體記憶裝置之一測試操作當該壓 縮測試訊號tpara被啓動時。 首先，該內部排址位址產生器1 0不管排址位址以回應 該壓縮測試訊號tpara啓動該些內部排址位址如a，/a ,b，/b， c，/ c，d，/ d。然後，讀取解碼區塊2 0輸出之讀取排址操作 訊號 rd—bankO， rd—bankl， rd—bank2 與 rd_bank3 ，及寫入 解碼區塊50輸出之該些寫入排址操作訊號 wt_bank0、 wt-bankl、wt__bank2與 wt_bank3皆被啓動。如果該寫入 啓動訊號WTen被啓動，該寫入控制區塊60與該寫入驅 動區塊7 0被啓動，然後資料被輸入至單元陣列8 0。此外， 如果讀取啓動訊號RDen被啓動，多數個輸出自單元陣列 80之資料LI00<0: 15>至LI<0: 15>被壓縮與輸出。 此外，測試區塊的操作方法，也就是用以解碼壓縮資料 與壓縮輸出資料之方法係被仔細地描述。 在習知記憶裝置中，每一個排址具有一資料墊，用以一 次接收四個資料。這四個資料被看作成一資料串 (BUNCH);而四個資料串構成一 16位元資料。在一寫 入操作中，相同的1 6位元資料被輸入至每一個排址。 在讀取操作中，1 6位元資料被輸入至被分類之四個資 料串的每一個排址；每一個數據（datum )係經由相同的 資料墊被輸入，介於每一個資料串的四個資料係被相互比 200523935 較。然後經由對應於每一個排址之資料墊，輸出比較結果。 在此，假如經由資料墊輸出之訊號的一邏輯狀態是高邏 輯準位，此半導體記憶裝置則不具有瑕疵單元；但是反之， 半導體ifi憶裝置具有至少一個瑕疵單元。 第2圖係用來描述第1圖中在閂鎖區塊1 4所包括閂鎖 器之結構電路圖。 如圖所述，此閂鎖器包括一個第一反相器11，第一閂鎖 單元14a，一第二閂鎖單元14b，一第一 NAND閘ND1與 一第二NAN D閘ND2。在此，此第一與第二閂鎖單元Ma 與14b係由兩個連接至反相器的電路集所構成。 此第一反相器I 1是用來將壓縮測試訊號tpara反相。第 一閂鎖單元1 4a是用來閂鎖一反相內部排址位址，例如 b a 0_addb;第二閂鎖單元14b是用來閂鎖一內部排址位址， 例如baO-add。第一 NAND閘ND 1耦接於此第一閂鎖單元 1 4 a與第一反相器I 1，並接收此反相內部排址位址之一反 相狀態，也就是說，內部排址位址與反相壓縮測試訊號用 以產生一個如第一內部排址位址a的NAND操作之結果訊 號。再者，此第二NAND閘ND2耦接於此第二閂鎖單元14b 與此第一反相器Π接收此內部排址位址的一反相狀態， 也就是反相內部排址位址，及一反相壓縮測試訊號以產生 一 NAND閘操作的一結果訊號如一第一內部排址位址/a。 第3圖係用來描述第1圖中在路由區塊1 6所包括的路 由器之結構電路圖。 如圖所示，路由器包括一個閂鎖與延遲區塊1 7，一第 200523935 二反相器12, 一第三NAND閘ND3與一第四NAND閘ND4。 此閂鎖與延遲區塊1 7接收第一內部排址位址，也就是 a，及第一反相內部排址位址，也就是/a，自閂鎖器輸出 藉以輸出一延遲訊號至該第三NAND閘。第二反相器12 用以反相壓縮測試訊號tpara。第三NAND閘ND3耦接至 閂鎖與延遲區塊· 1 7與第二反相器12接收一自閂鎖與延遲 區塊1 7之輸出訊號，及一反相壓縮測試訊號產生如一第 三內部排址位址c之NAND操作之一結果訊號。再者，該 第二NAN D閘ND2耦接於第一反相器II接收第三內部排 址位址，也就是c與一反相壓縮測試訊號以產生如一第三 反相排址位址/c之NAND操作之一結果訊號。 參考這些例子，每一個閂鎖器與每一個路由器個別的具 有相同之架構；因此則省略閂鎖器與路由器的詳細說明。 第4圖爲第1圖中描述讀取解碼區塊20的電路圖。 如圖所示，該讀取解碼區塊2 0，包括一控制訊號產生 器21與多數個解碼器22、24、26與28。該控制訊號產 生器2 1產生控制訊號如A L 0 b與A L 0 d以回應附加閂鎖訊 號AL0。每一個解碼器接收兩個內部排址位址以及選擇此 兩個內部排址位址之一以回應控制訊號如ALOb與ALOd， 藉以產生一反相選擇位址作爲讀取排址操作訊號。 更仔細地說，此控制訊號產生器2 1包括一第三反相器I 3 用以反相壓縮測試訊號，一第五NAND閘ND5用以產生 附加閂鎖訊號AL0的結果測試訊號與反相壓縮測試訊號 與一第四反相器14用以反相一第一控制訊號a l 0 b，也就 200523935 是第五N AND閘ND5輸出之訊號，藉以產生一第二控制 訊號A L 0 d。 每一個解碼器包括兩個NAND閘，兩個傳輸閘與一反相 器。每兩個NAND閘中之其中一個接收兩個內部排址位址 與產生NAND操作之一結果訊號；每兩個傳輸閘中之其中 一個傳輸此結果訊號以回應第一與第二控制訊號ALOb與 ALOd °然後’反相器係將兩個傳輸閘輸出之輸出訊號轉 換’藉以產生輸出訊號的反相訊號作爲讀取排址操作訊 號。 參考第4圖，讀取解碼區塊2〇包括四個解碼器。多數 個內部排址位址’也就是a，/a，b，/b，c，/c，d，/d，係被分 類成四個族群，每一個族群包括四個內部排址位址：（/a， /b，/c，/d)，（a，/b，c，/d)，（/a，b，/c，d)，（a , b，c， d) ° 在此’每一個解碼器，例如解碼器22、解碼器24、解 碼器2 6與解碼器2 8，解碼閂鎖區塊所輸出之一群非延遲 內部排址位址，也就是a，/a，b，/b，與路由區塊輸出之延 遲內部排址位址，也就是c，/c，d，/d，以回應第一與第二 控制訊號ALOb與ALOd。 在習知記憶體裝置中，需要一 RAS至CAS延遲tRCD， tRCD係由提供一列啓動訊號之一最小時間，以供應一行 啓動訊號。不過’如一附加閂鎖係被導入用以增加半導體 S己憶裝置之一操作速度，此行啓動訊號被供應在r a S至 C AS延遲tRCD之前，在列啓動訊號被供應之後。也就是， 200523935 根據此附加閂鎖，供應此行啓動訊號的時序係能被調整。 假使附加閂鎖訊號AL0不被啓動，例如此附加閂鎖訊 號是2或3，此行啓動訊號係在raS至C AS延遲tR CD之 前輸入，然後，在此有很多的時間餘裕（time margin)用 以存取資料以回應行啓動訊號。此例中，因爲有很多時間 餘裕’延遲內部排址位址，也就是c，/c，d，/d，，其係在 讀取解碼區塊2 0被解碼且藉由路由區塊1 6延遲。 此外’假使此附加閂鎖訊號A L 0被啓動，例如此附加 Η鎖爲0，此行啓動訊號係在RAS至CAS延遲tRCD之後 被輸入’然後，有許多時間餘裕用以存取資料以回應此行 啓動訊號接觸資料。在此例中，因爲一些時間餘裕，非延 遲內部排址位址，也就是如a，/a，b，/b在讀取解碼區塊20 中被解碼。 第5圖係根據第1圖所述之資料壓縮區塊40包括之dq 輸出緩衝器之電路圖。 如圖所示，此D Q輸出緩衝器包括在資料壓縮區塊4 0 中，此資料壓縮區塊40包括一選通控制產生器42，一比 較區塊44與一選通驅動區塊46。此外，在此顯示一 GIO 驅動器包括串列耦接於一供應電壓與接地之間的兩個Μ Ο S 電晶體Ρ Μ 1與Ν Μ 1。 此選通控制產生器42接收壓縮測試訊號tpara以及訊號 產生區塊所包括之選通訊號產生器輸出之選通訊號 i〇stb，藉以產生一第一與一第二資料選通訊號iostb2與 1 〇 s t 2 b。比較區塊4 4接收單元陣列8 0輸出之每一個資料 200523935 用以壓縮成1 6位元資料。最後地，此選通驅動區塊4 6輸 出一自比較區塊4 4輸出之壓縮資料至G10驅動器，以回 應第一與第二資料選通訊號iostb2與iostb2b。 ' 如上所述，此習知半導體記憶裝置能快速地藉由使用此 壓縮測試模式以測試所有之單元單位。 不過，包括在半導體記憶裝置之此測試模式不能測試一 排址插置模式（interleaving mode)，因爲包括在半導體記 憶裝置之所有排址係同步地被啓動。事實上，半導體記憶 裝置操作在此排址插置模式用以增加一操作速度。在排址 0 插置模式中，資料碰撞或偏離（skew)係發生在當資料是任 意地讀取與寫入在每一個排址間。 因此，用以測試一半導體記憶裝置在排址插置模式之操 作，資料不能被壓縮，所以結果是測試所需的時間會很長。 【發明內容】 因此本發明提出一種進階模式之半導體記憶裝置，用以 在半導體記億裝置的排址插置模式（interleaving mode)操 作中尋找錯誤以減少測試時間。 ® 從本發明的一觀點來看，本發明提出了 一種在壓縮測 試模式中測試具有多數個排址之半導體記憶裝置操作之方 法，包括下列步驟；（A )藉由同時啓動多數個排址以測 試該半導體記憶裝置（B )藉由隨機啓動多數個排址以測 試該半導體記憶裝置。 由本發明的另一觀點來看，本發明提出一種用以測試在 壓縮測試模式中具有多數個排址之半導體裝置操作之裝 200523935 置，包括一內部位址產生器，用以接收一外部排址位址以 及產生內部排址位址以回應一排址插置測試訊號；一讀取 操作測試區塊，用以接收內部排址位址與測試半導體記憶 裝置中的一讀取操作以回應排址插置測試訊號；一寫入操 作測試區塊，用以接收內部排址位址與測試半導體記憶裝 置的一寫入操作。 【實施方式】 以下將根據所附圖示仔細描述根據本發明之半導體記憶 體裝置。 第6圖係顯示根據本發明之使用在半導體記憶裝置中之 測試區塊圖。 如圖所不，此測試區塊包括一內部位址產生器100，一 讀取操作測試區塊與一寫入操作測試區塊。 此內部位址產生器1 00，接收一外部排址位址如ΒΑ0以 及產生內部排址位址如a與/a以回應一排址插置測試訊號 iocomp。此讀取操作測試區塊，用以接收內部排址位址如 a與/a及測試該半導體記憶裝置的一讀取操作以回應該排 址插置測試訊號iocomp。此寫入操作測試區塊，用以接 收內部排址位址如a與/a，以及測試此半導體記憶裝置的 一寫入操作。 在此，此讀取操作測試包括一讀取解碼區塊2 0 0，一壓 縮控制區塊3 0 0與一資料壓縮區塊4 0 0 ;以及一寫入操作 測試區塊，包括一寫入解碼區塊5 0 0，一寫入控制區塊6 0 0 與一寫入驅動區塊7 0 0。 •14- 200523935 更仔細地說，該內部排址位址產生器l 〇 〇轉換一排址位 址，例如 B A 0與 B A 1，以成爲多數個內部排址位址，也 就是a，/a，b，/b，c5 /c，d，/d，以回應一壓縮測試訊號tpara 與此排址插置測試訊號iocomp。在此，該內部排址位址， 也就是a，/a, b，/b，c，/c，d，/d，係被分類爲非延遲內部排 址位址，即a，/a，b，/b，與延遲內部排址位址，即 c, /c，d， /d。該些多數個內部排址位址如a，/a, b，/b，c，/c，d，/d 被輸入至該讀取解碼區塊2 0 0。此讀取解碼區塊2 0 0解碼 多數個內部排址位址，也就是a，/a，b，/b，c，/c，d，/d，藉 以產生多數個讀取排址操作訊號 rd__bank0，rd_bankl， rd_bank2 與rd_bank3，以回應一附加閂鎖訊骑AL0與該 排址插置測試訊號iocomp。此壓縮控制區.塊3 0 0係用以 控制該資料壓縮區塊4 0 0以回應該些讀取排址操作訊號 rd_bank0, rd — bankl，rd__b ank2 與 rd — bank3o 此資料壓縮 區塊400具有多數個DQ輸出緩衝器，用以壓縮每一個排 址所輸出的資料，藉以輸出一測試結果訊號以回應壓縮測 試訊號tpara與一排址非啓動訊號Xedb_ba。 此外，該非延遲內部排址位址，也就是a，/a，b，/b，被 輸入至寫入解碼區塊500。寫入解碼區塊500解碼內部排 址位址a，/a，b, /b的一部分，藉以產生多數個寫入排址操 作訊號 wt_b ankO, wt — bankl，wt_bank2 與 wt — bank3o 寫 入控制區塊6 0 0控制寫入驅動區塊7 0 0以回應一寫入啓動 訊號 WTen與多數個寫入排址操作訊號 wt_bank0, w t _ b a n k 1，w t _ b a n k 2 與 w t _ b a n k 3。寫入驅動區塊 7 〇 〇 用 -15- 200523935 以儲存輸入至包括在每一個排址之單元陣列8 0 0。 此外，該內部排址位址產生器1 〇 〇包括一閂鎖控制器 1 8 0，一緩衝區塊，一閂鎖區塊，一路由區塊。閂鎖控制 器1 8 0，用以接收壓縮測試訊號tpara與排址插置測試訊 號iocomp與控制一閂鎖控制訊號。緩衝區塊包括兩個緩 衝器，例如緩衝器1 2 0，每一個緩衝器用以接收一第一位 元排址位址ΒΑ0與一第二位元排址位址BA1，並且轉換 第一位元排址位址ΒΑ0與一第二位元排址位址BA1成爲 內咅β Ρ 址位址如 baO — add， baO — addb， bal—add，與 bal_addb，每一個皆對應至第一位元排址位址BAO與第二 位元排址位址B A 1。此閂鎖區塊包括兩個閂鎖器，如閂鎖 器140，每一個閂鎖器係被閂鎖控制訊號控制以傳輸內部 位址如 baO—addd， baO—addb， bal_add 與 bal—addb 至路由 區塊作爲非延遲內部排址位址如a，/a，b, /b。此路由區塊 也包括兩個路由器，例如路由器160，每一個路由器用以 延遲部分多數個內部排址位址如a，/a，b，/b，藉以產生作 爲延遲內部排址位址如c，/ c，d，/ d。 更仔細地說，壓縮測試區塊3 0 0包括一讀取控制區塊3 2 0 與一選通訊號產生區塊3 4 0。讀取控制區塊3 2 0包括多數 個讀取控制器，每一個控制器被一讀取啓動訊號RDen控 制以接收讀取排址操作訊號與輸出排址非插置訊號如 Xedb_ba至資料壓縮區塊40 0 ;以及一選通訊號產生區塊 34〇包括多數個選通訊號產生器，每一個選通訊號產生器 用以產生多數個選通訊號，例如i 〇 s t b ◦ -16- 200523935 在此，每一個讀取控制器，每一個選通訊號產生器與每 一個D Q輸出緩衝器係個別的對應至每一個包括在習知半 導體記憶裝置中之排址。此外，每一個緩衝區，每一個閂 鎖器以及每一個路由器在內部排址位址產生器中是個別地 對應至每一排址位址之每一位元。 接下來描述當壓縮測試訊號tpara被啓動時，半導體記 憶裝置的測試操作。 首先，內部排址位址產生器1 〇〇不管這些排址位址啓動 這些內部排址位址如a，/a，b，/b，c，/c，d，/d以回應壓縮 測試訊號tpara。然後，讀取解碼區塊2 0 0所輸出的這些 讀取排址操作訊號 rd__bank0，rd_bankl, rd_bank2與 rd_bank3以及寫入解碼區塊5 00所輸出的這些寫入排址操 作訊號 wt — bankO、wt_bankl、wt — bank2 與 wt_bank3 皆被 啓動。如果寫入啓動訊號WTen被啓動，寫入控制區塊600 與寫入驅動區塊7 0 0則被啓動，然後，資料被輸入至單元 陣列 800。此外，如果讀取啓動訊號RDen被啓動以回應 附加閂鎖訊號AL0與排址插置測試訊號iocomp，多數個 單元陣列8 00所輸出之資料LI00<0: 15>至LI<0: 15>則 被壓縮與輸出。此時，其他排址位址，如沒有被選擇到的 排址，輸出一邏輯高位準訊號取代測試結果訊號以回應排 址非啓動訊號如Xedb_ba。 在此，假如一經由資料墊所輸出之訊號的邏輯狀態是高 位準時，半導體記憶裝置不具有瑕疵單元；但是，否則此 半導體記憶裝置則至少具有一個瑕疵單元。 -17- 200523935 第7圖係描述在第6圖所示之閂鎖區塊的閂鎖器丨4 〇與 閂鎖控制器1 8 0之電路圖。 如圖所不，此問鎖控制器1 8 0包括第5反相器15與一 第六N AN D閘N D 6 ;閂鎖器1 4 0包括一第一閂鎖單元丨4 2， 一第二問鎖單元144，一第一 NAND閘ND1與一第二NAND 閘ND2。在此，此第一與第二閂鎖單元142與144係由兩 個電路集連接反相器所建構。 在閂鎖控制器1 80中，第五反相器15是用以反相排址 插置測試訊號iocomp。第六N AND閘接收第五反相器15 輸出的輸出訊號與壓縮測試訊號tpara藉以產生NAND操 作的一結果訊號。 此第一閂鎖單元1 42用以閂鎖一反相內部排址位址，如 ba0_addb ;以及第二閂鎖單元1 44則是用來閂鎖一內部排 址位址如b a 0 — a d d。第一 N A N D閘N D 1接收一問鎖控制器 1 8 0輸出的一輸出訊號與一反相內部排址位址，也就是內 部排址位址與一反相壓縮測試訊號以產生NAND操作的結 果訊號作爲一第一內部排址位址。再者，此第二NAN D閘 N D 2接收閂鎖控制器1 8 0所輸出的輸出訊號與反相壓縮測 試訊號來產生一 NAND操作的結果訊號作爲第一反相內部 排址位址/ a。 第8圖係描述在第6圖所示之路由區塊中的路由器之電 路圖。 如圖所示，此讀取解碼區塊2 0 0包括一控制訊號產生器 210與多數個解碼器2 2 0、240、2 6 0與2 8 0。此控制訊號 200523935 產生器210用以產生第一與第二控制訊號，如ALQb與 ALOd，以回應附加閂鎖訊號AL0、此壓縮測試訊號tpara 以及排址插置測試訊號i〇comp。每一個解碼器接收兩個 排址位址以回應此第一與第二控制訊號如ALOb與ALOd， 並且選擇這兩個內部排址位址的其中之一，藉以產生一反 相選擇位址作爲讀取排址操作訊號。在此，每一個解碼器 係與第4圖中的每一個習知解碼器的結構相同，因此，關 於每一個解碼器的詳細描述則省略。 更仔細地說，此控制訊號產生器210包括一第一 NOR 閘NR1用以執行此壓縮測試訊號tpara的操作與排址插置 測試訊號iocomp，一第九NAND閘ND9用以產生附加閂 鎖訊號AL0與第一 NOR閘NR1之輸出訊號於NAND操作 下的一結果訊號，以及一第六反相器16用以反相一第一 控制訊號ALOb，也就是自第九NAND閘ND9所輸出之訊 號，藉以產生一第二控制訊號A L 0 d。 第9圖係描述在第1圖所示之資料壓縮區塊的DQ輸出 緩衝器之電路圖。 如圖所示，此DQ輸出緩衝器，如緩衝器3 60，係包括 在一資料壓縮產區塊400中，此緩衝器包括一選通控制產 生器420，一比較區塊440，一選通驅動區塊460與一輸 出控制器48 0。此外，在此顯示一 GI0驅動器，包括兩個 串接於供應電壓與接地之間的M0S電晶體PM2與NM2。 此選通控制產生器42 0接收此壓縮測試訊號tpara與排 址非啓動訊號Xedb_ba與包括在訊號產生區塊3 4 0的選通 -19- 200523935 訊號產生器輸出之選通訊號i 〇 s t b，藉以產生一輸出控制 訊號tgiob、一第一與第二資料選通訊號i〇stb2與10stb2b。 比較區塊 44〇接收單元陣列 80輸出的每一個資料 LI00<0:15>至LI03<0:15>，用以壓縮此16位元的資料作 爲測S式結果訊號。再者’此選通驅動區塊4 6 0輸出比較區 塊 440所輸出之一壓縮資料至GI0驅動器以回應此第一 與第二資料選通訊號i〇stb2與iostb2b。最後，輸出控制 器4 8 0包括兩個N AN D閘，用以選擇性地輸出此測試結果 訊號與一邏輯高位準訊號以回應輸出控制訊號tgi 〇b。 在此，假如排址非啓動訊號如Xedb_ba被啓動後，此對 應排址會輸出邏輯高位準訊號。這是因爲一排址輸出一邏 輯低位準訊號假如此排址至少具有一個瑕疵單元。假如沒 被選擇的排址中的其中之一輸出一邏輯低位準訊號，在選 擇到的排址發現錯誤則是可能的。 第10圖係描述在第6圖所示之寫入解碼區塊之電路圖。 如圖所述’寫入解碼區塊500包括四個NAND閘，每一 個N AND閘用以接收非延遲內部排址位址，藉以產生寫入 排址操作訊號，如 w t _ b a n k 0。在此，寫入解碼區塊 5 0 0 僅接收非延遲內部排址位置，因爲寫入操作之閂鎖通常較 其用於半導體記憶裝置的讀取操作短一個時脈週期。 如上所述，此測試區塊藉由使用壓縮測試模式來測試半 導體記憶裝置中的排址插置模式。此外，此半導體記億裝 置能快速地測試所有的單元單位係藉由使用壓縮測試模 式。 -20- 200523935 在此，雖然此測試所使用之內部排址位址在本發明中係 藉由附加閂鎖所控制，但此測試能不用顧慮附加閂鎖來執 行。 因此，在排址插置模式中用以測試半導體記憶裝置的操 作’壓縮測試模式能被實行，而所需要的測試時間則明顯 的減少。 本.發明之應用係與韓國專利第 2004-18919與第 2004-0 1 8 24號之專利案相關，上述專利申請案係分別在2 0 04 年3月19號與2004年1月10號於韓國專利局被提出申 請，整個內容係藉由這些例子在此整合。 當本發明已依據這些特別實施例敘述之後，本發明係與 習知技術有種種不同，熟習此技藝者可在不脫離本發明的 精神與範圍內做種種的改變與修正，因此本發明之保護範 圍當視後附之專利範圍爲準。 【圖式簡單說明】 第1圖係顯示一用在習知半導體記憶裝置的一測試區塊 之方塊圖； 第2圖係用來描述第1圖中在閂鎖區塊所包括的閂鎖器 之結構電路圖； 第3圖係用來描述第1圖中在路由區塊所包括的路由器 之結構電路圖； 第4圖唯一如第1圖中描述讀取解碼區塊的電路圖； 第5圖係根據第1圖所述之資料壓縮區塊包括之D Q輸 出緩衝器之電路圖； -21- 200523935 第6圖係顯不根據本發明之使用在半導體記憶裝置中之 一測試區塊圖； 第7圖係描述在第6圖所示之閂鎖區塊的閂鎖器之電路 圖； 第8圖係描述在第6圖所示之路由區塊的路由器之電路 圖； 第9圖係描述在第1圖所示之資料壓縮區塊的DQ輸出 緩衝器之電路圖； 第10圖係描述在第6圖所示之寫入解碼區塊之電路圖。 元件代表符號 10、100 內部排址位址產生器 20 ' 200 讀取解碼區塊 2 1 控制訊號產生器 22 、 24 、 26 、 28 解碼器 30 壓縮控制區塊 32 、 320 讀取控制區塊 34、340 選通訊號產生區塊 3 6、360 DQ輸出緩衝器 40、400 資料壓縮區塊 42 、 420 選通控制產生器 44 ' 440 比較區塊 46' 460 選通驅動區塊 480 輸出控制器 200523935 50 、 500 寫入解碼區塊 60 、 600 寫入控制區塊 70 、 700 寫入驅動區塊 80 、 800 單元陣列 BAO 第一位元排址位址 BA1 第二位元排址位址 12 、 120 緩衝器 14 、 140 閂鎖器 16 、 160 路由器 11 第一反相器 14a 、 142 第一閂鎖單元 14b 、 144 第二閂鎖單元 ND1 第一 NAND閘 ND2 第二NAND閘 ND3 第三NAND閘 ND4 第四NAND閘 ND5 第五NAND閘 ND6 第六NAND閘 ND7 第七NAND閘 ND8 第八NAND閘 ND9 第九NAND閘 PM1、NM1 MOS電晶體 a，/a，b，/b 內部排址位址200523935 IX. Description of the invention: [Technical field to which the invention belongs] The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device with enhanced testing capabilities for discovering the operation of the semiconductor memory device in the insert mode. mistake. [Prior Art] A semiconductor memory device includes a plurality of memory cells. If any of the cells in the body device are out of the operating sequence, the semiconductor record is unusable. After the semiconductor memory device manufacturing process, a test program is needed to find defective cells in the semiconductor memory device. Generally, the semiconductor memory device has an additional area for measuring a circuit, and this circuit can test a cell when the semiconductor device is at a high speed. However, according to the increase in the integration of semiconductor devices, much time and effort are required to test the cells of the semiconductor devices and develop the semiconductor devices. Therefore, in order to save time for testing a semiconductor device, a compression test method is used. In this compression test mode, data is input to all banks included in the semiconductor via a part of the input / output pins (DQs) instead of all the input / output pins (DQs). It is used to confirm the data output from each unit cell. The output data is not output from all the addresses through all input / output pins at the same time. Among them, most of these gates, such as AND NOR gates, each correspond Until each input / output pin DQ s is stupid, there is a flaw in a row of semi-conductors installed here. Some test the synchronized input and output addresses of the test mode, and each DQs is turned on or off. 200523935 Figure 1 shows a block diagram of a test block used in a conventional semiconductor memory device. As shown in the figure, the test block includes an internal address generator 10, a read decode block 20, a compression control block 30, a data compression block 40, and a write decode Block 50, a write control block 60 and a write drive block 70. The internal address generator 10 converts bank addresses such as BAA0 and BA1 to become a plurality of internal address addresses, such as a, / a, b, / b, c, / c, d, / d. The plurality of internal addressing addresses such as a, / a, b, / b, c, / c, d, / d are all input to the read decoding block 20. The read and decode block 20 decodes a plurality of internal bank addresses such as a, / a, b, / b, c, / c, d, / d, thereby generating a plurality of read bank operation signals rd_bank0, rd_bankl , Rd_bank2 and rd_bank3 in response to the additional latch signal AL0. The compression control block 30 is used to control the data compression block 40 in response to most of the read addressing operation signals rd_bank0, rd_bankl, rd_bank2 and rd_bank3. The data compression block 40 has a plurality of DQ output buffers. For example, the D Q output buffer 36 is used to compress the data outputted by the data of each bank. In addition, some of the internal addresses such as a, / a5 b, / b are input to the write decoding block 50. The write decoding block 50 decodes most internal addressing addresses such as a, / a, b, / b, thereby generating a plurality of write addressing operation signals wt — bankO, wt_bankl, wt_bank2, wt — bank3. The write control block 60 is used to control the write drive block 70 in response to the write start signal W dingen and most write address operation signals wt_bank0, wt bankl, 200523935 wt —bank2, Wt_bank3. The write driving block 70 stores data input in a cell array 80 included in each address. In addition, the internal address generator 10 includes a buffer block, a lock block and a routing block. The buffer block includes two buffers, such as buffer 12, each of which is used to receive a first bit address BAA0 and a second bit address BA1 and convert the first bit The address BBA0 and the second bit address BA1 become the internal address such as baO — add, baO — addb, ba 1 — add and bal — addb. Each buffer corresponds to the first bit. The address BA 0 and the second bit address BA 1. The latch block includes two latches, such as latches 14, each of which is controlled by a compression test signal tpara to transmit internal addressing addresses such as baO — add, baO — addb, bal — add And bal-addb to the routing block such as some of the most internally located addresses a, / a, b, / b. The routing block also includes two routers, such as router 16, each router is used to delay some of the most internally-addressed addresses such as a, / a, b, / b to generate most other internally-addressed addresses such as c5 / c, d, / d. More specifically, the compression control block 30 includes a read control block 32 and a selection signal generation block 34. The read control block 32 includes a plurality of read controllers, and each controller is controlled by a read start signal RDen to receive a read address operation signal; the selection signal generation block 3 4 includes a plurality of selection signals. Generator, each selection signal generator is used to generate a plurality of selection signals, such as i 0stb. Here, each read controller, each selected signal number generator and each DQ output buffer are individually corresponding to each of the addresses included in the conventional semiconductor memory 200523935 device. In addition, each buffer, each latch, and each router in the internal addressing address generator 10 individually correspond to the bits of each addressing address. After that, a test operation of the semiconductor memory device is described when the compression test signal tpara is activated. First, the internal address generator 10 responds to the compression test signal tpara regardless of the address, and starts the internal address such as a, / a, b, / b, c, / c, d, / d. Then, read the read address operation signals rd_bankO, rd_bankl, rd_bank2 and rd_bank3 output from the decode block 20 and read the write address operation signals wt_bank0, wt-bankl, wt__bank2 and wt_bank3 are all enabled. If the write enable signal WTen is activated, the write control block 60 and the write drive block 70 are activated, and then data is input to the cell array 80. In addition, if the read enable signal RDe is activated, most of the data LI00 < 0: 15 > to LI < 0: 15 > output from the cell array 80 are compressed and output. In addition, the operation method of the test block, that is, the method used to decode the compressed data and compressed output data is carefully described. In the conventional memory device, each address has a data pad for receiving four data at a time. These four data are considered as a data string (BUNCH); and the four data strings constitute a 16-bit data. In a write operation, the same 16-bit data is input to each location. In the reading operation, 16-bit data is input to each address of the four data strings that are classified; each data (datum) is input through the same data pad, which is between four of each data string. These data are compared with each other compared with 200523935. Then through the data pad corresponding to each location, the comparison result is output. Here, if a logic state of the signal output through the data pad is a high logic level, the semiconductor memory device does not have a defective unit; but on the contrary, the semiconductor ifime memory device has at least one defective unit. FIG. 2 is a circuit diagram for describing the structure of the latch included in the latch block 14 in FIG. 1. FIG. As shown, the latch includes a first inverter 11, a first latch unit 14a, a second latch unit 14b, a first NAND gate ND1 and a second NAN D gate ND2. Here, the first and second latch units Ma and 14b are composed of two sets of circuits connected to the inverter. The first inverter I 1 is used to invert the compression test signal tpara. The first latch unit 14a is used to latch an inverted internal address, such as b a 0_addb; the second latch unit 14b is used to latch an internal address, such as baO-add. The first NAND gate ND1 is coupled to the first latch unit 14a and the first inverter I1, and receives an inverted state of one of the inverted internal bank addresses, that is, the internal bank The address and inverse compression test signals are used to generate a result signal of a NAND operation such as the first internal address a. Furthermore, the second NAND gate ND2 is coupled to the second latch unit 14b and the first inverter Π receives an inverted state of the internal address, that is, the inverted internal address. And an inverse compression test signal to generate a result signal of a NAND gate operation such as a first internal address / a. Fig. 3 is a circuit diagram for describing the structure of the router included in the routing block 16 in Fig. 1. As shown in the figure, the router includes a latch and delay block 17, a 200523935 second inverter 12, a third NAND gate ND3 and a fourth NAND gate ND4. The latch and delay block 17 receives the first internal address, that is, a, and the first inverted internal address, that is, / a, and outputs a delayed signal from the latch output to the The third NAND gate. The second inverter 12 is used to invert the compression test signal tpara. The third NAND gate ND3 is coupled to the latch and delay blocks. 17 and the second inverter 12 receive an output signal from the latch and delay blocks 17 and an inverse compression test signal is generated as a third The result signal of one of the NAND operations at the internal address c. Furthermore, the second NAN D gate ND2 is coupled to the first inverter II to receive a third internal address, that is, c and an inverse compression test signal to generate a third inverting address / One of the result signals of NAND operation of c. Referring to these examples, each latch has the same architecture as each router individually; therefore, detailed descriptions of the latches and routers are omitted. FIG. 4 is a circuit diagram describing reading the decoding block 20 in FIG. 1. As shown in the figure, the read decoding block 20 includes a control signal generator 21 and a plurality of decoders 22, 24, 26, and 28. The control signal generator 21 generates control signals such as A L 0 b and A L 0 d in response to the additional latch signal AL0. Each decoder receives two internal address addresses and selects one of the two internal address addresses in response to control signals such as ALOb and ALOd, thereby generating an inverted selection address as a read address operation signal. More specifically, the control signal generator 21 includes a third inverter I 3 for inverting the compression test signal, and a fifth NAND gate ND5 for generating the result of the additional latch signal AL0. The test signal and the inversion The compression test signal and a fourth inverter 14 are used to invert a first control signal al 0 b, that is, 200523935 is a signal output by the fifth N AND gate ND5 to generate a second control signal AL 0 d. Each decoder includes two NAND gates, two transmission gates, and an inverter. One of every two NAND gates receives two internally addressed addresses and generates one of the NAND operation result signals; one of every two transmission gates transmits this result signal in response to the first and second control signals ALOb and ALOd ° Then the 'inverter converts the output signals output by the two transmission gates' to generate the inverted signal of the output signal as the read address operation signal. Referring to FIG. 4, the read decoding block 20 includes four decoders. Most of the internal addressing addresses', namely a, / a, b, / b, c, / c, d, / d, are classified into four ethnic groups, each of which includes four internal addressing addresses: (/ A, / b, / c, / d), (a, / b, c, / d), (/ a, b, / c, d), (a, b, c, d) ° Here 'Each decoder, such as decoder 22, decoder 24, decoder 26, and decoder 28, decodes a group of non-delayed internal addressing addresses output by the latch block, that is, a, / a, b , / B, and the delay internal address of the output of the routing block, that is, c, / c, d, / d, in response to the first and second control signals ALOb and ALOd. In the conventional memory device, a RAS to CAS delay tRCD is required. TRCD is provided by one of a minimum time of a series of activation signals to supply a row of activation signals. However, if an additional latch is introduced to increase the operating speed of one of the semiconductor memory devices, the activation signal of this line is supplied before the delay to tRCD from RAS to C AS, and after the activation signal of the column is supplied. That is, 200523935 According to this additional latch, the timing sequence for supplying the activation signal of this line can be adjusted. If the additional latch signal AL0 is not activated, for example, the additional latch signal is 2 or 3, the activation signal of this line is input before the delay of tS CD from raS to C AS, and then there is a lot of time margin here. Used to access data in response to a line start signal. In this example, because there is a lot of time margin, the internal address is delayed, that is, c, / c, d, / d, which is read in decoding block 2 0 and decoded by routing block 1 6 delay. In addition, "If this additional latch signal AL 0 is activated, for example, this additional lock signal is 0, this line activation signal is input after the RAS to CAS delay tRCD" Then, there is a lot of time to access the data in response to this Start the signal contact information. In this example, because of some time margin, the non-delayed internal addressing address, that is, such as a, / a, b, / b is decoded in the read decoding block 20. FIG. 5 is a circuit diagram of a dq output buffer included in the data compression block 40 according to FIG. 1. As shown, the D Q output buffer is included in the data compression block 40. The data compression block 40 includes a gate control generator 42, a comparison block 44 and a gate driving block 46. In addition, it is shown here that a GIO driver includes two MOS transistors PM and NM 1 coupled in series between a supply voltage and ground. The gating control generator 42 receives the compression test signal tpara and the selection signal i0stb output by the selection signal generator included in the signal generation block, thereby generating a first and a second data selection signal iostb2 and 1 〇st 2 b. Compare each data output from the receiving unit array 80 of block 4 4 200523935 to compress it into 16-bit data. Finally, the gating drive block 46 outputs a compressed data output from the comparison block 44 to the G10 driver in response to the first and second data selection communication numbers iostb2 and iostb2b. As mentioned above, this conventional semiconductor memory device can quickly test all unit units by using this compression test mode. However, the test mode included in the semiconductor memory device cannot test an interleaving mode because all the addressing included in the semiconductor memory device are activated simultaneously. In fact, the semiconductor memory device operates in this address insertion mode to increase an operation speed. In the location 0 interpolation mode, data collision or skew occurs when data is read and written arbitrarily between each location. Therefore, to test the operation of a semiconductor memory device in the address insertion mode, data cannot be compressed, so the result is that the time required for the test will be long. [Summary of the Invention] Therefore, the present invention proposes an advanced mode semiconductor memory device for finding errors in the interleaving mode operation of a semiconductor memory device to reduce test time. From a viewpoint of the present invention, the present invention proposes a method for testing the operation of a semiconductor memory device having a plurality of locations in a compression test mode, including the following steps; (A) by activating the plurality of locations simultaneously to Testing the semiconductor memory device (B) tests the semiconductor memory device by randomly activating a plurality of locations. From another viewpoint of the present invention, the present invention provides a device for testing the operation of a semiconductor device having a plurality of addresses in a compression test mode. The device includes an internal address generator for receiving an external address. Address and generating an internal address to respond to an address insertion test signal; a read operation test block to receive an internal address and a read operation in a test semiconductor memory device to respond to the address A test signal is inserted; a write operation test block is used to receive an internal address and a write operation for testing a semiconductor memory device. [Embodiment] A semiconductor memory device according to the present invention will be described in detail below with reference to the accompanying drawings. Fig. 6 is a block diagram showing a test used in a semiconductor memory device according to the present invention. As shown in the figure, the test block includes an internal address generator 100, a read operation test block and a write operation test block. The internal address generator 100 receives an external address such as ΒΑ0 and generates internal address such as a and / a in response to an address insertion test signal iocomp. This read operation test block is used to receive internal address addresses such as a and / a and test a read operation of the semiconductor memory device in response to the address insertion test signal iocomp. The write operation test block is used to receive internal address addresses such as a and / a, and to test a write operation of the semiconductor memory device. Here, the read operation test includes a read decode block 200, a compression control block 300 and a data compression block 400; and a write operation test block including a write Decoding block 5 0 0, a write control block 6 0 0 and a write drive block 7 0 0. • 14- 200523935 More specifically, the internal address generator 100 converts an address, such as BA 0 and BA 1, to become the most internal address, which is a, / a , B, / b, c5 / c, d, / d, in response to a compression test signal tpara and an interposition test signal iocomp. Here, the internal address, that is, a, / a, b, / b, c, / c, d, / d, is classified as a non-delayed internal address, that is, a, / a, b, / b, and the delayed internal address, that is, c, / c, d, / d. The plurality of internal addressing addresses such as a, / a, b, / b, c, / c, d, / d are input to the read decoding block 2 0 0. This read decoding block 2 0 decodes most internal addressing addresses, that is, a, / a, b, / b, c, / c, d, / d, thereby generating a plurality of reading addressing operation signals. rd__bank0, rd_bankl, rd_bank2 and rd_bank3 in response to an additional latch signal riding AL0 and the address insertion test signal iocomp. This compression control area. Block 3 0 0 is used to control the data compression block 4 0 in response to some read addressing operation signals rd_bank0, rd — bankl, rd__b ank2 and rd — bank3o. This data compression block 400 has A plurality of DQ output buffers are used to compress the data output from each bank, thereby outputting a test result signal in response to the compression test signal tpara and a bank non-start signal Xedb_ba. In addition, the non-delayed internal address, that is, a, / a, b, / b, is input to the write decoding block 500. The write decoding block 500 decodes a part of the internal address a, / a, b, / b, thereby generating a plurality of write address operation signals wt_b ankO, wt — bankl, wt_bank2 and wt — bank3o write control area Block 6 0 controls the write drive block 7 0 in response to a write enable signal WTen and a plurality of write address operation signals wt_bank0, wt_bank 1, wt_bank 2 and wt_bank 3. Write the drive block 7 〇 〇 -15- 200523935 to store the input to the cell array 800 included in each address. In addition, the internal address generator 100 includes a latch controller 180, a buffer block, a latch block, and a routing block. The latch controller 180 is used to receive a compression test signal tpara and an address insertion test signal iocomp and control a latch control signal. The buffer block includes two buffers, such as buffer 1 2 0. Each buffer is used to receive a first bit address BAA0 and a second bit address BA1, and convert the first bit The address BBA0 and a second bit address BA1 become internal β β addresses such as baO — add, baO — addb, bal — add, and bal_addb, each of which corresponds to the first bit. The address BAO and the second bit address BA 1. This latch block includes two latches, such as latch 140, each latch is controlled by a latch control signal to transmit internal addresses such as baO_addd, baO_addb, bal_add and bal_addb to The routing block is used as a non-delayed internal address such as a, / a, b, / b. This routing block also includes two routers, such as router 160, each of which is used to delay some of the most internally addressed addresses such as a, / a, b, / b to generate a delayed internally addressed address such as c , / C, d, / d. More specifically, the compression test block 3 0 0 includes a read control block 3 2 0 and a selected signal generation block 3 4 0. The read control block 3 2 0 includes a plurality of read controllers. Each controller is controlled by a read start signal RDen to receive read address operation signals and output address non-inserted signals such as Xedb_ba to the data compression area. Block 40 0; and a selection signal generation block 34 0 includes a plurality of selection signal generators, each selection signal generator is used to generate a plurality of selection signals, such as i 〇stb ◦ -16- 200523935 Here, Each read controller, each selection signal generator and each DQ output buffer are individually corresponding to each of the addresses included in the conventional semiconductor memory device. In addition, each buffer, each latch, and each router individually corresponds to each bit of each address in the internal address generator. Next, the test operation of the semiconductor memory device when the compression test signal tpara is activated will be described. First, the internal address generator 100 starts these internal address addresses such as a, / a, b, / b, c, / c, d, / d in response to the compression test signals regardless of the address. tpara. Then, read the read address operation signals rd__bank0, rd_bankl, rd_bank2, and rd_bank3 output from the read decode block 2 0 0 and write write address operation signals wt — bankO, wt_bankl output from the decode block 5 00. , Wt — bank2 and wt_bank3 are all enabled. If the write enable signal WTen is activated, the write control block 600 and the write drive block 700 are activated, and then the data is input to the cell array 800. In addition, if the read enable signal RDe is activated in response to the additional latch signal AL0 and the address insertion test signal iocomp, the data LI00 < 0: 15 > to LI < 0: 15 > output by the plurality of cell arrays 8 00 then Compressed and output. At this time, if the other address is not selected, a logic high level signal is output instead of the test result signal in response to the non-starting signal of the address, such as Xedb_ba. Here, if the logic state of the signal output through the data pad is high, the semiconductor memory device does not have a defective unit; otherwise, the semiconductor memory device has at least one defective unit. -17- 200523935 Figure 7 is a circuit diagram describing the latch 丨 4 0 and the latch controller 180 in the latch block shown in Figure 6. As shown in the figure, the lock controller 1 80 includes a fifth inverter 15 and a sixth N AN D gate ND 6; the latch 1 4 0 includes a first latch unit 4 2, a first The two lock units 144 include a first NAND gate ND1 and a second NAND gate ND2. Here, the first and second latch units 142 and 144 are constructed by connecting two circuit sets to inverters. In the latch controller 180, the fifth inverter 15 is used to invert the address and insert the test signal iocomp. The sixth N AND gate receives the output signal and the compression test signal tpara from the fifth inverter 15 to generate a result signal of the NAND operation. The first latch unit 142 is used to latch an inverted internal address, such as ba0_addb; and the second latch unit 144 is used to latch an internal address, such as b a 0 — a d d. The first NAND gate ND 1 receives an output signal output from the lock controller 180 and an inverted internal address, that is, the internal address and an inverted compression test signal to generate the result of the NAND operation. The signal serves as a first internal address. Furthermore, the second NAN gate ND 2 receives the output signal output from the latch controller 180 and the inverse compression test signal to generate a NAND operation result signal as the first inverted internal address / / . FIG. 8 is a circuit diagram describing a router in the routing block shown in FIG. 6. FIG. As shown in the figure, the read decoding block 2 0 includes a control signal generator 210 and a plurality of decoders 2 2 0, 240, 2 6 0, and 2 8 0. The control signal 200523935 generator 210 is used to generate first and second control signals, such as ALQb and ALOd, in response to the additional latch signal AL0, the compression test signal tpara, and the address insertion test signal i0comp. Each decoder receives two addressing addresses in response to the first and second control signals such as ALOb and ALOd, and selects one of the two internal addressing addresses, thereby generating an inverted selection address as Read the address operation signal. Here, the structure of each decoder is the same as that of each of the conventional decoders in FIG. 4, and therefore, a detailed description of each decoder is omitted. More specifically, the control signal generator 210 includes a first NOR gate NR1 to perform the operation of the compression test signal tpara and an address insertion test signal iocomp, and a ninth NAND gate ND9 to generate an additional latch signal. The output signal of AL0 and the first NOR gate NR1 is a result signal under NAND operation, and a sixth inverter 16 is used to invert a first control signal ALOb, which is the signal output from the ninth NAND gate ND9. To generate a second control signal AL 0 d. FIG. 9 is a circuit diagram describing the DQ output buffer of the data compression block shown in FIG. 1. FIG. As shown in the figure, the DQ output buffer, such as buffer 3 60, is included in a data compression block 400. The buffer includes a gate control generator 420, a comparison block 440, and a gate. The driving block 460 and an output controller 480. In addition, a GI0 driver is shown here, including two M0S transistors PM2 and NM2 connected in series between the supply voltage and ground. The gating control generator 42 0 receives the compression test signal tpara and the non-starting signal Xedb_ba and the gating-19- 200523935 included in the signal generating block 3 4 0. The selection signal i 〇stb output by the signal generator, Thereby, an output control signal tgiob, a first and a second data selection signal i0stb2 and 10stb2b are generated. Each piece of data LI00 < 0: 15 > to LI03 < 0: 15 > output by the receiving block array 80 in the comparison block 44 is used to compress the 16-bit data as the S-type result signal. Furthermore, one of the gating driving blocks 460 output comparison block 440 outputs compressed data to the GI0 driver in response to the first and second data selection communication numbers iostb2 and iostb2b. Finally, the output controller 480 includes two N AN D gates for selectively outputting the test result signal and a logic high level signal in response to the output control signal tgi 0b. Here, if a non-starting signal such as Xedb_ba is activated, this corresponding address will output a logic high signal. This is because an address outputs a logic low level signal so that the address has at least one defective unit. If one of the unselected locations outputs a logic low level signal, it is possible to find an error in the selected location. FIG. 10 is a circuit diagram describing a write decoding block shown in FIG. 6. FIG. As shown in the figure, the write decoding block 500 includes four NAND gates, each N AND gate is used to receive a non-delayed internal address, thereby generating a write address operation signal, such as w t _ b a n k 0. Here, the write decode block 5 0 0 only receives the non-delayed internal address location, because the latch of the write operation is usually one clock cycle shorter than the read operation of the semiconductor memory device. As mentioned above, this test block tests the address insertion mode in a semiconductor memory device by using a compression test mode. In addition, this semiconductor memory device can quickly test all unit units by using a compression test mode. -20- 200523935 Here, although the internal address used in this test is controlled by the additional latch in the present invention, the test can be performed without concern for the additional latch. Therefore, the operation 'compression test mode for testing the semiconductor memory device in the address insertion mode can be implemented, and the required test time is significantly reduced. The application of this invention is related to the Korean Patent Nos. 2004-18919 and 2004-0 1 8 24. The above patent applications were filed on March 19, 2004 and January 10, 2004, respectively. The Korean Patent Office was filed and the entire content is incorporated here with these examples. After the present invention has been described according to these special embodiments, the present invention is different from the conventional technology. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection of the present invention The scope is subject to the scope of the attached patent. [Brief description of the drawings] FIG. 1 is a block diagram showing a test block used in a conventional semiconductor memory device; FIG. 2 is a diagram for describing a latch included in the latch block in FIG. 1 Structure circuit diagram; Figure 3 is used to describe the structure circuit diagram of the router included in the routing block in Figure 1; Figure 4 is the only circuit diagram that reads and decodes the block as described in Figure 1; Figure 5 is based on The circuit diagram of the DQ output buffer included in the data compression block described in Figure 1; -21- 200523935 Figure 6 shows a block diagram of a test block used in a semiconductor memory device according to the present invention; Figure 7 is The circuit diagram of the latch described in the latch block shown in Fig. 6; Fig. 8 is the circuit diagram of the router described in the routing block shown in Fig. 6; and Fig. 9 is described in Fig. 1 The circuit diagram of the DQ output buffer of the data compression block; FIG. 10 is a circuit diagram describing the write decoding block shown in FIG. Component symbol 10, 100 Internal address generator 20 '200 Read decode block 2 1 Control signal generator 22, 24, 26, 28 Decoder 30 Compression control block 32, 320 Read control block 34 , 340 selection signal generation block 3 6, 360 DQ output buffer 40, 400 data compression block 42, 420 gating control generator 44 '440 comparison block 46' 460 gating driving block 480 output controller 200523935 50, 500 write decode block 60, 600 write control block 70, 700 write drive block 80, 800 cell array BAO first bit address BA1 second bit address 12, 120 Buffer 14, 140 latch 16, 160 router 11 first inverter 14a, 142 first latch unit 14b, 144 second latch unit ND1 first NAND gate ND2 second NAND gate ND3 third NAND gate ND4 The fourth NAND gate ND5 The fifth NAND gate ND6 The sixth NAND gate ND7 The seventh NAND gate ND8 The eighth NAND gate ND9 The ninth NAND gate PM1, NM1 MOS transistors a, / a, b, / b internal address
-23- 200523935 i o c o mp 排址插置測試訊號 tp ar a 壓縮測試訊號 11 第一反相器 12 第二反相器-23- 200523935 i o c o mp address test signal tp ar a compression test signal 11 first inverter 12 second inverter
-24--twenty four-