TW200529439A - Method of fabricating thin film transistor array substrate and stacked thin film structure - Google Patents

Abstract

Method of fabricating thin film transistor array substrate is disclosed. The fabricating method of thin film transistor array substrate is forming a first patterned metal layer, a dielectric layer, an amorphous silicon layer, a second patterned metal layer and a passivation layer on a substrate orderly, first. Then, forming a patterned photoresist layer on the passivation layer. The patterned photoresist layer at least covers source/drain and the areas beside them, which formed with the first patterned metal layer. The patterned photoresist layer has a plurality of thinner regions on parts of edge. Each of the thinner regions stretches over on the parts of edge of one source/drain. After, etching with the patterned photoresist layer for mask until the source/drain and the amorphous silicon layer that under the thinner regions are exposed to form a plurality of stair-structures. Finally, forming a plurality of pixel electrodes to cover the stair-structures and electrically connect one source/drain, respectively.

Description

200529439 V. Description of the invention (1) Technology of the invention The present invention relates to a thin film substrate and a thin film laminated structure, and a method for manufacturing a thin film structure that can improve the yield of a process. Prior art transistor array substrates (TFT array manufacturing methods, and in particular, related to crystal array substrates and thin-film laminated junctions are targeted at the various aspects of the multimedia society, and progress has been greatly benefited by semiconductor devices. The enthusiasm of staff and devices has not improved. As far as the display is concerned, the cathode ray tube (CRT) is

Economy 'has been monopolizing the display market in recent years. However, for the environment where individuals operate most terminals / display devices on the table, or from the perspective of environmental protection, if the trend of energy saving is predicted, there are still many problems in cathode ray tubes due to space utilization and energy consumption. Demands for light, thin, short, small, and low power consumption cannot effectively provide a solution. Therefore, thin film transistor liquid crystal displays (T h i n F i 1 m) with superior characteristics such as high daylight quality, increased space utilization efficiency, low power consumption, and unregulated emission.

Transistor Liquid Crystal Display (TFT LCD) has gradually become the mainstream of the market. The display panel used in general color thin film transistor liquid crystal displays is mainly composed of a thin film transistor array substrate, a color filter array substrate (Co 1 or filter array substrate), and a liquid crystal layer. The thin film transistor array substrate is composed of a plurality of It consists of thin film transistors arranged on an array on a glass substrate, pixel electrodes (pi xel /, E 1 ectrode), scanning wires and data wires arranged in correspondence with the thin film transistors. The above film

200529439 V. Description of the invention (2) The transistor system includes Gate, Channel, Drain, and Source, and these thin-film transistor systems are used to control each pixel Action of liquid crystal molecules. Figures 1A to 1C are schematic partial cross-sectional views showing the manufacturing process of a conventional thin film transistor array substrate. Please refer to FIG. 1A. A conventional method for manufacturing a thin film transistor array substrate includes the following steps: First, a substrate is provided, and then a metal layer is formed on the substrate, and photolithography and photolithography are used. # Etching (Etching) pattern the first metal layer to form a gate electrode 1 1 0. Then, a dielectric layer 12 0 and an amorphous silicon layer 1 3 ο are sequentially and comprehensively deposited on the substrate 100 to cover the gate 丨 0. Then, a second metal layer is formed on the amorphous silicon layer 130, and the second metal layer is patterned by lithography and etching to form a source / drain 140. After that, a protective layer 501 is formed on the substrate 100 in a comprehensive manner, and a patterned photoresist layer 160 is formed on the protective layer 150 on the source / drain electrode 140. Next, referring to FIG. 1B, using the patterned photoresist layer 160 as a mask, isotropically etch the protective layer 150 to remove the protective layer not covered by the patterned photoresist layer 16 150, the amorphous silicon layer 130 and the dielectric layer 120. However, when the protective layer 150, the non-crystalline silicon layer 130, and the dielectric layer 120 are etched, the selection of the etching solution often makes the etching rate of the amorphous silicon layer 130 more than that of the dielectric layer 12 Etch rate of 〇, so when the amorphous silicon layer 130 is etched and the dielectric layer 120 is continued to be etched, the amorphous silicon layer 130 will continue to be etched, and an undercut phenomenon occurs in area a (Undercut ).

12406twf.ptd Page 8 200529439 V. Description of the invention (3) Finally, referring to Figure 1C, a pixel electrode 1 7 0 is formed on the substrate 1 0 0, and the pixel electrode 1 7 0 is a transparent protective layer 1 5 0 The opening is electrically connected to the source / drain 1400. However, the above-mentioned undercut phenomenon often makes the step coverage of the day element electrode 170 in the area A poor, and then breaks (Broken). Therefore, the image signal cannot be written smoothly. The day element electrode 170, at the same time, also reduces the process yield of the thin film transistor array substrate. SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a method for manufacturing a thin film transistor array substrate and a thin film laminated structure, which are suitable for improving the process yield. Based on the above object, the present invention proposes a method for manufacturing a thin film transistor array substrate. In this method, a first patterned metal layer, a dielectric layer, an amorphous stone layer, a second patterned metal layer, and a protective layer are sequentially formed on a substrate in order. The first patterned metal layer includes a plurality of scanning wirings and a plurality of gates connected to the scanning wiring, and the second patterned metal layer includes a plurality of data wirings and a plurality of source / sinks connected to the data wirings. pole. Next, a patterned photoresist layer is formed on the protective layer. The patterned photoresist layer covers at least the source / drain and its surrounding area. A part of the edge of the patterned photoresist layer has a plurality of smaller thicknesses. A thinned region, each of the first thinned regions straddling a portion of an edge of one of the source / drain electrodes, respectively. Then, using the patterned photoresist layer as a mask, the protective layer, the amorphous silicon layer, and the dielectric layer not covered by the patterned photoresist layer are removed, and the protective layer under the first thinned region is removed to form a corresponding Multiple stepped structures in the first thinned area

12406twf.ptd Page 9 200529439 V. Description of the invention (4) Finally, a plurality of day electrodes are formed on the substrate, each pixel electrode respectively covers at least one of the stepped structures, and is electrically connected to the source / Drain one of them. In the manufacturing method of the thin film transistor array substrate of the present invention, the method of forming the patterned photoresist layer is, for example, forming a photoresist layer on the protective layer first. Next, a half-tone mask is provided, and the half-tone mask is used as a mask for front exposure and development of the photoresist layer. The half-tone mask has a light-transmitting region, a semi-light-transmitting region, and a non-light-transmitting region, and the first thinned region corresponds to the semi-light-transmitting region of the half-tone mask. In addition, in the method for manufacturing a thin film transistor array substrate of the present invention, the first patterned metal layer and the second patterned metal layer both include a plurality of bonding pads, for example. The bonding pads are respectively connected to the ends of the scanning wiring and the data wiring, and a plurality of through holes are formed on the bonding pads, and the through holes are arranged in an array. Moreover, the manufacturing method of the present invention can also form a patterned photoresist layer in the following steps. First, for example, a photoresist layer is formed on the protective layer. Next, for example, the first patterned metal layer and the second patterned metal layer are used as a mask to expose the photoresist layer on the back side, and the energy of the exposure is to partially expose the photoresist layer. Furthermore, for example, a photomask is provided as a mask for front-side exposure of the photoresist layer, and the energy of the exposure is to partially expose the photoresist layer. In the first thinned region t, the photoresist layer above the source / drain is exposed during front exposure, and the rest of the photoresist layer in the first thinned region is exposed during back exposure.

12406twf.ptd Page 10 200529439 V. Description of the invention (5) Finally, the photoresist layer is developed. Among them, the width of the metal layer between the through holes is smaller than the exposure resolution when back exposure is performed. Based on the above object, the present invention further proposes a method for manufacturing a thin film laminated structure. This method firstly sequentially forms a dielectric layer, an amorphous stone layer, a first patterned metal layer, and a protective layer on a front surface of a substrate. Next, a patterned photoresist layer is formed on the protective layer. A part of the edges of the patterned photoresist layer has a thinned area with a smaller thickness, and the thinned area spans a part of the edge of the first patterned metal layer. Up. Then, using the patterned photoresist layer as a mask, the protective layer, the amorphous silicon layer, and the dielectric layer not covered by the patterned photoresist layer are removed, and the protective layer under the thinned area is removed to form a thin film corresponding to the thin layer. One of the staircase-like structures. In the manufacturing method of the thin film laminated structure of the present invention, the method of forming the patterned photoresist layer is, for example, forming a photoresist layer on the protective layer first. Then, for example, the first patterned metal layer is used as a mask to expose the photoresist layer on the back, and the energy of the exposure is to partially expose the photoresist layer. Furthermore, for example, a photomask is provided as a mask for front-side exposure of the photoresist layer, and the energy of the exposure is to partially expose the photoresist layer. In the thinned area, the photoresist layer above the first patterned metal layer is exposed during front exposure, and the rest of the thinned area is exposed during back exposure. Finally, the photoresist layer is developed. In addition, in the method for manufacturing a thin film laminated structure of the present invention, a patterned photoresist layer may be formed in the following steps. First, for example, a photoresist layer is formed on the protective layer. Then, for example, a half-tone mask is provided, and the half-tone mask is used as a mask to perform front exposure and development on the photoresist layer. Of which, half-tone

12406twf.ptd Page 11 200529439 V. Description of the invention (6) The photomask has transparent, semi-transparent, and non-transparent areas, and the thinned area corresponds to the semi-transparent area of the half-tone mask. In addition, in the manufacturing method of the thin film stacked structure of the present invention, before forming the dielectric layer, for example, it further includes forming a second patterned metal layer, and removing the protective layer and the amorphous silicon not covered by the patterned photoresist layer After the layer and the dielectric layer, a part of the second patterned metal layer is exposed. In addition, after removing part of the protective layer, the amorphous silicon layer, and the dielectric layer, it further includes forming a conductor layer on the substrate, and the conductor layer covers the stepped structure. In summary, in the manufacturing method of the thin film transistor array substrate and the thin film laminated structure of the present invention, the protective layer is isotropically etched with a patterned photoresist layer having a thinned area as a mask, wherein the thinned The fascia spans a portion of the edge of the patterned metal layer (eg, source / drain). Therefore, the conductor layer covering this area can be prevented from being broken, thereby improving the process yield of the thin film transistor array substrate and the thin film laminated structure. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, several embodiments are hereinafter described in detail with the accompanying drawings, as follows. Embodiments 2A to 2D are schematic cross-sectional views illustrating a manufacturing process of a thin film transistor array substrate according to an embodiment of the present invention. First, referring to FIG. 2A, a first patterned metal layer 210, a dielectric layer 220, an amorphous silicon layer 230, a second patterned metal layer 240 and a first patterned metal layer 210 are sequentially formed on a substrate 2000. Protective layer 250. The substrate 200 is, for example, a glass substrate or a transparent plastic substrate. First patterned metal layer 210

12406twf.ptd Page 12 200529439 V. Description of the invention (7) Includes multiple scanning wirings 2 1 2 and multiple gates 214 connected to the scanning wirings 2 1 2 In addition, a first patterned metal layer 2 1 is formed The method of 0 is, for example, first forming a first metal layer on the substrate 210. The method of forming the first metal layer is, for example, physical vapor deposition or chemical vapor deposition, and the material of the first metal layer may be tantalum. (Ta), chromium (Cr), molybdenum (Mo), titanium (Ti) or aluminum (A1) and other conductor materials. Next, a first photoresist layer is formed on the first metal layer. After that, a photomask is provided and the first photoresist layer is exposed and developed using the photomask as a mask to form a first patterned photoresist layer. Finally, using the first patterned photoresist layer as a mask, a portion of the first metal layer is removed to form the first patterned metal layer 210. ^ Please continue to refer to FIG. 2A. The dielectric layer 220 and the amorphous silicon layer 230 are comprehensively formed on the substrate 200 and cover the first patterned metal layer 21o. The method for forming the dielectric layer 2 2 0 is, for example, Plasma-Enhanced Chemical Vapor Deposition (PECVD) or other deposition methods. The material of the dielectric layer 22 0 is silicon nitride, for example. (SixNY), silicon oxynitride (SiON), silicon oxide (SiOx), or other dielectric materials. The dielectric layer 220 formed on the gate electrode 214 serves as a gate insulating layer. The first patterned metal layer 2 40 includes a plurality of data wirings 2 4 2 and a plurality of source / drain electrodes 2 44 connected to the data wirings 2 42. Among them, the source / sink & 244 is located on the dielectric layer 2 2 0 above the gate 2 1 4. In addition, the first patterned metal layer 2 10 and the second patterned metal layer 24 include, for example, a plurality of bonding pads 2 1 6, and the bonding pads 2 1 6 are respectively connected to a scanning pad.

200529439 V. Description of the invention (8) Aim at the ends of wiring 2 1 2 and data wiring 2 42. The bonding pads 2 1 6 are used for subsequent electrical connection with other components. In addition, the method of forming the second patterned metal layer 240 is, for example, first forming a second metal layer on the amorphous silicon layer 230. The method of forming the second metal layer is, for example, physical vapor deposition or chemical vapor phase. And other methods, and the material of the second metal layer may be conductive materials such as tantalum, chromium, molybdenum, titanium, or aluminum. Next, a second photoresist layer is formed on the second metal layer. After that, a photomask is provided and the second photoresist layer is exposed and developed using the photomask as a mask to form a second patterned photoresist layer. Finally, using the second patterned photoresist layer as a mask, a part of the second metal layer is removed to form a second patterned metal layer 2 40. Furthermore, after forming the amorphous silicon layer 230 and before forming the second patterned metal layer 240, for example, an ohmic contact layer 2 3 2 may be formed between the amorphous silicon layer 230 and the second patterned metal layer 240. The material of the ohmic contact layer 232 is, for example, doped amorphous silicon (n + a_Si). Next, a protective layer 250 is formed on the substrate 200 to cover the amorphous silicon layer 230 and the second patterned metal layer 240. In this embodiment, the method for forming the protective layer 250 is, for example, forming a silicon nitride layer by a plasma enhanced chemical vapor deposition method or other deposition methods. FIG. 3 is a schematic diagram showing the distribution of the patterned photoresist layer near the source / drain electrodes in this embodiment. Please refer to FIG. 2B and FIG. 3 together to form a patterned photoresist layer 2 60 on the protective layer 2 50. The patterned photoresist layer 2 6 0 covers at least the source / drain 2 4 4 and above its surrounding area. At the same time, the patterned photoresist layer 2 6 0 covers, for example, the edges of the bonding pad 2 1 6 and the scanning wiring 2 1 2

12406twf.ptd Page 14 200529439

Source / drain. The above-mentioned distribution of the patterned photoresist layer 2 60 is used for illustration and is not intended to limit the present invention. The patterned photoresist layer 1 2 60 in this embodiment may also be distributed on the substrate 2 in other distribution patterns. 〇A part of the edge suitable for patterning the photoresist layer 2 6 0 has a plurality of first thinned regions 2 6 2 with a small thickness, and each of the first thinned regions 2 6 2 spans / pole 2 respectively. 4 4 part of the edge above. Next, please refer to FIG. 2B and FIG. 2C at the same time, and remove the patterned photoresist layer 26 0 from the protective layer 25 0 and the amorphous silicon layer 2 3 0 with the pattern servant # 阳 展 26 as the mask. And the dielectric layer 2 2 0, and remove the first thinned region 26 2 below the 5050 to expose the source / non-polar 2 and the amorphous silicon in the peripheral region below the first thinned region 2 62. The layer 23 is formed below the first thinned region M1 to form a plurality of step-like structures S1. In addition, due to the patterning, it is covered above the edge of the bonding pad 216, so at this time, the central part of the middle 60 of the bonding pad P2il2 will also be exposed to the outside. In addition, the method of removing each material layer by using the patterned photoresist layer 2 60 as a mask is, for example, isotropic etching, and the etching rate of the etching solution used for the amorphous stone layer 2 3 0 is usually greater than Static etch rate for the dielectric layer 2 2 0. Finally, please refer to FIG. 2D, a plurality of day element electrodes 27 are formed on the substrate 200, and each day element electrode 2 70 respectively covers a step-like structure s 1 and is electrically connected to a source electrode. / Drain pole 2 4 4. In addition, the day electrode 27 can cover the dielectric layer 22 () above part of the scanning wiring 212, and the scanning layer 2 1 2 below it and the dielectric layer 2 2 between the two. Together form a pixel storage capacitor structure. In addition, at the same time as the day electrode 27 is formed, an electrode material layer 2 7 2 is also formed on the bonding pad 2 1 6 and

12406twf.ptd Page 15 200529439 V. Description of the invention (10) 216 Electrical connection. The material of the pixel electrode 270 and the electrode material layer 272 is, for example, a transparent conductive material such as indium tin oxide (Indium Tin Oxide, I TO) or tin oxide (Strontium Tin Oxide, STO). . In the manufacturing method of the thin film transistor array substrate of the present invention, since the patterned photoresist layer 2 60 has a design of the first thinned region 2 62, a stepped structure can be formed at the edge of the source / inverter 244. S1. In this way, even if the amorphous silicon layer 2 3 0 at the edge of the source / inverter 244 is undercut due to the difference in etching rate, discontinuities will not be formed at the edge of the source / drain 2 4 4 Vertical wall (such as area A in Fig. 1B), so that the day element Mg can be prevented from breaking here. A schematic cross-sectional view of the plate is shown in FIG. 4 and is formed on the protective layer 25. The method of forming the Ϊf photoresist layer 260 is, for example, first 70 I and layer 2 65. Then, for example, using the first m metal layer 240 as a mask, the patterned metal layer and the second patterned gold amount are used to expose the photoresist layer 2 65 and a part of the film f 265, and the exposure can be fully exposed. 2 / q light of required energy. The exposure energy is adjusted to the best result, for example, and the exact value of the exposure energy should be based on the exposure. The value 'detailed adjustment method is not to add more 敎 here. The resistance layer 2 6 0 domain part is designed to be hollow. It should be noted that if you want to 60, then you are joining 塾? The method shown in FIG. 4 forms the patterned light 6. The part of the patterned light 6 should be its central area when it is formed. FIG. 6 shows a bonding pad of the present invention.

200529439 V. Description of the invention (11) Top view. Please refer to FIG. 4 and FIG. 6 at the same time. For example, a plurality of through holes 2 1 8 are formed on the bonding pad 2 1 6. The through holes 2 1 8 are arranged in an array. In addition, the width D of the metal layer between the through holes 2 18 is preferably smaller than the resolution when the photoresist layer 2 65 is exposed on the back surface. In this way, when the back exposure is performed, the photoresist layer 2 65 can be partially exposed above the central area of the bonding pad 2 1 6 and the central area of the bonding pad 216 can be exposed in subsequent processes. Of course, the hollowed out pattern shown in Figure 6 is only an example, and is not intended to limit the style of the hollowed out pattern. Furthermore, for example, a photomask M10 is provided as a mask for front exposure of the photoresist layer 265, and the energy of the exposure is to partially expose the photoresist layer 265, wherein the exact value of the exposure energy is as described in the exposure energy of the back exposure. In the first thinned region 2 6 2, the photoresist layer 2 6 5 above the source / drain 2 4 4 is exposed during front exposure, and the rest of the light in the first thinned region 2 6 2 is exposed. The resist layer 2 6 5 is exposed during back exposure. In addition, the amorphous silicon layer 2 3 0 on the side of the scanning wiring 2 12 and the amorphous silicon layer 2 3 0 on the side of the bonding pad 2 16 also correspond to the non-light-transmitting area of the mask M10, for example. Finally, the photoresist layer 2 65 is developed. Referring to FIG. 5, the method of forming the patterned photoresist layer 260 is not limited to the method shown in FIG. 4, and the method described below can also be used. First, for example, a photoresist layer 2 65 is formed on the protective layer 2 50. Next, a half-tone mask M20 is provided, and the half-tone mask M20 is used as a mask for front-side exposure and development of the photoresist layer 2 65. The first thinned area 2 6 2 corresponds to the semi-transparent area of the half-tone mask M20, and the area next to the first thinned area 2 6 2 far from the source / drain 2 4 4 corresponds to, for example, a half Mode light

12406twf.ptd Page 17 200529439 V. Description of the invention (12) " '一 "' Cover the light-transmitting area of M20. In addition, the semi-transparent area of the 'mask M20 also corresponds to, for example, near the side of the bonding pad 2 1 6 and the scanning wiring 2 1 2. In the manufacturing method of the thin film transistor array substrate of the present invention, the source / drain pattern is not limited to that shown in the above embodiment, and other design changes are also possible. ′, 0 λ Figure 7 shows the distribution of the patterned photoresist layer near the source / drain of another pattern. Referring to FIG. 7 ', the source / drain 344 includes, for example, a first terminal 344a and a second terminal 3 44b. The first terminal 34 is shaped as τ = and spans both sides of the gate electrode 314. The second terminal 344b is two strip-shaped terminals, which are respectively disposed on both sides of the first terminal 3 44a, and also across the gate Λ Side / this type of design / elimination of the disadvantages of the poor performance of the thin film transistor caused by the source / impedance 344 and the gate 3 而 而 = ί. The design using this source / drain 344 in the present invention has its characteristics Still = the photoresist layer 3 6 0 covers at least the source / drain 344 and its surrounding area on the domain "=, and part of the edge of the patterned photoresist layer 360 has a plurality of thick first thinned regions 362, Each of the first thinned regions 3 2 6 has a partial edge / drain 344 above a portion of the edge. The “8 /-” drawing across a source board is a thin film transistor array substrate according to another embodiment of the present invention. Please refer to FIG. 8. This thin film transistor array substrate is used to form a second pattern. The metallized layer 24 is a different electrode 246. Lei You, you have a lot of capacitors, and the scan wiring 212 and ^ pole 246 are located above the scan wiring 212 '. At the same time, when the shaped dielectric layers 2 and 20 collectively constitute a daylight storage battery and form a patterned photoresist layer (not shown), the patterned photoresist

12406twf.ptd Page 18 200529439 V. Description of the invention (13) Part of the edge of the layer has a plurality of second thinned regions with a smaller thickness, and each second thinned region spans a capacitor electrode 2 4 Above part of the edge of step 6, a stepped structure is formed on one side of the capacitor electrode 24. In this embodiment, the remaining steps of the manufacturing method are the same as in the previous embodiment. Therefore, the day element structure 2 70 is covered When the stepped structure s 2 is used, fracture can also be avoided. The technology disclosed in the present invention can also be applied to other locations on the thin film transistor array substrate, and its application examples are described below. Section 9 A ~ FIG. 9C is a schematic cross-sectional view of a manufacturing process of a thin film laminated structure according to an embodiment of the present invention.

First, referring to FIG. 9A, a dielectric layer 420, an amorphous silicon layer 430, a first patterned metal layer 440, and a protective layer 450 are sequentially formed on a front surface of a substrate 400. In addition, an ohmic contact layer 4 3 2 is formed between the amorphous silicon layer 4 3 0 and the first patterned metal layer 4 4 0, for example. Next, a patterned photoresist layer 460 is formed on the protective layer 450. A part of the edges of the patterned photoresist layer 460 has a thinned region 4 62 with a small thickness, and the thinned region 462 is formed across Above a portion of the edges of the first patterned metal layer 440. After that, using the patterned photoresist layer 4 60 as a mask, the protection layer 450, the amorphous silicon layer 430, and the dielectric layer 420 that are not covered by the patterned photoresist layer 460 are removed, and the thinned area 4 6 is removed. The protective layer under 2 is 4 50. In this way, the step-like structure S 3 of the thinned region 4 62 can be formed. Ten should be

In addition, for example, after removing the patterned photoresist layer 4 6 0 without covering the layer 4 50, the amorphous silicon layer 4 3 0, and the dielectric layer 4 2 0, the substrate 4

12406twf.ptd

200529439 V. Description of the invention (14) The conductor layer 470, the conductor layer 470 covers the stepped structure S3. Since the conductor layer 470 covers the stepped structure S 3, the conductor layer 470 will not be broken due to the undercut phenomenon. The material of the conductive layer 470 is, for example, a transparent conductive material such as indium tin oxide or samarium tin oxide. 10 and 11 are schematic cross-sectional views illustrating a method for forming a patterned photoresist layer having a thinned region in a method for manufacturing a thin film laminated structure according to the present invention. Referring to FIG. 10, a method of forming the patterned photoresist layer 460 is, for example, forming a photoresist layer 465 on the protective layer 450 first. Next, for example, the first patterned metal layer 4 40 is used as a mask to expose the photoresist layer 4 6 5, and the energy of the exposure is to partially expose the photoresist layer 4 6 5. Furthermore, for example, a photomask M30 is provided as a mask to perform front exposure on the photoresist layer 465, and the energy of the exposure is to expose part of the photoresist layer 465. At the same time, in the thinned region 462, the photoresist layer 465 above the first patterned metal layer 440 is exposed during front exposure, and the remaining photoresist layer 4 6 5 of the thinned region 462 is on the back. Exposure is performed during exposure. The method of determining the energy of each exposure is the same as the exposure method described in Figure 4 as an example. Finally, the photoresist layer 4 65 is developed. Referring to FIG. 11, the method of forming the patterned photoresist layer 460 is not limited to the method shown in FIG. 10, and the method described below may also be adopted. First, for example, a photoresist layer 45 is formed on the protective layer 450. Next, for example, a half-tone mask M4 0 is provided, and a half-tone mask is provided.

12406twf.ptd Page 20 200529439 V. Description of the invention (15) M40 is the front exposure and development of the photoresist layer 465 for the mask. The half-tone mask M40 has a light-transmitting region, a semi-light-transmitting region, and a non-light-transmitting region, and the thinned region 4 6 2 corresponds to the semi-light-transmissive region of the half-tone mask M4 0, and the thinned region 4 6 The area next to 2 away from the first patterned metal layer 440 is, for example, a light transmitting area corresponding to the half-tone mask M40. Fig. 12 is a schematic cross-sectional view of a thin film laminated structure according to another embodiment of the present invention. Please refer to FIG. 12. In the manufacturing method of the thin film stack structure, the method mainly includes forming a second patterned metal layer 410 before forming the dielectric layer 420. In addition, after removing the protective layer 450, the amorphous silicon layer 430, and the dielectric layer 420 that are not covered by the patterned photoresist layer 460, the second patterned metal layer 410 is exposed. In this embodiment, the remaining steps of the manufacturing method are the same as in the previous embodiment, so a stepped structure S4 is also formed. Therefore, after the conductive layer 470 is covered on the stepped structure S4 and the second patterned metal layer 410 and the first patterned metal layer 440 are electrically connected, the method still has the advantage of preventing the conductive layer 470 from being undercut. The advantage of breaking. FIG. 13 is a schematic diagram showing the distribution of a patterned photoresist layer in the manufacturing method of the thin film laminated structure of the present invention. Referring to FIG. 13, the manufacturing method of the thin film laminated structure of the present invention can be applied to, for example, a repair structure of a thin film transistor array substrate, and of course, it is not limited to be applied here. Among them, the patterned photoresist layer 4 60 has a thinned area 4 6 2 with a small thickness, and the thinned area 4 6 2 is a portion spanning the first patterned metal layer 4 4 0. Φ square on the edge. In summary, the manufacturing method of the thin film transistor array substrate and the thin film laminated structure of the present invention is to form a pattern with a thinned area before etching the protective layer.

12406twf.ptd Page 21 200529439 V. Description of the invention (16) Part of the edge of the photoresist layer is engraved with an isotropic surname, and the crystalline silicon layer extends out of the amorphous stone during the pattern remaining process. The conductor layer in the region breaks, and the process yield of the layer structure. Although the present invention has been limited to the present invention, within any and the range, the thinned zone attached to the patterned metal layer (such as the source edge) Above. Then the patterned photoresist layer is used as the mask. The protective layer under the thinned area can be completely removed, and the edges of the non-chemicalized metal layer can be removed. Therefore, even if the undercut occurs in the isotropic layer, it will not cause Covering this to further improve the thin-film transistor array substrate and the thin-film stack are disclosed as above in a preferred embodiment, but it is not intended to be used by those skilled in the art, and can be slightly modified and retouched without departing from the spirit of the present invention. Please define the scope of the patent.

12406twf.ptd Page 22 200529439 Brief Description of Drawings Figures 1 A to 1 C show a partial cross-section of the conventional manufacturing process of a thin film transistor array substrate. Figures 2A to 2D are schematic cross-sectional views illustrating a manufacturing process of a thin film transistor array substrate according to an embodiment of the present invention. FIG. 3 is a schematic diagram showing the distribution of the patterned photoresist layer near the source / drain in this embodiment. 4 and 5 are schematic cross-sectional views showing a method for forming a patterned photoresist layer having a thinned region in a method for manufacturing a thin film transistor array substrate according to the present invention. FIG. 6 is a top view of a bonding pad according to the present invention. FIG. 7 is a schematic diagram showing the distribution of the patterned photoresist layer near the source / drain of another pattern. FIG. 8 is a schematic cross-sectional view of a thin film transistor array substrate according to another embodiment of the present invention. 9A to 9C are schematic cross-sectional views showing a manufacturing process of a thin film laminated structure according to an embodiment of the present invention. 10 and 11 are schematic cross-sectional views illustrating a method for forming a patterned photoresist layer having a thinned region in a method for manufacturing a thin film laminated structure according to the present invention. Fig. 12 is a schematic cross-sectional view of a thin film laminated structure according to another embodiment of the present invention. FIG. 13 is a schematic diagram showing the distribution of a patterned photoresist layer in the manufacturing method of the thin film laminated structure of the present invention. [Schematic description]

12406twf.ptd Page 23 200529439 Schematic description 100 substrate 1 10 gate 120 dielectric layer 130 amorphous silicon layer 140 source / drain 150 protective layer 160 patterned photoresist layer 170 day element 2 0 0, 4 0 0: substrates 210, 440: first patterned metal layer 2 1 2: scanning wiring 2 1 4, 3 1 4 · gate 216: bonding pad 2 1 8: through hole 220, 420: dielectric layer 2 3 0, 4 3 0: Amorphous silicon layers 232, 432 ·· ohmic contact layers 240, 240a, 410: second patterned metal layer 2 4 2: data wiring 2 4 4, 3 4 4: source / non-polar 2 50, 4 5 0: protective layers 260, 360, 460: patterned photoresist layers 262, 362, 462: first thinned regions 265, 465: photoresist layers

12406twf.ptd Page 24 200529439 Schematic description 270 272 470 Pixel electrode electrode material layer Conductor layer A: Regional stepped structure SI, S2, S3, S4 Μ 1 0, Μ 3 0 Half-tone mask D: width

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Claims (1)

200529439 VI. Application Patent Scope 1. A method for manufacturing a thin film transistor array substrate, comprising: sequentially forming a first patterned metal layer, a dielectric layer, an amorphous silicon layer, and a second pattern on a substrate; A metallized layer and a protective layer, wherein the first patterned metal layer includes a plurality of scan wirings and a plurality of gates connected to the scan wirings, and the second patterned metal layer includes a plurality of data wirings and A plurality of source / drain electrodes connected to the data wirings; a patterned photoresist layer is formed on the protective layer, and the patterned photoresist layer covers at least the source / drain electrodes and the surrounding area; A portion of the edge of the patterned photoresist layer has a plurality of first thinned regions with a smaller thickness, and each of the first thinned regions spans over a portion of one of the source / drain electrodes; Using the patterned photoresist layer as a mask, remove the protective layer, the amorphous silicon layer, and the dielectric layer not covered by the patterned photoresist layer, and remove the protection under the first thinned regions. Layer to form the first thinning A plurality of stepped structures; and a plurality of day electrodes formed on the substrate, each of the day electrodes each covering at least one of the step structures and electrically connected to the sources / sinks, respectively. One of them. 2. The method for manufacturing a thin film transistor array substrate according to item 1 of the scope of patent application, wherein the method of forming the patterned photoresist layer comprises: forming a photoresist layer on the protective layer; and providing a half-tone photomask And using the half-tone mask as a mask to perform front exposure and development of the photoresist layer, wherein the half-tone mask has a transparent region, a semi-transmissive region, and a non-transmissive region, and the first thinning Fauna Correspondence 12406twf.ptd Page 26 200529439 6. The scope of the patent application is in the half mode 3. Rushen's manufacturing methods are all covered with a few scanning wirings. 4. Rushen's manufacturing method is covered by the first act A partial exposure of the light layer is provided to provide an exposure, and the thinned area is performed on the backside to produce the manufacturing electrode on the backside of 5. and the manufacturing electrode is exposed on the backside. The exposure is exposed to the light as described in the method. Please specialize, please include more and the through hole, please specialize, its protective layer is a photoresistive layer, the photomask should be more, and the time to enter the resistive layer, please specialize, please expose its special, part of the semi-transparent area . Several bonding pads of the first patterned metal layer and the second patterned gold in the thin film transistor array substrate described in Item 1 above, the bonding pads are respectively connected to the ends of the data wirings, and the The bonding pads are shaped, and the through holes are arranged in an array. The method for forming the patterned photoresist layer in the thin film transistor array substrate described in Item 3 includes: forming a photoresist layer on the substrate; exposing the patterned metal layer and the second patterned metal layer as a cover for back exposure, The energy of the exposure is to make the photoresist, and the photoresist layer is exposed with the mask as a mask. The energy of the photoresist layer is partially exposed, and the photoresist is above the first source / drain electrodes. The layer is exposed on the front side of the photoresist layer that exposes the rest of the first thinned regions; and development is performed. The width of the metal layer between the through-holes in the thin film transistor array substrate described in Item 4 is smaller than the optical resolution. The second patterned metal layer in the thin film transistor array substrate described in Item 1 further includes a plurality of capacitors above the scanning wirings, and the patterned photoresist layer 12406twf.ptd Page 27 200529439 VI. Part of the edge of the patent application has a plurality of second thinned areas with a small thickness, each of which is located across one of the capacitor electrodes. Above part of the edge. 7. The method for manufacturing a thin film transistor array substrate according to item 1 of the scope of patent application, wherein the method of forming the first patterned metal layer comprises: forming a first metal layer on the substrate; and forming the first metal layer on the first metal. Forming a first patterned photoresist layer on the layer; and using the first patterned photoresist layer as a mask, removing a part of the first metal layer to form the first patterned metal layer. 8. The method for manufacturing a thin film transistor array substrate according to item 1 of the scope of patent application, wherein the method of forming the second patterned metal layer includes: forming a second metal layer on the amorphous stone layer; Forming a second patterned photoresist layer on the second metal layer; and using the second patterned photoresist layer as a mask, removing a part of the second metal layer to form the second patterned metal layer. 9. The method for manufacturing a thin film transistor array substrate according to item 1 of the scope of patent application, wherein after the amorphous silicon layer is formed and before the second patterned metal layer is formed, it is further included in the amorphous silicon layer and the first silicon layer. An ohmic contact layer is formed between the two patterned metal layers. 10. The method for manufacturing a thin-film transistor array substrate according to claim 1 in the patent application, wherein the method for removing the material layers includes isotropic etching. Π. The method for manufacturing a thin film transistor array substrate according to item 9 of the scope of the patent application, wherein the method for removing the material layers further includes using an etch 12406twf.ptd Page 28 200529439 froo Introduction to the layer of silicon crystals etched at a high rate br The pair of liquids to etch the m and benefit from the special, tu. The structure of the laminated laminated film is a thin layer of the protective layer and the top layer of the gold plated base case is a picture of a layer of dielectric layer silicon crystal kr layer transversal photoresistance area diagram The thin layer should be thin, and the photoresistance of the thin film in the resistance area is smaller than the thickness. The upper layer is 4 ^. In addition to the edge removal, the screen of the sub-screen is layer-by-layer metallization resistance plan. Figure 1 should be used in the thin film and the layer should be in a crystalline form with the corresponding layer instead of the protective layer. Make sure that it should be covered under the cover of the area. The removal and layering of the structure of the layered structure of the ZPP special order one is described in the item 2 11 of the Fan Li special request in the case of 3 11 The 111, belongs to the second-tier gold first protection case The second part of the figure covers the light-storage electrochemical system of the exposed layer that covers the front part, and the figure is formed into the layer after the static electricity is removed in the transfer and the layer and layer are of French silicon. Fang Jinjing made the illegal party to make M ·. Structure layer or item 2 1 × No. Fan Li specially requested to apply the above-mentioned laminated film including the method of layer photoresistance plan of the method, the light area in the molding, the light is transparent to the screen, and the cover is a cover. Light and light tone and half tone; half of the layer should be balanced with its light. First, the shadow mask is exposed to light and the above type light layer is exposed to protect half of the surface. In order to cope with the system and reduce the light of the region. Translucent non-region and light-domain translucent half-light translucent half-light I2406twf.ptd Page 29 200529439 VI. Application for patent scope 15. The method for manufacturing the thin film laminated structure described in the patent application scope item 12 or item 13, wherein the method of forming the patterned photoresist layer includes: A photoresist layer is formed on the protective layer; the photoresist layer is exposed on the back using the first patterned metal layer as a mask, and the energy of the exposure is to partially expose the photoresist layer; a photomask is provided, and The photomask is a mask for front exposure of the photoresist layer, and the energy of the exposure is to partially expose the photoresist layer. In the thinned area, the photoresist layer is above the first patterned metal layer. The exposure is performed during front exposure, and the photoresist layer in the rest of the thinned area is exposed during back exposure; and the photoresist layer is developed. 16. The method for manufacturing a thin-film laminated structure according to item 12 of the scope of patent application, wherein the method for removing the material layers includes isotropic etching. 1 7. The method for manufacturing a thin-film laminated structure according to item 16 of the scope of patent application, wherein the method for removing the material layers further includes using an etching solution, and the remaining etching solution is applied to the amorphous stone layer. The #etch rate is greater than the etch rate of the dielectric layer. 1 8. The method for manufacturing a thin film laminated structure according to item 12 of the scope of patent application, wherein after removing part of the protective layer, the amorphous silicon layer, and the dielectric layer, it further includes forming on the substrate A conductor layer covering the stepped structure. 19. The method for manufacturing a thin film laminated structure according to item 12 of the scope of patent application, wherein after the amorphous silicon layer is formed and before the first patterned metal layer is formed, it is further included in the amorphous silicon layer and the First patterned metal 12406twf.ptd Page 30 200529439 6. Scope of patent application An ohmic contact layer is formed between the layers. llliiill p. 31 12406twf.ptd