TW200527858A - High-speed processing mechanism of packet-switching - Google Patents

Abstract

The IPv6 high-speed processing mechanism of packet-switching is a system unit having the function of IPv6 high-speed packet-switching. The packet is divided into the control packet and the data packet by attribute. The control packet is processed by a CPU module, the data packet is processed by the table-loop-up unit of the module itself to obtain the corresponding output port, and the data packet is directly transmitted out without the processing of CPU, so as to accelerate the transmission speed, and achieve the purpose of wire-speed switching for IPv6 packet. Various kinds of packets are processed by separating the processing of packet header and packet payload, so as to reduce the processing time of packet, and improve the problem that the wire-speed switching of IPv6 cannot be accomplished in the prior art, because most of the network equipment only supports the switching of wire-speed for IPv4 currently.

Description

200527858 发明 Description of the invention: [Technical field to which the invention belongs] The present invention relates to a high-speed packet exchange processing mechanism, and particularly to a method for detecting the sixth version of a network protocol packet using the j-processor technology and determining the packet attribute as a control packet Or data packets, and the packet exchange processing mechanism that processes them separately. [Prior Art #?]

Due to the rapid development of the World Wide Web and the Internet in recent years, the number of people using the Internet has increased rapidly, and the fourth version of IPv4 (IPv4) addresses available on the Internet is expected to soon It is not enough, so a new generation of IP (Internet Protocol) version 6 (referred to as IPv6) is proposed to solve this problem. At the same time, based on past experience of using the Internet, it is known that there are many deficiencies in the original network protocols, such as its support for real-time services, congestion control, and security measures. Therefore, when designing IPv6, in addition to expanding the address space to address the most urgent address shortages, we also re-examined all aspects of the original IP protocol functions in an effort to improve. However, most of the existing network equipment only supports wire-speed exchange of IPv4 packets, and cannot achieve wire-speed exchange of IPv6 packets. Therefore, it is urgent to study how to make Internet users quickly connect to the IPv6 network to improve the quality of the IPv6 network. It can be seen that there are still many shortcomings in the above-mentioned conventional articles, and they are not a good designer. They need to be improved. · &Quot; In view of the various shortcomings derived from the above-mentioned custom, the creators of this case are eager to improve and innovate. After years of painstaking research, they have successfully developed 12 200527858 this high-speed IPv6 packet processing module. [Summary of the Invention] One of the objectives of the present invention is to provide an IPv6 packet high-speed exchange processing mechanism, which is to improve and expand the functions of traditional IPv4 network equipment to the line speed conversion capability of IPv6 packets.

Another object of the present invention is to provide a programmable packet exchange processing mechanism that is particularly suitable for the diverse service requirements of IPv6 networks. The IPv6 packet high-speed exchange processing mechanism that can achieve the above-mentioned purpose of the invention uses the detection and judgment of packet types and attributes to achieve the purpose of wire-speed exchange, and increases the programmability and adaptability of software and hardware. The method is to use a network processor to detect packets passing through each of its ports. Each gateway monitors and retrieves the header related information of the packet according to the pre-programmed content to determine the type and property of the packet, and simultaneously performs the line-speed exchange of the data packet and the subsequent processing of the control packet.

[Embodiment] The present invention is to improve and expand the functions of traditional network protocol version 4 (IPv4) network equipment to the wire-speed exchange capability of IPv6 packets to cope with the network protocol version 6 (IPv6) network huge traffic. Growth of quantity. It also provides a programmable packet exchange processing method, which is especially suitable for the diverse service requirements of IPv6 networks.

Please refer to Figure 1, which is a block diagram of the IPv6 packet high-speed exchange processing mechanism. The architecture of the IPv6 packet high-speed exchange processing mechanism is divided into peripheral control interface unitsΗ, peripheral data interface units 2, central processing unit and memory unit 3, PCI 13 200527858 bus interface unit 4, table lookup unit 7, and system bus 8 and other single _ Α 6, buffer management row 8 and so on. Its main functions can be summarized as follows. 1. 'The type of rhyme received packets is ipν4〇Ρν6 packets, which are processed separately. -、 Determine whether the attribute of the received packet is a control packet or a data packet. If it is a control packet. • Transfer the content of the packet to the central processing module for processing. If it is a data packet, directly forward the packet to the appropriate address based on its destination address. Output port. Third, transmit IPv4 and iPv6 packets. 4. Separate the header and payload of the packet to speed up the packet processing time. 5. IPV4 / IPv6 routing table creation, deletion, modification, and lookup. 6. IPv4 / IPv6 packet level classification and queue management. 7. Each port can switch software configuration according to different types of hardware interface modules used. 8. 5G bps non-blocking switching architecture. The detailed functions of each unit in the IPv6 packet high-speed exchange processing module are described below: (1) Peripheral control interface unit 1 In order to simplify the IPv6 packet high-speed exchange processing module and various interface modules (including: 10/100 Ethernet) Network interface module, 1G Ethernet interface module,

PoS (packer over SDH / SONET) interface module, communication with asynchronous transfer mode (ATM) interface module, etc.) and reduce the need for connection lines. We cut the relationship between the two 14 and 200527858 into data and Control and other two interfaces. At the same time, the 16 peripheral data interface units are also divided into two groups, each of which is composed of 8 peripheral data interface units, and the parent,, and ′ and the other are correspondingly controlled by a peripheral control interface unit. Peripheral control interface unit k 4. For various interface modules, including module identification code, module reset, module women's clothing, module interruption, module clock selection, and module status start and monitoring, etc. 'The activation of various control signals is determined by the central processing unit and the memory unit. (0) Peripheral data interface unit 2 Refer to Figure 2 #. The peripheral data interface unit is a peripheral data interface unit sequencer 2. The packet header processor 22, the receiving packetizer 23, the packet payload processing state 24, and the transmitting packetizer 25 are described as follows: • Peripheral data interface unit sequencer 21: controls the operation of the entire peripheral data interface unit ' These include: the start and calculation of registers, counters, decoders, buffers, and first-in-first-out, etc., packet material and reception, and communication with other single-fans, which can be programmed in a finite state. The sequence of machine control execution. = Packet header processor 22: The receiving end part, combines the packet header of the packet with the surrounding and shell material: the sample control information planned in advance by the sequencer 21 in the early 70s, and transmits it to the management unit via the system bus. At the transmitting end, the data sent by the official management unit 6 is stored in it, and it is disassembled into the control information for the peripheral interface single sequencer 2 i__ and the header message of the lpy Qing v6 packet, according to the transmission rate Demand, in order to send the heart tearing% packet header data out of 15 200527858. • Receiving packetizer 23: Receive external signals through serial pins, and form a complete IPv4 / IPv6 packet through a serial-to-parallel conversion circuit. After determining that the packet cyclic redundancy (CRC) check code is correct, The packet is then cut into two parts: the IPv4 / IPv6 packet header and the IPv4 / IPv6 packet payload. The IPv4 / IPv6 packet header part is sent to the packet header processor 22 for processing; the IPv4 / IPv6 packet payload part is sent to the packet payload processor 24 for processing. 'Packet payload processor 24: The receiving part expands the received IPv4 / IPv6 packet payload into a 32-bit wide data length, and groups it in groups of 16 via direct access memory (DMA) The mode is transmitted to the buffer management unit 7 through the system bus 8. At the transmitting end, the data transmitted by the buffer management unit 7 through the direct access memory (DMA) mode (same as the receiving end, are all 32-bit wide data length, and are grouped by 16 Send) is stored in it, and the data is sent out in order according to the transmission rate requirements. • Packet sender 25: Receives IPv4 / IPv6 packet header information through the packet header processor 22, and also receives IPv4 / IPv6 packet payload information from the packet payload processor 24. Combine the two into a complete IPv4 / IPv6 packet, and add the generated cyclic redundancy (CRC) check code to the appropriate field of the transmitted packet. The parallel-to-serial conversion circuit uses the serial pins to convert the IPv4 / IPv6 The packet is transmitted. (3) CPU and memory unit 3 200527858 Lane 2 31 Address decoder 32, bus buffer 33, system bus controller 34, read-only memory 35, and random access memory% The structure is summarized as follows: The central processor 3 1 'controls the operation of the entire IPv6 packet exchange processing module, including the start of each single S and the execution of control commands, the start and monitoring of the system register, and the The unit „requires the mutual pure material system flow of the material. • Address decoder 32 Xiao bus buffer 33: The address decoder is the address processor of the central processor; the bus buffer stomach 33 is used as the central processor η Buffer between read-only memory 35 and system bus controller 34. • System bus controller 34: responsible for controlling data exchange with system bus. • read-only memory 35 and random access memory%: The capacity of read-only memory% is 2M bytes, which is a storage control program, and the capacity of random access memory% is 32K bytes, which is used to store temporary planning data. Because most of its dynamic data can be streamed through PCI Order interface one way The central processor and memory unit 3 are acquired, so there is no need for large-capacity data space. (4) PCI bus interface unit⑽The bus interface unit provides the function of the Pα bus interface, which enables: to tear V6 packet exchange processing modules and The central processing modules can be quickly edited, and operate in a 33MHz 32-bit transmission mode. (5) Table lookup unit The table lookup unit provides the addition, update, and modification of IPv4 / IPv6 routing tables. Functions such as table maintenance are performed by the middle processor and memory unit 3. Responsibility · The query of the table is issued by the early data sequencer 21 of the peripheral data interface of the peripheral data interface unit 2 to obtain relevant information The size of the table is 5 bytes, and it uses the content addressable mode to operate. Its data is stored in the longest pre-matching manner, the destination address, the corresponding library to the corresponding output port, and the corresponding output destination address. (Six) queue management unit 6. Please refer to Figure 4, the queue management unit 6 is composed of the queue management unit sequence server 61, queue memory manager 62, Ding α ZZ hidden body 63, The column judgment selector 6t and the queue sender 65 are described as follows: ° The queue management unit sequencer 61: controls the operation of the entire queue management unit 6, including: a register, a counter , Decoders, buffers, and first-in-first-out (™ 0), etc., and calculation and communication with other units, and the sequence of execution is controlled by a programmable finite state machine. Queue memory manager 62: It accepts the instructions from the queue management unit sequencer 6 丨 and ## to determine the selection of H 64 to manage the address allocation, ^ recycling, and check the use of the memory of the queue. • Queue memory 6.3: Provide 512K bits Set of random memory for storage queue. Queue queuing selector 64: determines the priority of queue processing, selects the next queue to be processed, and notifies queue management unit sequencer 6i and queue memory manager 62. 18 200527858 • The receiving and sending state 65: receiving and transmitting the queued data transferred from the central processing unit and the memory unit 3 and the peripheral data interface unit 2 via the system bus 8. (VII) Buffer management unit 7 Please refer to FIG. 5. The buffer management unit 7 is composed of a buffer management unit-sequencer 71, buffer memory manager 72, buffer memory 73, and packet classifier 74. , And the broadcast packet monitor 75, etc., which are described as follows: • Buffer management unit sequencer 71: Controls the operation of the entire peripheral data interface unit 2, including: register, counter, decoder, buffer, and First-in-first-out (FIFO), etc. are initiated and communicated with other units, and the order of execution is controlled by a personalizable finite state machine. • • Dance memory manager 72: accepts instructions from the buffer management unit sequencer B and the packet classifier 74 to manage the address allocation, space reclamation, and check usage of the buffer memory 73. • Buffer Memory 73: Provides 64M bytes of random memory for storing buffers. ° Packet classifier 74: Receives and transmits packet payload data forwarded from the central processing unit and memory unit 3 and the peripheral data interface unit 2 via the system and system bus 8, and informs the buffer management unit sequencer 71 and How the buffer memory manager 72 sorts and stores packets according to their sizes. Broadcast packet monitor 75: Accept the order of the buffer management unit sequencer 71, "Delete whether the sent packet is a broadcast packet. If so, it will continue to monitor the transmission of the packet 19 200527858 until all the packets should be transmitted The buffer will only be emptied when all the ports have been transmitted. (8) System bus 8 System bus 8 provides the central processing unit and memory unit 3 and peripheral data interface unit 2, peripheral control interface unit 1, check Table unit 5, queue management unit 6, buffer management unit 7 and other units of system control and data exchange channels; it also provides an interface to allow the central processing unit and memory unit 3 to directly access the register of other units Please refer to Table 1 for the data structure of the table lookup table of the present invention, as explained later: The present invention must not only be able to process IPv4 and IPv6 packets at the same time, but also not bring too much to the system. Extra burden. In the design of the Forwarding Table of the look-up unit 5, because the address length (128 bits) of the IPv6 packet is much longer than the bit length of the IPv4 packet Length (32 bits), so we designed a two-stage table lookup table. The first stage table is shared by IPv4 and IPv6 uni-casting, and the second stage table is multi-pointed by IPv4. Multicasting is shared with IPv6 unicast. The two-stage lookup table data structure can be expressed by {key value, data} pairing. Among them, the key value length is 96 bits to facilitate the lookup unit. Operation. And these 96 bits can be subdivided into key0 (16 bits), keyl (32 bits) and key2 (32 bits). Because the key value part is .IPv4 / CIDR (class Internet routing) Or IPv6 / prefix (prefix) address value. After excluding IPv6 multicast and embedded 20 200527858 IPv4 (Embedded IPv4 address) address, the above-mentioned method of filling in the key value can perfectly separate IPv4 and IPv6 data. In this way, the purpose of sharing the form can be achieved. Table 1. Data in the table lookup table Name Key Value (Key) Data (Data) rtrTsp If it is IPv4, the key value is filled in key2; If it is IPv6, the input value is filled in key 1 and key2 typedef struct {int8umaskBits; int8u queueld; int8uty pe; int8u iflndex; int32uappDatal; int32u appData2; int8u fabricld; int8upadl; int 16u nextLookupTag;} IpRouteData; ipmcastTsp If it is EPv4 (multicast), the record value is filled in _2; if it is IPv6, the key value is filled in keyO, key 1 and key2 typedef struct {QsQueueVector ftvdVector; int32u vectorCount; inti 6u fabricVector; inti 6u egressVNID; inti 6u nextLookupTag; intl6upadl;} IPMcastFwdCacheEntiyData; Please refer to Figure 6 'When querying the transmission table, whether it is single-point transmission or multiple Point-to-point IPv4 packets can directly find the required routing data; while IPv6 packets will use the first 64 bits of the prefix as the key value for the first-stage query. If the obtained data type block is ipRcmteTypeRemote , You must combine the nextL〇〇kupTag field with the rest of the prefix (prefix) as the key value to perform the second-stage query to obtain 21 200527858 routing data. Regardless of the query method of the transmission form, LPM (Longest-Prefix Match) algorithm is used. In addition to querying, each table needs to provide basic operations such as Get / Get-next, Se1> Create, and Delete (the message action can be regarded as a Get operation). As shown in Figure 7, the processing flow can be divided into a data plane (Control Plane) and a control plane (Control Plane) to explain: 1. Data plane: the received packet data will first separate the packet header and packet payload, the program According to the packet headers of different properties (such as IPv4 unicast, multicast, IPv6 unicast, etc.), the data query of the table lookup unit 5 is started according to the method described in the previous section. If the transmission data can be obtained, the network layer (Network Layer) header data is modified according to the transmission data, and the payload is sent to the queue unit 6, and the packet is sent out to achieve the purpose of packet exchange; if the transmission data cannot be obtained, The complete data of the packet (including the header and payload) β is sent to the control plane for subsequent processing. 2. Control plane: After receiving the packet from the data plane, the forwarder 51 on the control plane will find the appropriate packet route according to the routing table of the current system, and join the appropriate network. After layering the data, the packet is sent to the queue unit 6 of the data plane. At the same time, if the transmission program finds that the packet is not sent through the default route location, it will use the Set-Create operation to add the transmitted data to the lookup unit Transfer form 52. On the other hand, when the control plane is affected by routing protocols (Routing 22 200527858

Pr0c01) or manual operation 53 when the routing table 54 is changed 'will also delete the old transmission data related to the table lookup unit & to correspond to the routing table of the system. Compared with other conventional technologies, the high-speed IPv6 packet processing module provided by this creation has the following advantages: 1. It can increase the speed of IPv6 packet exchange and provide better network service quality. 2. Can provide-Programmable packet exchange processing method, which is especially suitable for 11 > ¥ 6 network's diverse service needs. 3. Each port can switch the software configuration in real time according to the different types of hardware interface modules used to improve the adaptability of interface modules and reduce the complexity and timeliness of developing various interface modules. The above detailed description is a specific description of one of the feasible embodiments of this creation, but this embodiment is not intended to limit the scope of patents for this creation.

Equivalent implementations or changes made by the spirit of creative art should be included in the scope of patents in this case. A • 9 In summary, this case is not only innovative in terms of technical ideas, but also has many of the above-mentioned effects beyond conventional methods. It has fully complied with the statutory creation patent requirements of novelty and progress, and applied in accordance with the law. The Bureau approves this application for a patent for creation, and encourages creation to the greatest extent. [Brief description of the drawings] Please refer to the following drawings of the present invention for further understanding of the 200527858 technical content of the present invention and its purpose and effectiveness. The drawings related to this embodiment are as follows: Figure-is a high-speed IPv6 packet processing mechanism Block diagram, Figure 2 is a block diagram of the peripheral data interface unit; Figure 3 is a block diagram of the CPU and a memory unit; Figure 4 is a block diagram of the queue management unit; Figure 5 is the buffer management Block diagram of the unit; Figure 6 is a flowchart of the query method of the routing table;

FIG. 7 is a flowchart of the packet transmission process. [Representative symbols of main parts] 1 Peripheral control interface unit 2 Peripheral data interface unit 21 Peripheral data interface unit sequencer 22 Packet header processor 23 Receiver packetizer 24 Packet payload processor ·, 25 Transmission packetizer " 3 Central processing And memory unit 31 CPU 32 address decoder 33 bus buffer 34 system bus controller 24 200527858 35 read-only memory 36 random access memory 4 PCI bus interface unit 5 look-up table unit 6 伫Queue Management Unit 61 Queue Management Unit Sequencer 62 Queue Memory Manager

63 Queue Memory 64 Queue Judgment Selector 65 Queue Receiver 7 Buffer Management Unit 71 Buffer Management Unit Sequencer 72 Buffer Memory Manager

73 Buffer memory 74 Packet classifier 75 Broadcast packet monitor 8 System bus 25

Claims (1)

200527858 Scope of patent application: 1 '.. A high-speed packet exchange processing mechanism that uses _ and judging packet attributes to achieve wire-speed exchange, including:, a central processing unit and a memory unit; at least-week « A data interface unit, which includes a peripheral_interface unit sequencer, a packet header processor, a receiving packet device, a packet payload processor, and a transmitting packet device; Based on the longest leading element, each peripheral control interface unit can control at least one peripheral control interface unit or a plurality of peripheral data interface units; a table lookup unit whose content adopts the addressing mode to store data;-system bus , Which can be used by the central processing unit and the memory unit to directly access the temporary register of other units as a data exchange channel between different units. // After the peripheral data interface unit receives the packet and classifies it, it sends it to the inquiry form. 7L queries routing related information and forwards it to the queue management unit through the system bus and sends the packet to the destination. 2 · If the scope of patent application is the first! A high-speed packet exchange processing mechanism described in the above item. The CPU and the memory unit are composed of a CPU, a bit decoder, a bus buffer, a system bus controller, and a read-only memory. And random access memory. Such as applying for a patent_ # 丨 rhyme description—a kind of high-speed packet exchange processing mechanism, 26 200527858, where the peripheral control interface code. The control signal provided by the unit can be identified by the module. As described in item 1 of the scope of patent application-a kind of packet high-speed money processing mechanism, the signal provided by the peripheral interface interface can be reset by the city group. 5. As described in item 丨 of the patent application scope-a high-speed packet exchange processing mechanism, in which the control signals provided by the peripheral control interface unit can be installed by the module. 6. If you apply for profit 1, please refer to the first description-a kind of high-speed packet exchange processing mechanism, in which the control signal provided by the peripheral control interface unit can be interrupted by the module. φ 7 · If you apply for a patent _th rhyme of _ a kind of high-speed packet exchange processing mechanism, the control signal provided by the peripheral control interface unit can be selected for the module clock. • If you apply for a patent_ 1st rhyme—a high-speed packet exchange processing mechanism, where the control signals provided by the peripheral control interface unit can be the start and monitoring of the module status. 9. As described in the first patent application scope-a kind of high-speed packet exchange processing mechanism, the data stored in the table lookup unit can be the destination address. Affirm the patent fen # 1 rhyme of _ a kind of packet high-speed exchange processing mechanism, in which the data stored in the table lookup unit can be the corresponding output Chunkou. ^ As described in item 4 of the patent scope of claim 4-a packet height exchange processing mechanism, wherein the data stored in the table lookup unit can be the corresponding output destination address. Application of the high-speed packet processing mechanism described in item 1 of patent peu, 27 200527858 ° Increase 1 punch processing unit, which consists of-buffer management unit sequencer,-buffer memory manager,-buffer Memory, a packet classifier, and a broadcast packet monitor. 4 As described in item 1 of the scope of the patent application—a high-speed packet exchange processing mechanism, in which the cooking menu _ is managed by the order unit H, the queue memory manager, the queue memory, the queue judgment selector, and It consists of a queue receiver. 14. As described in the first rhyme of the scope of patent application-a high-speed packet exchange processing mechanism, the peripheral data interface unit can transmit and receive data signals with the 1Q / Ethernet interface module. 15. As described in item 1 of the scope of patent application-a kind of high-speed packet exchange processing mechanism ', wherein the peripheral data interface unit can transmit and receive data signals with the 1G Ethernet interface module. 16. If you apply for the special rhyme ㈣1 rhyme—a kind of high-speed packet exchange processing mechanism, in which the peripheral data interface unit can transmit and receive data signals with the asynchronous transmission mode interface module. As described in the "Monthly Patent" item 1-a high-speed packet exchange processing mechanism, in which the peripheral data interface unit can transmit and receive data signals with the pos interface module. The high-speed packet exchange processing mechanism ♦ enables the central processing unit and the memory unit as described in item 1 of the patent application scope. It can use a PCI bus interface unit to quickly transfer data between the unit and other units. 28 18