TW200527179A - Clock generator - Google Patents

Abstract

A clock generator has the first PLL (phase lock loop), the second PLL and the third PLL. The first PLL receives an input oscillation signal and a input clock signal, which need to spread spectrum, to generate the first clock signal and the second clock signal. The first PLL chooses the first or the second clock signal to generate the third clock signal. Otherwise, the second PLL receives the input oscillation signal to generate the fourth, the fifth and the sixth clock signals. Then, the third PLL receives the input oscillation signal to generate the seventh and the eighth clock signals. The present invention only need one input oscillation signal, then the present invention could generate the plurality of output clock signals.

Description

200527179 V. Description of the invention (1) Technical field to which the invention belongs The present invention relates to a clock generator ', and in particular to a clock generator capable of generating different clock signals. Prior art In a notebook computer, many different devices, such as a VGA card or a local area network (LAN), are included, and each device has its required operating clock. In order to make the working clock stable, in a notebook computer, a quartz crystal is usually used to first oscillate a predetermined reference frequency signal, and then input this predetermined reference frequency signal to the clock generator. Then, a phase lock loop (Phase lock loop, PLL for short) in the clock generator outputs a stable working clock signal according to the input predetermined reference frequency. Figure 1 Block diagram of the A-series phase-locked loop. Please refer to Figure 1A. The phase-locked loop is mainly composed of a phase comparator 1 0, a frequency divider 1 0 3, a reference signal generator 105, a voltage control oscillator (Voltage Control Oscillator (VCO) 107), and a low-pass filter. It is composed of a low-pass filter (LPF) 109, a charge pump 111, a compensation circuit 113, and a control circuit 115. The voltage controlled oscillator 丨 〇 7 receives and oscillates the clock signal CLK according to the signal output by the low-pass filter 1 09, and simultaneously outputs it to the output terminal 〇i and the frequency divider 103. The frequency divider 103 generates a reference signal f ′ according to the clock signal CL: generation ratio and comparison signal, and at the same time, the reference signal generation state 5 f generates a reference signal f ′, and also sends a phase comparison. The device reads the device 1 0 1 and compares the comparison signal fa with the reference signal fr, and then 9 pays the value signal V and sends it to the charging pump i. While charging

200527179 V. Description of the invention (2) Pump 1 1 1 raises the difference signal V by a predetermined level, and then outputs it to the low-pass ferrule 109. FIG. 1B shows a block diagram of a conventional clock generator. Please refer to Figure 1. The clock generator 100 uses a one-to-one method to generate the working clock. In more detail, a predetermined frequency signal corresponds to an output clock signal. For example, the predetermined frequency signals f !, f2, and f3 are respectively input to the phase-locked loops 102, 104, and 106 in the clock generator 100, and the phase-locked loops 1 0 2, 1 0 4, 1 0 6 are based on The predetermined frequency signals fi, f 2, and f 3 generate clock signals CLK 1, CLK 2, and CLK 3, respectively. Please continue to refer to FIG. 1B. As mentioned earlier, the device for generating the predetermined frequency signals ^, f2, and f3 usually uses a quartz crystal as an oscillation source. However, because the volume of the quartz crystal is very large, it cannot be designed in the wafer, but needs to be designed outside the wafer. In this way, the volume of the clock generating circuit will be relatively large. In addition, quartz crystals are also very expensive. For example, the conventional clock generator shown in FIG. 1B requires three predetermined frequency signals, so three quartz crystals are required. Based on the above reasons, we can know that if the conventional clock generator 100 needs to generate more working clocks, the number of quartz oscillators will be larger, so the volume will be larger and the price will be higher. The more expensive it is. In addition, in a computer system, a Spread Spectrum Controller (SSC) is required to control the spread-spectrum function of the VGA card. The conventional technique uses a phase-locked loop to receive the input clock signal, and then outputs it to the spread spectrum controller to make the spread spectrum controller operate.

12276TWF.PTD Page 6 200527179 V. Description of the invention (3) However, the disadvantage of the conventional technology is that when the spread-spectrum controller does not operate, the phase-locked loop is also idle, which is equivalent to wasting an additional phase-locked loop. Inside the clock generator. SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a clock generator that can generate different clock signals by using a predetermined frequency signal. Yet another object of the present invention is to provide a clock generator. When the spread-spectrum controller is not in operation, the phase-locked loop coupled thereto can also be used for other purposes without causing waste. Another object of the present invention is to provide a clock generator, which can not only generate a clock signal of different frequencies by using a predetermined frequency signal, but also receive an input clock signal to perform a frequency spreading operation. Another object of the present invention is to provide a clock generator that can use a predetermined frequency signal to generate clock signals that are commonly used at different frequencies, and can also generate a clock signal with a special frequency according to the input predetermined frequency signal. To achieve the above and other objectives, the present invention provides a clock generator including a frequency-multiplexed circuit and a multi-frequency phase-locked loop. In terms of frequency multiplexing circuits, it includes a spread-spectrum controller, an internal phase-locked loop, and a multiplexer. The spread spectrum controller is used to cause the frequency multiplexing circuit to perform spread spectrum processing on the received input clock signal to obtain the first clock signal. In addition, the internal phase-locked loop is used to enable the frequency multiplexing circuit to receive a fixed predetermined frequency signal to obtain a second clock signal. The frequency of the second clock signal is equal to the frequency of the predetermined frequency signal multiplied by N and then divided by M, and N and M

12276TWF.PTD Page 7 200527179 V. Description of the invention (4) is a positive integer. The aforementioned first clock and second clock are simultaneously input to the input terminal of the multiplexer, and the multiplexer selects the first clock signal or the second clock signal to output the third clock signal. In addition, in the multi-frequency phase-locked circuit, the aforementioned predetermined frequency signal is received to output a fourth clock signal and a fifth clock signal. The frequency of the fourth clock signal is equal to the frequency of the aforementioned predetermined frequency signal multiplied by T and then divided by U. The frequency of the fifth clock signal is equal to the frequency of the aforementioned predetermined frequency signal multiplied by τ and then divided by V. Among them, T, U, and V need to have a certain correlation to improve the accuracy of the output clock signal of the multi-frequency phase-locked loop. Therefore, the present invention sets T, U, and V as multiples of the product of any of 2X, 3Y, and 5Z, and X, Y, and Z are all positive integers. In a better case, the multi-frequency phase-locked loop further includes receiving a predetermined frequency signal mentioned above to output a sixth clock signal. The frequency of the sixth clock signal is the frequency of the predetermined frequency signal multiplied by T and then divided by W, and W is also set to be a multiple of the product of any of 2 \, 3 ¥, and 52, and X, Υ, and Z is a positive integer. In the above, T, U, V, and W are all set to multiples of 2 ×, 32, and 52. This is because in a notebook computer, the operating frequency required by most devices is a certain The frequency is multiplied by the product of any of 2 ×, 3Υ, and 52, so the present invention adopts the above design. In one embodiment of the present invention, the clock generator further includes a first switch module and a second switch module. The first switch module is coupled to the third clock signal and the output enable signal, and the first switch module determines whether to output the third clock signal according to the output enable signal. this

12276TWF.PTD Page 8 200527179 V. Description of the invention (5) In addition, the second switch module receives the fourth clock signal and the output enable signal, and the second switch module is also determined based on the output enable signal. Whether to output the fourth clock signal. In a preferred case, the first switch module and the second switch module include a multiplexer. From another viewpoint, the present invention provides a clock generator, which is mainly composed of a frequency multiplexing circuit, a multi-frequency phase-locked loop, and a specific frequency phase-locked loop. Similarly, the frequency multiplexing circuit still includes a spread-spectrum controller and an internal phase-locked loop and multiplexer. The frequency multiplexing circuit uses the spread spectrum controller to perform the spread spectrum processing and obtains the first clock signal. In addition, the frequency multiplexing circuit receives the fixed predetermined frequency signal through the internal phase-locked loop and obtains the second clock signal. . The multiplexer then selects the first clock signal or the second clock signal to output the third clock signal. The multi-frequency phase-locked loop will also receive the aforementioned predetermined frequency to output the fourth clock signal and the fifth clock signal. In terms of a specific frequency phase-locked loop, it also receives the aforementioned predetermined frequency signal to obtain a specific frequency signal, and outputs a sixth clock signal. In addition, the frequency of the sixth clock signal is equal to the frequency of the specific frequency signal multiplied by Q and then divided by P, and both Q and P are positive integers. In one embodiment of the present invention, the clock generator further includes a first switch module, a second switch module, and a third switch module. The first switch module is connected to the third clock signal and the output enable signal, and the first switch module determines whether to output the third clock signal according to the output enable signal. In addition, the second switch module receives the fourth clock signal and the output enable signal, and the second switch module is also based on the output.

12276TWF.PTD Page 9 200527179 V. Description of the invention (6) Enable the signal to decide whether to output the fourth clock signal. In addition, the third switch module receives the sixth clock signal and the output enable signal, and the third switch module also determines whether to output the sixth clock signal based on the output enable signal. In a preferred case, the first, second and third switch modules include a multiplexer. From another viewpoint, the present invention provides a frequency multiplexer circuit of a clock generator, which includes a frequency spreading controller, an internal phase locked loop, and a multiplexer. The spread-spectrum controller is used to make the phase-locked loop perform spread-spectrum processing on the received input clock signal to obtain the first clock signal. In addition, the internal phase-locked loop is used to enable the frequency multiplexing circuit to receive a fixed predetermined frequency signal to obtain a second clock signal. In addition, the frequency of the above-mentioned second clock signal is equal to the frequency of the predetermined frequency signal multiplied by N and then divided by M, and N and M are positive integers. The multiplexer receives the first clock signal and the second clock signal, and selects the first clock signal or the second clock signal to output the third clock signal. In one embodiment of the present invention, the clock generator of the present invention further includes a specific frequency phase-locked loop, which is used to receive the aforementioned predetermined frequency signal and obtain a specific frequency signal to output a fourth clock signal, wherein, The frequency of the fourth clock signal is equal to the frequency of the specific frequency signal multiplied by Q and then divided by P, and both Q and P are positive integers. From another perspective, the present invention provides a clock generator including a multi-frequency phase-locked loop, which is characterized in that the multi-frequency phase-locked loop receives a fixed predetermined frequency signal to output a first clock signal and a second clock Signal.

12276TWF.PTD Page 10 200527179 V. Description of the invention (7) where the frequency of the first clock signal is equal to the frequency of the predetermined frequency signal times T and then divided by U, and the frequency of the second clock signal is equal to the predetermined frequency The frequency of the signal is multiplied by T and then divided by V. The foregoing T, U, and V are multiples of the product of any of 2X, 3Y, and 5Z, and X, Υ, and Z are all positive integers. In a better case, the above-mentioned multi-frequency phase-locked loop further includes receiving a predetermined frequency to output a third clock signal. The frequency of the third clock signal is the frequency of the predetermined frequency signal multiplied by T and then divided by W, and W is a multiple of the product of any of 2 ×, 3Υ, and 52, and X, Υ, and Z are positive Integer. In one embodiment of the present invention, the clock generator of the present invention further includes a specific frequency phase-locked loop for receiving the aforementioned predetermined frequency signal to obtain a specific frequency signal and outputting a fourth clock signal. Among them, the frequency of the fourth clock signal is equal to the frequency of the specific frequency signal multiplied by Q and then divided by P, and Q and P are positive integers. In summary, because the present invention sorts out the required clock signals by a rule of the least common multiple, it only needs to use a fixed predetermined frequency signal to generate different clock signals. Also, because the present invention only needs to use a fixed predetermined frequency signal, in contrast, only one quartz crystal to be used is required, so that the volume and price of the clock generator of the present invention are greatly reduced. In addition, the frequency multiplexing circuit in the clock generator of the present invention can output a clock signal when the spread spectrum controller is idle, without causing waste due to idleness. To make the above and other objects, features and advantages of the present invention clearer

12276TWF.PTD Page 11 200527179 V. Description of the invention (8) It is easy to understand. Several examples are given below in conjunction with the attached drawings for detailed explanations as follows. > Embodiment First Embodiment FIG. 2 is a block diagram of a clock generator according to a first embodiment of the present invention. Referring to FIG. 2A, in this embodiment, the clock generator includes a frequency multiplexing circuit 2000, which receives an input clock signal Ti and a predetermined frequency signal I to generate a third clock signal CLK3. In this embodiment, the predetermined frequency signal f! Is 14.318 MHz. Looking at the internal structure of the frequency multiplexing circuit 2 0 in detail, please continue to refer to FIG. 2A. The receiving system of the multiplexer 21 receives the input clock signal L and the predetermined frequency signal d. 〇4. The internal phase-locked loop 204 outputs its output to the spread spectrum controller 202 and the multiplexer 206. The Xi Gong device 2 0 6 receives and receives the output of the internal phase-locked loop 204 and the spread spectrum controller 202, respectively. In this embodiment, the purpose of arranging the spread spectrum controller 202 is to perform a spread spectrum operation on a device such as a video graphics array (v i d e o g a p h i c s a r r a y, hereinafter referred to as V G A). The designer can use the spread spectrum control enable signal SSC-EN to control the multiplexer 206 switching output. When the clock generator of the present invention is to spread the VGA, the spread spectrum control enable signal SSC-EN can control the multiplexer 206 to turn on the input terminal 206a and the output terminal 2 0 6 c 'to select the spread spectrum controller 2 〇2 output to generate the clock signal CLK3. If the frequency multiplexing circuit 2000 is not used for frequency spreading, the frequency spreading control enable signal SSC-EN enables the multiplexer to turn on the input terminal 2 6 b and the output terminal.

12276TWF.PTD Page 12 200527179

The output of the internal phase-locked loop 2 ο 4 is selected to generate the clock signals 2 0 6c, CLK3. The picture selector, the multiplexer 21 selects the SEL according to the selection signal sel, and the multiplexer 21 selects the input clock :: loop 204. The internal phase-locked loop 2 0 4 series generates the clock signal CLK1 after dividing the input clock ~ pulse | sign / multiplying by M, where m * n are both numbers, and the numbers of M and N | 'can be familiar with this technique Designed by the actual situation. Next, the spread spectrum controller 202 will generate the clock signal CLK2 according to the clock signal "^. If the clock generator of the present invention does not need to perform the spread spectrum operation, selecting the signal SE L makes the multiplexer 2丨 Select a predetermined frequency signal f! And send it to the internal phase-locked loop 2 0 4 to generate a clock signal cl κ 1. Another alternative embodiment, 'qing', refers to FIG. 2B, which shows the internal block of another frequency multiplexing circuit. In FIG. 2B, the frequency multiplexing circuit 200 only needs a predetermined frequency number as an input, so the multiplexer 21 'in FIG. 2B can be saved, and the internal structure of the frequency multiplexing circuit 200 can be more improved. Simplicity. In this figure, the predetermined frequency signal of the frequency multiplexing circuit 200 can be selected to be 27 MHz. Second Embodiment FIG. 3A is a block diagram of a clock generator according to a second embodiment of the present invention. Please Referring to FIG. 3A ', in this embodiment, the clock generator of the present invention includes a multi-frequency phase-locked loop 300. The multi-frequency phase-locked loop 300 receives the same predetermined frequency signal as the first embodiment. f I, when simultaneous generation

12276TWF.PTD Page 13 200527179 V. Description of the Invention (ίο) The clock CLK1 and the clock CLK2. Generally speaking, if the input frequency signal and the output clock signal have a one-to-one relationship, that is, when the phase-locked loop receives a predetermined frequency signal to generate a clock signal, its clock signal The accuracy is very high. However, if the clock generator of the present invention receives one frequency signal and generates multiple clock signals, there needs to be some correlation between each output clock signal to improve the accuracy of the frequency of the output signal. Please continue to refer to FIG. 3A. The multi-frequency phase-locked loop 3 0 0 has a frequency setting circuit 3 0 2, 3 0 4, 3 0 6. In this embodiment, the multi-frequency phase-locked loop 300 receives a predetermined frequency signal fi, and causes the frequency setting circuit 3 002 to multiply the frequency of the frequency signal f! By T, and then sends them to the frequency setting circuit 3 〇 4 And the frequency setting circuit 3 0 6. Among them, the frequency setting circuit 3 0 4 multiplies the predetermined frequency signal f! By T and then divides by u, and then generates a clock signal C L K 1 by the multi-frequency phase-locked loop 3 0 0. The frequency setting circuit 3 0 6 multiplies the predetermined frequency signal f! By T and then divides by V, and the multi-frequency phase-locked loop 3 0 0 generates a clock signal CLK2. In this embodiment, τ, U, and V are all positive integers, and are also multiples of the product of any of 2, 3, and 52. Similarly, X, γ, and Z are also positive integers. In the present embodiment, the reason why T, U, and V are set to a multiple of any of 2 ×, 3Υ, and 52 is because in a notebook computer, the operating frequency of many devices is 2 ×, 3Y, and The multiple of the product of any two of 5Z. For example, the operating frequency of VGA is 27MHz. Therefore, the present invention takes the least common multiple of the working frequency commonly used in pen-sized computers to obtain the relationship between the clock signals CLK1 and CLK2, and therefore can improve accuracy.

12276TWF.PTD Page 14 200527179 V. Description of the invention (11) Degree 0 Although the 'multi-frequency phase-locked loop 3' in this embodiment receives the frequency signal ί! To generate the clock signals CLK1 and CLK2, this is not the case. To define the invention. FIG. 3B is a block diagram of another clock generator according to the second embodiment of the present invention. Please refer to FIG. 3B. In addition to generating the clock signals CLK1 and CLK2, the multi-frequency phase-locked loop 3 can also generate C L κ 3 as shown in FIG. The same principle as in Fig. 3 A, the multi-frequency phase-locked loop 3 00 receives the reservation, and after the signal f! Causes the frequency setting circuits 3 02 and 3 08 to multiply the predetermined frequency signal L by T and then divide by w, Then, the multi-frequency phase-locked loop 30 () generates a clock signal CLK3. Among them, D and W are multiples of 2X, 3Y, and M, and any multiple of the product of the two. Integer. FIG. 3C is a schematic block diagram of a part of a multi-frequency phase-locked loop. Referring to FIG. 3C, the voltage controlled oscillator 31 is coupled to the frequency divider 33 and the frequency settings 3 0 4 3 0, 6 and 3 0 8. The output of the frequency divider 3 3 is connected to the phase comparator 35. When the voltage-controlled oscillator 3 丨 starts to oscillate, the output clock No. CLK 0UT will be generated to the frequency divider 3 3. The divider 3 3 divides the output clock signal = Τ2 ί by Τ to generate a clock signal CLKA, where T is a multiple of the product of any of the three 3J ”5 Z. In addition, the phase, = fclock signal * ^ 1 ^ and the predetermined frequency signal f !, and the phase / secondary lacks i to generate a comparison clock signal based on the result of the comparison between the two, and then compares the clock signal CLKCOM with the subsequent voltage boost after w After the programs such as and two waves are passed (please refer to Figure 丨 A for the detailed principle), it is then fed back to the voltage-controlled oscillation circuit 31. For a month, continue to refer to Figure 3 c 'Frequency setting circuit 3 〇 *, 3 〇6, and 3 〇 8 same

200527179 V. Description of the invention (12) The output clock signal CLK0UT will also be received. Among them, the frequency setting circuit divides the frequency of the output clock signal CLK 0 UT by u to generate the clock signal CLK1; the frequency setting circuit 306 divides the frequency of the output clock signal CLK〇UT by V 'to generate the clock The signal c LK 2; and the frequency setting circuit 3 08 divides the frequency of the output clock signal CLK0UT by w to generate the clock signal CLK3. Among them, U, V, and the boundary systems 2x, 3y, and 5z, any two of them ^ product, multiple. When the entire multi-frequency phase-locked loop 30 () stabilizes, the frequency of the clock signal CLKA will be equal to the frequency of the predetermined frequency signal f !. That is to say, the frequency of the output clock signal CLKOUT will be equal to τ times the frequency of the frequency signal ίI. In general, the frequency setting circuits 304, 306, and 308 can be implemented by a frequency divider circuit. Third Embodiment FIG. 4 shows Yi Zhaonv Road aa & _ 也 t, 丨 ^ @. Pearlitis π According to the clock generator block 1 of the second embodiment of the present invention # 22: In the second embodiment, it is mentioned that the working frequency of v 22 in the notebook computer Φ J Γ is a predetermined frequency signal fl multiplied Up 2 ×, 3Υ and Gan: from digging! The product of the two is a multiple, but not all of the devices. 1. Examples; this is true for J 5. The operating frequency of some devices cannot be generated using the method of the second phase-locked loop 300. Therefore, a certain secondary clock signal must be used. Therefore, in this embodiment, particularly: In the embodiment, J = J4: 0 to generate a specific clock signal. Invented at the combined cost of ί 回 J ；; 40 ° can be produced with other circuits $ 工 雷 # 寺 脉As in this embodiment, the frequency is set to fm / f & The fixed-frequency phase-locked loop 400 is combined and the combined cost is 100%. The frequency multiplexing circuit 2 0 0 is in the first embodiment.

12276TWF.PTD Page 16 200527179 V. The description of the invention (13) has already been introduced, and here is no longer 簪, +, ,, .. Road 4 0 0 俜 to receive the above-mentioned reservation. Outside the specific frequency phase-locked circuit 4υυ you receive the above-mentioned pre-frequency signal and the clock signal CLK5. Clock A 5 Tiger CLK4

Please continue to refer to FIG. 4. Specify and cover the clutter, gate A setting circuit 4 0 2 and frequency setting circuit 2 2/2 ° including the frequency, and also receive the predetermined frequency signal ^ 40 4 true = = buccal phase lock After loop 400, make it special; Phase; ufl, after passing the frequency setting circuit 402, the frequency phase-locked loop 4 0 0 is output to the pulse %% clock CLK5 from the special macro; in this embodiment, the time The pulse frequency is the frequency of the clock signal CLK5, for example, wr. The frequency of the clock signal CLK5 is 24. Γ generates z out of K frequency. The frequency setting circuit in the second embodiment is widely used. The signal sent by 4 2 is multiplied by Q and divided by ρ, and the phase loop 4 00 will generate a clock or a gap Γϊ, and 0 will make the frequency of the fourth embodiment half locked. Where side 4 and QR are positive integers. 5 is a block diagram of a clock generator according to a fourth embodiment of the present invention. Referring to FIG. 5, in this embodiment, the clock generator of the present invention includes an evening frequency phase locked loop 300 and a specific frequency phase locked loop 4 00. Among them, the multi-frequency phase-locked loop 300 and the specific frequency phase-locked loop 400 are simultaneously receiving a predetermined frequency signal and generating a clock signal (^) {1, CLK2, CLK3, CLK4, and CLK 5 'and their respective working principles The above embodiments have been described, and will not be repeated here. 25th Embodiment 16 is a block diagram of a clock generator according to a fifth embodiment of the present invention. Referring to FIG. 6 in the second embodiment, in this embodiment, The frequency multiplexing circuit 200 in the first embodiment and the multi-frequency phase-locked loop 3 in the second embodiment are

12276TWF.PTD Page 17 200527179 V. Description of the invention (14) Synthesis of the clock generator of the present invention. For the individual working principles, please refer to the first embodiment and the second embodiment, and will not be repeated here. Sixth Embodiment FIG. 7 is a block diagram of a clock generator according to a sixth embodiment of the present invention. Please refer to FIG. 7. In this embodiment, the clock generator of the present invention includes a frequency multiplexing circuit 200, a multi-frequency phase-locked loop 300, and a specific frequency phase-locked loop 400, which receives an input clock. The signal Ti and the predetermined frequency signal f I are used to generate clock signals CLK3, CLK4, CLK5, CLK6, CLK7, CLK8 and CLK9. The frequency of CLK9 is the frequency of the predetermined frequency signal f !. In this embodiment, the frequency of the predetermined frequency signal f! Is, for example, 1 4 · 3 1 8 Μ Η z. In addition, in this embodiment, the frequency setting circuit 3 0 2 multiplies the frequency of the predetermined frequency signal ^ received by the multi-frequency phase-locked loop 3 0 0 by 5 times 8 times 2 7 and sends them to the frequency setting circuits respectively. 3 0 4, 3 0 6 and 3 0 8. Among them, the frequency setting circuit 304 divides the frequency of the clock signal sent by the frequency setting circuit 302 by 2X1 divided by 3Y1 divided by 5Z1. In addition, the frequency setting circuit 3 0 6 divides the frequency of the clock signal sent by the frequency setting circuit 3 2 by 2X2 divided by 3Y2 by 5Z2, and the frequency setting circuit 3 0 8 is the frequency setting circuit 3 0 2 The frequency of the clock signal sent is divided by 2X3 divided by 3Y3 divided by 5Z3. The aforementioned XI, X2, X3, Yl, Y2, Y3, Zl, Z2, and Z3 are all positive integers. The detailed working principles of the frequency multiplexing circuit 2000, the multi-frequency phase-locked loop 300, and the specific frequency phase-locked loop 400 are all mentioned in the above embodiments, so the present invention will not repeat them here. In the above six embodiments, the manner in which the present invention can be changed is proposed, but the present invention is not limited to this design. As long as the clock

12276TWF.PTD Page 18 200527179 V. Description of the invention (15) The generator is composed of a phase-locked loop, and can use a fixed predetermined frequency signal to generate multiple clock signal outputs, which is in line with the spirit of the present invention. Therefore, those skilled in this art can make changes according to actual needs. For example, FIG. 8 is a block diagram of a more power-saving clock generator according to a preferred embodiment of the present invention. In FIG. 8, each output clock signal is input to, for example, the switching circuit of the multiplexer 81, and each switching circuit is, for example, as shown by the multiplexer 81, and receives the output enable signal 0-En to determine Whether to output the clock signals CLK3, CLK4, CLK5, CLK6, CLK7, CLK8 and CLK9. When the clock generation circuit is in the power saving mode, the output enable signals 0-EN can control the output of all the switching circuits to be turned off to save power loss. To sum up, the clock generator of the present invention has the following advantages: 1. The clock generator of the present invention needs only one input frequency because it sorts out the required clock signals to a rule of the least common multiple. The signal can generate multiple different clock signals. Therefore, the number of quartz crystals required is only one, which effectively reduces the volume occupied by the clock generator of the present invention on the circuit. At the same time, because the number of quartz crystals is small, the overall price of the clock generator of the present invention can also be reduced. 2. The phase-locked loop in the clock generator of the present invention, when the spread spectrum controller is idle, will not be idle with it, but will instead output a clock signal, so it will not cause waste. 3. The clock generator of the present invention also combines different phase-locked circuits, so it can not only use one input frequency signal to generate multiple different

12276TWF.PTD Page 19 200527179 5. The clock signal of the description of the invention (16) can also perform spread spectrum operation at the same time. 4. As mentioned above, because different phase-locked loops are combined, it can not only generate clock signals of common frequencies, but also generate clock signals of specific frequencies. Although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application.

12276TWF.PTD Page 20 200527179 Brief description of the diagram Figure 1 A block diagram of a conventional phase-locked loop. FIG. 1B shows a block diagram of a conventional clock generator. Fig. 2A is a block diagram of a frequency multiplexing circuit of the first embodiment of the present invention. Fig. 2B is a block diagram of a frequency multiplexing circuit of the present invention. FIG. 3A is a block diagram of a clock generator of the second embodiment of the present invention. FIG. 3B is a block diagram of the clock generator of the second embodiment of the present invention. Figure 3 Schematic diagram of some internal blocks of the C series multi-frequency phase-locked loop. FIG. 4 is a block diagram of a clock generator according to a third embodiment of the present invention. FIG. 5 is a block diagram of a clock generator according to a fourth embodiment of the present invention. FIG. 6 is a block diagram of a clock generator according to a fifth embodiment of the present invention. FIG. 7 is a block diagram of a clock generator according to a sixth embodiment of the present invention. FIG. 8 is a block diagram of a more power-saving clock generator according to a preferred embodiment of the present invention. [Illustration of diagrammatic symbols] 21, 81, 206: Multiplexer 3 5, 1 0 1: Phase comparator 3 3, 1 0 3: Frequency divider 1 0 5: Reference signal generator 31, 107: Voltage-controlled oscillation 1 0 9: Low-pass filter 1 1 1: Charging pump 1 1 3: Compensation circuit

12276TWF.PTD Page 21 200527179 Brief description of the drawings 1 1 5: Control circuit 1 0 0: Clock generators 102, 104, 106: Phase-locked loop 200: Frequency multiplexing circuit 2 0 2: Spread spectrum controller 2 0 4: Internal phase-locked loops 206a, 206b: Input 2 0 6 c: Output 3 0 0: Multi-frequency phase-locked loops 302, 304, 306, 308, 402, 404: Frequency setting circuit 4 0 0: Specific frequency lock Phase loop

12276TWF.PTD Page 22

Claims (1)

200527179 6. Scope of patent application 1. A clock generator includes: a frequency multiplexing circuit including: a frequency spreading controller for causing the frequency multiplexing circuit to receive an input clock signal and perform a frequency spreading process To obtain a first clock signal; an internal phase-locked loop to enable the frequency multiplexing circuit to receive a predetermined frequency signal and obtain a second clock signal, wherein the frequency of the second clock signal is equal to Multiplying the frequency of the predetermined frequency signal by N divided by M, and N and M are positive integers; and a multiplexer for selecting one of the first clock signal and the second clock signal to output A third clock signal; and a multi-frequency phase-locked loop for receiving the predetermined frequency signal and outputting a fourth clock signal and a fifth clock signal, wherein the frequency of the fourth clock signal is equal to the The frequency of the predetermined frequency signal is multiplied by T divided by U. The frequency of the fifth clock signal is equal to the frequency of the predetermined frequency signal times T divided by V, and T, U, and V are all three of 2 ×, 3, and 52. The multiple of the product of any two, and X, Υ And Z are positive integers. 2. The clock generator according to item 1 of the scope of patent application, wherein the multi-frequency phase-locked loop further includes receiving the predetermined frequency and outputting a sixth clock signal, the frequency of the sixth clock signal being the predetermined frequency. The frequency of the frequency signal is multiplied by T divided by W, and W is a multiple of the product of any of 2 ×, 3Υ, and 52, and X, Υ, and Z are positive integers. 3. The clock generator as described in item 1 of the patent application scope, including: 12276TWF.PTD Page 23 200527179 Sixth, the scope of application for patent No. _ _ switch module receives the —— clock signal and an output enable signal j and the first switch module determines according to the output enable signal Whether to output the third clock signal; and _ a second switch module j receives the fourth clock signal and the output enable signal and the second switch module determines whether to output the signal according to the output enable signal The fourth clock signal output 04. As described in the clock generator described in item 3 of the patent scope, the first switch module and the second switch module include _ a multiplexer 〇5. 一 丨A clock generator includes ·· _ A frequency multiplexing circuit includes • — 丨 丨 a spread spectrum controller for causing the frequency multiplexing circuit to receive an input clock signal and perform _ A first clock signal _ is obtained by spread spectrum processing _ an internal phase-locked loop for the frequency multiplexer circuit to receive _ a predetermined frequency signal 5 to obtain a _ 丨 丨 _ second clock signal. Among them, the first •- _ The frequency of the clock signal is equal to the frequency of the predetermined frequency signal multiplied by N divided by M, and N and M are positive integers:: and a multiplexer for changing from the first clock signal to the second clock signal Alternatively, output a second clock signal y _ 丨 a multi-frequency phase-locked loop j to receive the predetermined frequency signal, output a fourth clock signal and a fifth clock signal, wherein the fourth clock signal The frequency of the clock signal is equal to the frequency of the predetermined frequency signal times T divided by U, the frequency of the fifth clock signal is equal to the frequency of the predetermined frequency signal times ^ Γ divided by V, and T U and V are both 2 × , 3Υ and 5 Any of the three persons •. • The plot of the rider 'times 12276TWF.PTD Page 24 200527179 6. Number of patent applications, and X, Υ, and Z are positive integers; and a specific frequency phase-locked loop for receiving the predetermined frequency signal, obtaining a specific frequency signal, and outputting a The sixth clock signal, wherein the frequency of the sixth clock signal is equal to the frequency of the specific frequency signal times Q divided by P, and both Q and P are positive integers. 6. The clock generator according to item 5 of the scope of patent application, wherein the multi-frequency phase-locked loop further includes receiving the predetermined frequency and outputting a sixth clock signal, and the frequency of the sixth clock signal is the predetermined frequency. The frequency of the frequency signal is multiplied by T divided by W, and W is a multiple of the product of any of 2 ×, 3Υ, and 52, and X, Υ, and Z are positive integers. 7. The clock generator according to item 5 of the scope of patent application, further comprising: a first switch module, which receives the third clock signal and an output enable signal, and the first switch module is based on The output enable signal is used to decide whether to output the third clock signal; and a second switch module receives the fourth clock signal and the output enable signal, and the second switch module is based on the output Enable the signal to decide whether to output the fourth clock signal. A third switch module receives the sixth clock signal and the output enable signal, and the third switch module determines whether to output the fourth clock signal according to the output enable signal 8 · According to the clock generator described in item 7 of the scope of the patent application, the first switch module, the second switch module and the third switch module include a multiplexer. 12276TWF.PTD Page 25 200527179 6. Scope of patent application 9. A frequency multiplexing circuit of a clock generator includes: a spread spectrum controller for causing the frequency multiplexing circuit to receive an input clock signal to perform a A frequency spreading process is performed to obtain a first clock signal; an internal phase-locked loop is used to enable the frequency multiplexing circuit to receive a predetermined frequency signal and obtain a second clock signal, wherein the second clock signal A frequency equal to the frequency of the predetermined frequency signal multiplied by N divided by M, where N and M are positive integers; and a multiplexer for selecting from the first clock signal and the second clock signal, The third clock signal is output. 10. The frequency multiplexing circuit of the clock generator according to item 9 of the scope of the patent application, further comprising: a first switch module that receives the third clock signal and an output enable signal, and the The first switch module determines whether to output the third clock signal according to the output enable signal; and a second switch module receives the fourth clock signal and the output enable signal, and the first The two switch modules determine whether to output the fourth clock signal according to the output enable signal. 1 1 · According to the frequency multiplexer circuit of the clock generator described in item 10 of the scope of patent application, the first switch module and the second switch module include a multiplexer. 12. A clock generator includes a multi-frequency phase-locked loop, which is characterized in that the multi-frequency phase-locked loop receives a predetermined frequency signal and outputs a first clock signal and a second clock signal, wherein , The frequency of the first clock signal is equal to the frequency of the predetermined frequency signal multiplied by T divided by U, and the second 12276TWF.PTD Page 26 200527179 6. The frequency of the clock signal of the patent application is equal to the frequency of the predetermined frequency signal multiplied by τ divided by V, and T, U and V are all two of 2X, 3 ¥ and 52. The product of multiples, and X, Y, and Z are all positive integers. 1 3. The clock generator according to item 12 of the scope of patent application, wherein the multi-frequency phase-locked loop further includes receiving the predetermined frequency and outputting a third clock signal, and the frequency of the third clock signal is The frequency of the predetermined frequency signal is multiplied by T divided by W, and W is a multiple of the product of any of 2 ×, 3Υ, and 52, and X, Υ, and Z are all positive integers. 14. The clock generator according to item 12 of the scope of patent application, further comprising a specific frequency phase-locked loop for receiving the predetermined frequency signal, obtaining a specific frequency signal, and outputting a fourth clock signal Wherein, the frequency of the fourth clock signal is equal to the frequency of the specific frequency signal times Q divided by P, and Q and P are positive integers. 1 5. According to the clock generator described in item 14 of the scope of patent application, the frequency of the specific frequency signal is 2 4. 5 7 6MHz. 12276TWF.PTD Page 27